qemu/hw/ssi/xilinx_spips.c
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   1/*
   2 * QEMU model of the Xilinx Zynq SPI controller
   3 *
   4 * Copyright (c) 2012 Peter A. G. Crosthwaite
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "hw/sysbus.h"
  27#include "sysemu/sysemu.h"
  28#include "hw/ptimer.h"
  29#include "qemu/log.h"
  30#include "qemu/bitops.h"
  31#include "hw/ssi/xilinx_spips.h"
  32#include "qapi/error.h"
  33#include "hw/register-dep.h"
  34#include "sysemu/dma.h"
  35
  36#ifndef XILINX_SPIPS_ERR_DEBUG
  37#define XILINX_SPIPS_ERR_DEBUG 0
  38#endif
  39
  40#define DB_PRINT_L(level, ...) do { \
  41    if (XILINX_SPIPS_ERR_DEBUG > (level)) { \
  42        qemu_log_mask(DEV_LOG_SPI, ": %s: ", __func__); \
  43        qemu_log_mask(DEV_LOG_SPI, ## __VA_ARGS__); \
  44    } \
  45} while (0);
  46
  47/* config register */
  48#define R_CONFIG            (0x00 / 4)
  49#define IFMODE              (1U << 31)
  50#define R_CONFIG_ENDIAN     (1 << 26)
  51#define MODEFAIL_GEN_EN     (1 << 17)
  52#define MAN_START_COM       (1 << 16)
  53#define MAN_START_EN        (1 << 15)
  54#define MANUAL_CS           (1 << 14)
  55#define CS                  (0xF << 10)
  56#define CS_SHIFT            (10)
  57#define PERI_SEL            (1 << 9)
  58#define REF_CLK             (1 << 8)
  59#define FIFO_WIDTH          (3 << 6)
  60#define BAUD_RATE_DIV       (7 << 3)
  61#define CLK_PH              (1 << 2)
  62#define CLK_POL             (1 << 1)
  63#define MODE_SEL            (1 << 0)
  64#define R_CONFIG_RSVD       (0x7bf40000)
  65
  66/* interrupt mechanism */
  67#define R_INTR_STATUS       (0x04 / 4)
  68#define R_INTR_EN           (0x08 / 4)
  69#define R_INTR_DIS          (0x0C / 4)
  70#define R_INTR_MASK         (0x10 / 4)
  71#define IXR_TX_FIFO_UNDERFLOW   (1 << 6)
  72/* FIXME: Poll timeout not implemented */
  73#define IXR_RX_FIFO_EMPTY       (1 << 11)
  74#define IXR_GENERIC_FIFO_FULL   (1 << 10)
  75#define IXR_GENERIC_FIFO_NOT_FULL (1 << 9)
  76#define IXR_TX_FIFO_EMPTY       (1 << 8)
  77#define IXR_GENERIC_FIFO_EMPTY  (1 << 7)
  78#define IXR_RX_FIFO_FULL        (1 << 5)
  79#define IXR_RX_FIFO_NOT_EMPTY   (1 << 4)
  80#define IXR_TX_FIFO_FULL        (1 << 3)
  81#define IXR_TX_FIFO_NOT_FULL    (1 << 2)
  82#define IXR_TX_FIFO_MODE_FAIL   (1 << 1)
  83#define IXR_RX_FIFO_OVERFLOW    (1 << 0)
  84#define IXR_ALL                 ((1 << 13) - 1)
  85#define GQSPI_IXR_MASK          0xFBE
  86
  87#define IXR_SELF_CLEAR \
  88( IXR_GENERIC_FIFO_EMPTY \
  89| IXR_GENERIC_FIFO_FULL  \
  90| IXR_GENERIC_FIFO_NOT_FULL \
  91| IXR_TX_FIFO_EMPTY \
  92| IXR_TX_FIFO_FULL  \
  93| IXR_TX_FIFO_NOT_FULL \
  94| IXR_RX_FIFO_EMPTY \
  95| IXR_RX_FIFO_FULL  \
  96| IXR_RX_FIFO_NOT_EMPTY)
  97
  98#define R_EN                (0x14 / 4)
  99#define R_DELAY             (0x18 / 4)
 100#define R_TX_DATA           (0x1C / 4)
 101#define R_RX_DATA           (0x20 / 4)
 102#define R_SLAVE_IDLE_COUNT  (0x24 / 4)
 103#define R_TX_THRES          (0x28 / 4)
 104#define R_RX_THRES          (0x2C / 4)
 105#define R_TXD1              (0x80 / 4)
 106#define R_TXD2              (0x84 / 4)
 107#define R_TXD3              (0x88 / 4)
 108
 109#define R_LQSPI_CFG         (0xa0 / 4)
 110#define R_LQSPI_CFG_RESET       0x03A002EB
 111#define LQSPI_CFG_LQ_MODE       (1U << 31)
 112#define LQSPI_CFG_TWO_MEM       (1 << 30)
 113#define LQSPI_CFG_SEP_BUS       (1 << 29)
 114#define LQSPI_CFG_U_PAGE        (1 << 28)
 115#define LQSPI_CFG_ADDR4         (1 << 27)
 116#define LQSPI_CFG_MODE_EN       (1 << 25)
 117#define LQSPI_CFG_MODE_WIDTH    8
 118#define LQSPI_CFG_MODE_SHIFT    16
 119#define LQSPI_CFG_DUMMY_WIDTH   3
 120#define LQSPI_CFG_DUMMY_SHIFT   8
 121#define LQSPI_CFG_INST_CODE     0xFF
 122
 123#define R_CMND        (0xc0 / 4)
 124    #define R_CMND_RXFIFO_DRAIN   (1 << 19)
 125    /* FIXME: Implement */
 126    DEP_FIELD(CMND, PARTIAL_BYTE_LEN, 3, 16)
 127#define R_CMND_EXT_ADD        (1 << 15)
 128    /* FIXME: implement on finer grain than byte level */
 129    DEP_FIELD(CMND, RX_DISCARD, 7, 8)
 130    /* FIXME: Implement */
 131    DEP_FIELD(CMND, DUMMY_CYCLES, 6, 2)
 132#define R_CMND_DMA_EN         (1 << 1)
 133#define R_CMND_PUSH_WAIT      (1 << 0)
 134
 135#define R_TRANSFER_SIZE     (0xc4 / 4)
 136
 137#define R_LQSPI_STS         (0xA4 / 4)
 138#define LQSPI_STS_WR_RECVD      (1 << 1)
 139
 140#define R_MOD_ID            (0xFC / 4)
 141
 142#define R_GQSPI_SELECT          (0x144 / 4)
 143    DEP_FIELD(GQSPI_SELECT, GENERIC_QSPI_EN,          1, 0)
 144#define R_GQSPI_ISR         (0x104 / 4)
 145#define R_GQSPI_IER         (0x108 / 4)
 146#define R_GQSPI_IDR         (0x10c / 4)
 147#define R_GQSPI_IMR         (0x110 / 4)
 148#define R_GQSPI_TX_THRESH   (0x128 / 4)
 149#define R_GQSPI_RX_THRESH   (0x12c / 4)
 150
 151#define R_GQSPI_CNFG        (0x100 / 4)
 152    DEP_FIELD(GQSPI_CNFG, MODE_EN,               2, 30)
 153    DEP_FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE,   1, 29)
 154    DEP_FIELD(GQSPI_CNFG, GEN_FIFO_START,        1, 28)
 155    DEP_FIELD(GQSPI_CNFG, ENDIAN,                1, 26)
 156    /* FIXME: Poll timeout not implemented this phase */
 157    DEP_FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT,       1, 20)
 158    /* QEMU doesnt care about any of these last three */
 159    DEP_FIELD(GQSPI_CNFG, BR,                    3, 3)
 160    DEP_FIELD(GQSPI_CNFG, CPH,                   1, 2)
 161    DEP_FIELD(GQSPI_CNFG, CPL,                   1, 1)
 162
 163#define R_GQSPI_GEN_FIFO        (0x140 / 4)
 164
 165#define R_GQSPI_TXD             (0x11c / 4)
 166#define R_GQSPI_RXD             (0x120 / 4)
 167
 168#define R_GQSPI_FIFO_CTRL       (0x14c / 4)
 169    DEP_FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET,       1, 2)
 170    DEP_FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET,       1, 1)
 171    DEP_FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET,  1, 0)
 172
 173#define R_GQSPI_GFIFO_THRESH    (0x150 / 4)
 174
 175#define R_GQSPI_DATA_STS (0x15c / 4)
 176
 177/* We use the snapshot register to hold the core state for the currently
 178 * or most recently executed command. So the generic fifo format is defined
 179 * for the snapshot register
 180 */
 181#define R_GQSPI_GF_SNAPSHOT (0x160 / 4)
 182    DEP_FIELD(GQSPI_GF_SNAPSHOT, POLL,              1, 19)
 183    DEP_FIELD(GQSPI_GF_SNAPSHOT, STRIPE,            1, 18)
 184    DEP_FIELD(GQSPI_GF_SNAPSHOT, RECIEVE,           1, 17)
 185    DEP_FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT,          1, 16)
 186    DEP_FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT,   2, 14)
 187    DEP_FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT,       2, 12)
 188    DEP_FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE,          2, 10)
 189    DEP_FIELD(GQSPI_GF_SNAPSHOT, EXPONENT,          1, 9)
 190    DEP_FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER,         1, 8)
 191    DEP_FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA,    8, 0)
 192
 193#define R_GQSPI_MOD_ID        (0x168 / 4)
 194#define R_GQSPI_MOD_ID_VALUE  0x010A0000
 195
 196/* size of TXRX FIFOs */
 197#define RXFF_A          (128)
 198#define TXFF_A          (128)
 199
 200#define RXFF_A_Q          (64 * 4)
 201#define TXFF_A_Q          (64 * 4)
 202
 203/* 16MB per linear region */
 204#define LQSPI_ADDRESS_BITS 24
 205
 206#define SNOOP_CHECKING 0xFF
 207#define SNOOP_NONE 0xFE
 208#define SNOOP_STRIPING 0
 209
 210static inline int num_effective_busses(XilinxSPIPS *s)
 211{
 212    return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
 213            s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
 214}
 215
 216static void xilinx_spips_update_cs_lines_legacy_mangle(XilinxSPIPS *s,
 217                                                       int *field) {
 218    *field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT);
 219    /* In dual parallel, mirror low CS to both */
 220    if (num_effective_busses(s) == 2) {
 221        /* Signle bit chip-select for qspi */
 222        *field &= 0x1;
 223        *field &= ~(1 << 1);
 224        *field |= *field << 1;
 225    /* Dual stack U-Page */
 226    } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM &&
 227               s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) {
 228        /* Signle bit chip-select for qspi */
 229        *field &= 0x1;
 230        /* change from CS0 to CS1 */
 231        *field <<= 1;
 232    }
 233    /* Auto CS */
 234    if (!(s->regs[R_CONFIG] & MANUAL_CS) &&
 235        fifo_is_empty(&s->tx_fifo)) {
 236        *field = 0;
 237    }
 238}
 239
 240static void xilinx_spips_update_cs_lines_generic_mangle(XilinxSPIPS *s,
 241                                                        int *field) {
 242    *field = DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT);
 243}
 244
 245static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
 246{
 247    int i;
 248    int field = 0;
 249
 250    if (!DEP_AF_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) {
 251        xilinx_spips_update_cs_lines_legacy_mangle(s, &field);
 252    } else {
 253        if (!s->regs[R_GQSPI_GF_SNAPSHOT]) {
 254            return;
 255        }
 256        xilinx_spips_update_cs_lines_generic_mangle(s, &field);
 257    }
 258
 259    for (i = 0; i < s->num_cs; i++) {
 260        bool old_state = s->cs_lines_state[i];
 261        bool new_state = field & (1 << i);
 262
 263        if (old_state != new_state) {
 264            s->cs_lines_state[i] = new_state;
 265            s->rx_discard = DEP_AF_EX32(s->regs, CMND, RX_DISCARD);
 266            DB_PRINT_L(0, "%sselecting slave %d\n", new_state ? "" : "de", i);
 267        }
 268        qemu_set_irq(s->cs_lines[i], !new_state);
 269    }
 270
 271    if (!(field & ((1 << s->num_cs) - 1))) {
 272        s->snoop_state = SNOOP_CHECKING;
 273        s->link_state = 1;
 274        s->link_state_next = 1;
 275        s->link_state_next_when = 0;
 276        DB_PRINT_L(1, "moving to snoop check state\n");
 277    }
 278}
 279
 280
 281#define ZYNQMP_ONLY(a) ((zynqmp) ? (a) : (0))
 282
 283static void xilinx_spips_update_ixr(XilinxSPIPS *s)
 284{
 285    int new_irqline;
 286    uint32_t qspi_int, gqspi_int;
 287    bool zynqmp = false;
 288
 289    if (object_dynamic_cast(OBJECT(s), TYPE_ZYNQMP_QSPIPS)) {
 290        zynqmp = true;
 291    }
 292
 293    /* these are pure functions of fifo state, set them here */
 294    s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR;
 295    s->regs[R_GQSPI_ISR] |=
 296        (fifo_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) |
 297        (fifo_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) |
 298        (s->fifo_g.num < s->regs[R_GQSPI_GFIFO_THRESH] ?
 299                                    IXR_GENERIC_FIFO_NOT_FULL : 0) |
 300
 301        (fifo_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) |
 302        (fifo_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) |
 303        (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ?
 304                                    IXR_RX_FIFO_NOT_EMPTY : 0) |
 305
 306        (fifo_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) |
 307        (fifo_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) |
 308        (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ?
 309                                    IXR_TX_FIFO_NOT_FULL : 0);
 310
 311    if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
 312        s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR;
 313        s->regs[R_INTR_STATUS] |=
 314            (fifo_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
 315            (s->rx_fifo.num >= s->regs[R_RX_THRES] ?
 316                                    IXR_RX_FIFO_NOT_EMPTY : 0) |
 317            ZYNQMP_ONLY(fifo_is_empty(&s->tx_fifo) ? IXR_TX_FIFO_EMPTY : 0) |
 318            (fifo_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
 319            (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
 320    }
 321
 322    /* QSPI/SPI Interrupt Trigger Status */
 323    qspi_int = s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS];
 324    /* GQSPI Interrupt Trigger Status */
 325    gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] &
 326                   GQSPI_IXR_MASK;
 327    /* drive external interrupt pin */
 328    new_irqline = !!((qspi_int | gqspi_int) & IXR_ALL);
 329    if (new_irqline != s->irqline) {
 330        DB_PRINT_L(0, "IRQ state is changing %" PRIx32 " -> %" PRIx32 "\n",
 331                   s->irqline, new_irqline);
 332        s->irqline = new_irqline;
 333        qemu_set_irq(s->irq, s->irqline);
 334    }
 335}
 336
 337static void xilinx_spips_reset(DeviceState *d)
 338{
 339    XilinxSPIPS *s = XILINX_SPIPS(d);
 340
 341    int i;
 342    for (i = 0; i < XLNX_SPIPS_R_MAX; i++) {
 343        s->regs[i] = 0;
 344    }
 345
 346    fifo_reset(&s->rx_fifo);
 347    fifo_reset(&s->rx_fifo);
 348    fifo_reset(&s->rx_fifo_g);
 349    fifo_reset(&s->rx_fifo_g);
 350    fifo_reset(&s->fifo_g);
 351    /* non zero resets */
 352    s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
 353    s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
 354    s->regs[R_TX_THRES] = 1;
 355    s->regs[R_RX_THRES] = 1;
 356    s->regs[R_GQSPI_TX_THRESH] = 1;
 357    s->regs[R_GQSPI_RX_THRESH] = 1;
 358    s->regs[R_GQSPI_GFIFO_THRESH] = 1;
 359    s->regs[R_GQSPI_IMR] = GQSPI_IXR_MASK;
 360    /* FIXME: move magic number definition somewhere sensible */
 361    s->regs[R_MOD_ID] = 0x01090106;
 362    s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
 363    s->link_state = 1;
 364    s->link_state_next = 1;
 365    s->link_state_next_when = 0;
 366    s->snoop_state = SNOOP_CHECKING;
 367    s->man_start_com = false;
 368    s->man_start_com_g = false;
 369    xilinx_spips_update_ixr(s);
 370    xilinx_spips_update_cs_lines(s);
 371}
 372
 373/* N way (num) in place bit striper. Lay out row wise bits column wise
 374 * (from element 0 to N-1). num is the length of x, and dir reverses the
 375 * direction of the transform. be determines the bit endianess scheme.
 376 * false to lay out bits LSB to MSB (little endian) and true for big endian.
 377 *
 378 * Best illustrated by examples:
 379 * Each digit in the below array is a single bit (num == 3, be == false):
 380 *
 381 * {{ 76543210, }  ----- stripe (dir == false) -----> {{ FCheb630, }
 382 *  { hgfedcba, }                                      { GDAfc741, }
 383 *  { HGFEDCBA, }} <---- upstripe (dir == true) -----  { HEBgda52, }}
 384 *
 385 * Same but with be == true:
 386 *
 387 * {{ 76543210, }  ----- stripe (dir == false) -----> {{ 741gdaFC, }
 388 *  { hgfedcba, }                                      { 630fcHEB, }
 389 *  { HGFEDCBA, }} <---- upstripe (dir == true) -----  { 52hebGDA, }}
 390 */
 391
 392static inline void stripe8(uint8_t *x, int num, bool dir, bool be)
 393{
 394    uint8_t r[num];
 395    memset(r, 0, sizeof(uint8_t) * num);
 396    int idx[2] = {0, 0};
 397    int bit[2] = {0, be ? 7 : 0};
 398    int d = dir;
 399
 400    for (idx[0] = 0; idx[0] < num; ++idx[0]) {
 401        for (bit[0] = be ? 7 : 0; bit[0] != (be ? -1 : 8); bit[0] += be ? -1 : 1) {
 402            r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0;
 403            idx[1] = (idx[1] + 1) % num;
 404            if (!idx[1]) {
 405                bit[1] += be ? -1 : 1;
 406            }
 407        }
 408    }
 409    memcpy(x, r, sizeof(uint8_t) * num);
 410}
 411
 412static void xilinx_spips_flush_fifo_g(XilinxSPIPS *s)
 413{
 414    XilinxQSPIPS *qs = XILINX_QSPIPS(s);
 415    while (s->regs[R_GQSPI_DATA_STS] || !fifo_is_empty(&s->fifo_g)) {
 416        uint8_t tx_rx[2];
 417        int num_stripes;
 418        int i;
 419        uint8_t busses;
 420        uint8_t spi_mode = DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, SPI_MODE);
 421
 422        /* memset() get's optimised out and results in the kernel seeing bogus
 423         * data and complaining. So until memset_s() is supported let's just do
 424         * it like this.
 425         */
 426        memset(tx_rx, 0, sizeof(tx_rx));
 427        i = tx_rx[0];
 428        i += tx_rx[1];
 429
 430        if (!s->regs[R_GQSPI_DATA_STS]) {
 431            uint8_t imm;
 432
 433            s->regs[R_GQSPI_GF_SNAPSHOT] = fifo_pop32(&s->fifo_g);
 434            DB_PRINT_L(0, "Popped GQSPI command %" PRIx32 "\n",
 435                       s->regs[R_GQSPI_GF_SNAPSHOT]);
 436            if (!s->regs[R_GQSPI_GF_SNAPSHOT]) {
 437                DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing");
 438                continue;
 439            }
 440            xilinx_spips_update_cs_lines(s);
 441
 442            busses = DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
 443            if (qs->spi_mode != spi_mode) {
 444                qs->spi_mode = spi_mode;
 445                switch (busses) {
 446                case 0:
 447                    break;
 448                case 3:
 449                    ssi_set_datalines(s->spi[0], 1 << (qs->spi_mode - 1));
 450                    ssi_set_datalines(s->spi[1], 1 << (qs->spi_mode - 1));
 451                    break;
 452                default:
 453                    ssi_set_datalines(s->spi[busses - 1],
 454                                      1 << (qs->spi_mode - 1));
 455                }
 456            }
 457
 458            imm = DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA);
 459            if (!DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) {
 460                /* immedate transfer */
 461                if (DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) ||
 462                    DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) {
 463                    s->regs[R_GQSPI_DATA_STS] = 1;
 464                /* CS setup/hold - do nothing */
 465                } else {
 466                    s->regs[R_GQSPI_DATA_STS] = 0;
 467                }
 468            /* exponential transfer */
 469            } else if (DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) {
 470                if (imm > 31) {
 471                    qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too long"
 472                                  " - 2 ^ %" PRId8 " requested\n", imm);
 473                }
 474                s->regs[R_GQSPI_DATA_STS] = 1ul << imm;
 475            /* non-exponential data transfer */
 476            } else {
 477                s->regs[R_GQSPI_DATA_STS] = imm;
 478            }
 479            /* Dummy transfers are in terms of clocks rather than bytes */
 480            if (!DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) &&
 481                !DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) {
 482                s->regs[R_GQSPI_DATA_STS] *= 1 << (spi_mode - 1);
 483                s->regs[R_GQSPI_DATA_STS] /= 8;
 484            }
 485        }
 486
 487        /* Zero length transfer? no thanks! */
 488        if (!s->regs[R_GQSPI_DATA_STS]) {
 489            continue;
 490        }
 491
 492        if (DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) &&
 493            fifo_is_full(&s->rx_fifo_g)) {
 494            /* No space in RX fifo for transfer - try again later */
 495            return;
 496        }
 497
 498        num_stripes = DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) ? 2 : 1;
 499        if (!DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) &&
 500            !DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) {
 501            num_stripes = 1;
 502        }
 503
 504        if (!DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) {
 505            tx_rx[0] = DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA);
 506        } else if (DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) {
 507            for (i = 0; i < num_stripes; ++i) {
 508                if (!fifo_is_empty(&s->tx_fifo_g)) {
 509                    tx_rx[i] = fifo_pop8(&s->tx_fifo_g);
 510                    s->tx_fifo_g_align++;
 511                } else {
 512                    return;
 513                }
 514            }
 515        }
 516        if (num_stripes == 1) {
 517            /* mirror */
 518            for (i = 1; i < 2; ++i) {
 519                tx_rx[i] = tx_rx[0];
 520            }
 521        }
 522
 523        busses = DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
 524        for (i = 0; i < 2; ++i) {
 525            if (busses & (1 << i)) {
 526                DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]);
 527            }
 528            tx_rx[i] = ssi_transfer(s->spi[i], tx_rx[i]);
 529            if (busses & (1 << i)) {
 530                DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]);
 531            }
 532        }
 533
 534        switch (busses) {
 535        case 0x3:
 536            if (num_stripes == 2) {
 537                s->regs[R_GQSPI_DATA_STS]--;
 538            }
 539            /* fallthrough */
 540        default:
 541            if (s->regs[R_GQSPI_DATA_STS] != 0) {
 542                /* Don't let this wrap around */
 543                s->regs[R_GQSPI_DATA_STS]--;
 544            }
 545        }
 546
 547        if (DEP_AF_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) {
 548
 549            for (i = 0; i < 2; ++i) {
 550                if (busses & (1 << i)) {
 551                    DB_PRINT_L(1, "bus %d push_byte = %02x\n",
 552                               i, tx_rx[i]);
 553                   fifo_push8(&s->rx_fifo_g, tx_rx[i]);
 554                   s->rx_fifo_g_align++;
 555                }
 556            }
 557        }
 558
 559        if (!s->regs[R_GQSPI_DATA_STS]) {
 560            for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) {
 561                fifo_pop8(&s->tx_fifo_g);
 562            }
 563            for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) {
 564                fifo_push8(&s->rx_fifo_g, 0);
 565            }
 566        }
 567    }
 568}
 569
 570static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command)
 571{
 572    if (!qs) {
 573        /* The SPI device is not a QSPI device */
 574        return -1;
 575    }
 576
 577    switch (command) { /* check for dummies */
 578    case READ: /* no dummy bytes/cycles */
 579    case PP:
 580    case DPP:
 581    case QPP:
 582    case READ_4:
 583    case PP_4:
 584    case QPP_4:
 585        return 0;
 586    case FAST_READ: /* 1 dummy byte */
 587    case DOR:
 588    case QOR:
 589    case DOR_4:
 590    case QOR_4:
 591        return 1 * (1 << (qs->spi_mode - 1));
 592    case DIOR: /* FIXME: these vary between vendor - set to spansion */
 593    case FAST_READ_4:
 594    case DIOR_4:
 595        return 2 * (1 << (qs->spi_mode - 1));
 596    case QIOR: /* 2 Mode and 1 dummy byte */
 597    case QIOR_4:
 598        return 5 * (1 << (qs->spi_mode - 1));
 599    default:
 600        return -1;
 601    }
 602}
 603
 604static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
 605{
 606    int debug_level = 0;
 607    XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s),
 608                                                           TYPE_XILINX_QSPIPS);
 609
 610    for (;;) {
 611        int i;
 612        uint8_t tx = 0;
 613        uint8_t tx_rx[num_effective_busses(s)];
 614        int num_dummies;
 615
 616        if (fifo_is_empty(&s->tx_fifo)) {
 617            xilinx_spips_update_ixr(s);
 618            return;
 619        } else if (s->snoop_state == SNOOP_STRIPING) {
 620            tx_rx[0] = fifo_pop8(&s->tx_fifo);
 621            stripe8(tx_rx, num_effective_busses(s), false, true);
 622        } else {
 623            tx = fifo_pop8(&s->tx_fifo);
 624            for (i = 0; i < num_effective_busses(s); ++i) {
 625                tx_rx[i] = tx;
 626            }
 627        }
 628
 629        for (i = 0; i < num_effective_busses(s); ++i) {
 630            int len = s->snoop_state == SNOOP_STRIPING ? 4 : 8;
 631
 632            if (s->snoop_state == SNOOP_STRIPING) {
 633                len = 8 / num_effective_busses(s);
 634                tx_rx[i] >>= 8 - len;
 635            }
 636            DB_PRINT_L(debug_level, "tx = %02x (len = %d)\n", tx_rx[i], len);
 637            tx_rx[i] = ssi_transfer_bits(s->spi[num_effective_busses(s) - 1 - i],
 638                                         (uint32_t)tx_rx[i], len);
 639            DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]);
 640            if (s->snoop_state == SNOOP_STRIPING) {
 641                tx_rx[i] <<= 8 - len;
 642            }
 643        }
 644
 645        if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) {
 646            DB_PRINT_L(debug_level, "dircarding drained rx byte\n");
 647            /* Do nothing */
 648        } else if (s->rx_discard) {
 649            DB_PRINT_L(debug_level, "dircarding discarded rx byte\n");
 650            s->rx_discard -= 8 / s->link_state;
 651        } else if (fifo_is_full(&s->rx_fifo)) {
 652            s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
 653            DB_PRINT_L(0, "rx FIFO overflow");
 654        } else if (s->snoop_state == SNOOP_STRIPING) {
 655            stripe8(tx_rx, num_effective_busses(s), true, true);
 656            fifo_push8(&s->rx_fifo, (uint8_t)tx_rx[0]);
 657            DB_PRINT_L(debug_level, "pushing striped rx byte\n");
 658        } else {
 659           DB_PRINT_L(debug_level, "pushing unstriped rx byte\n");
 660           fifo_push8(&s->rx_fifo, (uint8_t)tx_rx[0]);
 661        }
 662
 663        if (s->link_state_next_when) {
 664            s->link_state_next_when--;
 665            if (!s->link_state_next_when) {
 666                s->link_state = s->link_state_next;
 667            }
 668        }
 669
 670        DB_PRINT_L(debug_level, "initial snoop state: %x\n",
 671                   (unsigned)s->snoop_state);
 672        switch (s->snoop_state) {
 673        case (SNOOP_CHECKING):
 674            /* assume 3 address bytes */
 675            s->snoop_state =  3;
 676            switch (tx) { /* new instruction code */
 677            case READ: /* 3 address bytes, no dummy bytes/cycles */
 678            case PP:
 679            case DPP:
 680            case QPP:
 681            case FAST_READ:
 682            case DOR:
 683            case QOR:
 684            case DIOR:
 685            case QIOR:
 686                s->snoop_state += !!(s->regs[R_CMND] & R_CMND_EXT_ADD);
 687                break;
 688            case READ_4:
 689            case PP_4:
 690            case QPP_4:
 691            case FAST_READ_4:
 692            case DOR_4:
 693            case QOR_4:
 694            case DIOR_4:
 695                s->snoop_state++;
 696                break;
 697            }
 698            num_dummies = xilinx_spips_num_dummies(q, tx);
 699            if (num_dummies == -1) {
 700                s->snoop_state = SNOOP_NONE;
 701            } else {
 702                s->snoop_state += num_dummies;
 703            }
 704            switch (tx) {
 705            case DPP:
 706            case DOR:
 707            case DOR_4:
 708                s->link_state_next = 2;
 709                s->link_state_next_when = s->snoop_state;
 710                break;
 711            case QPP:
 712            case QPP_4:
 713            case QOR:
 714            case QOR_4:
 715                s->link_state_next = 4;
 716                s->link_state_next_when = s->snoop_state;
 717                break;
 718            case DIOR:
 719            case DIOR_4:
 720                s->link_state = 2;
 721                break;
 722            case QIOR:
 723            case QIOR_4:
 724                s->link_state = 4;
 725                break;
 726            }
 727            break;
 728        case (SNOOP_STRIPING):
 729        case (SNOOP_NONE):
 730            /* Once we hit the boring stuff - squelch debug noise */
 731            if (!debug_level) {
 732                DB_PRINT_L(0, "squelching debug info ....\n");
 733                debug_level = 1;
 734            }
 735            break;
 736        default:
 737            s->snoop_state--;
 738        }
 739        DB_PRINT_L(debug_level, "final snoop state: %x\n",
 740                   (unsigned)s->snoop_state);
 741    }
 742}
 743
 744static inline void tx_data_bytes(Fifo *fifo, uint32_t value, int num, bool be)
 745{
 746    int i;
 747    for (i = 0; i < num && !fifo_is_full(fifo); ++i) {
 748        if (be) {
 749            fifo_push8(fifo, (uint8_t)(value >> 24));
 750            value <<= 8;
 751        } else {
 752            fifo_push8(fifo, (uint8_t)value);
 753            value >>= 8;
 754        }
 755    }
 756}
 757
 758static void xilinx_spips_check_zero_pump(XilinxSPIPS *s)
 759{
 760    if (!s->regs[R_TRANSFER_SIZE]) {
 761        return;
 762    }
 763
 764    if (!fifo_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) {
 765        return;
 766    }
 767
 768    /*
 769     * The zero pump must never fill tx fifo such that rx overflow is
 770     * possible
 771     */
 772    while (s->regs[R_TRANSFER_SIZE] &&
 773           s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) {
 774        /* endianess just doesn't matter when zero pumping */
 775        tx_data_bytes(&s->tx_fifo, 0, 4, false);
 776        s->regs[R_TRANSFER_SIZE] &= ~0x03ull;
 777        s->regs[R_TRANSFER_SIZE] -= 4;
 778    }
 779}
 780
 781static void xilinx_spips_check_flush(XilinxSPIPS *s)
 782{
 783    bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] ||
 784                          !fifo_is_empty(&s->fifo_g);
 785
 786    if (DEP_AF_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) {
 787        if (s->man_start_com_g ||
 788            (gqspi_has_work &&
 789             !DEP_AF_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) {
 790            xilinx_spips_flush_fifo_g(s);
 791        }
 792    } else {
 793        if (s->man_start_com ||
 794            (!fifo_is_empty(&s->tx_fifo) &&
 795             !(s->regs[R_CONFIG] & MAN_START_EN))) {
 796            xilinx_spips_check_zero_pump(s);
 797            xilinx_spips_flush_txfifo(s);
 798        }
 799    }
 800
 801    if (fifo_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) {
 802        s->man_start_com = false;
 803    }
 804
 805    if (!gqspi_has_work) {
 806        s->man_start_com_g = false;
 807    }
 808    xilinx_spips_update_ixr(s);
 809}
 810
 811static inline int rx_data_bytes(XilinxSPIPS *s, uint8_t *value, int max)
 812{
 813    int i;
 814
 815    for (i = 0; i < max && !fifo_is_empty(&s->rx_fifo); ++i) {
 816        value[i] = fifo_pop8(&s->rx_fifo);
 817    }
 818
 819    return max - i;
 820}
 821
 822static void zynqmp_qspips_notify(void *opaque)
 823{
 824    ZynqMPQSPIPS *rq = ZYNQMP_QSPIPS(opaque);
 825    XilinxSPIPS *s = XILINX_SPIPS(rq);
 826    Fifo *recv_fifo;
 827
 828    if (DEP_AF_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) {
 829        if (!(DEP_AF_EX32(s->regs, GQSPI_CNFG, MODE_EN) == 2)) {
 830            return;
 831        }
 832        recv_fifo = &s->rx_fifo_g;
 833    } else {
 834        if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) {
 835            return;
 836        }
 837        recv_fifo = &s->rx_fifo;
 838    }
 839
 840    while (/* FIXME: impelement byte granularity */
 841           recv_fifo->num >= 4 /* FIXME: APIify */
 842           && stream_can_push(rq->dma, zynqmp_qspips_notify, rq))
 843    {
 844        size_t ret;
 845        uint32_t num;
 846        const void *rxd = fifo_pop_buf(recv_fifo, 4, &num);
 847
 848        memcpy(rq->dma_buf, rxd, num);
 849
 850        ret = stream_push(rq->dma, rq->dma_buf, 4, 0);
 851        assert(ret == 4); /* FIXME - implement short return */
 852        xilinx_spips_check_flush(s);
 853    }
 854}
 855
 856static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
 857                                                        unsigned size)
 858{
 859    XilinxSPIPS *s = opaque;
 860    uint32_t mask = ~0;
 861    uint32_t ret;
 862    uint8_t rx_buf[4];
 863    int shortfall;
 864    const void *rxd;
 865    uint32_t rx_num;
 866
 867    memset(rx_buf, 0, sizeof(rx_buf));
 868
 869    addr >>= 2;
 870    switch (addr) {
 871    case R_CONFIG:
 872        mask = ~(R_CONFIG_RSVD | MAN_START_COM);
 873        break;
 874    case R_INTR_STATUS:
 875        ret = s->regs[addr] & IXR_ALL;
 876        s->regs[addr] = 0;
 877        DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
 878        xilinx_spips_update_ixr(s);
 879        return ret;
 880    case R_INTR_MASK:
 881        mask = IXR_ALL;
 882        break;
 883    case  R_EN:
 884        mask = 0x1;
 885        break;
 886    case R_SLAVE_IDLE_COUNT:
 887        mask = 0xFF;
 888        break;
 889    case R_MOD_ID:
 890        mask = 0x01FFFFFF;
 891        break;
 892    case R_INTR_EN:
 893    case R_INTR_DIS:
 894    case R_TX_DATA:
 895        mask = 0;
 896        break;
 897    case R_RX_DATA:
 898        memset(rx_buf, 0, sizeof(rx_buf));
 899        shortfall = rx_data_bytes(s, rx_buf, s->num_txrx_bytes);
 900        ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ? cpu_to_be32(*(uint32_t *)rx_buf)
 901                        : cpu_to_le32(*(uint32_t *)rx_buf);
 902        if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) {
 903            ret <<= 8 * shortfall;
 904        }
 905        DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
 906        xilinx_spips_check_flush(s);
 907        xilinx_spips_update_ixr(s);
 908        return ret;
 909    case R_GQSPI_RXD:
 910        if (fifo_is_empty(&s->rx_fifo_g)) {
 911            qemu_log_mask(LOG_GUEST_ERROR, "Read from empty GQSPI RX FIFO\n");
 912            return 0;
 913        }
 914        rxd = fifo_pop_buf(&s->rx_fifo_g, 4, &rx_num);
 915        assert(!(rx_num % 4));
 916        memcpy(rx_buf, rxd, rx_num);
 917        ret = DEP_AF_EX32(s->regs, GQSPI_CNFG, ENDIAN) ?
 918              cpu_to_be32(*(uint32_t *)rx_buf) :
 919              cpu_to_le32(*(uint32_t *)rx_buf);
 920        xilinx_spips_check_flush(s);
 921        xilinx_spips_update_ixr(s);
 922        return ret;
 923    }
 924    DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4,
 925               s->regs[addr] & mask);
 926    return s->regs[addr] & mask;
 927
 928}
 929
 930static void xilinx_spips_write(void *opaque, hwaddr addr,
 931                                        uint64_t value, unsigned size)
 932{
 933    int mask = ~0;
 934    int tx_btt = 0;
 935    XilinxSPIPS *s = opaque;
 936
 937    DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
 938    addr >>= 2;
 939    switch (addr) {
 940    case R_CONFIG:
 941        mask = ~(R_CONFIG_RSVD | MAN_START_COM);
 942        if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) {
 943            s->man_start_com = true;
 944        }
 945        break;
 946    case R_INTR_STATUS:
 947        mask = IXR_ALL;
 948        s->regs[R_INTR_STATUS] &= ~(mask & value);
 949        goto no_reg_update;
 950    case R_INTR_DIS:
 951        mask = IXR_ALL;
 952        s->regs[R_INTR_MASK] &= ~(mask & value);
 953        goto no_reg_update;
 954    case R_INTR_EN:
 955        mask = IXR_ALL;
 956        s->regs[R_INTR_MASK] |= mask & value;
 957        goto no_reg_update;
 958    case R_EN:
 959        mask = 0x1;
 960        break;
 961    case R_SLAVE_IDLE_COUNT:
 962        mask = 0xFF;
 963        break;
 964    case R_RX_DATA:
 965    case R_INTR_MASK:
 966    case R_MOD_ID:
 967        mask = 0;
 968        break;
 969    case R_TX_DATA:
 970        tx_btt = s->num_txrx_bytes;
 971        tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes,
 972                      s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
 973        goto no_reg_update;
 974    case R_TXD3:
 975        tx_btt++;
 976    case R_TXD2:
 977        tx_btt++;
 978    case R_TXD1:
 979        tx_btt++;
 980        tx_data_bytes(&s->tx_fifo, (uint32_t)value, tx_btt,
 981                      s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
 982        goto no_reg_update;
 983    case R_GQSPI_CNFG:
 984        mask = ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK);
 985        if (DEP_F_EX32(value, GQSPI_CNFG, GEN_FIFO_START) &&
 986            DEP_AF_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) {
 987            s->man_start_com_g = true;
 988        }
 989        break;
 990    case R_GQSPI_GEN_FIFO:
 991        if (!fifo_is_full(&s->fifo_g)) {
 992            fifo_push32(&s->fifo_g, value);
 993        }
 994        goto no_reg_update;
 995    case R_GQSPI_TXD:
 996        tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4,
 997                      DEP_AF_EX32(s->regs, GQSPI_CNFG, ENDIAN));
 998        goto no_reg_update;
 999    case R_GQSPI_FIFO_CTRL:
1000        mask = 0;
1001        if (DEP_F_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) {
1002           fifo_reset(&s->fifo_g);
1003        }
1004        if (DEP_F_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) {
1005           fifo_reset(&s->tx_fifo_g);
1006        }
1007        if (DEP_F_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) {
1008           fifo_reset(&s->rx_fifo_g);
1009        }
1010        break;
1011    case R_GQSPI_IDR:
1012        s->regs[R_GQSPI_IMR] |= value;
1013        goto no_reg_update;
1014    case R_GQSPI_IER:
1015        s->regs[R_GQSPI_IMR] &= ~value;
1016        goto no_reg_update;
1017    case R_GQSPI_ISR:
1018        s->regs[R_GQSPI_ISR] &= ~value;
1019        goto no_reg_update;
1020    case R_GQSPI_IMR:
1021    case R_GQSPI_RXD:
1022    case R_GQSPI_GF_SNAPSHOT:
1023    case R_GQSPI_MOD_ID:
1024        mask = 0;
1025        break;
1026    }
1027    s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
1028no_reg_update:
1029    xilinx_spips_update_cs_lines(s);
1030    xilinx_spips_check_flush(s);
1031    xilinx_spips_update_cs_lines(s);
1032    xilinx_spips_update_ixr(s);
1033}
1034
1035static const MemoryRegionOps spips_ops = {
1036    .read = xilinx_spips_read,
1037    .write = xilinx_spips_write,
1038    .endianness = DEVICE_LITTLE_ENDIAN,
1039};
1040
1041static void xilinx_qspips_write(void *opaque, hwaddr addr,
1042                                uint64_t value, unsigned size)
1043{
1044    XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
1045    XilinxSPIPS *s = XILINX_SPIPS(opaque);
1046
1047    uint32_t lqspi_cfg_old = s->regs[R_LQSPI_CFG];
1048
1049    xilinx_spips_write(opaque, addr, value, size);
1050    addr >>= 2;
1051
1052    if (addr == R_LQSPI_CFG &&
1053               ((lqspi_cfg_old ^ value) & ~LQSPI_CFG_U_PAGE)) {
1054        q->lqspi_cached_addr = ~0ULL;
1055        if (q->lqspi_size) {
1056#define LQSPI_HACK_CHUNK_SIZE (1 * 1024 * 1024)
1057            uint32_t src = q->lqspi_src;
1058            uint32_t dst = q->lqspi_dst;
1059            uint32_t btt = q->lqspi_size;
1060
1061            assert(!(btt % LQSPI_HACK_CHUNK_SIZE));
1062            fprintf(stderr, "QEMU: Syncing LQSPI - this may be slow "
1063                    "(1 \".\" / MByte):");
1064
1065            while (btt) {
1066                uint8_t lqspi_hack_buf[LQSPI_HACK_CHUNK_SIZE];
1067                dma_memory_read(q->hack_as, src, lqspi_hack_buf,
1068                                LQSPI_HACK_CHUNK_SIZE);
1069                dma_memory_write(q->hack_as, dst, lqspi_hack_buf,
1070                                 LQSPI_HACK_CHUNK_SIZE);
1071                fprintf(stderr, ".");
1072                btt -= LQSPI_HACK_CHUNK_SIZE;
1073                src += LQSPI_HACK_CHUNK_SIZE;
1074                dst += LQSPI_HACK_CHUNK_SIZE;
1075            }
1076            fprintf(stderr, "\n");
1077        }
1078    }
1079    if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) {
1080        fifo_reset(&s->rx_fifo);
1081    }
1082    if (object_dynamic_cast(OBJECT(s), TYPE_ZYNQMP_QSPIPS)) {
1083        zynqmp_qspips_notify(s);
1084    }
1085}
1086
1087static const MemoryRegionOps qspips_ops = {
1088    .read = xilinx_spips_read,
1089    .write = xilinx_qspips_write,
1090    .endianness = DEVICE_LITTLE_ENDIAN,
1091};
1092
1093static uint64_t
1094lqspi_read(void *opaque, hwaddr addr, unsigned int size)
1095{
1096    int i;
1097    XilinxQSPIPS *q = opaque;
1098    XilinxSPIPS *s = opaque;
1099    uint32_t ret;
1100    int addr_width;
1101    uint8_t inst_code;
1102
1103    addr_width = (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4 ? 27 : 24) +
1104                 (num_effective_busses(s) == 2 ? 1 : 0);
1105    addr &= (1ull << addr_width) - 1;
1106
1107    if (addr >= q->lqspi_cached_addr &&
1108            addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
1109        uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr];
1110        ret = cpu_to_le32(*(uint32_t *)retp);
1111        DB_PRINT_L(1, "addr: %08x, data: %08x\n", (unsigned)addr,
1112                   (unsigned)ret);
1113        return ret;
1114    } else {
1115        int flash_addr = (addr / num_effective_busses(s));
1116        int slave = flash_addr >> LQSPI_ADDRESS_BITS;
1117        int cache_entry = 0;
1118        uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE;
1119
1120        s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
1121        s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0;
1122
1123        DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
1124
1125        fifo_reset(&s->tx_fifo);
1126        fifo_reset(&s->rx_fifo);
1127
1128        /* instruction */
1129        DB_PRINT_L(0, "pushing read instruction: %02x\n",
1130                   (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] &
1131                                       LQSPI_CFG_INST_CODE));
1132        inst_code = s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE;
1133        fifo_push8(&s->tx_fifo, inst_code);
1134        /* read address */
1135        DB_PRINT_L(0, "pushing read address %06x\n", flash_addr);
1136        if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) {
1137            fifo_push8(&s->tx_fifo, (uint8_t)(flash_addr >> 24));
1138        }
1139        fifo_push8(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
1140        fifo_push8(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
1141        fifo_push8(&s->tx_fifo, (uint8_t)flash_addr);
1142        /* mode bits */
1143        i = 0;
1144        if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
1145            i++;
1146            fifo_push8(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
1147                                              LQSPI_CFG_MODE_SHIFT,
1148                                              LQSPI_CFG_MODE_WIDTH));
1149        }
1150        /* dummy bytes */
1151        for (; i < xilinx_spips_num_dummies(q, inst_code); ++i) {
1152            DB_PRINT_L(0, "pushing dummy byte\n");
1153            fifo_push8(&s->tx_fifo, 0);
1154        }
1155        xilinx_spips_update_cs_lines(s);
1156        xilinx_spips_flush_txfifo(s);
1157        fifo_reset(&s->rx_fifo);
1158
1159        DB_PRINT_L(0, "starting QSPI data read\n");
1160
1161        while (cache_entry < LQSPI_CACHE_SIZE) {
1162            for (i = 0; i < 64; ++i) {
1163                tx_data_bytes(&s->tx_fifo, 0, 1, false);
1164            }
1165            xilinx_spips_flush_txfifo(s);
1166            for (i = 0; i < 64; ++i) {
1167                q->lqspi_buf[cache_entry++] = fifo_pop8(&s->rx_fifo);
1168            }
1169        }
1170
1171        s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
1172        s->regs[R_LQSPI_STS] |= u_page_save;
1173        xilinx_spips_update_cs_lines(s);
1174
1175        q->lqspi_cached_addr = flash_addr * num_effective_busses(s);
1176        return lqspi_read(opaque, addr, size);
1177    }
1178}
1179
1180static void lqspi_write(void *opaque, hwaddr addr,
1181                        uint64_t value, unsigned size)
1182{
1183    qemu_log_mask(LOG_GUEST_ERROR, "Write to QSPI Linear region\n");
1184}
1185
1186static const MemoryRegionOps lqspi_ops = {
1187    .read = lqspi_read,
1188    .write = lqspi_write,
1189    .endianness = DEVICE_NATIVE_ENDIAN,
1190    .valid = {
1191        .min_access_size = 1,
1192        .max_access_size = 4
1193    }
1194};
1195
1196static void xilinx_spips_realize(DeviceState *dev, Error **errp)
1197{
1198    XilinxSPIPS *s = XILINX_SPIPS(dev);
1199    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1200    XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
1201    qemu_irq *cs;
1202    int i;
1203
1204    DB_PRINT_L(0, "realized spips\n");
1205
1206    s->spi = g_new(SSIBus *, s->num_busses);
1207    for (i = 0; i < s->num_busses; ++i) {
1208        char bus_name[16];
1209        snprintf(bus_name, 16, "spi%d", i);
1210        s->spi[i] = ssi_create_bus(dev, bus_name);
1211    }
1212
1213    s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
1214    s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses);
1215    for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) {
1216        ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]);
1217    }
1218
1219    sysbus_init_irq(sbd, &s->irq);
1220    qdev_init_gpio_out(dev, s->cs_lines, s->num_cs * s->num_busses);
1221
1222    memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s,
1223                          "spi", XLNX_SPIPS_R_MAX * 4);
1224    sysbus_init_mmio(sbd, &s->iomem);
1225
1226    s->irqline = -1;
1227
1228    fifo_create8(&s->rx_fifo, xsc->rx_fifo_size);
1229    fifo_create8(&s->tx_fifo, xsc->tx_fifo_size);
1230    /* FIXME: Move to zynqmp specific state */
1231    fifo_create8(&s->rx_fifo_g, xsc->rx_fifo_size);
1232    fifo_create8(&s->tx_fifo_g, xsc->tx_fifo_size);
1233    fifo_create32(&s->fifo_g, 32);
1234}
1235
1236static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
1237{
1238    XilinxSPIPS *s = XILINX_SPIPS(dev);
1239    XilinxQSPIPS *q = XILINX_QSPIPS(dev);
1240    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1241
1242    DB_PRINT_L(0, "realized qspips\n");
1243
1244    s->num_busses = 2;
1245    s->num_cs = 2;
1246    s->num_txrx_bytes = 4;
1247
1248    xilinx_spips_realize(dev, errp);
1249    q->hack_as = q->hack_dma ? address_space_init_shareable(q->hack_dma,
1250                NULL) : &address_space_memory;
1251    memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi",
1252                          (1 << LQSPI_ADDRESS_BITS) * 2);
1253    sysbus_init_mmio(sbd, &s->mmlqspi);
1254
1255    q->lqspi_cached_addr = ~0ULL;
1256}
1257
1258static void zynqmp_qspips_init(Object *obj)
1259{
1260    ZynqMPQSPIPS *rq = ZYNQMP_QSPIPS(obj);
1261
1262    object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE,
1263                             (Object **)&rq->dma,
1264                             object_property_allow_set_link,
1265                             OBJ_PROP_LINK_UNREF_ON_RELEASE,
1266                             NULL);
1267}
1268
1269static int xilinx_spips_post_load(void *opaque, int version_id)
1270{
1271    xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
1272    xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
1273    return 0;
1274}
1275
1276static const VMStateDescription vmstate_xilinx_spips = {
1277    .name = "xilinx_spips",
1278    .version_id = 2,
1279    .minimum_version_id = 2,
1280    .post_load = xilinx_spips_post_load,
1281    .fields = (VMStateField[]) {
1282        VMSTATE_FIFO(tx_fifo, XilinxSPIPS),
1283        VMSTATE_FIFO(rx_fifo, XilinxSPIPS),
1284        VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX),
1285        VMSTATE_UINT8(snoop_state, XilinxSPIPS),
1286        VMSTATE_END_OF_LIST()
1287    }
1288};
1289
1290static Property xilinx_spips_properties[] = {
1291    DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
1292    DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
1293    DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
1294    DEFINE_PROP_END_OF_LIST(),
1295};
1296
1297static Property xilinx_qspips_properties[] = {
1298    DEFINE_PROP_UINT32("lqspi-size", XilinxQSPIPS, lqspi_size, 0),
1299    DEFINE_PROP_UINT32("lqspi-src", XilinxQSPIPS, lqspi_src, 0),
1300    DEFINE_PROP_UINT32("lqspi-dst", XilinxQSPIPS, lqspi_dst, 0),
1301    DEFINE_PROP_END_OF_LIST(),
1302};
1303
1304static void xilinx_qspips_init(Object *obj)
1305{
1306    XilinxQSPIPS *q = XILINX_QSPIPS(obj);
1307
1308    object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
1309                             (Object **) &q->hack_dma,
1310                             qdev_prop_allow_set_link_before_realize,
1311                             OBJ_PROP_LINK_UNREF_ON_RELEASE,
1312                             &error_abort);
1313}
1314
1315static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
1316{
1317    DeviceClass *dc = DEVICE_CLASS(klass);
1318    XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
1319
1320    dc->realize = xilinx_qspips_realize;
1321    dc->props = xilinx_qspips_properties;
1322    xsc->reg_ops = &qspips_ops;
1323    xsc->rx_fifo_size = RXFF_A_Q;
1324    xsc->tx_fifo_size = TXFF_A_Q;
1325}
1326
1327static void xilinx_spips_class_init(ObjectClass *klass, void *data)
1328{
1329    DeviceClass *dc = DEVICE_CLASS(klass);
1330    XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
1331
1332    dc->realize = xilinx_spips_realize;
1333    dc->reset = xilinx_spips_reset;
1334    dc->props = xilinx_spips_properties;
1335    dc->vmsd = &vmstate_xilinx_spips;
1336
1337    xsc->reg_ops = &spips_ops;
1338    xsc->rx_fifo_size = RXFF_A;
1339    xsc->tx_fifo_size = TXFF_A;
1340}
1341
1342static const TypeInfo xilinx_spips_info = {
1343    .name  = TYPE_XILINX_SPIPS,
1344    .parent = TYPE_SYS_BUS_DEVICE,
1345    .instance_size  = sizeof(XilinxSPIPS),
1346    .class_init = xilinx_spips_class_init,
1347    .class_size = sizeof(XilinxSPIPSClass),
1348};
1349
1350static const TypeInfo xilinx_qspips_info = {
1351    .name  = TYPE_XILINX_QSPIPS,
1352    .parent = TYPE_XILINX_SPIPS,
1353    .instance_size  = sizeof(XilinxQSPIPS),
1354    .class_init = xilinx_qspips_class_init,
1355    .instance_init = xilinx_qspips_init,
1356};
1357
1358static const TypeInfo zynqmp_qspips_info = {
1359    .name  = TYPE_ZYNQMP_QSPIPS,
1360    .parent = TYPE_XILINX_QSPIPS,
1361    .instance_size  = sizeof(ZynqMPQSPIPS),
1362    .instance_init = zynqmp_qspips_init,
1363};
1364
1365static void xilinx_spips_register_types(void)
1366{
1367    type_register_static(&xilinx_spips_info);
1368    type_register_static(&xilinx_qspips_info);
1369    type_register_static(&zynqmp_qspips_info);
1370}
1371
1372type_init(xilinx_spips_register_types)
1373