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25#ifndef TARGET_ARM_INTERNALS_H
26#define TARGET_ARM_INTERNALS_H
27
28
29#define BANK_USRSYS 0
30#define BANK_SVC 1
31#define BANK_ABT 2
32#define BANK_UND 3
33#define BANK_IRQ 4
34#define BANK_FIQ 5
35#define BANK_HYP 6
36#define BANK_MON 7
37
38static inline bool excp_is_internal(int excp)
39{
40
41
42
43 return excp == EXCP_INTERRUPT
44 || excp == EXCP_HLT
45 || excp == EXCP_DEBUG
46 || excp == EXCP_HALTED
47 || excp == EXCP_EXCEPTION_EXIT
48 || excp == EXCP_KERNEL_TRAP
49 || excp == EXCP_SEMIHOST;
50}
51
52
53
54
55static const char * const excnames[] = {
56 [EXCP_UDEF] = "Undefined Instruction",
57 [EXCP_SWI] = "SVC",
58 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
59 [EXCP_DATA_ABORT] = "Data Abort",
60 [EXCP_IRQ] = "IRQ",
61 [EXCP_FIQ] = "FIQ",
62 [EXCP_BKPT] = "Breakpoint",
63 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
64 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
65 [EXCP_HVC] = "Hypervisor Call",
66 [EXCP_HYP_TRAP] = "Hypervisor Trap",
67 [EXCP_SMC] = "Secure Monitor Call",
68 [EXCP_VIRQ] = "Virtual IRQ",
69 [EXCP_VFIQ] = "Virtual FIQ",
70 [EXCP_SEMIHOST] = "Semihosting call",
71 [EXCP_WFI] = "WFI",
72};
73
74
75
76
77#define GTIMER_SCALE 16
78
79
80
81
82
83
84
85static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
86{
87 static const unsigned int map[4] = {
88 [1] = BANK_SVC,
89 [2] = BANK_HYP,
90 [3] = BANK_MON,
91 };
92 assert(el >= 1 && el <= 3);
93 return map[el];
94}
95
96
97static inline int bank_number(int mode)
98{
99 switch (mode) {
100 case ARM_CPU_MODE_USR:
101 case ARM_CPU_MODE_SYS:
102 return BANK_USRSYS;
103 case ARM_CPU_MODE_SVC:
104 return BANK_SVC;
105 case ARM_CPU_MODE_ABT:
106 return BANK_ABT;
107 case ARM_CPU_MODE_UND:
108 return BANK_UND;
109 case ARM_CPU_MODE_IRQ:
110 return BANK_IRQ;
111 case ARM_CPU_MODE_FIQ:
112 return BANK_FIQ;
113 case ARM_CPU_MODE_HYP:
114 return BANK_HYP;
115 case ARM_CPU_MODE_MON:
116 return BANK_MON;
117 }
118 g_assert_not_reached();
119}
120
121void switch_mode(CPUARMState *, int);
122void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
123void arm_translate_init(void);
124
125enum arm_fprounding {
126 FPROUNDING_TIEEVEN,
127 FPROUNDING_POSINF,
128 FPROUNDING_NEGINF,
129 FPROUNDING_ZERO,
130 FPROUNDING_TIEAWAY,
131 FPROUNDING_ODD
132};
133
134int arm_rmode_to_sf(int rmode);
135
136static inline void aarch64_save_sp(CPUARMState *env, int el)
137{
138 if (env->pstate & PSTATE_SP) {
139 env->sp_el[el] = env->xregs[31];
140 } else {
141 env->sp_el[0] = env->xregs[31];
142 }
143}
144
145static inline void aarch64_restore_sp(CPUARMState *env, int el)
146{
147 if (env->pstate & PSTATE_SP) {
148 env->xregs[31] = env->sp_el[el];
149 } else {
150 env->xregs[31] = env->sp_el[0];
151 }
152}
153
154static inline void update_spsel(CPUARMState *env, uint32_t imm)
155{
156 unsigned int cur_el = arm_current_el(env);
157
158
159
160 if (!((imm ^ env->pstate) & PSTATE_SP)) {
161 return;
162 }
163 aarch64_save_sp(env, cur_el);
164 env->pstate = deposit32(env->pstate, 0, 1, imm);
165
166
167
168
169 assert(cur_el >= 1 && cur_el <= 3);
170 aarch64_restore_sp(env, cur_el);
171}
172
173
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176
177
178
179
180static inline unsigned int arm_pamax(ARMCPU *cpu)
181{
182 static const unsigned int pamax_map[] = {
183 [0] = 32,
184 [1] = 36,
185 [2] = 40,
186 [3] = 42,
187 [4] = 44,
188 [5] = 48,
189 };
190 unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);
191
192
193
194 assert(parange < ARRAY_SIZE(pamax_map));
195 return pamax_map[parange];
196}
197
198
199
200
201
202static inline bool extended_addresses_enabled_el(CPUARMState *env,
203 unsigned int el,
204 TCR *tcr)
205{
206 return arm_el_is_aa64(env, el) ||
207 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
208}
209
210static inline bool extended_addresses_enabled(CPUARMState *env)
211{
212 unsigned int cur_el = arm_current_el(env);
213 TCR *tcr;
214
215 if (cur_el == 0) {
216
217 cur_el = 1;
218 }
219
220 tcr = &env->cp15.tcr_el[cur_el];
221 return extended_addresses_enabled_el(env, cur_el, tcr);
222}
223
224
225enum arm_exception_class {
226 EC_UNCATEGORIZED = 0x00,
227 EC_WFX_TRAP = 0x01,
228 EC_CP15RTTRAP = 0x03,
229 EC_CP15RRTTRAP = 0x04,
230 EC_CP14RTTRAP = 0x05,
231 EC_CP14DTTRAP = 0x06,
232 EC_ADVSIMDFPACCESSTRAP = 0x07,
233 EC_FPIDTRAP = 0x08,
234 EC_CP14RRTTRAP = 0x0c,
235 EC_ILLEGALSTATE = 0x0e,
236 EC_AA32_SVC = 0x11,
237 EC_AA32_HVC = 0x12,
238 EC_AA32_SMC = 0x13,
239 EC_AA64_SVC = 0x15,
240 EC_AA64_HVC = 0x16,
241 EC_AA64_SMC = 0x17,
242 EC_SYSTEMREGISTERTRAP = 0x18,
243 EC_INSNABORT = 0x20,
244 EC_INSNABORT_SAME_EL = 0x21,
245 EC_PCALIGNMENT = 0x22,
246 EC_DATAABORT = 0x24,
247 EC_DATAABORT_SAME_EL = 0x25,
248 EC_SPALIGNMENT = 0x26,
249 EC_AA32_FPTRAP = 0x28,
250 EC_AA64_FPTRAP = 0x2c,
251 EC_SERROR = 0x2f,
252 EC_BREAKPOINT = 0x30,
253 EC_BREAKPOINT_SAME_EL = 0x31,
254 EC_SOFTWARESTEP = 0x32,
255 EC_SOFTWARESTEP_SAME_EL = 0x33,
256 EC_WATCHPOINT = 0x34,
257 EC_WATCHPOINT_SAME_EL = 0x35,
258 EC_AA32_BKPT = 0x38,
259 EC_VECTORCATCH = 0x3a,
260 EC_AA64_BKPT = 0x3c,
261};
262
263#define ARM_EL_EC_SHIFT 26
264#define ARM_EL_IL_SHIFT 25
265#define ARM_EL_ISV_SHIFT 24
266#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
267#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
268
269
270
271
272
273
274
275
276
277
278static inline uint32_t syn_uncategorized(void)
279{
280 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
281}
282
283static inline uint32_t syn_aa64_svc(uint32_t imm16)
284{
285 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
286}
287
288static inline uint32_t syn_aa64_hvc(uint32_t imm16)
289{
290 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
291}
292
293static inline uint32_t syn_aa64_smc(uint32_t imm16)
294{
295 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
296}
297
298static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
299{
300 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
301 | (is_16bit ? 0 : ARM_EL_IL);
302}
303
304static inline uint32_t syn_aa32_hvc(uint32_t imm16)
305{
306 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
307}
308
309static inline uint32_t syn_aa32_smc(void)
310{
311 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
312}
313
314static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
315{
316 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
317}
318
319static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
320{
321 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
322 | (is_16bit ? 0 : ARM_EL_IL);
323}
324
325static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
326 int crn, int crm, int rt,
327 int isread)
328{
329 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
330 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
331 | (crm << 1) | isread;
332}
333
334static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
335 int crn, int crm, int rt, int isread,
336 bool is_16bit)
337{
338 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
339 | (is_16bit ? 0 : ARM_EL_IL)
340 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
341 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
342}
343
344static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
345 int crn, int crm, int rt, int isread,
346 bool is_16bit)
347{
348 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
349 | (is_16bit ? 0 : ARM_EL_IL)
350 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
351 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
352}
353
354static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
355 int rt, int rt2, int isread,
356 bool is_16bit)
357{
358 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
359 | (is_16bit ? 0 : ARM_EL_IL)
360 | (cv << 24) | (cond << 20) | (opc1 << 16)
361 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
362}
363
364static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
365 int rt, int rt2, int isread,
366 bool is_16bit)
367{
368 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
369 | (is_16bit ? 0 : ARM_EL_IL)
370 | (cv << 24) | (cond << 20) | (opc1 << 16)
371 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
372}
373
374static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
375{
376 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
377 | (is_16bit ? 0 : ARM_EL_IL)
378 | (cv << 24) | (cond << 20);
379}
380
381static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
382{
383 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
384 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc;
385}
386
387static inline uint32_t syn_data_abort_no_iss(int same_el,
388 int ea, int cm, int s1ptw,
389 int wnr, int fsc)
390{
391 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
392 | ARM_EL_IL
393 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
394}
395
396static inline uint32_t syn_data_abort_with_iss(int same_el,
397 int sas, int sse, int srt,
398 int sf, int ar,
399 int ea, int cm, int s1ptw,
400 int wnr, int fsc,
401 bool is_16bit)
402{
403 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
404 | (is_16bit ? 0 : ARM_EL_IL)
405 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16)
406 | (sf << 15) | (ar << 14)
407 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
408}
409
410static inline uint32_t syn_swstep(int same_el, int isv, int ex)
411{
412 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
413 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22;
414}
415
416static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
417{
418 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
419 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22;
420}
421
422static inline uint32_t syn_breakpoint(int same_el)
423{
424 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
425 | ARM_EL_IL | 0x22;
426}
427
428static inline uint32_t syn_wfx(int cv, int cond, int ti)
429{
430 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL |
431 (cv << 24) | (cond << 20) | ti;
432}
433
434
435
436
437void hw_watchpoint_update(ARMCPU *cpu, int n);
438
439
440
441
442void hw_watchpoint_update_all(ARMCPU *cpu);
443
444
445
446void hw_breakpoint_update(ARMCPU *cpu, int n);
447
448
449
450
451void hw_breakpoint_update_all(ARMCPU *cpu);
452
453
454bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
455
456
457void arm_debug_excp_handler(CPUState *cs);
458
459#ifdef CONFIG_USER_ONLY
460static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
461{
462 return false;
463}
464#else
465
466bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
467
468void arm_handle_psci_call(ARMCPU *cpu);
469#endif
470
471
472
473
474
475
476
477typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
478struct ARMMMUFaultInfo {
479 target_ulong s2addr;
480 bool stage2;
481 bool s1ptw;
482};
483
484
485bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,
486 uint32_t *fsr, ARMMMUFaultInfo *fi);
487
488
489
490bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
491
492
493void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
494 MMUAccessType access_type,
495 int mmu_idx, uintptr_t retaddr);
496
497
498static inline void arm_call_el_change_hook(ARMCPU *cpu)
499{
500 if (cpu->el_change_hook) {
501 cpu->el_change_hook(cpu, cpu->el_change_hook_opaque);
502 }
503}
504
505#endif
506