1
2
3
4
5
6
7
8
9
10
11
12
13#include "qemu/osdep.h"
14#include "qapi/error.h"
15#include "qemu-common.h"
16#include "cpu.h"
17#include "exec/address-spaces.h"
18#include "hw/arm/aspeed_soc.h"
19#include "hw/char/serial.h"
20#include "qemu/log.h"
21#include "hw/i2c/aspeed_i2c.h"
22#include "net/net.h"
23
24#define ASPEED_SOC_UART_5_BASE 0x00184000
25#define ASPEED_SOC_IOMEM_SIZE 0x00200000
26#define ASPEED_SOC_IOMEM_BASE 0x1E600000
27#define ASPEED_SOC_FMC_BASE 0x1E620000
28#define ASPEED_SOC_SPI_BASE 0x1E630000
29#define ASPEED_SOC_SPI2_BASE 0x1E631000
30#define ASPEED_SOC_VIC_BASE 0x1E6C0000
31#define ASPEED_SOC_SDMC_BASE 0x1E6E0000
32#define ASPEED_SOC_SCU_BASE 0x1E6E2000
33#define ASPEED_SOC_SRAM_BASE 0x1E720000
34#define ASPEED_SOC_TIMER_BASE 0x1E782000
35#define ASPEED_SOC_WDT_BASE 0x1E785000
36#define ASPEED_SOC_I2C_BASE 0x1E78A000
37#define ASPEED_SOC_ETH1_BASE 0x1E660000
38#define ASPEED_SOC_ETH2_BASE 0x1E680000
39
40static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
41static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
42
43#define AST2400_SDRAM_BASE 0x40000000
44#define AST2500_SDRAM_BASE 0x80000000
45
46static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
47static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
48
49static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE,
50 ASPEED_SOC_SPI2_BASE};
51static const char *aspeed_soc_ast2500_typenames[] = {
52 "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
53
54static const AspeedSoCInfo aspeed_socs[] = {
55 {
56 .name = "ast2400-a0",
57 .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
58 .silicon_rev = AST2400_A0_SILICON_REV,
59 .sdram_base = AST2400_SDRAM_BASE,
60 .sram_size = 0x8000,
61 .spis_num = 1,
62 .spi_bases = aspeed_soc_ast2400_spi_bases,
63 .fmc_typename = "aspeed.smc.fmc",
64 .spi_typename = aspeed_soc_ast2400_typenames,
65 .wdts_num = 2,
66 }, {
67 .name = "ast2400-a1",
68 .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
69 .silicon_rev = AST2400_A1_SILICON_REV,
70 .sdram_base = AST2400_SDRAM_BASE,
71 .sram_size = 0x8000,
72 .spis_num = 1,
73 .spi_bases = aspeed_soc_ast2400_spi_bases,
74 .fmc_typename = "aspeed.smc.fmc",
75 .spi_typename = aspeed_soc_ast2400_typenames,
76 .wdts_num = 2,
77 }, {
78 .name = "ast2400",
79 .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
80 .silicon_rev = AST2400_A0_SILICON_REV,
81 .sdram_base = AST2400_SDRAM_BASE,
82 .sram_size = 0x8000,
83 .spis_num = 1,
84 .spi_bases = aspeed_soc_ast2400_spi_bases,
85 .fmc_typename = "aspeed.smc.fmc",
86 .spi_typename = aspeed_soc_ast2400_typenames,
87 .wdts_num = 2,
88 }, {
89 .name = "ast2500-a1",
90 .cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
91 .silicon_rev = AST2500_A1_SILICON_REV,
92 .sdram_base = AST2500_SDRAM_BASE,
93 .sram_size = 0x9000,
94 .spis_num = 2,
95 .spi_bases = aspeed_soc_ast2500_spi_bases,
96 .fmc_typename = "aspeed.smc.ast2500-fmc",
97 .spi_typename = aspeed_soc_ast2500_typenames,
98 .wdts_num = 3,
99 },
100};
101
102
103
104
105
106
107static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size)
108{
109 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
110 __func__, offset, size);
111 return 0;
112}
113
114static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value,
115 unsigned size)
116{
117 qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
118 __func__, offset, value, size);
119}
120
121static const MemoryRegionOps aspeed_soc_io_ops = {
122 .read = aspeed_soc_io_read,
123 .write = aspeed_soc_io_write,
124 .endianness = DEVICE_LITTLE_ENDIAN,
125};
126
127static void aspeed_soc_init(Object *obj)
128{
129 AspeedSoCState *s = ASPEED_SOC(obj);
130 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
131 int i;
132
133 object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type);
134 object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
135
136 object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
137 object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
138 qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
139
140 object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
141 object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
142 qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
143
144 object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
145 object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
146 qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
147
148 object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
149 object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
150 qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
151 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
152 sc->info->silicon_rev);
153 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
154 "hw-strap1", &error_abort);
155 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
156 "hw-strap2", &error_abort);
157 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
158 "hw-prot-key", &error_abort);
159
160 object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename);
161 object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);
162 qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());
163 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
164 &error_abort);
165
166 for (i = 0; i < sc->info->spis_num; i++) {
167 object_initialize(&s->spi[i], sizeof(s->spi[i]),
168 sc->info->spi_typename[i]);
169 object_property_add_child(obj, "spi[*]", OBJECT(&s->spi[i]), NULL);
170 qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
171 }
172
173 object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC);
174 object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);
175 qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());
176 qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
177 sc->info->silicon_rev);
178 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
179 "ram-size", &error_abort);
180
181 for (i = 0; i < sc->info->wdts_num; i++) {
182 object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
183 object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL);
184 qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default());
185 qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
186 sc->info->silicon_rev);
187 }
188
189 object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100);
190 object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL);
191 qdev_set_parent_bus(DEVICE(&s->ftgmac100), sysbus_get_default());
192}
193
194static void aspeed_soc_realize(DeviceState *dev, Error **errp)
195{
196 int i;
197 AspeedSoCState *s = ASPEED_SOC(dev);
198 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
199 Error *err = NULL, *local_err = NULL;
200
201
202 memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL,
203 "aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE);
204 memory_region_add_subregion_overlap(get_system_memory(),
205 ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);
206
207
208 object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
209 if (err) {
210 error_propagate(errp, err);
211 return;
212 }
213
214
215 memory_region_init_ram_nomigrate(&s->sram, OBJECT(dev), "aspeed.sram",
216 sc->info->sram_size, &err);
217 if (err) {
218 error_propagate(errp, err);
219 return;
220 }
221 vmstate_register_ram_global(&s->sram);
222 memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
223 &s->sram);
224
225
226 object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
227 if (err) {
228 error_propagate(errp, err);
229 return;
230 }
231 sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
232 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
233 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
234 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
235 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
236
237
238 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
239 if (err) {
240 error_propagate(errp, err);
241 return;
242 }
243 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
244 for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
245 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
246 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
247 }
248
249
250 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
251 if (err) {
252 error_propagate(errp, err);
253 return;
254 }
255 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
256
257
258 if (serial_hds[0]) {
259 qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
260 serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,
261 uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
262 }
263
264
265 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
266 if (err) {
267 error_propagate(errp, err);
268 return;
269 }
270 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
271 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
272 qdev_get_gpio_in(DEVICE(&s->vic), 12));
273
274
275 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
276 if (err) {
277 error_propagate(errp, err);
278 return;
279 }
280 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
281 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
282 s->fmc.ctrl->flash_window_base);
283 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
284 qdev_get_gpio_in(DEVICE(&s->vic), 19));
285
286
287 for (i = 0; i < sc->info->spis_num; i++) {
288 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
289 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
290 &local_err);
291 error_propagate(&err, local_err);
292 if (err) {
293 error_propagate(errp, err);
294 return;
295 }
296 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]);
297 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
298 s->spi[i].ctrl->flash_window_base);
299 }
300
301
302 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
303 if (err) {
304 error_propagate(errp, err);
305 return;
306 }
307 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
308
309
310 for (i = 0; i < sc->info->wdts_num; i++) {
311 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
312 if (err) {
313 error_propagate(errp, err);
314 return;
315 }
316 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
317 ASPEED_SOC_WDT_BASE + i * 0x20);
318 }
319
320
321 qdev_set_nic_properties(DEVICE(&s->ftgmac100), &nd_table[0]);
322 object_property_set_bool(OBJECT(&s->ftgmac100), true, "aspeed", &err);
323 object_property_set_bool(OBJECT(&s->ftgmac100), true, "realized",
324 &local_err);
325 error_propagate(&err, local_err);
326 if (err) {
327 error_propagate(errp, err);
328 return;
329 }
330 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100), 0, ASPEED_SOC_ETH1_BASE);
331 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100), 0,
332 qdev_get_gpio_in(DEVICE(&s->vic), 2));
333}
334
335static void aspeed_soc_class_init(ObjectClass *oc, void *data)
336{
337 DeviceClass *dc = DEVICE_CLASS(oc);
338 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
339
340 sc->info = (AspeedSoCInfo *) data;
341 dc->realize = aspeed_soc_realize;
342
343 dc->user_creatable = false;
344}
345
346static const TypeInfo aspeed_soc_type_info = {
347 .name = TYPE_ASPEED_SOC,
348 .parent = TYPE_DEVICE,
349 .instance_init = aspeed_soc_init,
350 .instance_size = sizeof(AspeedSoCState),
351 .class_size = sizeof(AspeedSoCClass),
352 .abstract = true,
353};
354
355static void aspeed_soc_register_types(void)
356{
357 int i;
358
359 type_register_static(&aspeed_soc_type_info);
360 for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
361 TypeInfo ti = {
362 .name = aspeed_socs[i].name,
363 .parent = TYPE_ASPEED_SOC,
364 .class_init = aspeed_soc_class_init,
365 .class_data = (void *) &aspeed_socs[i],
366 };
367 type_register(&ti);
368 }
369}
370
371type_init(aspeed_soc_register_types)
372
