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28#include "qemu/osdep.h"
29#include "hw/sysbus.h"
30#include "hw/register-dep.h"
31#include "qemu/bitops.h"
32#include "qemu/log.h"
33#include "qapi/error.h"
34#include "hw/fdt_generic_util.h"
35
36#ifndef ARM_CCI400_ERR_DEBUG
37#define ARM_CCI400_ERR_DEBUG 0
38#endif
39
40#define TYPE_ARM_CCI400 "arm,cci-400"
41#define TYPE_ARM_CCI400_IOMMU_MEMORY_REGION "arm,cci-400-iommu-memory-region"
42
43#define ARM_CCI400(obj) \
44 OBJECT_CHECK(CCI, (obj), TYPE_ARM_CCI400)
45
46DEP_REG32(CONTROL_OVERRIDE_REGISTER, 0x0)
47 DEP_FIELD(CONTROL_OVERRIDE_REGISTER, DISABLE_RETRY_REDUCTION_BUFFERS, 1, 5)
48 DEP_FIELD(CONTROL_OVERRIDE_REGISTER, DISABLE_PRIORITY_PROMOTION, 1, 4)
49 DEP_FIELD(CONTROL_OVERRIDE_REGISTER, TERMINATE_BARRIERS, 1, 3)
50 DEP_FIELD(CONTROL_OVERRIDE_REGISTER, DISABLE_SPECULATIVE_FETCHES, 1, 2)
51 DEP_FIELD(CONTROL_OVERRIDE_REGISTER, DVM_MESSAGE_DISABLE, 1, 1)
52 DEP_FIELD(CONTROL_OVERRIDE_REGISTER, SNOOP_DISABLE, 1, 0)
53DEP_REG32(SPECULATION_CONTROL_REGISTER, 0x4)
54 DEP_FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_S4, 1, 20)
55 DEP_FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_S3, 1, 19)
56 DEP_FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_S2, 1, 18)
57 DEP_FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_S1, 1, 17)
58 DEP_FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_S0, 1, 16)
59 DEP_FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_M2, 1, 2)
60 DEP_FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_M1, 1, 1)
61 DEP_FIELD(SPECULATION_CONTROL_REGISTER, DISABLE_SPECULATIVE_FETCHES_M0, 1, 0)
62DEP_REG32(SECURE_ACCESS_REGISTER, 0x8)
63 DEP_FIELD(SECURE_ACCESS_REGISTER, SECURE_ACCESS_CONTROL, 1, 0)
64DEP_REG32(STATUS_REGISTER, 0xc)
65 DEP_FIELD(STATUS_REGISTER, CCI_STATUS, 1, 0)
66DEP_REG32(IMPRECISE_ERROR_REGISTER, 0x10)
67 DEP_FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_S4, 1, 20)
68 DEP_FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_S3, 1, 19)
69 DEP_FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_S2, 1, 18)
70 DEP_FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_S1, 1, 17)
71 DEP_FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_S0, 1, 16)
72 DEP_FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_M2, 1, 2)
73 DEP_FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_M1, 1, 1)
74 DEP_FIELD(IMPRECISE_ERROR_REGISTER, IMP_ERR_M0, 1, 0)
75DEP_REG32(PERFORMANCE_MONITOR_CONTROL_REGISTER, 0x100)
76 DEP_FIELD(PERFORMANCE_MONITOR_CONTROL_REGISTER, PMU_COUNT_NUM, 5, 11)
77 DEP_FIELD(PERFORMANCE_MONITOR_CONTROL_REGISTER, DP, 1, 5)
78 DEP_FIELD(PERFORMANCE_MONITOR_CONTROL_REGISTER, EX, 1, 4)
79 DEP_FIELD(PERFORMANCE_MONITOR_CONTROL_REGISTER, CCD, 1, 3)
80 DEP_FIELD(PERFORMANCE_MONITOR_CONTROL_REGISTER, CCR, 1, 2)
81 DEP_FIELD(PERFORMANCE_MONITOR_CONTROL_REGISTER, RST, 1, 1)
82 DEP_FIELD(PERFORMANCE_MONITOR_CONTROL_REGISTER, CEN, 1, 0)
83DEP_REG32(PERIPHERAL_ID4, 0xfd0)
84 DEP_FIELD(PERIPHERAL_ID4, PERIPH_ID_4, 8, 0)
85DEP_REG32(PERIPHERAL_ID5, 0xfd4)
86 DEP_FIELD(PERIPHERAL_ID5, PERIPH_ID_5, 8, 0)
87DEP_REG32(PERIPHERAL_ID6, 0xfd8)
88 DEP_FIELD(PERIPHERAL_ID6, PERIPH_ID_6, 8, 0)
89DEP_REG32(PERIPHERAL_ID7, 0xfdc)
90 DEP_FIELD(PERIPHERAL_ID7, PERIPH_ID_7, 8, 0)
91DEP_REG32(PERIPHERAL_ID0, 0xfe0)
92 DEP_FIELD(PERIPHERAL_ID0, PERIPHERAL_ID0, 8, 0)
93DEP_REG32(PERIPHERAL_ID1, 0xfe4)
94 DEP_FIELD(PERIPHERAL_ID1, PERIPHERAL_ID1, 8, 0)
95DEP_REG32(PERIPHERAL_ID2, 0xfe8)
96 DEP_FIELD(PERIPHERAL_ID2, PERIPH_ID_2, 8, 0)
97DEP_REG32(PERIPHERAL_ID3, 0xfec)
98 DEP_FIELD(PERIPHERAL_ID3, REV_AND, 4, 4)
99 DEP_FIELD(PERIPHERAL_ID3, CUST_MOD_NUM, 4, 0)
100DEP_REG32(COMPONENT_ID0, 0xff0)
101 DEP_FIELD(COMPONENT_ID0, COMPONENT_ID0, 8, 0)
102DEP_REG32(COMPONENT_ID1, 0xff4)
103 DEP_FIELD(COMPONENT_ID1, COMPONENT_ID1, 8, 0)
104DEP_REG32(COMPONENT_ID2, 0xff8)
105 DEP_FIELD(COMPONENT_ID2, COMPONENT_ID2, 8, 0)
106DEP_REG32(COMPONENT_ID3, 0xffc)
107 DEP_FIELD(COMPONENT_ID3, COMPONENT_ID3, 8, 0)
108DEP_REG32(SNOOP_CONTROL_REGISTER_S0, 0x1000)
109 DEP_FIELD(SNOOP_CONTROL_REGISTER_S0, SUPPORT_DVMS, 1, 31)
110 DEP_FIELD(SNOOP_CONTROL_REGISTER_S0, SUPPORT_SNOOPS, 1, 30)
111 DEP_FIELD(SNOOP_CONTROL_REGISTER_S0, ENABLE_DVMS, 1, 1)
112DEP_REG32(SHAREABLE_OVERRIDE_REGISTER_S0, 0x1004)
113 DEP_FIELD(SHAREABLE_OVERRIDE_REGISTER_S0, AXDOMAIN_OVERRIDE, 2, 0)
114DEP_REG32(READ_QOS_OVERRIDE_REGISTER_S0, 0x1100)
115 DEP_FIELD(READ_QOS_OVERRIDE_REGISTER_S0, ARQOS_OVERRIDE_READBACK, 4, 8)
116 DEP_FIELD(READ_QOS_OVERRIDE_REGISTER_S0, ARQOS_VALUE, 4, 0)
117DEP_REG32(WRITE_QOS_OVERRIDE_REGISTER_S0, 0x1104)
118 DEP_FIELD(WRITE_QOS_OVERRIDE_REGISTER_S0, AWQOS_OVERRIDE_READBACK, 4, 8)
119 DEP_FIELD(WRITE_QOS_OVERRIDE_REGISTER_S0, AWQOS_VALUE, 4, 0)
120DEP_REG32(QOS_CONTROL_REGISTER_S0, 0x110c)
121 DEP_FIELD(QOS_CONTROL_REGISTER_S0, QOS_REGULATION_DISABLED, 1, 31)
122 DEP_FIELD(QOS_CONTROL_REGISTER_S0, BANDWIDTH_REGULATION_MODE, 1, 21)
123 DEP_FIELD(QOS_CONTROL_REGISTER_S0, ARQOS_REGULATION_MODE, 1, 20)
124 DEP_FIELD(QOS_CONTROL_REGISTER_S0, AWQOS_REGULATION_MODE, 1, 16)
125 DEP_FIELD(QOS_CONTROL_REGISTER_S0, AR_OT_REGULATION, 1, 3)
126 DEP_FIELD(QOS_CONTROL_REGISTER_S0, AW_OT_REGULATION, 1, 2)
127 DEP_FIELD(QOS_CONTROL_REGISTER_S0, ARQOS_REGULATION, 1, 1)
128 DEP_FIELD(QOS_CONTROL_REGISTER_S0, AWQOS_REGULATION, 1, 0)
129DEP_REG32(MAX_OT_REGISTER_S0, 0x1110)
130 DEP_FIELD(MAX_OT_REGISTER_S0, INT_OT_AR, 6, 24)
131 DEP_FIELD(MAX_OT_REGISTER_S0, FRAC_OT_AR, 8, 16)
132 DEP_FIELD(MAX_OT_REGISTER_S0, INT_OT_AW, 6, 8)
133 DEP_FIELD(MAX_OT_REGISTER_S0, FRAC_OT_AW, 8, 0)
134DEP_REG32(TARGET_LATENCY_REGISTER_S0, 0x1130)
135 DEP_FIELD(TARGET_LATENCY_REGISTER_S0, AR_LAT, 12, 16)
136 DEP_FIELD(TARGET_LATENCY_REGISTER_S0, AW_LAT, 12, 0)
137DEP_REG32(LATENCY_REGULATION_REGISTER_S0, 0x1134)
138 DEP_FIELD(LATENCY_REGULATION_REGISTER_S0, AR_SCALE_FACT, 3, 8)
139 DEP_FIELD(LATENCY_REGULATION_REGISTER_S0, AW_SCALE_FACT, 3, 0)
140DEP_REG32(QOS_RANGE_REGISTER_S0, 0x1138)
141 DEP_FIELD(QOS_RANGE_REGISTER_S0, MAX_ARQOS, 4, 24)
142 DEP_FIELD(QOS_RANGE_REGISTER_S0, MIN_ARQOS, 4, 16)
143 DEP_FIELD(QOS_RANGE_REGISTER_S0, MAX_AWQOS, 4, 8)
144 DEP_FIELD(QOS_RANGE_REGISTER_S0, MIN_AWQOS, 4, 0)
145DEP_REG32(SNOOP_CONTROL_REGISTER_S1, 0x2000)
146 DEP_FIELD(SNOOP_CONTROL_REGISTER_S1, SUPPORT_DVMS, 1, 31)
147 DEP_FIELD(SNOOP_CONTROL_REGISTER_S1, SUPPORT_SNOOPS, 1, 30)
148 DEP_FIELD(SNOOP_CONTROL_REGISTER_S1, ENABLE_DVMS, 1, 1)
149DEP_REG32(SHAREABLE_OVERRIDE_REGISTER_S1, 0x2004)
150 DEP_FIELD(SHAREABLE_OVERRIDE_REGISTER_S1, AXDOMAIN_OVERRIDE, 2, 0)
151DEP_REG32(READ_QOS_OVERRIDE_REGISTER_S1, 0x2100)
152 DEP_FIELD(READ_QOS_OVERRIDE_REGISTER_S1, ARQOS_OVERRIDE_READBACK, 4, 8)
153 DEP_FIELD(READ_QOS_OVERRIDE_REGISTER_S1, ARQOS_VALUE, 4, 0)
154DEP_REG32(WRITE_QOS_OVERRIDE_REGISTER_S1, 0x2104)
155 DEP_FIELD(WRITE_QOS_OVERRIDE_REGISTER_S1, AWQOS_OVERRIDE_READBACK, 4, 8)
156 DEP_FIELD(WRITE_QOS_OVERRIDE_REGISTER_S1, AWQOS_VALUE, 4, 0)
157DEP_REG32(QOS_CONTROL_REGISTER_S1, 0x210c)
158 DEP_FIELD(QOS_CONTROL_REGISTER_S1, QOS_REGULATION_DISABLED, 1, 31)
159 DEP_FIELD(QOS_CONTROL_REGISTER_S1, BANDWIDTH_REGULATION_MODE, 1, 21)
160 DEP_FIELD(QOS_CONTROL_REGISTER_S1, ARQOS_REGULATION_MODE, 1, 20)
161 DEP_FIELD(QOS_CONTROL_REGISTER_S1, AWQOS_REGULATION_MODE, 1, 16)
162 DEP_FIELD(QOS_CONTROL_REGISTER_S1, AR_OT_REGULATION, 1, 3)
163 DEP_FIELD(QOS_CONTROL_REGISTER_S1, AW_OT_REGULATION, 1, 2)
164 DEP_FIELD(QOS_CONTROL_REGISTER_S1, ARQOS_REGULATION, 1, 1)
165 DEP_FIELD(QOS_CONTROL_REGISTER_S1, AWQOS_REGULATION, 1, 0)
166DEP_REG32(MAX_OT_REGISTER_S1, 0x2110)
167 DEP_FIELD(MAX_OT_REGISTER_S1, INT_OT_AR, 6, 24)
168 DEP_FIELD(MAX_OT_REGISTER_S1, FRAC_OT_AR, 8, 16)
169 DEP_FIELD(MAX_OT_REGISTER_S1, INT_OT_AW, 6, 8)
170 DEP_FIELD(MAX_OT_REGISTER_S1, FRAC_OT_AW, 8, 0)
171DEP_REG32(TARGET_LATENCY_REGISTER_S1, 0x2130)
172 DEP_FIELD(TARGET_LATENCY_REGISTER_S1, AR_LAT, 12, 16)
173 DEP_FIELD(TARGET_LATENCY_REGISTER_S1, AW_LAT, 12, 0)
174DEP_REG32(LATENCY_REGULATION_REGISTER_S1, 0x2134)
175 DEP_FIELD(LATENCY_REGULATION_REGISTER_S1, AR_SCALE_FACT, 3, 8)
176 DEP_FIELD(LATENCY_REGULATION_REGISTER_S1, AW_SCALE_FACT, 3, 0)
177DEP_REG32(QOS_RANGE_REGISTER_S1, 0x2138)
178 DEP_FIELD(QOS_RANGE_REGISTER_S1, MAX_ARQOS, 4, 24)
179 DEP_FIELD(QOS_RANGE_REGISTER_S1, MIN_ARQOS, 4, 16)
180 DEP_FIELD(QOS_RANGE_REGISTER_S1, MAX_AWQOS, 4, 8)
181 DEP_FIELD(QOS_RANGE_REGISTER_S1, MIN_AWQOS, 4, 0)
182DEP_REG32(SNOOP_CONTROL_REGISTER_S2, 0x3000)
183 DEP_FIELD(SNOOP_CONTROL_REGISTER_S2, SUPPORT_DVMS, 1, 31)
184 DEP_FIELD(SNOOP_CONTROL_REGISTER_S2, SUPPORT_SNOOPS, 1, 30)
185 DEP_FIELD(SNOOP_CONTROL_REGISTER_S2, ENABLE_DVMS, 1, 1)
186DEP_REG32(SHAREABLE_OVERRIDE_REGISTER_S2, 0x3004)
187 DEP_FIELD(SHAREABLE_OVERRIDE_REGISTER_S2, AXDOMAIN_OVERRIDE, 2, 0)
188DEP_REG32(READ_QOS_OVERRIDE_REGISTER_S2, 0x3100)
189 DEP_FIELD(READ_QOS_OVERRIDE_REGISTER_S2, ARQOS_OVERRIDE_READBACK, 4, 8)
190 DEP_FIELD(READ_QOS_OVERRIDE_REGISTER_S2, ARQOS_VALUE, 4, 0)
191DEP_REG32(WRITE_QOS_OVERRIDE_REGISTER_S2, 0x3104)
192 DEP_FIELD(WRITE_QOS_OVERRIDE_REGISTER_S2, AWQOS_OVERRIDE_READBACK, 4, 8)
193 DEP_FIELD(WRITE_QOS_OVERRIDE_REGISTER_S2, AWQOS_VALUE, 4, 0)
194DEP_REG32(QOS_CONTROL_REGISTER_S2, 0x310c)
195 DEP_FIELD(QOS_CONTROL_REGISTER_S2, QOS_REGULATION_DISABLED, 1, 31)
196 DEP_FIELD(QOS_CONTROL_REGISTER_S2, BANDWIDTH_REGULATION_MODE, 1, 21)
197 DEP_FIELD(QOS_CONTROL_REGISTER_S2, ARQOS_REGULATION_MODE, 1, 20)
198 DEP_FIELD(QOS_CONTROL_REGISTER_S2, AWQOS_REGULATION_MODE, 1, 16)
199 DEP_FIELD(QOS_CONTROL_REGISTER_S2, AR_OT_REGULATION, 1, 3)
200 DEP_FIELD(QOS_CONTROL_REGISTER_S2, AW_OT_REGULATION, 1, 2)
201 DEP_FIELD(QOS_CONTROL_REGISTER_S2, ARQOS_REGULATION, 1, 1)
202 DEP_FIELD(QOS_CONTROL_REGISTER_S2, AWQOS_REGULATION, 1, 0)
203DEP_REG32(MAX_OT_REGISTER_S2, 0x3110)
204 DEP_FIELD(MAX_OT_REGISTER_S2, INT_OT_AR, 6, 24)
205 DEP_FIELD(MAX_OT_REGISTER_S2, FRAC_OT_AR, 8, 16)
206 DEP_FIELD(MAX_OT_REGISTER_S2, INT_OT_AW, 6, 8)
207 DEP_FIELD(MAX_OT_REGISTER_S2, FRAC_OT_AW, 8, 0)
208DEP_REG32(TARGET_LATENCY_REGISTER_S2, 0x3130)
209 DEP_FIELD(TARGET_LATENCY_REGISTER_S2, AR_LAT, 12, 16)
210 DEP_FIELD(TARGET_LATENCY_REGISTER_S2, AW_LAT, 12, 0)
211DEP_REG32(LATENCY_REGULATION_REGISTER_S2, 0x3134)
212 DEP_FIELD(LATENCY_REGULATION_REGISTER_S2, AR_SCALE_FACT, 3, 8)
213 DEP_FIELD(LATENCY_REGULATION_REGISTER_S2, AW_SCALE_FACT, 3, 0)
214DEP_REG32(QOS_RANGE_REGISTER_S2, 0x3138)
215 DEP_FIELD(QOS_RANGE_REGISTER_S2, MAX_ARQOS, 4, 24)
216 DEP_FIELD(QOS_RANGE_REGISTER_S2, MIN_ARQOS, 4, 16)
217 DEP_FIELD(QOS_RANGE_REGISTER_S2, MAX_AWQOS, 4, 8)
218 DEP_FIELD(QOS_RANGE_REGISTER_S2, MIN_AWQOS, 4, 0)
219DEP_REG32(SNOOP_CONTROL_REGISTER_S3, 0x4000)
220 DEP_FIELD(SNOOP_CONTROL_REGISTER_S3, SUPPORT_DVMS, 1, 31)
221 DEP_FIELD(SNOOP_CONTROL_REGISTER_S3, SUPPORT_SNOOPS, 1, 30)
222 DEP_FIELD(SNOOP_CONTROL_REGISTER_S3, ENABLE_DVMS, 1, 1)
223 DEP_FIELD(SNOOP_CONTROL_REGISTER_S3, ENABLE_SNOOPS, 1, 0)
224DEP_REG32(READ_QOS_OVERRIDE_REGISTER_S3, 0x4100)
225 DEP_FIELD(READ_QOS_OVERRIDE_REGISTER_S3, ARQOS_OVERRIDE_READBACK, 4, 8)
226 DEP_FIELD(READ_QOS_OVERRIDE_REGISTER_S3, ARQOS_VALUE, 4, 0)
227DEP_REG32(WRITE_QOS_OVERRIDE_REGISTER_S3, 0x4104)
228 DEP_FIELD(WRITE_QOS_OVERRIDE_REGISTER_S3, AWQOS_OVERRIDE_READBACK, 4, 8)
229 DEP_FIELD(WRITE_QOS_OVERRIDE_REGISTER_S3, AWQOS_VALUE, 4, 0)
230DEP_REG32(QOS_CONTROL_REGISTER_S3, 0x410c)
231 DEP_FIELD(QOS_CONTROL_REGISTER_S3, QOS_REGULATION_DISABLED, 1, 31)
232 DEP_FIELD(QOS_CONTROL_REGISTER_S3, BANDWIDTH_REGULATION_MODE, 1, 21)
233 DEP_FIELD(QOS_CONTROL_REGISTER_S3, ARQOS_REGULATION_MODE, 1, 20)
234 DEP_FIELD(QOS_CONTROL_REGISTER_S3, AWQOS_REGULATION_MODE, 1, 16)
235 DEP_FIELD(QOS_CONTROL_REGISTER_S3, ARQOS_REGULATION, 1, 1)
236 DEP_FIELD(QOS_CONTROL_REGISTER_S3, AWQOS_REGULATION, 1, 0)
237DEP_REG32(TARGET_LATENCY_REGISTER_S3, 0x4130)
238 DEP_FIELD(TARGET_LATENCY_REGISTER_S3, AR_LAT, 12, 16)
239 DEP_FIELD(TARGET_LATENCY_REGISTER_S3, AW_LAT, 12, 0)
240DEP_REG32(LATENCY_REGULATION_REGISTER_S3, 0x4134)
241 DEP_FIELD(LATENCY_REGULATION_REGISTER_S3, AR_SCALE_FACT, 3, 8)
242 DEP_FIELD(LATENCY_REGULATION_REGISTER_S3, AW_SCALE_FACT, 3, 0)
243DEP_REG32(QOS_RANGE_REGISTER_S3, 0x4138)
244 DEP_FIELD(QOS_RANGE_REGISTER_S3, MAX_ARQOS, 4, 24)
245 DEP_FIELD(QOS_RANGE_REGISTER_S3, MIN_ARQOS, 4, 16)
246 DEP_FIELD(QOS_RANGE_REGISTER_S3, MAX_AWQOS, 4, 8)
247 DEP_FIELD(QOS_RANGE_REGISTER_S3, MIN_AWQOS, 4, 0)
248DEP_REG32(SNOOP_CONTROL_REGISTER_S4, 0x5000)
249 DEP_FIELD(SNOOP_CONTROL_REGISTER_S4, SUPPORT_DVMS, 1, 31)
250 DEP_FIELD(SNOOP_CONTROL_REGISTER_S4, SUPPORT_SNOOPS, 1, 30)
251 DEP_FIELD(SNOOP_CONTROL_REGISTER_S4, ENABLE_DVMS, 1, 1)
252 DEP_FIELD(SNOOP_CONTROL_REGISTER_S4, ENABLE_SNOOPS, 1, 0)
253DEP_REG32(READ_QOS_OVERRIDE_REGISTER_S4, 0x5100)
254 DEP_FIELD(READ_QOS_OVERRIDE_REGISTER_S4, ARQOS_OVERRIDE_READBACK, 4, 8)
255 DEP_FIELD(READ_QOS_OVERRIDE_REGISTER_S4, ARQOS_VALUE, 4, 0)
256DEP_REG32(WRITE_QOS_OVERRIDE_REGISTER_S4, 0x5104)
257 DEP_FIELD(WRITE_QOS_OVERRIDE_REGISTER_S4, AWQOS_OVERRIDE_READBACK, 4, 8)
258 DEP_FIELD(WRITE_QOS_OVERRIDE_REGISTER_S4, AWQOS_VALUE, 4, 0)
259DEP_REG32(QOS_CONTROL_REGISTER_S4, 0x510c)
260 DEP_FIELD(QOS_CONTROL_REGISTER_S4, QOS_REGULATION_DISABLED, 1, 31)
261 DEP_FIELD(QOS_CONTROL_REGISTER_S4, BANDWIDTH_REGULATION_MODE, 1, 21)
262 DEP_FIELD(QOS_CONTROL_REGISTER_S4, ARQOS_REGULATION_MODE, 1, 20)
263 DEP_FIELD(QOS_CONTROL_REGISTER_S4, AWQOS_REGULATION_MODE, 1, 16)
264 DEP_FIELD(QOS_CONTROL_REGISTER_S4, ARQOS_REGULATION, 1, 1)
265 DEP_FIELD(QOS_CONTROL_REGISTER_S4, AWQOS_REGULATION, 1, 0)
266DEP_REG32(TARGET_LATENCY_REGISTER_S4, 0x5130)
267 DEP_FIELD(TARGET_LATENCY_REGISTER_S4, AR_LAT, 12, 16)
268 DEP_FIELD(TARGET_LATENCY_REGISTER_S4, AW_LAT, 12, 0)
269DEP_REG32(LATENCY_REGULATION_REGISTER_S4, 0x5134)
270 DEP_FIELD(LATENCY_REGULATION_REGISTER_S4, AR_SCALE_FACT, 3, 8)
271 DEP_FIELD(LATENCY_REGULATION_REGISTER_S4, AW_SCALE_FACT, 3, 0)
272DEP_REG32(QOS_RANGE_REGISTER_S4, 0x5138)
273 DEP_FIELD(QOS_RANGE_REGISTER_S4, MAX_ARQOS, 4, 24)
274 DEP_FIELD(QOS_RANGE_REGISTER_S4, MIN_ARQOS, 4, 16)
275 DEP_FIELD(QOS_RANGE_REGISTER_S4, MAX_AWQOS, 4, 8)
276 DEP_FIELD(QOS_RANGE_REGISTER_S4, MIN_AWQOS, 4, 0)
277DEP_REG32(CYCLE_COUNTER, 0x9004)
278DEP_REG32(CYCLE_COUNTER_CONTROL, 0x9008)
279 DEP_FIELD(CYCLE_COUNTER_CONTROL, CCNT_EN, 1, 0)
280DEP_REG32(CYCLE_COUNT_OVERFLOW, 0x900c)
281 DEP_FIELD(CYCLE_COUNT_OVERFLOW, CCNT_OVERFLOW, 1, 0)
282DEP_REG32(ESR0, 0xa000)
283 DEP_FIELD(ESR0, EVT_IF0, 3, 5)
284 DEP_FIELD(ESR0, EVT_CNT0, 5, 0)
285DEP_REG32(EVENT_COUNTER0, 0xa004)
286DEP_REG32(EVENT_COUNTER0_CONTROL, 0xa008)
287 DEP_FIELD(EVENT_COUNTER0_CONTROL, CNT0_EN, 1, 0)
288DEP_REG32(EVENT_COUNTER0_OVERFLOW, 0xa00c)
289 DEP_FIELD(EVENT_COUNTER0_OVERFLOW, CNT0_OVERFLOW, 1, 0)
290DEP_REG32(ESR1, 0xb000)
291 DEP_FIELD(ESR1, EVT_IF1, 3, 5)
292 DEP_FIELD(ESR1, EVT_CNT1, 5, 0)
293DEP_REG32(EVENT_COUNTER1, 0xb004)
294DEP_REG32(EVENT_COUNTER1_CONTROL, 0xb008)
295 DEP_FIELD(EVENT_COUNTER1_CONTROL, CNT1_EN, 1, 0)
296DEP_REG32(EVENT_COUNTER1_OVERFLOW, 0xb00c)
297 DEP_FIELD(EVENT_COUNTER1_OVERFLOW, CNT1_OVERFLOW, 1, 0)
298DEP_REG32(ESR2, 0xc000)
299 DEP_FIELD(ESR2, EVT_IF2, 3, 5)
300 DEP_FIELD(ESR2, EVT_CNT2, 5, 0)
301DEP_REG32(EVENT_COUNTER2, 0xc004)
302DEP_REG32(EVENT_COUNTER2_CONTROL, 0xc008)
303 DEP_FIELD(EVENT_COUNTER2_CONTROL, CNT2_EN, 1, 0)
304DEP_REG32(EVENT_COUNTER2_OVERFLOW, 0xc00c)
305 DEP_FIELD(EVENT_COUNTER2_OVERFLOW, CNT2_OVERFLOW, 1, 0)
306DEP_REG32(ESR3, 0xd000)
307 DEP_FIELD(ESR3, EVT_IF3, 3, 5)
308 DEP_FIELD(ESR3, EVT_CNT3, 5, 0)
309DEP_REG32(EVENT_COUNTER3, 0xd004)
310DEP_REG32(EVENT_COUNTER3_CONTROL, 0xd008)
311 DEP_FIELD(EVENT_COUNTER3_CONTROL, CNT3_EN, 1, 0)
312DEP_REG32(EVENT_COUNTER3_OVERFLOW, 0xd00c)
313 DEP_FIELD(EVENT_COUNTER3_OVERFLOW, CNT3_OVERFLOW, 1, 0)
314
315#define R_MAX (R_EVENT_COUNTER3_OVERFLOW + 1)
316
317typedef struct CCI {
318 SysBusDevice parent_obj;
319 MemoryRegion iomem;
320 IOMMUMemoryRegion iommu;
321
322 struct {
323 uint64_t stripe_granule_sz;
324 } cfg;
325
326
327 AddressSpace *as[3];
328 MemoryRegion *M[3];
329
330 uint32_t regs[R_MAX];
331 DepRegisterInfo regs_info[R_MAX];
332
333 uint64_t enable_mask;
334} CCI;
335
336static DepRegisterAccessInfo cci400_regs_info[] = {
337 { .name = "CONTROL_OVERRIDE_REGISTER",
338 .decode.addr = A_CONTROL_OVERRIDE_REGISTER,
339 },{ .name = "SPECULATION_CONTROL_REGISTER",
340 .decode.addr = A_SPECULATION_CONTROL_REGISTER,
341 },{ .name = "SECURE_ACCESS_REGISTER",
342 .decode.addr = A_SECURE_ACCESS_REGISTER,
343 },{ .name = "STATUS_REGISTER", .decode.addr = A_STATUS_REGISTER,
344 .ro = 0x1,
345 },{ .name = "IMPRECISE_ERROR_REGISTER",
346 .decode.addr = A_IMPRECISE_ERROR_REGISTER,
347 .w1c = 0x1f0007,
348 },{ .name = "PERFORMANCE_MONITOR_CONTROL_REGISTER",
349 .decode.addr = A_PERFORMANCE_MONITOR_CONTROL_REGISTER,
350 .reset = 0x2000,
351 .ro = 0xf800,
352 },{ .name = "PERIPHERAL_ID4", .decode.addr = A_PERIPHERAL_ID4,
353 .reset = 0x44,
354 .ro = 0xff,
355 },{ .name = "PERIPHERAL_ID5", .decode.addr = A_PERIPHERAL_ID5,
356 .ro = 0xff,
357 },{ .name = "PERIPHERAL_ID6", .decode.addr = A_PERIPHERAL_ID6,
358 .ro = 0xff,
359 },{ .name = "PERIPHERAL_ID7", .decode.addr = A_PERIPHERAL_ID7,
360 .ro = 0xff,
361 },{ .name = "PERIPHERAL_ID0", .decode.addr = A_PERIPHERAL_ID0,
362 .reset = 0x20,
363 .ro = 0xff,
364 },{ .name = "PERIPHERAL_ID1", .decode.addr = A_PERIPHERAL_ID1,
365 .reset = 0xb4,
366 .ro = 0xff,
367 },{ .name = "PERIPHERAL_ID2", .decode.addr = A_PERIPHERAL_ID2,
368 .reset = 0x9b,
369 .ro = 0xff,
370 },{ .name = "PERIPHERAL_ID3", .decode.addr = A_PERIPHERAL_ID3,
371 .ro = 0xff,
372 },{ .name = "COMPONENT_ID0", .decode.addr = A_COMPONENT_ID0,
373 .reset = 0xd,
374 .ro = 0xff,
375 },{ .name = "COMPONENT_ID1", .decode.addr = A_COMPONENT_ID1,
376 .reset = 0xf0,
377 .ro = 0xff,
378 },{ .name = "COMPONENT_ID2", .decode.addr = A_COMPONENT_ID2,
379 .reset = 0x5,
380 .ro = 0xff,
381 },{ .name = "COMPONENT_ID3", .decode.addr = A_COMPONENT_ID3,
382 .reset = 0xb1,
383 .ro = 0xff,
384 },{ .name = "SNOOP_CONTROL_REGISTER_S0",
385 .decode.addr = A_SNOOP_CONTROL_REGISTER_S0,
386 .reset = 0x80000000,
387 .ro = 0xc0000000,
388 },{ .name = "SHAREABLE_OVERRIDE_REGISTER_S0",
389 .decode.addr = A_SHAREABLE_OVERRIDE_REGISTER_S0,
390 },{ .name = "READ_QOS_OVERRIDE_REGISTER_S0",
391 .decode.addr = A_READ_QOS_OVERRIDE_REGISTER_S0,
392 .ro = 0xf00,
393 },{ .name = "WRITE_QOS_OVERRIDE_REGISTER_S0",
394 .decode.addr = A_WRITE_QOS_OVERRIDE_REGISTER_S0,
395 .ro = 0xf00,
396 },{ .name = "QOS_CONTROL_REGISTER_S0",
397 .decode.addr = A_QOS_CONTROL_REGISTER_S0,
398 .ro = 0x80000000,
399 },{ .name = "MAX_OT_REGISTER_S0", .decode.addr = A_MAX_OT_REGISTER_S0,
400 },{ .name = "TARGET_LATENCY_REGISTER_S0",
401 .decode.addr = A_TARGET_LATENCY_REGISTER_S0,
402 },{ .name = "LATENCY_REGULATION_REGISTER_S0",
403 .decode.addr = A_LATENCY_REGULATION_REGISTER_S0,
404 },{ .name = "QOS_RANGE_REGISTER_S0",
405 .decode.addr = A_QOS_RANGE_REGISTER_S0,
406 },{ .name = "SNOOP_CONTROL_REGISTER_S1",
407 .decode.addr = A_SNOOP_CONTROL_REGISTER_S1,
408 .ro = 0xc0000002,
409 },{ .name = "SHAREABLE_OVERRIDE_REGISTER_S1",
410 .decode.addr = A_SHAREABLE_OVERRIDE_REGISTER_S1,
411 },{ .name = "READ_QOS_OVERRIDE_REGISTER_S1",
412 .decode.addr = A_READ_QOS_OVERRIDE_REGISTER_S1,
413 .ro = 0xf00,
414 },{ .name = "WRITE_QOS_OVERRIDE_REGISTER_S1",
415 .decode.addr = A_WRITE_QOS_OVERRIDE_REGISTER_S1,
416 .ro = 0xf00,
417 },{ .name = "QOS_CONTROL_REGISTER_S1",
418 .decode.addr = A_QOS_CONTROL_REGISTER_S1,
419 .ro = 0x80000000,
420 },{ .name = "MAX_OT_REGISTER_S1", .decode.addr = A_MAX_OT_REGISTER_S1,
421 },{ .name = "TARGET_LATENCY_REGISTER_S1",
422 .decode.addr = A_TARGET_LATENCY_REGISTER_S1,
423 },{ .name = "LATENCY_REGULATION_REGISTER_S1",
424 .decode.addr = A_LATENCY_REGULATION_REGISTER_S1,
425 },{ .name = "QOS_RANGE_REGISTER_S1",
426 .decode.addr = A_QOS_RANGE_REGISTER_S1,
427 },{ .name = "SNOOP_CONTROL_REGISTER_S2",
428 .decode.addr = A_SNOOP_CONTROL_REGISTER_S2,
429 .ro = 0xc0000002,
430 },{ .name = "SHAREABLE_OVERRIDE_REGISTER_S2",
431 .decode.addr = A_SHAREABLE_OVERRIDE_REGISTER_S2,
432 },{ .name = "READ_QOS_OVERRIDE_REGISTER_S2",
433 .decode.addr = A_READ_QOS_OVERRIDE_REGISTER_S2,
434 .ro = 0xf00,
435 },{ .name = "WRITE_QOS_OVERRIDE_REGISTER_S2",
436 .decode.addr = A_WRITE_QOS_OVERRIDE_REGISTER_S2,
437 .ro = 0xf00,
438 },{ .name = "QOS_CONTROL_REGISTER_S2",
439 .decode.addr = A_QOS_CONTROL_REGISTER_S2,
440 .ro = 0x80000000,
441 },{ .name = "MAX_OT_REGISTER_S2", .decode.addr = A_MAX_OT_REGISTER_S2,
442 },{ .name = "TARGET_LATENCY_REGISTER_S2",
443 .decode.addr = A_TARGET_LATENCY_REGISTER_S2,
444 },{ .name = "LATENCY_REGULATION_REGISTER_S2",
445 .decode.addr = A_LATENCY_REGULATION_REGISTER_S2,
446 },{ .name = "QOS_RANGE_REGISTER_S2",
447 .decode.addr = A_QOS_RANGE_REGISTER_S2,
448 },{ .name = "SNOOP_CONTROL_REGISTER_S3",
449 .decode.addr = A_SNOOP_CONTROL_REGISTER_S3,
450 .reset = 0xc0000000,
451 .ro = 0xc0000000,
452 },{ .name = "READ_QOS_OVERRIDE_REGISTER_S3",
453 .decode.addr = A_READ_QOS_OVERRIDE_REGISTER_S3,
454 .ro = 0xf00,
455 },{ .name = "WRITE_QOS_OVERRIDE_REGISTER_S3",
456 .decode.addr = A_WRITE_QOS_OVERRIDE_REGISTER_S3,
457 .ro = 0xf00,
458 },{ .name = "QOS_CONTROL_REGISTER_S3",
459 .decode.addr = A_QOS_CONTROL_REGISTER_S3,
460 .ro = 0x80000000,
461 },{ .name = "TARGET_LATENCY_REGISTER_S3",
462 .decode.addr = A_TARGET_LATENCY_REGISTER_S3,
463 },{ .name = "LATENCY_REGULATION_REGISTER_S3",
464 .decode.addr = A_LATENCY_REGULATION_REGISTER_S3,
465 },{ .name = "QOS_RANGE_REGISTER_S3",
466 .decode.addr = A_QOS_RANGE_REGISTER_S3,
467 },{ .name = "SNOOP_CONTROL_REGISTER_S4",
468 .decode.addr = A_SNOOP_CONTROL_REGISTER_S4,
469 .reset = 0xc0000000,
470 .ro = 0xc0000000,
471 },{ .name = "READ_QOS_OVERRIDE_REGISTER_S4",
472 .decode.addr = A_READ_QOS_OVERRIDE_REGISTER_S4,
473 .ro = 0xf00,
474 },{ .name = "WRITE_QOS_OVERRIDE_REGISTER_S4",
475 .decode.addr = A_WRITE_QOS_OVERRIDE_REGISTER_S4,
476 .ro = 0xf00,
477 },{ .name = "QOS_CONTROL_REGISTER_S4",
478 .decode.addr = A_QOS_CONTROL_REGISTER_S4,
479 .ro = 0x80000000,
480 },{ .name = "TARGET_LATENCY_REGISTER_S4",
481 .decode.addr = A_TARGET_LATENCY_REGISTER_S4,
482 },{ .name = "LATENCY_REGULATION_REGISTER_S4",
483 .decode.addr = A_LATENCY_REGULATION_REGISTER_S4,
484 },{ .name = "QOS_RANGE_REGISTER_S4",
485 .decode.addr = A_QOS_RANGE_REGISTER_S4,
486 },{ .name = "CYCLE_COUNTER", .decode.addr = A_CYCLE_COUNTER,
487 },{ .name = "CYCLE_COUNTER_CONTROL",
488 .decode.addr = A_CYCLE_COUNTER_CONTROL,
489 },{ .name = "CYCLE_COUNT_OVERFLOW", .decode.addr = A_CYCLE_COUNT_OVERFLOW,
490 .w1c = 0x1,
491 },{ .name = "ESR0", .decode.addr = A_ESR0,
492 },{ .name = "EVENT_COUNTER0", .decode.addr = A_EVENT_COUNTER0,
493 },{ .name = "EVENT_COUNTER0_CONTROL",
494 .decode.addr = A_EVENT_COUNTER0_CONTROL,
495 },{ .name = "EVENT_COUNTER0_OVERFLOW",
496 .decode.addr = A_EVENT_COUNTER0_OVERFLOW,
497 .w1c = 0x1,
498 },{ .name = "ESR1", .decode.addr = A_ESR1,
499 },{ .name = "EVENT_COUNTER1", .decode.addr = A_EVENT_COUNTER1,
500 },{ .name = "EVENT_COUNTER1_CONTROL",
501 .decode.addr = A_EVENT_COUNTER1_CONTROL,
502 },{ .name = "EVENT_COUNTER1_OVERFLOW",
503 .decode.addr = A_EVENT_COUNTER1_OVERFLOW,
504 .w1c = 0x1,
505 },{ .name = "ESR2", .decode.addr = A_ESR2,
506 },{ .name = "EVENT_COUNTER2", .decode.addr = A_EVENT_COUNTER2,
507 },{ .name = "EVENT_COUNTER2_CONTROL",
508 .decode.addr = A_EVENT_COUNTER2_CONTROL,
509 },{ .name = "EVENT_COUNTER2_OVERFLOW",
510 .decode.addr = A_EVENT_COUNTER2_OVERFLOW,
511 .w1c = 0x1,
512 },{ .name = "ESR3", .decode.addr = A_ESR3,
513 },{ .name = "EVENT_COUNTER3", .decode.addr = A_EVENT_COUNTER3,
514 },{ .name = "EVENT_COUNTER3_CONTROL",
515 .decode.addr = A_EVENT_COUNTER3_CONTROL,
516 },{ .name = "EVENT_COUNTER3_OVERFLOW",
517 .decode.addr = A_EVENT_COUNTER3_OVERFLOW,
518 .w1c = 0x1,
519 }
520};
521
522static void cci400_reset(DeviceState *dev)
523{
524 CCI *s = ARM_CCI400(dev);
525 unsigned int i;
526
527 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
528 dep_register_reset(&s->regs_info[i]);
529 }
530
531}
532
533static uint64_t cci400_read(void *opaque, hwaddr addr, unsigned size)
534{
535 CCI *s = ARM_CCI400(opaque);
536 DepRegisterInfo *r = &s->regs_info[addr / 4];
537
538 if (!r->data) {
539 qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
540 object_get_canonical_path(OBJECT(s)),
541 addr);
542 return 0;
543 }
544 return dep_register_read(r);
545}
546
547static void cci400_write(void *opaque, hwaddr addr, uint64_t value,
548 unsigned size)
549{
550 CCI *s = ARM_CCI400(opaque);
551 DepRegisterInfo *r = &s->regs_info[addr / 4];
552
553 if (!r->data) {
554 qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
555 object_get_canonical_path(OBJECT(s)),
556 addr, value);
557 return;
558 }
559 dep_register_write(r, value, ~0);
560}
561
562static const MemoryRegionOps cci400_ops = {
563 .read = cci400_read,
564 .write = cci400_write,
565 .endianness = DEVICE_LITTLE_ENDIAN,
566 .valid = {
567 .min_access_size = 4,
568 .max_access_size = 4,
569 },
570};
571
572static IOMMUTLBEntry cci_translate(IOMMUMemoryRegion *mr, hwaddr addr,
573 bool is_write, MemTxAttrs *attr)
574{
575 CCI *s = container_of(mr, CCI, iommu);;
576 IOMMUTLBEntry ret = {
577 .iova = addr,
578 .translated_addr = addr,
579 .addr_mask = s->cfg.stripe_granule_sz - 1,
580 .perm = IOMMU_RW,
581 };
582 unsigned int i, mi = 0;
583 bool valid = false;
584
585
586 for (i = 1; i < ARRAY_SIZE(s->as); i++) {
587 bool t;
588 t = address_space_access_valid(s->as[i], addr, 4, false);
589 if (i > 1) {
590 assert(valid == t);
591 }
592 valid = t;
593 }
594 if (valid) {
595 unsigned int stripe_idx = !!(addr & s->cfg.stripe_granule_sz);
596
597 mi = 1 + stripe_idx;
598 }
599
600 ret.target_as = s->as[mi];
601 return ret;
602}
603
604static void cci400_realize(DeviceState *dev, Error **errp)
605{
606 CCI *s = ARM_CCI400(dev);
607 const char *prefix = object_get_canonical_path(OBJECT(dev));
608 unsigned int i;
609
610 for (i = 0; i < ARRAY_SIZE(cci400_regs_info); ++i) {
611 DepRegisterInfo *r = &s->regs_info[cci400_regs_info[i].decode.addr/4];
612
613 *r = (DepRegisterInfo) {
614 .data = (uint8_t *)&s->regs[
615 cci400_regs_info[i].decode.addr/4],
616 .data_size = sizeof(uint32_t),
617 .access = &cci400_regs_info[i],
618 .debug = ARM_CCI400_ERR_DEBUG,
619 .prefix = prefix,
620 .opaque = s,
621 };
622 }
623
624 for (i = 0; i < ARRAY_SIZE(s->M); i++) {
625 s->as[i] = address_space_init_shareable(s->M[i], NULL);
626 assert(s->as[i]);
627 }
628}
629
630static void sig_handler(void *opaque, int n, int level)
631{
632 CCI *s = ARM_CCI400(opaque);
633 uint64_t level64 = level;
634
635 s->enable_mask &= ~(1ULL << n);
636 s->enable_mask |= level64 << n;
637 memory_region_set_enabled(MEMORY_REGION(&s->iommu), !!s->enable_mask);
638}
639
640static void cci400_init(Object *obj)
641{
642 CCI *s = ARM_CCI400(obj);
643 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
644 unsigned int i;
645
646 memory_region_init_io(&s->iomem, obj, &cci400_ops, s,
647 TYPE_ARM_CCI400, R_MAX * 4);
648 sysbus_init_mmio(sbd, &s->iomem);
649
650 memory_region_init_iommu(&s->iommu, sizeof(s->iommu),
651 TYPE_ARM_CCI400_IOMMU_MEMORY_REGION,
652 OBJECT(s),
653 "cci-iommu", UINT64_MAX);
654 sysbus_init_mmio(sbd, MEMORY_REGION(&s->iommu));
655
656 for (i = 0; i < ARRAY_SIZE(s->M); i++) {
657 char *name = g_strdup_printf("M%d", i);
658 object_property_add_link(obj, name, TYPE_MEMORY_REGION,
659 (Object **)&s->M[i],
660 qdev_prop_allow_set_link_before_realize,
661 OBJ_PROP_LINK_UNREF_ON_RELEASE,
662 &error_abort);
663 g_free(name);
664 }
665
666 qdev_init_gpio_in_named(DEVICE(sbd), sig_handler, "enable", 16);
667
668
669 s->cfg.stripe_granule_sz = 4096;
670}
671
672static const VMStateDescription vmstate_cci400 = {
673 .name = TYPE_ARM_CCI400,
674 .version_id = 1,
675 .minimum_version_id = 1,
676 .minimum_version_id_old = 1,
677 .fields = (VMStateField[]) {
678 VMSTATE_UINT32_ARRAY(regs, CCI, R_MAX),
679 VMSTATE_END_OF_LIST(),
680 }
681};
682
683static const FDTGenericGPIOSet gpio_sets[] = {
684 {
685 .names = &fdt_generic_gpio_name_set_gpio,
686 .gpios = (FDTGenericGPIOConnection[]) {
687 { .name = "enable", .fdt_index = 0, .range = 16 },
688 { },
689 },
690 },
691 { },
692};
693
694static void cci400_class_init(ObjectClass *klass, void *data)
695{
696 DeviceClass *dc = DEVICE_CLASS(klass);
697 FDTGenericGPIOClass *fggc = FDT_GENERIC_GPIO_CLASS(klass);
698
699 dc->reset = cci400_reset;
700 dc->realize = cci400_realize;
701 dc->vmsd = &vmstate_cci400;
702 fggc->controller_gpios = gpio_sets;
703}
704
705static void cci400_iommu_memory_region_class_init(ObjectClass *klass,
706 void *data)
707{
708 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
709
710 imrc->translate_attr = cci_translate;
711}
712
713static const TypeInfo cci400_info = {
714 .name = TYPE_ARM_CCI400,
715 .parent = TYPE_SYS_BUS_DEVICE,
716 .instance_size = sizeof(CCI),
717 .class_init = cci400_class_init,
718 .instance_init = cci400_init,
719 .interfaces = (InterfaceInfo[]) {
720 { TYPE_FDT_GENERIC_GPIO },
721 { }
722 },
723};
724
725static const TypeInfo cci400_iommu_memory_region_info = {
726 .name = TYPE_ARM_CCI400_IOMMU_MEMORY_REGION,
727 .parent = TYPE_IOMMU_MEMORY_REGION,
728 .class_init = cci400_iommu_memory_region_class_init,
729};
730
731static void cci400_register_types(void)
732{
733 type_register_static(&cci400_info);
734 type_register_static(&cci400_iommu_memory_region_info);
735}
736
737type_init(cci400_register_types)
738
