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36#include "qemu/osdep.h"
37#include "net/net.h"
38#include "net/tap.h"
39#include "qemu/range.h"
40#include "sysemu/sysemu.h"
41#include "hw/pci/msi.h"
42#include "hw/pci/msix.h"
43
44#include "hw/net/e1000_regs.h"
45
46#include "e1000x_common.h"
47#include "e1000e_core.h"
48
49#include "trace.h"
50#include "qapi/error.h"
51
52#define TYPE_E1000E "e1000e"
53#define E1000E(obj) OBJECT_CHECK(E1000EState, (obj), TYPE_E1000E)
54
55typedef struct E1000EState {
56 PCIDevice parent_obj;
57 NICState *nic;
58 NICConf conf;
59
60 MemoryRegion mmio;
61 MemoryRegion flash;
62 MemoryRegion io;
63 MemoryRegion msix;
64
65 uint32_t ioaddr;
66
67 uint16_t subsys_ven;
68 uint16_t subsys;
69
70 uint16_t subsys_ven_used;
71 uint16_t subsys_used;
72
73 bool disable_vnet;
74
75 E1000ECore core;
76
77} E1000EState;
78
79#define E1000E_MMIO_IDX 0
80#define E1000E_FLASH_IDX 1
81#define E1000E_IO_IDX 2
82#define E1000E_MSIX_IDX 3
83
84#define E1000E_MMIO_SIZE (128 * 1024)
85#define E1000E_FLASH_SIZE (128 * 1024)
86#define E1000E_IO_SIZE (32)
87#define E1000E_MSIX_SIZE (16 * 1024)
88
89#define E1000E_MSIX_TABLE (0x0000)
90#define E1000E_MSIX_PBA (0x2000)
91
92static uint64_t
93e1000e_mmio_read(void *opaque, hwaddr addr, unsigned size)
94{
95 E1000EState *s = opaque;
96 return e1000e_core_read(&s->core, addr, size);
97}
98
99static void
100e1000e_mmio_write(void *opaque, hwaddr addr,
101 uint64_t val, unsigned size)
102{
103 E1000EState *s = opaque;
104 e1000e_core_write(&s->core, addr, val, size);
105}
106
107static bool
108e1000e_io_get_reg_index(E1000EState *s, uint32_t *idx)
109{
110 if (s->ioaddr < 0x1FFFF) {
111 *idx = s->ioaddr;
112 return true;
113 }
114
115 if (s->ioaddr < 0x7FFFF) {
116 trace_e1000e_wrn_io_addr_undefined(s->ioaddr);
117 return false;
118 }
119
120 if (s->ioaddr < 0xFFFFF) {
121 trace_e1000e_wrn_io_addr_flash(s->ioaddr);
122 return false;
123 }
124
125 trace_e1000e_wrn_io_addr_unknown(s->ioaddr);
126 return false;
127}
128
129static uint64_t
130e1000e_io_read(void *opaque, hwaddr addr, unsigned size)
131{
132 E1000EState *s = opaque;
133 uint32_t idx = 0;
134 uint64_t val;
135
136 switch (addr) {
137 case E1000_IOADDR:
138 trace_e1000e_io_read_addr(s->ioaddr);
139 return s->ioaddr;
140 case E1000_IODATA:
141 if (e1000e_io_get_reg_index(s, &idx)) {
142 val = e1000e_core_read(&s->core, idx, sizeof(val));
143 trace_e1000e_io_read_data(idx, val);
144 return val;
145 }
146 return 0;
147 default:
148 trace_e1000e_wrn_io_read_unknown(addr);
149 return 0;
150 }
151}
152
153static void
154e1000e_io_write(void *opaque, hwaddr addr,
155 uint64_t val, unsigned size)
156{
157 E1000EState *s = opaque;
158 uint32_t idx = 0;
159
160 switch (addr) {
161 case E1000_IOADDR:
162 trace_e1000e_io_write_addr(val);
163 s->ioaddr = (uint32_t) val;
164 return;
165 case E1000_IODATA:
166 if (e1000e_io_get_reg_index(s, &idx)) {
167 trace_e1000e_io_write_data(idx, val);
168 e1000e_core_write(&s->core, idx, val, sizeof(val));
169 }
170 return;
171 default:
172 trace_e1000e_wrn_io_write_unknown(addr);
173 return;
174 }
175}
176
177static const MemoryRegionOps mmio_ops = {
178 .read = e1000e_mmio_read,
179 .write = e1000e_mmio_write,
180 .endianness = DEVICE_LITTLE_ENDIAN,
181 .impl = {
182 .min_access_size = 4,
183 .max_access_size = 4,
184 },
185};
186
187static const MemoryRegionOps io_ops = {
188 .read = e1000e_io_read,
189 .write = e1000e_io_write,
190 .endianness = DEVICE_LITTLE_ENDIAN,
191 .impl = {
192 .min_access_size = 4,
193 .max_access_size = 4,
194 },
195};
196
197static int
198e1000e_nc_can_receive(NetClientState *nc)
199{
200 E1000EState *s = qemu_get_nic_opaque(nc);
201 return e1000e_can_receive(&s->core);
202}
203
204static ssize_t
205e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
206{
207 E1000EState *s = qemu_get_nic_opaque(nc);
208 return e1000e_receive_iov(&s->core, iov, iovcnt);
209}
210
211static ssize_t
212e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size)
213{
214 E1000EState *s = qemu_get_nic_opaque(nc);
215 return e1000e_receive(&s->core, buf, size);
216}
217
218static void
219e1000e_set_link_status(NetClientState *nc)
220{
221 E1000EState *s = qemu_get_nic_opaque(nc);
222 e1000e_core_set_link_status(&s->core);
223}
224
225static NetClientInfo net_e1000e_info = {
226 .type = NET_CLIENT_DRIVER_NIC,
227 .size = sizeof(NICState),
228 .can_receive = e1000e_nc_can_receive,
229 .receive = e1000e_nc_receive,
230 .receive_iov = e1000e_nc_receive_iov,
231 .link_status_changed = e1000e_set_link_status,
232};
233
234
235
236
237
238static const uint16_t e1000e_eeprom_template[64] = {
239
240 0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff,
241
242 0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058,
243
244 0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704,
245
246 0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706,
247
248 0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff,
249
250 0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff,
251
252 0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff,
253
254 0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000,
255};
256
257static void e1000e_core_realize(E1000EState *s)
258{
259 s->core.owner = &s->parent_obj;
260 s->core.owner_nic = s->nic;
261}
262
263static void
264e1000e_unuse_msix_vectors(E1000EState *s, int num_vectors)
265{
266 int i;
267 for (i = 0; i < num_vectors; i++) {
268 msix_vector_unuse(PCI_DEVICE(s), i);
269 }
270}
271
272static bool
273e1000e_use_msix_vectors(E1000EState *s, int num_vectors)
274{
275 int i;
276 for (i = 0; i < num_vectors; i++) {
277 int res = msix_vector_use(PCI_DEVICE(s), i);
278 if (res < 0) {
279 trace_e1000e_msix_use_vector_fail(i, res);
280 e1000e_unuse_msix_vectors(s, i);
281 return false;
282 }
283 }
284 return true;
285}
286
287static void
288e1000e_init_msix(E1000EState *s)
289{
290 PCIDevice *d = PCI_DEVICE(s);
291 int res = msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM,
292 &s->msix,
293 E1000E_MSIX_IDX, E1000E_MSIX_TABLE,
294 &s->msix,
295 E1000E_MSIX_IDX, E1000E_MSIX_PBA,
296 0xA0, NULL);
297
298 if (res < 0) {
299 trace_e1000e_msix_init_fail(res);
300 } else {
301 if (!e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM)) {
302 msix_uninit(d, &s->msix, &s->msix);
303 }
304 }
305}
306
307static void
308e1000e_cleanup_msix(E1000EState *s)
309{
310 if (msix_present(PCI_DEVICE(s))) {
311 e1000e_unuse_msix_vectors(s, E1000E_MSIX_VEC_NUM);
312 msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix);
313 }
314}
315
316static void
317e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr)
318{
319 DeviceState *dev = DEVICE(pci_dev);
320 NetClientState *nc;
321 int i;
322
323 s->nic = qemu_new_nic(&net_e1000e_info, &s->conf,
324 object_get_typename(OBJECT(s)), dev->id, s);
325
326 s->core.max_queue_num = s->conf.peers.queues - 1;
327
328 trace_e1000e_mac_set_permanent(MAC_ARG(macaddr));
329 memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac));
330
331 qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr);
332
333
334 if (s->disable_vnet) {
335 s->core.has_vnet = false;
336 trace_e1000e_cfg_support_virtio(false);
337 return;
338 } else {
339 s->core.has_vnet = true;
340 }
341
342 for (i = 0; i < s->conf.peers.queues; i++) {
343 nc = qemu_get_subqueue(s->nic, i);
344 if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) {
345 s->core.has_vnet = false;
346 trace_e1000e_cfg_support_virtio(false);
347 return;
348 }
349 }
350
351 trace_e1000e_cfg_support_virtio(true);
352
353 for (i = 0; i < s->conf.peers.queues; i++) {
354 nc = qemu_get_subqueue(s->nic, i);
355 qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr));
356 qemu_using_vnet_hdr(nc->peer, true);
357 }
358}
359
360static inline uint64_t
361e1000e_gen_dsn(uint8_t *mac)
362{
363 return (uint64_t)(mac[5]) |
364 (uint64_t)(mac[4]) << 8 |
365 (uint64_t)(mac[3]) << 16 |
366 (uint64_t)(0x00FF) << 24 |
367 (uint64_t)(0x00FF) << 32 |
368 (uint64_t)(mac[2]) << 40 |
369 (uint64_t)(mac[1]) << 48 |
370 (uint64_t)(mac[0]) << 56;
371}
372
373static int
374e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
375{
376 Error *local_err = NULL;
377 int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset,
378 PCI_PM_SIZEOF, &local_err);
379
380 if (local_err) {
381 error_report_err(local_err);
382 return ret;
383 }
384
385 pci_set_word(pdev->config + offset + PCI_PM_PMC,
386 PCI_PM_CAP_VER_1_1 |
387 pmc);
388
389 pci_set_word(pdev->wmask + offset + PCI_PM_CTRL,
390 PCI_PM_CTRL_STATE_MASK |
391 PCI_PM_CTRL_PME_ENABLE |
392 PCI_PM_CTRL_DATA_SEL_MASK);
393
394 pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL,
395 PCI_PM_CTRL_PME_STATUS);
396
397 return ret;
398}
399
400static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address,
401 uint32_t val, int len)
402{
403 E1000EState *s = E1000E(pci_dev);
404
405 pci_default_write_config(pci_dev, address, val, len);
406
407 if (range_covers_byte(address, len, PCI_COMMAND) &&
408 (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
409 e1000e_start_recv(&s->core);
410 }
411}
412
413static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
414{
415 static const uint16_t e1000e_pmrb_offset = 0x0C8;
416 static const uint16_t e1000e_pcie_offset = 0x0E0;
417 static const uint16_t e1000e_aer_offset = 0x100;
418 static const uint16_t e1000e_dsn_offset = 0x140;
419 E1000EState *s = E1000E(pci_dev);
420 uint8_t *macaddr;
421 int ret;
422
423 trace_e1000e_cb_pci_realize();
424
425 pci_dev->config_write = e1000e_write_config;
426
427 pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
428 pci_dev->config[PCI_INTERRUPT_PIN] = 1;
429
430 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven);
431 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys);
432
433 s->subsys_ven_used = s->subsys_ven;
434 s->subsys_used = s->subsys;
435
436
437 memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s,
438 "e1000e-mmio", E1000E_MMIO_SIZE);
439 pci_register_bar(pci_dev, E1000E_MMIO_IDX,
440 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
441
442
443
444
445
446 memory_region_init(&s->flash, OBJECT(s),
447 "e1000e-flash", E1000E_FLASH_SIZE);
448 pci_register_bar(pci_dev, E1000E_FLASH_IDX,
449 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash);
450
451 memory_region_init_io(&s->io, OBJECT(s), &io_ops, s,
452 "e1000e-io", E1000E_IO_SIZE);
453 pci_register_bar(pci_dev, E1000E_IO_IDX,
454 PCI_BASE_ADDRESS_SPACE_IO, &s->io);
455
456 memory_region_init(&s->msix, OBJECT(s), "e1000e-msix",
457 E1000E_MSIX_SIZE);
458 pci_register_bar(pci_dev, E1000E_MSIX_IDX,
459 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix);
460
461
462 qemu_macaddr_default_if_unset(&s->conf.macaddr);
463 macaddr = s->conf.macaddr.a;
464
465 e1000e_init_msix(s);
466
467 if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) {
468 hw_error("Failed to initialize PCIe capability");
469 }
470
471 ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL);
472 if (ret) {
473 trace_e1000e_msi_init_fail(ret);
474 }
475
476 if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset,
477 PCI_PM_CAP_DSI) < 0) {
478 hw_error("Failed to initialize PM capability");
479 }
480
481 if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset,
482 PCI_ERR_SIZEOF, NULL) < 0) {
483 hw_error("Failed to initialize AER capability");
484 }
485
486 pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset,
487 e1000e_gen_dsn(macaddr));
488
489 e1000e_init_net_peer(s, pci_dev, macaddr);
490
491
492 e1000e_core_realize(s);
493
494 e1000e_core_pci_realize(&s->core,
495 e1000e_eeprom_template,
496 sizeof(e1000e_eeprom_template),
497 macaddr);
498}
499
500static void e1000e_pci_uninit(PCIDevice *pci_dev)
501{
502 E1000EState *s = E1000E(pci_dev);
503
504 trace_e1000e_cb_pci_uninit();
505
506 e1000e_core_pci_uninit(&s->core);
507
508 pcie_aer_exit(pci_dev);
509 pcie_cap_exit(pci_dev);
510
511 qemu_del_nic(s->nic);
512
513 e1000e_cleanup_msix(s);
514 msi_uninit(pci_dev);
515}
516
517static void e1000e_qdev_reset(DeviceState *dev)
518{
519 E1000EState *s = E1000E(dev);
520
521 trace_e1000e_cb_qdev_reset();
522
523 e1000e_core_reset(&s->core);
524}
525
526static int e1000e_pre_save(void *opaque)
527{
528 E1000EState *s = opaque;
529
530 trace_e1000e_cb_pre_save();
531
532 e1000e_core_pre_save(&s->core);
533
534 return 0;
535}
536
537static int e1000e_post_load(void *opaque, int version_id)
538{
539 E1000EState *s = opaque;
540
541 trace_e1000e_cb_post_load();
542
543 if ((s->subsys != s->subsys_used) ||
544 (s->subsys_ven != s->subsys_ven_used)) {
545 fprintf(stderr,
546 "ERROR: Cannot migrate while device properties "
547 "(subsys/subsys_ven) differ");
548 return -1;
549 }
550
551 return e1000e_core_post_load(&s->core);
552}
553
554static const VMStateDescription e1000e_vmstate_tx = {
555 .name = "e1000e-tx",
556 .version_id = 1,
557 .minimum_version_id = 1,
558 .fields = (VMStateField[]) {
559 VMSTATE_UINT8(props.sum_needed, struct e1000e_tx),
560 VMSTATE_UINT8(props.ipcss, struct e1000e_tx),
561 VMSTATE_UINT8(props.ipcso, struct e1000e_tx),
562 VMSTATE_UINT16(props.ipcse, struct e1000e_tx),
563 VMSTATE_UINT8(props.tucss, struct e1000e_tx),
564 VMSTATE_UINT8(props.tucso, struct e1000e_tx),
565 VMSTATE_UINT16(props.tucse, struct e1000e_tx),
566 VMSTATE_UINT8(props.hdr_len, struct e1000e_tx),
567 VMSTATE_UINT16(props.mss, struct e1000e_tx),
568 VMSTATE_UINT32(props.paylen, struct e1000e_tx),
569 VMSTATE_INT8(props.ip, struct e1000e_tx),
570 VMSTATE_INT8(props.tcp, struct e1000e_tx),
571 VMSTATE_BOOL(props.tse, struct e1000e_tx),
572 VMSTATE_BOOL(props.cptse, struct e1000e_tx),
573 VMSTATE_BOOL(skip_cp, struct e1000e_tx),
574 VMSTATE_END_OF_LIST()
575 }
576};
577
578static const VMStateDescription e1000e_vmstate_intr_timer = {
579 .name = "e1000e-intr-timer",
580 .version_id = 1,
581 .minimum_version_id = 1,
582 .fields = (VMStateField[]) {
583 VMSTATE_TIMER_PTR(timer, E1000IntrDelayTimer),
584 VMSTATE_BOOL(running, E1000IntrDelayTimer),
585 VMSTATE_END_OF_LIST()
586 }
587};
588
589#define VMSTATE_E1000E_INTR_DELAY_TIMER(_f, _s) \
590 VMSTATE_STRUCT(_f, _s, 0, \
591 e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
592
593#define VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(_f, _s, _num) \
594 VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0, \
595 e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
596
597static const VMStateDescription e1000e_vmstate = {
598 .name = "e1000e",
599 .version_id = 1,
600 .minimum_version_id = 1,
601 .pre_save = e1000e_pre_save,
602 .post_load = e1000e_post_load,
603 .fields = (VMStateField[]) {
604 VMSTATE_PCI_DEVICE(parent_obj, E1000EState),
605 VMSTATE_MSIX(parent_obj, E1000EState),
606
607 VMSTATE_UINT32(ioaddr, E1000EState),
608 VMSTATE_UINT32(core.rxbuf_min_shift, E1000EState),
609 VMSTATE_UINT8(core.rx_desc_len, E1000EState),
610 VMSTATE_UINT32_ARRAY(core.rxbuf_sizes, E1000EState,
611 E1000_PSRCTL_BUFFS_PER_DESC),
612 VMSTATE_UINT32(core.rx_desc_buf_size, E1000EState),
613 VMSTATE_UINT16_ARRAY(core.eeprom, E1000EState, E1000E_EEPROM_SIZE),
614 VMSTATE_UINT16_2DARRAY(core.phy, E1000EState,
615 E1000E_PHY_PAGES, E1000E_PHY_PAGE_SIZE),
616 VMSTATE_UINT32_ARRAY(core.mac, E1000EState, E1000E_MAC_SIZE),
617 VMSTATE_UINT8_ARRAY(core.permanent_mac, E1000EState, ETH_ALEN),
618
619 VMSTATE_UINT32(core.delayed_causes, E1000EState),
620
621 VMSTATE_UINT16(subsys, E1000EState),
622 VMSTATE_UINT16(subsys_ven, E1000EState),
623
624 VMSTATE_E1000E_INTR_DELAY_TIMER(core.rdtr, E1000EState),
625 VMSTATE_E1000E_INTR_DELAY_TIMER(core.radv, E1000EState),
626 VMSTATE_E1000E_INTR_DELAY_TIMER(core.raid, E1000EState),
627 VMSTATE_E1000E_INTR_DELAY_TIMER(core.tadv, E1000EState),
628 VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState),
629
630 VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState),
631 VMSTATE_BOOL(core.itr_intr_pending, E1000EState),
632
633 VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState,
634 E1000E_MSIX_VEC_NUM),
635 VMSTATE_BOOL_ARRAY(core.eitr_intr_pending, E1000EState,
636 E1000E_MSIX_VEC_NUM),
637
638 VMSTATE_UINT32(core.itr_guest_value, E1000EState),
639 VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState,
640 E1000E_MSIX_VEC_NUM),
641
642 VMSTATE_UINT16(core.vet, E1000EState),
643
644 VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0,
645 e1000e_vmstate_tx, struct e1000e_tx),
646 VMSTATE_END_OF_LIST()
647 }
648};
649
650static PropertyInfo e1000e_prop_disable_vnet,
651 e1000e_prop_subsys_ven,
652 e1000e_prop_subsys;
653
654static Property e1000e_properties[] = {
655 DEFINE_NIC_PROPERTIES(E1000EState, conf),
656 DEFINE_PROP_SIGNED("disable_vnet_hdr", E1000EState, disable_vnet, false,
657 e1000e_prop_disable_vnet, bool),
658 DEFINE_PROP_SIGNED("subsys_ven", E1000EState, subsys_ven,
659 PCI_VENDOR_ID_INTEL,
660 e1000e_prop_subsys_ven, uint16_t),
661 DEFINE_PROP_SIGNED("subsys", E1000EState, subsys, 0,
662 e1000e_prop_subsys, uint16_t),
663 DEFINE_PROP_END_OF_LIST(),
664};
665
666static void e1000e_class_init(ObjectClass *class, void *data)
667{
668 DeviceClass *dc = DEVICE_CLASS(class);
669 PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
670
671 c->realize = e1000e_pci_realize;
672 c->exit = e1000e_pci_uninit;
673 c->vendor_id = PCI_VENDOR_ID_INTEL;
674 c->device_id = E1000_DEV_ID_82574L;
675 c->revision = 0;
676 c->romfile = "efi-e1000e.rom";
677 c->class_id = PCI_CLASS_NETWORK_ETHERNET;
678 c->is_express = 1;
679
680 dc->desc = "Intel 82574L GbE Controller";
681 dc->reset = e1000e_qdev_reset;
682 dc->vmsd = &e1000e_vmstate;
683 dc->props = e1000e_properties;
684
685 e1000e_prop_disable_vnet = qdev_prop_uint8;
686 e1000e_prop_disable_vnet.description = "Do not use virtio headers, "
687 "perform SW offloads emulation "
688 "instead";
689
690 e1000e_prop_subsys_ven = qdev_prop_uint16;
691 e1000e_prop_subsys_ven.description = "PCI device Subsystem Vendor ID";
692
693 e1000e_prop_subsys = qdev_prop_uint16;
694 e1000e_prop_subsys.description = "PCI device Subsystem ID";
695
696 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
697}
698
699static void e1000e_instance_init(Object *obj)
700{
701 E1000EState *s = E1000E(obj);
702 device_add_bootindex_property(obj, &s->conf.bootindex,
703 "bootindex", "/ethernet-phy@0",
704 DEVICE(obj), NULL);
705}
706
707static const TypeInfo e1000e_info = {
708 .name = TYPE_E1000E,
709 .parent = TYPE_PCI_DEVICE,
710 .instance_size = sizeof(E1000EState),
711 .class_init = e1000e_class_init,
712 .instance_init = e1000e_instance_init,
713 .interfaces = (InterfaceInfo[]) {
714 { INTERFACE_PCIE_DEVICE },
715 { }
716 },
717};
718
719static void e1000e_register_types(void)
720{
721 type_register_static(&e1000e_info);
722}
723
724type_init(e1000e_register_types)
725
