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28#include "qemu/osdep.h"
29#include "hw/sysbus.h"
30#include "hw/register-dep.h"
31#include "qemu/bitops.h"
32#include "qemu/log.h"
33
34#ifndef XILINX_PCIE_ATTRIB_ERR_DEBUG
35#define XILINX_PCIE_ATTRIB_ERR_DEBUG 0
36#endif
37
38#define TYPE_XILINX_PCIE_ATTRIB "xlnx.nwl-pcie-attrib"
39
40#define XILINX_PCIE_ATTRIB(obj) \
41 OBJECT_CHECK(PCIE_ATTRIB, (obj), TYPE_XILINX_PCIE_ATTRIB)
42
43DEP_REG32(ATTR_0, 0x0)
44 DEP_FIELD(ATTR_0, ATTR_AER_CAP_ECRC_GEN_CAPABLE, 1, 1)
45 DEP_FIELD(ATTR_0, ATTR_AER_CAP_ECRC_CHECK_CAPABLE, 1, 0)
46DEP_REG32(ATTR_1, 0x4)
47 DEP_FIELD(ATTR_1, ATTR_AER_CAP_ID, 16, 0)
48DEP_REG32(ATTR_2, 0x8)
49 DEP_FIELD(ATTR_2, ATTR_AER_CAP_VERSION, 4, 1)
50 DEP_FIELD(ATTR_2, ATTR_AER_CAP_PERMIT_ROOTERR_UPDATE, 1, 0)
51DEP_REG32(ATTR_3, 0xc)
52 DEP_FIELD(ATTR_3, ATTR_AER_BASE_PTR, 12, 0)
53DEP_REG32(ATTR_4, 0x10)
54 DEP_FIELD(ATTR_4, ATTR_AER_CAP_ON, 1, 12)
55 DEP_FIELD(ATTR_4, ATTR_AER_CAP_NEXTPTR, 12, 0)
56DEP_REG32(ATTR_5, 0x14)
57 DEP_FIELD(ATTR_5, ATTR_AER_CAP_OPTIONAL_ERR_SUPPORT, 16, 0)
58DEP_REG32(ATTR_6, 0x18)
59 DEP_FIELD(ATTR_6, ATTR_AER_CAP_MULTIHEADER, 1, 8)
60 DEP_FIELD(ATTR_6, ATTR_AER_CAP_OPTIONAL_ERR_SUPPORT, 8, 0)
61DEP_REG32(ATTR_7, 0x1c)
62 DEP_FIELD(ATTR_7, ATTR_BAR0, 16, 0)
63DEP_REG32(ATTR_8, 0x20)
64 DEP_FIELD(ATTR_8, ATTR_BAR0, 16, 0)
65DEP_REG32(ATTR_9, 0x24)
66 DEP_FIELD(ATTR_9, ATTR_BAR1, 16, 0)
67DEP_REG32(ATTR_10, 0x28)
68 DEP_FIELD(ATTR_10, ATTR_BAR1, 16, 0)
69DEP_REG32(ATTR_11, 0x2c)
70 DEP_FIELD(ATTR_11, ATTR_BAR2, 16, 0)
71DEP_REG32(ATTR_12, 0x30)
72 DEP_FIELD(ATTR_12, ATTR_BAR2, 16, 0)
73DEP_REG32(ATTR_13, 0x34)
74 DEP_FIELD(ATTR_13, ATTR_BAR3, 16, 0)
75DEP_REG32(ATTR_14, 0x38)
76 DEP_FIELD(ATTR_14, ATTR_BAR3, 16, 0)
77DEP_REG32(ATTR_15, 0x3c)
78 DEP_FIELD(ATTR_15, ATTR_BAR4, 16, 0)
79DEP_REG32(ATTR_16, 0x40)
80 DEP_FIELD(ATTR_16, ATTR_BAR4, 16, 0)
81DEP_REG32(ATTR_17, 0x44)
82 DEP_FIELD(ATTR_17, ATTR_BAR5, 16, 0)
83DEP_REG32(ATTR_18, 0x48)
84 DEP_FIELD(ATTR_18, ATTR_BAR5, 16, 0)
85DEP_REG32(ATTR_19, 0x4c)
86 DEP_FIELD(ATTR_19, ATTR_EXPANSION_ROM, 16, 0)
87DEP_REG32(ATTR_20, 0x50)
88 DEP_FIELD(ATTR_20, ATTR_EXPANSION_ROM, 16, 0)
89DEP_REG32(ATTR_21, 0x54)
90 DEP_FIELD(ATTR_21, ATTR_CAPABILITIES_PTR, 8, 0)
91DEP_REG32(ATTR_22, 0x58)
92 DEP_FIELD(ATTR_22, ATTR_CARDBUS_CIS_POINTER, 16, 0)
93DEP_REG32(ATTR_23, 0x5c)
94 DEP_FIELD(ATTR_23, ATTR_CARDBUS_CIS_POINTER, 16, 0)
95DEP_REG32(ATTR_24, 0x60)
96 DEP_FIELD(ATTR_24, ATTR_CLASS_CODE, 16, 0)
97DEP_REG32(ATTR_25, 0x64)
98 DEP_FIELD(ATTR_25, ATTR_DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED, 1, 15)
99 DEP_FIELD(ATTR_25, ATTR_DEV_CAP2_ARI_FORWARDING_SUPPORTED, 1, 14)
100 DEP_FIELD(ATTR_25, ATTR_CPL_TIMEOUT_RANGES_SUPPORTED, 4, 10)
101 DEP_FIELD(ATTR_25, ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED, 1, 9)
102 DEP_FIELD(ATTR_25, ATTR_CMD_INTX_IMPLEMENTED, 1, 8)
103 DEP_FIELD(ATTR_25, ATTR_CLASS_CODE, 8, 0)
104DEP_REG32(ATTR_26, 0x68)
105 DEP_FIELD(ATTR_26, ATTR_DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE, 1, 13)
106 DEP_FIELD(ATTR_26, ATTR_DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE, 1, 12)
107 DEP_FIELD(ATTR_26, ATTR_ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED, 1, 11)
108 DEP_FIELD(ATTR_26, ATTR_DEV_CAP2_MAX_ENDEND_TLP_PREFIXES, 2, 9)
109 DEP_FIELD(ATTR_26, ATTR_DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED, 1, 8)
110 DEP_FIELD(ATTR_26, ATTR_DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED, 1, 7)
111 DEP_FIELD(ATTR_26, ATTR_DEV_CAP2_TPH_COMPLETER_SUPPORTED, 2, 5)
112 DEP_FIELD(ATTR_26, ATTR_DEV_CAP2_LTR_MECHANISM_SUPPORTED, 1, 4)
113 DEP_FIELD(ATTR_26, ATTR_DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING, 1, 3)
114 DEP_FIELD(ATTR_26, ATTR_DEV_CAP2_CAS128_COMPLETER_SUPPORTED, 1, 2)
115 DEP_FIELD(ATTR_26, ATTR_DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED, 1, 1)
116 DEP_FIELD(ATTR_26, ATTR_DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED, 1, 0)
117DEP_REG32(ATTR_27, 0x6c)
118 DEP_FIELD(ATTR_27, ATTR_DEV_CAP_ROLE_BASED_ERROR, 1, 13)
119 DEP_FIELD(ATTR_27, ATTR_DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT, 2, 11)
120 DEP_FIELD(ATTR_27, ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED, 3, 8)
121 DEP_FIELD(ATTR_27, ATTR_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE, 1, 7)
122 DEP_FIELD(ATTR_27, ATTR_DEV_CAP_EXT_TAG_SUPPORTED, 1, 6)
123 DEP_FIELD(ATTR_27, ATTR_DEV_CAP_ENDPOINT_L1_LATENCY, 3, 3)
124 DEP_FIELD(ATTR_27, ATTR_DEV_CAP_ENDPOINT_L0S_LATENCY, 3, 0)
125DEP_REG32(ATTR_28, 0x70)
126 DEP_FIELD(ATTR_28, ATTR_DEV_CONTROL_EXT_TAG_DEFAULT, 1, 9)
127 DEP_FIELD(ATTR_28, ATTR_DEV_CONTROL_AUX_POWER_SUPPORTED, 1, 8)
128 DEP_FIELD(ATTR_28, ATTR_DEV_CAP_RSVD_31_29, 3, 5)
129 DEP_FIELD(ATTR_28, ATTR_DEV_CAP_RSVD_17_16, 2, 3)
130 DEP_FIELD(ATTR_28, ATTR_DEV_CAP_RSVD_14_12, 3, 0)
131DEP_REG32(ATTR_29, 0x74)
132 DEP_FIELD(ATTR_29, ATTR_DSN_BASE_PTR, 12, 0)
133DEP_REG32(ATTR_30, 0x78)
134 DEP_FIELD(ATTR_30, ATTR_DSN_CAP_ID, 16, 0)
135DEP_REG32(ATTR_31, 0x7c)
136 DEP_FIELD(ATTR_31, ATTR_DSN_CAP_ON, 1, 12)
137 DEP_FIELD(ATTR_31, ATTR_DSN_CAP_NEXTPTR, 12, 0)
138DEP_REG32(ATTR_32, 0x80)
139 DEP_FIELD(ATTR_32, ATTR_EXT_CFG_CAP_PTR, 6, 4)
140 DEP_FIELD(ATTR_32, ATTR_DSN_CAP_VERSION, 4, 0)
141DEP_REG32(ATTR_33, 0x84)
142 DEP_FIELD(ATTR_33, ATTR_EXT_CFG_XP_CAP_PTR, 10, 0)
143DEP_REG32(ATTR_34, 0x88)
144 DEP_FIELD(ATTR_34, ATTR_INTERRUPT_PIN, 8, 8)
145 DEP_FIELD(ATTR_34, ATTR_HEADER_TYPE, 8, 0)
146DEP_REG32(ATTR_35, 0x8c)
147 DEP_FIELD(ATTR_35, ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP, 1, 15)
148 DEP_FIELD(ATTR_35, ATTR_LINK_CAP_CLOCK_POWER_MANAGEMENT, 1, 14)
149 DEP_FIELD(ATTR_35, ATTR_LINK_CAP_ASPM_SUPPORT, 2, 12)
150 DEP_FIELD(ATTR_35, ATTR_LAST_CONFIG_DWORD, 10, 2)
151 DEP_FIELD(ATTR_35, ATTR_IS_SWITCH, 1, 1)
152 DEP_FIELD(ATTR_35, ATTR_INTERRUPT_STAT_AUTO, 1, 0)
153DEP_REG32(ATTR_36, 0x90)
154 DEP_FIELD(ATTR_36, ATTR_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1, 3, 12)
155 DEP_FIELD(ATTR_36, ATTR_LINK_CAP_L0S_EXIT_LATENCY_GEN2, 3, 9)
156 DEP_FIELD(ATTR_36, ATTR_LINK_CAP_L0S_EXIT_LATENCY_GEN1, 3, 6)
157 DEP_FIELD(ATTR_36, ATTR_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2, 3, 3)
158 DEP_FIELD(ATTR_36, ATTR_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1, 3, 0)
159DEP_REG32(ATTR_37, 0x94)
160 DEP_FIELD(ATTR_37, ATTR_LINK_CAP_RSVD_23, 1, 15)
161 DEP_FIELD(ATTR_37, ATTR_LINK_CAP_ASPM_OPTIONALITY, 1, 14)
162 DEP_FIELD(ATTR_37, ATTR_LINK_CAP_MAX_LINK_SPEED, 4, 10)
163 DEP_FIELD(ATTR_37, ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP, 1, 9)
164 DEP_FIELD(ATTR_37, ATTR_LINK_CAP_L1_EXIT_LATENCY_GEN2, 3, 6)
165 DEP_FIELD(ATTR_37, ATTR_LINK_CAP_L1_EXIT_LATENCY_GEN1, 3, 3)
166 DEP_FIELD(ATTR_37, ATTR_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2, 3, 0)
167DEP_REG32(ATTR_38, 0x98)
168 DEP_FIELD(ATTR_38, ATTR_MPS_FORCE, 1, 9)
169 DEP_FIELD(ATTR_38, ATTR_LINK_STATUS_SLOT_CLOCK_CONFIG, 1, 8)
170 DEP_FIELD(ATTR_38, ATTR_LINK_CTRL2_TARGET_LINK_SPEED, 4, 4)
171 DEP_FIELD(ATTR_38, ATTR_LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE, 1, 3)
172 DEP_FIELD(ATTR_38, ATTR_LINK_CTRL2_DEEMPHASIS, 1, 2)
173 DEP_FIELD(ATTR_38, ATTR_LINK_CONTROL_RCB, 1, 1)
174 DEP_FIELD(ATTR_38, ATTR_LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE, 1, 0)
175DEP_REG32(ATTR_39, 0x9c)
176 DEP_FIELD(ATTR_39, ATTR_MSI_CAP_64_BIT_ADDR_CAPABLE, 1, 8)
177 DEP_FIELD(ATTR_39, ATTR_MSI_BASE_PTR, 8, 0)
178DEP_REG32(ATTR_40, 0xa0)
179 DEP_FIELD(ATTR_40, ATTR_MSI_CAP_MULTIMSGCAP, 3, 9)
180 DEP_FIELD(ATTR_40, ATTR_MSI_CAP_MULTIMSG_EXTENSION, 1, 8)
181 DEP_FIELD(ATTR_40, ATTR_MSI_CAP_ID, 8, 0)
182DEP_REG32(ATTR_41, 0xa4)
183 DEP_FIELD(ATTR_41, ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE, 1, 9)
184 DEP_FIELD(ATTR_41, ATTR_MSI_CAP_ON, 1, 8)
185 DEP_FIELD(ATTR_41, ATTR_MSI_CAP_NEXTPTR, 8, 0)
186DEP_REG32(ATTR_42, 0xa8)
187 DEP_FIELD(ATTR_42, ATTR_MSIX_CAP_ID, 8, 8)
188 DEP_FIELD(ATTR_42, ATTR_MSIX_BASE_PTR, 8, 0)
189DEP_REG32(ATTR_43, 0xac)
190 DEP_FIELD(ATTR_43, ATTR_MSIX_CAP_PBA_BIR, 3, 9)
191 DEP_FIELD(ATTR_43, ATTR_MSIX_CAP_ON, 1, 8)
192 DEP_FIELD(ATTR_43, ATTR_MSIX_CAP_NEXTPTR, 8, 0)
193DEP_REG32(ATTR_44, 0xb0)
194 DEP_FIELD(ATTR_44, ATTR_MSIX_CAP_PBA_OFFSET, 16, 0)
195DEP_REG32(ATTR_45, 0xb4)
196 DEP_FIELD(ATTR_45, ATTR_MSIX_CAP_PBA_OFFSET, 13, 3)
197 DEP_FIELD(ATTR_45, ATTR_MSIX_CAP_TABLE_BIR, 3, 0)
198DEP_REG32(ATTR_46, 0xb8)
199 DEP_FIELD(ATTR_46, ATTR_MSIX_CAP_TABLE_OFFSET, 16, 0)
200DEP_REG32(ATTR_47, 0xbc)
201 DEP_FIELD(ATTR_47, ATTR_MSIX_CAP_TABLE_OFFSET, 13, 0)
202DEP_REG32(ATTR_48, 0xc0)
203 DEP_FIELD(ATTR_48, ATTR_MSIX_CAP_TABLE_SIZE, 11, 0)
204DEP_REG32(ATTR_49, 0xc4)
205 DEP_FIELD(ATTR_49, ATTR_PCIE_CAP_CAPABILITY_ID, 8, 8)
206 DEP_FIELD(ATTR_49, ATTR_PCIE_BASE_PTR, 8, 0)
207DEP_REG32(ATTR_50, 0xc8)
208 DEP_FIELD(ATTR_50, ATTR_PCIE_CAP_NEXTPTR, 8, 8)
209 DEP_FIELD(ATTR_50, ATTR_PCIE_CAP_DEVICE_PORT_TYPE, 4, 4)
210 DEP_FIELD(ATTR_50, ATTR_PCIE_CAP_CAPABILITY_VERSION, 4, 0)
211DEP_REG32(ATTR_51, 0xcc)
212 DEP_FIELD(ATTR_51, ATTR_PM_BASE_PTR, 8, 8)
213 DEP_FIELD(ATTR_51, ATTR_PCIE_REVISION, 4, 4)
214 DEP_FIELD(ATTR_51, ATTR_PCIE_CAP_SLOT_IMPLEMENTED, 1, 3)
215 DEP_FIELD(ATTR_51, ATTR_PCIE_CAP_RSVD_15_14, 2, 1)
216 DEP_FIELD(ATTR_51, ATTR_PCIE_CAP_ON, 1, 0)
217DEP_REG32(ATTR_52, 0xd0)
218 DEP_FIELD(ATTR_52, ATTR_PM_CAP_ID, 8, 6)
219 DEP_FIELD(ATTR_52, ATTR_PM_CAP_DSI, 1, 5)
220 DEP_FIELD(ATTR_52, ATTR_PM_CAP_D2SUPPORT, 1, 4)
221 DEP_FIELD(ATTR_52, ATTR_PM_CAP_D1SUPPORT, 1, 3)
222 DEP_FIELD(ATTR_52, ATTR_PM_CAP_AUXCURRENT, 3, 0)
223DEP_REG32(ATTR_53, 0xd4)
224 DEP_FIELD(ATTR_53, ATTR_PM_CAP_RSVD_04, 1, 15)
225 DEP_FIELD(ATTR_53, ATTR_PM_CAP_PMESUPPORT, 5, 10)
226 DEP_FIELD(ATTR_53, ATTR_PM_CAP_PME_CLOCK, 1, 9)
227 DEP_FIELD(ATTR_53, ATTR_PM_CAP_ON, 1, 8)
228 DEP_FIELD(ATTR_53, ATTR_PM_CAP_NEXTPTR, 8, 0)
229DEP_REG32(ATTR_54, 0xd8)
230 DEP_FIELD(ATTR_54, ATTR_PM_DATA_SCALE4, 2, 14)
231 DEP_FIELD(ATTR_54, ATTR_PM_DATA_SCALE3, 2, 12)
232 DEP_FIELD(ATTR_54, ATTR_PM_DATA_SCALE2, 2, 10)
233 DEP_FIELD(ATTR_54, ATTR_PM_DATA_SCALE1, 2, 8)
234 DEP_FIELD(ATTR_54, ATTR_PM_DATA_SCALE0, 2, 6)
235 DEP_FIELD(ATTR_54, ATTR_PM_CSR_NOSOFTRST, 1, 5)
236 DEP_FIELD(ATTR_54, ATTR_PM_CSR_BPCCEN, 1, 4)
237 DEP_FIELD(ATTR_54, ATTR_PM_CSR_B2B3, 1, 3)
238 DEP_FIELD(ATTR_54, ATTR_PM_CAP_VERSION, 3, 0)
239DEP_REG32(ATTR_55, 0xdc)
240 DEP_FIELD(ATTR_55, ATTR_PM_DATA0, 8, 6)
241 DEP_FIELD(ATTR_55, ATTR_PM_DATA_SCALE7, 2, 4)
242 DEP_FIELD(ATTR_55, ATTR_PM_DATA_SCALE6, 2, 2)
243 DEP_FIELD(ATTR_55, ATTR_PM_DATA_SCALE5, 2, 0)
244DEP_REG32(ATTR_56, 0xe0)
245 DEP_FIELD(ATTR_56, ATTR_PM_DATA2, 8, 8)
246 DEP_FIELD(ATTR_56, ATTR_PM_DATA1, 8, 0)
247DEP_REG32(ATTR_57, 0xe4)
248 DEP_FIELD(ATTR_57, ATTR_PM_DATA4, 8, 8)
249 DEP_FIELD(ATTR_57, ATTR_PM_DATA3, 8, 0)
250DEP_REG32(ATTR_58, 0xe8)
251 DEP_FIELD(ATTR_58, ATTR_PM_DATA6, 8, 8)
252 DEP_FIELD(ATTR_58, ATTR_PM_DATA5, 8, 0)
253DEP_REG32(ATTR_59, 0xec)
254 DEP_FIELD(ATTR_59, ATTR_PM_DATA7, 8, 0)
255DEP_REG32(ATTR_60, 0xf0)
256 DEP_FIELD(ATTR_60, ATTR_RBAR_BASE_PTR, 12, 0)
257DEP_REG32(ATTR_61, 0xf4)
258 DEP_FIELD(ATTR_61, ATTR_RBAR_CAP_ON, 1, 12)
259 DEP_FIELD(ATTR_61, ATTR_RBAR_CAP_NEXTPTR, 12, 0)
260DEP_REG32(ATTR_62, 0xf8)
261 DEP_FIELD(ATTR_62, ATTR_RBAR_CAP_ID, 16, 0)
262DEP_REG32(ATTR_63, 0xfc)
263 DEP_FIELD(ATTR_63, ATTR_RBAR_NUM, 3, 4)
264 DEP_FIELD(ATTR_63, ATTR_RBAR_CAP_VERSION, 4, 0)
265DEP_REG32(ATTR_64, 0x100)
266 DEP_FIELD(ATTR_64, ATTR_RBAR_CAP_SUP0, 16, 0)
267DEP_REG32(ATTR_65, 0x104)
268 DEP_FIELD(ATTR_65, ATTR_RBAR_CAP_SUP0, 16, 0)
269DEP_REG32(ATTR_66, 0x108)
270 DEP_FIELD(ATTR_66, ATTR_RBAR_CAP_SUP1, 16, 0)
271DEP_REG32(ATTR_67, 0x10c)
272 DEP_FIELD(ATTR_67, ATTR_RBAR_CAP_SUP1, 16, 0)
273DEP_REG32(ATTR_68, 0x110)
274 DEP_FIELD(ATTR_68, ATTR_RBAR_CAP_SUP2, 16, 0)
275DEP_REG32(ATTR_69, 0x114)
276 DEP_FIELD(ATTR_69, ATTR_RBAR_CAP_SUP2, 16, 0)
277DEP_REG32(ATTR_70, 0x118)
278 DEP_FIELD(ATTR_70, ATTR_RBAR_CAP_SUP3, 16, 0)
279DEP_REG32(ATTR_71, 0x11c)
280 DEP_FIELD(ATTR_71, ATTR_RBAR_CAP_SUP3, 16, 0)
281DEP_REG32(ATTR_72, 0x120)
282 DEP_FIELD(ATTR_72, ATTR_RBAR_CAP_SUP4, 16, 0)
283DEP_REG32(ATTR_73, 0x124)
284 DEP_FIELD(ATTR_73, ATTR_RBAR_CAP_SUP4, 16, 0)
285DEP_REG32(ATTR_74, 0x128)
286 DEP_FIELD(ATTR_74, ATTR_RBAR_CAP_SUP5, 16, 0)
287DEP_REG32(ATTR_75, 0x12c)
288 DEP_FIELD(ATTR_75, ATTR_RBAR_CAP_SUP5, 16, 0)
289DEP_REG32(ATTR_76, 0x130)
290 DEP_FIELD(ATTR_76, ATTR_RBAR_CAP_INDEX4, 3, 12)
291 DEP_FIELD(ATTR_76, ATTR_RBAR_CAP_INDEX3, 3, 9)
292 DEP_FIELD(ATTR_76, ATTR_RBAR_CAP_INDEX2, 3, 6)
293 DEP_FIELD(ATTR_76, ATTR_RBAR_CAP_INDEX1, 3, 3)
294 DEP_FIELD(ATTR_76, ATTR_RBAR_CAP_INDEX0, 3, 0)
295DEP_REG32(ATTR_77, 0x134)
296 DEP_FIELD(ATTR_77, ATTR_RBAR_CAP_CONTROL_ENCODEDBAR1, 5, 8)
297 DEP_FIELD(ATTR_77, ATTR_RBAR_CAP_CONTROL_ENCODEDBAR0, 5, 3)
298 DEP_FIELD(ATTR_77, ATTR_RBAR_CAP_INDEX5, 3, 0)
299DEP_REG32(ATTR_78, 0x138)
300 DEP_FIELD(ATTR_78, ATTR_RBAR_CAP_CONTROL_ENCODEDBAR4, 5, 10)
301 DEP_FIELD(ATTR_78, ATTR_RBAR_CAP_CONTROL_ENCODEDBAR3, 5, 5)
302 DEP_FIELD(ATTR_78, ATTR_RBAR_CAP_CONTROL_ENCODEDBAR2, 5, 0)
303DEP_REG32(ATTR_79, 0x13c)
304 DEP_FIELD(ATTR_79, ATTR_SLOT_CAP_NO_CMD_COMPLETED_SUPPORT, 1, 13)
305 DEP_FIELD(ATTR_79, ATTR_SLOT_CAP_MRL_SENSOR_PRESENT, 1, 12)
306 DEP_FIELD(ATTR_79, ATTR_SLOT_CAP_HOTPLUG_SURPRISE, 1, 11)
307 DEP_FIELD(ATTR_79, ATTR_SLOT_CAP_HOTPLUG_CAPABLE, 1, 10)
308 DEP_FIELD(ATTR_79, ATTR_SLOT_CAP_ELEC_INTERLOCK_PRESENT, 1, 9)
309 DEP_FIELD(ATTR_79, ATTR_SLOT_CAP_ATT_INDICATOR_PRESENT, 1, 8)
310 DEP_FIELD(ATTR_79, ATTR_SLOT_CAP_ATT_BUTTON_PRESENT, 1, 7)
311 DEP_FIELD(ATTR_79, ATTR_SELECT_DLL_IF, 1, 6)
312 DEP_FIELD(ATTR_79, ATTR_ROOT_CAP_CRS_SW_VISIBILITY, 1, 5)
313 DEP_FIELD(ATTR_79, ATTR_RBAR_CAP_CONTROL_ENCODEDBAR5, 5, 0)
314DEP_REG32(ATTR_80, 0x140)
315 DEP_FIELD(ATTR_80, ATTR_SLOT_CAP_POWER_INDICATOR_PRESENT, 1, 14)
316 DEP_FIELD(ATTR_80, ATTR_SLOT_CAP_POWER_CONTROLLER_PRESENT, 1, 13)
317 DEP_FIELD(ATTR_80, ATTR_SLOT_CAP_PHYSICAL_SLOT_NUM, 13, 0)
318DEP_REG32(ATTR_81, 0x144)
319 DEP_FIELD(ATTR_81, ATTR_SSL_MESSAGE_AUTO, 1, 10)
320 DEP_FIELD(ATTR_81, ATTR_SLOT_CAP_SLOT_POWER_LIMIT_VALUE, 8, 2)
321 DEP_FIELD(ATTR_81, ATTR_SLOT_CAP_SLOT_POWER_LIMIT_SCALE, 2, 0)
322DEP_REG32(ATTR_82, 0x148)
323 DEP_FIELD(ATTR_82, ATTR_VC_BASE_PTR, 12, 0)
324DEP_REG32(ATTR_83, 0x14c)
325 DEP_FIELD(ATTR_83, ATTR_VC_CAP_ON, 1, 12)
326 DEP_FIELD(ATTR_83, ATTR_VC_CAP_NEXTPTR, 12, 0)
327DEP_REG32(ATTR_84, 0x150)
328 DEP_FIELD(ATTR_84, ATTR_VC_CAP_ID, 16, 0)
329DEP_REG32(ATTR_85, 0x154)
330 DEP_FIELD(ATTR_85, ATTR_VSEC_BASE_PTR, 12, 1)
331 DEP_FIELD(ATTR_85, ATTR_VC_CAP_REJECT_SNOOP_TRANSACTIONS, 1, 0)
332DEP_REG32(ATTR_86, 0x158)
333 DEP_FIELD(ATTR_86, ATTR_VSEC_CAP_HDR_ID, 16, 0)
334DEP_REG32(ATTR_87, 0x15c)
335 DEP_FIELD(ATTR_87, ATTR_VSEC_CAP_HDR_REVISION, 4, 12)
336 DEP_FIELD(ATTR_87, ATTR_VSEC_CAP_HDR_LENGTH, 12, 0)
337DEP_REG32(ATTR_88, 0x160)
338 DEP_FIELD(ATTR_88, ATTR_VSEC_CAP_ID, 16, 0)
339DEP_REG32(ATTR_89, 0x164)
340 DEP_FIELD(ATTR_89, ATTR_VSEC_CAP_ON, 1, 13)
341 DEP_FIELD(ATTR_89, ATTR_VSEC_CAP_NEXTPTR, 12, 1)
342 DEP_FIELD(ATTR_89, ATTR_VSEC_CAP_IS_LINK_VISIBLE, 1, 0)
343DEP_REG32(ATTR_90, 0x168)
344 DEP_FIELD(ATTR_90, ATTR_CRM_MODULE_RSTS, 7, 7)
345 DEP_FIELD(ATTR_90, ATTR_USER_CLK_FREQ, 3, 4)
346 DEP_FIELD(ATTR_90, ATTR_VSEC_CAP_VERSION, 4, 0)
347DEP_REG32(ATTR_91, 0x16c)
348 DEP_FIELD(ATTR_91, ATTR_LL_ACK_TIMEOUT_EN, 1, 15)
349 DEP_FIELD(ATTR_91, ATTR_LL_ACK_TIMEOUT, 15, 0)
350DEP_REG32(ATTR_92, 0x170)
351 DEP_FIELD(ATTR_92, ATTR_LL_ACK_TIMEOUT_FUNC, 2, 0)
352DEP_REG32(ATTR_93, 0x174)
353 DEP_FIELD(ATTR_93, ATTR_LL_REPLAY_TIMEOUT_EN, 1, 15)
354 DEP_FIELD(ATTR_93, ATTR_LL_REPLAY_TIMEOUT, 15, 0)
355DEP_REG32(ATTR_94, 0x178)
356 DEP_FIELD(ATTR_94, ATTR_LL_REPLAY_TIMEOUT_FUNC, 2, 0)
357DEP_REG32(ATTR_95, 0x17c)
358 DEP_FIELD(ATTR_95, ATTR_PM_ASPML0S_TIMEOUT_EN, 1, 15)
359 DEP_FIELD(ATTR_95, ATTR_PM_ASPML0S_TIMEOUT, 15, 0)
360DEP_REG32(ATTR_96, 0x180)
361 DEP_FIELD(ATTR_96, ATTR_INFER_EI, 5, 6)
362 DEP_FIELD(ATTR_96, ATTR_ENTER_RVRY_EI_L0, 1, 5)
363 DEP_FIELD(ATTR_96, ATTR_DISABLE_SCRAMBLING, 1, 4)
364 DEP_FIELD(ATTR_96, ATTR_DISABLE_LANE_REVERSAL, 1, 3)
365 DEP_FIELD(ATTR_96, ATTR_PM_ASPM_FASTEXIT, 1, 2)
366 DEP_FIELD(ATTR_96, ATTR_PM_ASPML0S_TIMEOUT_FUNC, 2, 0)
367DEP_REG32(ATTR_97, 0x184)
368 DEP_FIELD(ATTR_97, ATTR_LTSSM_MAX_LINK_WIDTH, 6, 6)
369 DEP_FIELD(ATTR_97, ATTR_LINK_CAP_MAX_LINK_WIDTH, 6, 0)
370DEP_REG32(ATTR_98, 0x188)
371 DEP_FIELD(ATTR_98, ATTR_N_FTS_COMCLK_GEN2, 8, 8)
372 DEP_FIELD(ATTR_98, ATTR_N_FTS_COMCLK_GEN1, 8, 0)
373DEP_REG32(ATTR_99, 0x18c)
374 DEP_FIELD(ATTR_99, ATTR_N_FTS_GEN2, 8, 8)
375 DEP_FIELD(ATTR_99, ATTR_N_FTS_GEN1, 8, 0)
376DEP_REG32(ATTR_100, 0x190)
377 DEP_FIELD(ATTR_100, ATTR_DNSTREAM_LINK_NUM, 8, 8)
378 DEP_FIELD(ATTR_100, ATTR_EXIT_LOOPBACK_ON_EI, 1, 7)
379 DEP_FIELD(ATTR_100, ATTR_UPSTREAM_FACING, 1, 6)
380 DEP_FIELD(ATTR_100, ATTR_UPCONFIG_CAPABLE, 1, 5)
381 DEP_FIELD(ATTR_100, ATTR_PL_FAST_TRAIN, 1, 4)
382 DEP_FIELD(ATTR_100, ATTR_PL_AUTO_CONFIG, 3, 1)
383 DEP_FIELD(ATTR_100, ATTR_ALLOW_X8_GEN2, 1, 0)
384DEP_REG32(ATTR_101, 0x194)
385 DEP_FIELD(ATTR_101, ATTR_ENABLE_MSG_ROUTE, 11, 5)
386 DEP_FIELD(ATTR_101, ATTR_DISABLE_RX_POISONED_RESP, 1, 4)
387 DEP_FIELD(ATTR_101, ATTR_DISABLE_RX_TC_FILTER, 1, 3)
388 DEP_FIELD(ATTR_101, ATTR_DISABLE_ID_CHECK, 1, 2)
389 DEP_FIELD(ATTR_101, ATTR_DISABLE_BAR_FILTERING, 1, 1)
390 DEP_FIELD(ATTR_101, ATTR_DISABLE_ASPM_L1_TIMER, 1, 0)
391DEP_REG32(ATTR_102, 0x198)
392 DEP_FIELD(ATTR_102, ATTR_TL_TX_RAM_RDATA_LATENCY, 2, 14)
393 DEP_FIELD(ATTR_102, ATTR_TL_TX_RAM_RADDR_LATENCY, 1, 13)
394 DEP_FIELD(ATTR_102, ATTR_PM_MF, 1, 12)
395 DEP_FIELD(ATTR_102, ATTR_DISABLE_ERR_MSG, 1, 11)
396 DEP_FIELD(ATTR_102, ATTR_USE_RID_PINS, 1, 10)
397 DEP_FIELD(ATTR_102, ATTR_DISABLE_LOCKED_FILTER, 1, 9)
398 DEP_FIELD(ATTR_102, ATTR_DISABLE_PPM_FILTER, 1, 8)
399 DEP_FIELD(ATTR_102, ATTR_TL_RBYPASS, 1, 7)
400 DEP_FIELD(ATTR_102, ATTR_TL_TX_CHECKS_DISABLE, 1, 6)
401 DEP_FIELD(ATTR_102, ATTR_TL_TFC_DISABLE, 1, 5)
402 DEP_FIELD(ATTR_102, ATTR_TL_RX_RAM_WRITE_LATENCY, 1, 4)
403 DEP_FIELD(ATTR_102, ATTR_TL_RX_RAM_RDATA_LATENCY, 2, 2)
404 DEP_FIELD(ATTR_102, ATTR_TL_RX_RAM_RADDR_LATENCY, 1, 1)
405 DEP_FIELD(ATTR_102, ATTR_ENABLE_RX_TD_ECRC_TRIM, 1, 0)
406DEP_REG32(ATTR_103, 0x19c)
407 DEP_FIELD(ATTR_103, ATTR_VC0_CPL_INFINITE, 1, 5)
408 DEP_FIELD(ATTR_103, ATTR_VC_CAP_VERSION, 4, 1)
409 DEP_FIELD(ATTR_103, ATTR_TL_TX_RAM_WRITE_LATENCY, 1, 0)
410DEP_REG32(ATTR_104, 0x1a0)
411 DEP_FIELD(ATTR_104, ATTR_VC0_RX_RAM_LIMIT, 13, 0)
412DEP_REG32(ATTR_105, 0x1a4)
413 DEP_FIELD(ATTR_105, ATTR_VC0_TOTAL_CREDITS_CD, 11, 0)
414DEP_REG32(ATTR_106, 0x1a8)
415 DEP_FIELD(ATTR_106, ATTR_VC0_TOTAL_CREDITS_NPH, 7, 7)
416 DEP_FIELD(ATTR_106, ATTR_VC0_TOTAL_CREDITS_CH, 7, 0)
417DEP_REG32(ATTR_107, 0x1ac)
418 DEP_FIELD(ATTR_107, ATTR_VC0_TOTAL_CREDITS_NPD, 11, 0)
419DEP_REG32(ATTR_108, 0x1b0)
420 DEP_FIELD(ATTR_108, ATTR_VC0_TOTAL_CREDITS_PD, 11, 0)
421DEP_REG32(ATTR_109, 0x1b4)
422 DEP_FIELD(ATTR_109, ATTR_TECRC_EP_INV, 1, 15)
423 DEP_FIELD(ATTR_109, ATTR_RECRC_CHK_TRIM, 1, 14)
424 DEP_FIELD(ATTR_109, ATTR_RECRC_CHK, 2, 12)
425 DEP_FIELD(ATTR_109, ATTR_VC0_TX_LASTPACKET, 5, 7)
426 DEP_FIELD(ATTR_109, ATTR_VC0_TOTAL_CREDITS_PH, 7, 0)
427DEP_REG32(ATTR_110, 0x1b8)
428 DEP_FIELD(ATTR_110, ATTR_RP_AUTO_SPD_LOOPCNT, 5, 11)
429 DEP_FIELD(ATTR_110, ATTR_RP_AUTO_SPD, 2, 9)
430 DEP_FIELD(ATTR_110, ATTR_USER_CLK2_DIV2, 1, 8)
431 DEP_FIELD(ATTR_110, ATTR_TRN_NP_FC, 1, 7)
432 DEP_FIELD(ATTR_110, ATTR_TRN_DW, 1, 6)
433 DEP_FIELD(ATTR_110, ATTR_UR_CFG1, 1, 5)
434 DEP_FIELD(ATTR_110, ATTR_UR_ATOMIC, 1, 4)
435 DEP_FIELD(ATTR_110, ATTR_UR_PRS_RESPONSE, 1, 3)
436 DEP_FIELD(ATTR_110, ATTR_UR_INV_REQ, 1, 2)
437 DEP_FIELD(ATTR_110, ATTR_CFG_ECRC_ERR_CPLSTAT, 2, 0)
438DEP_REG32(ATTR_111, 0x1bc)
439 DEP_FIELD(ATTR_111, ATTR_SPARE_BIT8, 1, 9)
440 DEP_FIELD(ATTR_111, ATTR_SPARE_BIT7, 1, 8)
441 DEP_FIELD(ATTR_111, ATTR_SPARE_BIT6, 1, 7)
442 DEP_FIELD(ATTR_111, ATTR_SPARE_BIT5, 1, 6)
443 DEP_FIELD(ATTR_111, ATTR_SPARE_BIT4, 1, 5)
444 DEP_FIELD(ATTR_111, ATTR_SPARE_BIT3, 1, 4)
445 DEP_FIELD(ATTR_111, ATTR_SPARE_BIT2, 1, 3)
446 DEP_FIELD(ATTR_111, ATTR_SPARE_BIT1, 1, 2)
447 DEP_FIELD(ATTR_111, ATTR_SPARE_BIT0, 1, 1)
448 DEP_FIELD(ATTR_111, ATTR_TEST_MODE_PIN_CHAR, 1, 0)
449DEP_REG32(ATTR_112, 0x1c0)
450 DEP_FIELD(ATTR_112, ATTR_SPARE_BYTE1, 8, 8)
451 DEP_FIELD(ATTR_112, ATTR_SPARE_BYTE0, 8, 0)
452DEP_REG32(ATTR_113, 0x1c4)
453 DEP_FIELD(ATTR_113, ATTR_SPARE_BYTE3, 8, 8)
454 DEP_FIELD(ATTR_113, ATTR_SPARE_BYTE2, 8, 0)
455DEP_REG32(ATTR_114, 0x1c8)
456 DEP_FIELD(ATTR_114, ATTR_SPARE_WORD0, 16, 0)
457DEP_REG32(ATTR_115, 0x1cc)
458 DEP_FIELD(ATTR_115, ATTR_SPARE_WORD0, 16, 0)
459DEP_REG32(ATTR_116, 0x1d0)
460 DEP_FIELD(ATTR_116, ATTR_SPARE_WORD1, 16, 0)
461DEP_REG32(ATTR_117, 0x1d4)
462 DEP_FIELD(ATTR_117, ATTR_SPARE_WORD1, 16, 0)
463DEP_REG32(ATTR_118, 0x1d8)
464 DEP_FIELD(ATTR_118, ATTR_SPARE_WORD2, 16, 0)
465DEP_REG32(ATTR_119, 0x1dc)
466 DEP_FIELD(ATTR_119, ATTR_SPARE_WORD2, 16, 0)
467DEP_REG32(ATTR_120, 0x1e0)
468 DEP_FIELD(ATTR_120, ATTR_SPARE_WORD3, 16, 0)
469DEP_REG32(ATTR_121, 0x1e4)
470 DEP_FIELD(ATTR_121, ATTR_SPARE_WORD3, 16, 0)
471DEP_REG32(ID, 0x200)
472 DEP_FIELD(ID, CFG_VEND_ID, 16, 16)
473 DEP_FIELD(ID, CFG_DEV_ID, 16, 0)
474DEP_REG32(SUBSYS_ID, 0x204)
475 DEP_FIELD(SUBSYS_ID, CFG_SUBSYS_VEND_ID, 16, 16)
476 DEP_FIELD(SUBSYS_ID, CFG_SUBSYS_ID, 16, 0)
477DEP_REG32(REV_ID, 0x208)
478 DEP_FIELD(REV_ID, CFG_REV_ID, 8, 0)
479DEP_REG32(DSN_0, 0x20c)
480DEP_REG32(DSN_1, 0x210)
481DEP_REG32(MGMT_CTRL, 0x214)
482 DEP_FIELD(MGMT_CTRL, CFG_MGMT_WR_READONLY, 1, 1)
483 DEP_FIELD(MGMT_CTRL, CFG_MGMT_WR_RW1C_AS_RW, 1, 0)
484DEP_REG32(PM_CTRL, 0x218)
485 DEP_FIELD(PM_CTRL, CFG_TRN_PENDING, 1, 3)
486 DEP_FIELD(PM_CTRL, CFG_PM_SEND_PME_TO, 1, 2)
487 DEP_FIELD(PM_CTRL, CFG_PM_TURNOFF_OK, 1, 1)
488 DEP_FIELD(PM_CTRL, CFG_PM_WAKE, 1, 0)
489DEP_REG32(RST_CTRL, 0x220)
490 DEP_FIELD(RST_CTRL, PL_RST_N, 1, 6)
491 DEP_FIELD(RST_CTRL, FUNC_LVL_RST_N, 1, 5)
492 DEP_FIELD(RST_CTRL, DL_RST_N, 1, 3)
493 DEP_FIELD(RST_CTRL, TL_RST_N, 1, 2)
494 DEP_FIELD(RST_CTRL, CM_STICKY_RST_N, 1, 1)
495 DEP_FIELD(RST_CTRL, CM_RST_N, 1, 0)
496DEP_REG32(DBG_CTRL, 0x224)
497 DEP_FIELD(DBG_CTRL, PL_DBG_MODE, 3, 3)
498 DEP_FIELD(DBG_CTRL, DBG_SUB_MODE, 1, 2)
499 DEP_FIELD(DBG_CTRL, DBG_MODE, 2, 0)
500DEP_REG32(PL_LINK_CTRL_STATUS, 0x228)
501 DEP_FIELD(PL_LINK_CTRL_STATUS, DIR_LINK_CHANGE_DONE, 1, 22)
502 DEP_FIELD(PL_LINK_CTRL_STATUS, DIR_LINK_CHANGE, 2, 20)
503 DEP_FIELD(PL_LINK_CTRL_STATUS, DIR_LINK_AUTON, 1, 19)
504 DEP_FIELD(PL_LINK_CTRL_STATUS, DIR_LINK_SPEED, 1, 18)
505 DEP_FIELD(PL_LINK_CTRL_STATUS, DIR_LINK_WIDTH, 2, 16)
506 DEP_FIELD(PL_LINK_CTRL_STATUS, LINK_UP, 1, 11)
507 DEP_FIELD(PL_LINK_CTRL_STATUS, LANE_REVERSAL, 2, 9)
508 DEP_FIELD(PL_LINK_CTRL_STATUS, LTSSM_STATE, 6, 3)
509 DEP_FIELD(PL_LINK_CTRL_STATUS, LINK_WIDTH, 2, 1)
510 DEP_FIELD(PL_LINK_CTRL_STATUS, LINK_RATE, 1, 0)
511DEP_REG32(DIR_LTSSM, 0x22c)
512 DEP_FIELD(DIR_LTSSM, PL_DIR_LTSSM_STALL, 1, 7)
513 DEP_FIELD(DIR_LTSSM, PL_DIR_LTSSM_NEW_VLD, 1, 6)
514 DEP_FIELD(DIR_LTSSM, PL_DIR_LTSSM_NEW, 6, 0)
515DEP_REG32(EP_CTRL, 0x230)
516 DEP_FIELD(EP_CTRL, PL_UPSTREAM_DEEMPH_SOURCE, 1, 1)
517 DEP_FIELD(EP_CTRL, PL_RECEIVED_HOT_RST, 1, 0)
518DEP_REG32(RP_CTRL, 0x234)
519 DEP_FIELD(RP_CTRL, PL_DOWNSTREAM_DEEMPH_SOURCE, 1, 1)
520 DEP_FIELD(RP_CTRL, PL_TRANSMIT_HOT_RST, 1, 0)
521DEP_REG32(PCIE_STATUS, 0x238)
522 DEP_FIELD(PCIE_STATUS, PHY_RDY, 1, 1)
523 DEP_FIELD(PCIE_STATUS, PCIE_LINK_UP, 1, 0)
524DEP_REG32(MISC_CTRL, 0x300)
525 DEP_FIELD(MISC_CTRL, SLVERR_ENABLE, 1, 0)
526DEP_REG32(ISR, 0x304)
527 DEP_FIELD(ISR, PCIE_RESET, 1, 1)
528 DEP_FIELD(ISR, ADDR_DECODE_ERR, 1, 0)
529DEP_REG32(IMR, 0x308)
530 DEP_FIELD(IMR, PCIE_RESET, 1, 1)
531 DEP_FIELD(IMR, ADDR_DECODE_ERR, 1, 0)
532DEP_REG32(IER, 0x30c)
533 DEP_FIELD(IER, PCIE_RESET, 1, 1)
534 DEP_FIELD(IER, ADDR_DECODE_ERR, 1, 0)
535DEP_REG32(IDR, 0x310)
536 DEP_FIELD(IDR, PCIE_RESET, 1, 1)
537 DEP_FIELD(IDR, ADDR_DECODE_ERR, 1, 0)
538DEP_REG32(ECO_0, 0x314)
539DEP_REG32(ECO_1, 0x318)
540DEP_REG32(CB, 0x31c)
541 DEP_FIELD(CB, CB1, 1, 1)
542 DEP_FIELD(CB, CB0, 1, 0)
543
544#define R_MAX (R_CB + 1)
545
546typedef struct PCIE_ATTRIB {
547 SysBusDevice parent_obj;
548 MemoryRegion iomem;
549 qemu_irq irq_imr;
550
551 uint32_t regs[R_MAX];
552 DepRegisterInfo regs_info[R_MAX];
553} PCIE_ATTRIB;
554
555static void imr_update_irq(PCIE_ATTRIB *s)
556{
557 bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];
558 qemu_set_irq(s->irq_imr, pending);
559}
560
561static void isr_postw(DepRegisterInfo *reg, uint64_t val64)
562{
563 PCIE_ATTRIB *s = XILINX_PCIE_ATTRIB(reg->opaque);
564 imr_update_irq(s);
565}
566
567static uint64_t ier_prew(DepRegisterInfo *reg, uint64_t val64)
568{
569 PCIE_ATTRIB *s = XILINX_PCIE_ATTRIB(reg->opaque);
570 uint32_t val = val64;
571
572 s->regs[R_IMR] &= ~val;
573 imr_update_irq(s);
574 return 0;
575}
576
577static uint64_t idr_prew(DepRegisterInfo *reg, uint64_t val64)
578{
579 PCIE_ATTRIB *s = XILINX_PCIE_ATTRIB(reg->opaque);
580 uint32_t val = val64;
581
582 s->regs[R_IMR] |= val;
583 imr_update_irq(s);
584 return 0;
585}
586
587static DepRegisterAccessInfo pcie_attrib_regs_info[] = {
588 { .name = "ATTR_0", .decode.addr = A_ATTR_0,
589 .reset = 0x3,
590 },{ .name = "ATTR_1", .decode.addr = A_ATTR_1,
591 .reset = 0x1,
592 },{ .name = "ATTR_2", .decode.addr = A_ATTR_2,
593 .reset = 0x2,
594 },{ .name = "ATTR_3", .decode.addr = A_ATTR_3,
595 .reset = 0x140,
596 },{ .name = "ATTR_4", .decode.addr = A_ATTR_4,
597 .reset = 0x1000,
598 },{ .name = "ATTR_5", .decode.addr = A_ATTR_5,
599 .reset = 0xff07,
600 },{ .name = "ATTR_6", .decode.addr = A_ATTR_6,
601 .reset = 0x7,
602 },{ .name = "ATTR_7", .decode.addr = A_ATTR_7,
603 .reset = 0x4,
604 },{ .name = "ATTR_8", .decode.addr = A_ATTR_8,
605 .reset = 0xfff0,
606 },{ .name = "ATTR_9", .decode.addr = A_ATTR_9,
607 .reset = 0xffff,
608 },{ .name = "ATTR_10", .decode.addr = A_ATTR_10,
609 .reset = 0xffff,
610 },{ .name = "ATTR_11", .decode.addr = A_ATTR_11,
611 .reset = 0x4,
612 },{ .name = "ATTR_12", .decode.addr = A_ATTR_12,
613 .reset = 0xfff0,
614 },{ .name = "ATTR_13", .decode.addr = A_ATTR_13,
615 .reset = 0xffff,
616 },{ .name = "ATTR_14", .decode.addr = A_ATTR_14,
617 .reset = 0xffff,
618 },{ .name = "ATTR_15", .decode.addr = A_ATTR_15,
619 .reset = 0x4,
620 },{ .name = "ATTR_16", .decode.addr = A_ATTR_16,
621 .reset = 0xfff0,
622 },{ .name = "ATTR_17", .decode.addr = A_ATTR_17,
623 .reset = 0xffff,
624 },{ .name = "ATTR_18", .decode.addr = A_ATTR_18,
625 .reset = 0xffff,
626 },{ .name = "ATTR_19", .decode.addr = A_ATTR_19,
627 },{ .name = "ATTR_20", .decode.addr = A_ATTR_20,
628 },{ .name = "ATTR_21", .decode.addr = A_ATTR_21,
629 .reset = 0x40,
630 },{ .name = "ATTR_22", .decode.addr = A_ATTR_22,
631 },{ .name = "ATTR_23", .decode.addr = A_ATTR_23,
632 },{ .name = "ATTR_24", .decode.addr = A_ATTR_24,
633 .reset = 0x8000,
634 },{ .name = "ATTR_25", .decode.addr = A_ATTR_25,
635 .reset = 0x905,
636 },{ .name = "ATTR_26", .decode.addr = A_ATTR_26,
637 .reset = 0x3000,
638 },{ .name = "ATTR_27", .decode.addr = A_ATTR_27,
639 .reset = 0x2138,
640 },{ .name = "ATTR_28", .decode.addr = A_ATTR_28,
641 },{ .name = "ATTR_29", .decode.addr = A_ATTR_29,
642 .reset = 0x100,
643 },{ .name = "ATTR_30", .decode.addr = A_ATTR_30,
644 .reset = 0x3,
645 },{ .name = "ATTR_31", .decode.addr = A_ATTR_31,
646 .reset = 0x110c,
647 },{ .name = "ATTR_32", .decode.addr = A_ATTR_32,
648 .reset = 0x3f1,
649 },{ .name = "ATTR_33", .decode.addr = A_ATTR_33,
650 .reset = 0x3ff,
651 },{ .name = "ATTR_34", .decode.addr = A_ATTR_34,
652 .reset = 0x100,
653 },{ .name = "ATTR_35", .decode.addr = A_ATTR_35,
654 .reset = 0xffd,
655 },{ .name = "ATTR_36", .decode.addr = A_ATTR_36,
656 .reset = 0x7fff,
657 },{ .name = "ATTR_37", .decode.addr = A_ATTR_37,
658 .reset = 0x49ff,
659 },{ .name = "ATTR_38", .decode.addr = A_ATTR_38,
660 .reset = 0x120,
661 },{ .name = "ATTR_39", .decode.addr = A_ATTR_39,
662 .reset = 0x148,
663 },{ .name = "ATTR_40", .decode.addr = A_ATTR_40,
664 .reset = 0x405,
665 },{ .name = "ATTR_41", .decode.addr = A_ATTR_41,
666 .reset = 0x160,
667 },{ .name = "ATTR_42", .decode.addr = A_ATTR_42,
668 .reset = 0x119c,
669 },{ .name = "ATTR_43", .decode.addr = A_ATTR_43,
670 .reset = 0x100,
671 },{ .name = "ATTR_44", .decode.addr = A_ATTR_44,
672 .reset = 0x1,
673 },{ .name = "ATTR_45", .decode.addr = A_ATTR_45,
674 .reset = 0x8000,
675 },{ .name = "ATTR_46", .decode.addr = A_ATTR_46,
676 .reset = 0x1,
677 },{ .name = "ATTR_47", .decode.addr = A_ATTR_47,
678 },{ .name = "ATTR_48", .decode.addr = A_ATTR_48,
679 .reset = 0x3,
680 },{ .name = "ATTR_49", .decode.addr = A_ATTR_49,
681 .reset = 0x1060,
682 },{ .name = "ATTR_50", .decode.addr = A_ATTR_50,
683 .reset = 0x9c02,
684 },{ .name = "ATTR_51", .decode.addr = A_ATTR_51,
685 .reset = 0x4021,
686 },{ .name = "ATTR_52", .decode.addr = A_ATTR_52,
687 .reset = 0x40,
688 },{ .name = "ATTR_53", .decode.addr = A_ATTR_53,
689 .reset = 0x3d48,
690 },{ .name = "ATTR_54", .decode.addr = A_ATTR_54,
691 .reset = 0x23,
692 },{ .name = "ATTR_55", .decode.addr = A_ATTR_55,
693 },{ .name = "ATTR_56", .decode.addr = A_ATTR_56,
694 },{ .name = "ATTR_57", .decode.addr = A_ATTR_57,
695 },{ .name = "ATTR_58", .decode.addr = A_ATTR_58,
696 },{ .name = "ATTR_59", .decode.addr = A_ATTR_59,
697 },{ .name = "ATTR_60", .decode.addr = A_ATTR_60,
698 .reset = 0x178,
699 },{ .name = "ATTR_61", .decode.addr = A_ATTR_61,
700 },{ .name = "ATTR_62", .decode.addr = A_ATTR_62,
701 .reset = 0x15,
702 },{ .name = "ATTR_63", .decode.addr = A_ATTR_63,
703 .reset = 0x1,
704 },{ .name = "ATTR_64", .decode.addr = A_ATTR_64,
705 .reset = 0x1,
706 },{ .name = "ATTR_65", .decode.addr = A_ATTR_65,
707 },{ .name = "ATTR_66", .decode.addr = A_ATTR_66,
708 .reset = 0x1,
709 },{ .name = "ATTR_67", .decode.addr = A_ATTR_67,
710 },{ .name = "ATTR_68", .decode.addr = A_ATTR_68,
711 .reset = 0x1,
712 },{ .name = "ATTR_69", .decode.addr = A_ATTR_69,
713 },{ .name = "ATTR_70", .decode.addr = A_ATTR_70,
714 .reset = 0x1,
715 },{ .name = "ATTR_71", .decode.addr = A_ATTR_71,
716 },{ .name = "ATTR_72", .decode.addr = A_ATTR_72,
717 .reset = 0x1,
718 },{ .name = "ATTR_73", .decode.addr = A_ATTR_73,
719 },{ .name = "ATTR_74", .decode.addr = A_ATTR_74,
720 .reset = 0x1,
721 },{ .name = "ATTR_75", .decode.addr = A_ATTR_75,
722 },{ .name = "ATTR_76", .decode.addr = A_ATTR_76,
723 },{ .name = "ATTR_77", .decode.addr = A_ATTR_77,
724 },{ .name = "ATTR_78", .decode.addr = A_ATTR_78,
725 },{ .name = "ATTR_79", .decode.addr = A_ATTR_79,
726 },{ .name = "ATTR_80", .decode.addr = A_ATTR_80,
727 },{ .name = "ATTR_81", .decode.addr = A_ATTR_81,
728 },{ .name = "ATTR_82", .decode.addr = A_ATTR_82,
729 .reset = 0x10c,
730 },{ .name = "ATTR_83", .decode.addr = A_ATTR_83,
731 .reset = 0x1128,
732 },{ .name = "ATTR_84", .decode.addr = A_ATTR_84,
733 .reset = 0x2,
734 },{ .name = "ATTR_85", .decode.addr = A_ATTR_85,
735 .reset = 0x250,
736 },{ .name = "ATTR_86", .decode.addr = A_ATTR_86,
737 .reset = 0x1234,
738 },{ .name = "ATTR_87", .decode.addr = A_ATTR_87,
739 .reset = 0x1018,
740 },{ .name = "ATTR_88", .decode.addr = A_ATTR_88,
741 .reset = 0xb,
742 },{ .name = "ATTR_89", .decode.addr = A_ATTR_89,
743 .reset = 0x2281,
744 },{ .name = "ATTR_90", .decode.addr = A_ATTR_90,
745 .reset = 0x31,
746 },{ .name = "ATTR_91", .decode.addr = A_ATTR_91,
747 },{ .name = "ATTR_92", .decode.addr = A_ATTR_92,
748 },{ .name = "ATTR_93", .decode.addr = A_ATTR_93,
749 },{ .name = "ATTR_94", .decode.addr = A_ATTR_94,
750 .reset = 0x1,
751 },{ .name = "ATTR_95", .decode.addr = A_ATTR_95,
752 },{ .name = "ATTR_96", .decode.addr = A_ATTR_96,
753 .reset = 0x28,
754 },{ .name = "ATTR_97", .decode.addr = A_ATTR_97,
755 .reset = 0x104,
756 },{ .name = "ATTR_98", .decode.addr = A_ATTR_98,
757 .reset = 0xffff,
758 },{ .name = "ATTR_99", .decode.addr = A_ATTR_99,
759 .reset = 0xffff,
760 },{ .name = "ATTR_100", .decode.addr = A_ATTR_100,
761 .reset = 0xf0,
762 },{ .name = "ATTR_101", .decode.addr = A_ATTR_101,
763 },{ .name = "ATTR_102", .decode.addr = A_ATTR_102,
764 .reset = 0x8008,
765 },{ .name = "ATTR_103", .decode.addr = A_ATTR_103,
766 .reset = 0x22,
767 },{ .name = "ATTR_104", .decode.addr = A_ATTR_104,
768 .reset = 0x3ff,
769 },{ .name = "ATTR_105", .decode.addr = A_ATTR_105,
770 .reset = 0x172,
771 },{ .name = "ATTR_106", .decode.addr = A_ATTR_106,
772 .reset = 0x248,
773 },{ .name = "ATTR_107", .decode.addr = A_ATTR_107,
774 .reset = 0x8,
775 },{ .name = "ATTR_108", .decode.addr = A_ATTR_108,
776 .reset = 0x20,
777 },{ .name = "ATTR_109", .decode.addr = A_ATTR_109,
778 .reset = 0x7e04,
779 },{ .name = "ATTR_110", .decode.addr = A_ATTR_110,
780 .reset = 0xfabc,
781 },{ .name = "ATTR_111", .decode.addr = A_ATTR_111,
782 },{ .name = "ATTR_112", .decode.addr = A_ATTR_112,
783 },{ .name = "ATTR_113", .decode.addr = A_ATTR_113,
784 },{ .name = "ATTR_114", .decode.addr = A_ATTR_114,
785 },{ .name = "ATTR_115", .decode.addr = A_ATTR_115,
786 },{ .name = "ATTR_116", .decode.addr = A_ATTR_116,
787 },{ .name = "ATTR_117", .decode.addr = A_ATTR_117,
788 },{ .name = "ATTR_118", .decode.addr = A_ATTR_118,
789 },{ .name = "ATTR_119", .decode.addr = A_ATTR_119,
790 },{ .name = "ATTR_120", .decode.addr = A_ATTR_120,
791 },{ .name = "ATTR_121", .decode.addr = A_ATTR_121,
792 },{ .name = "ID", .decode.addr = A_ID,
793 .reset = 0x10ee7024,
794 },{ .name = "SUBSYS_ID", .decode.addr = A_SUBSYS_ID,
795 .reset = 0x10ee0007,
796 },{ .name = "REV_ID", .decode.addr = A_REV_ID,
797 },{ .name = "DSN_0", .decode.addr = A_DSN_0,
798 },{ .name = "DSN_1", .decode.addr = A_DSN_1,
799 },{ .name = "MGMT_CTRL", .decode.addr = A_MGMT_CTRL,
800 },{ .name = "PM_CTRL", .decode.addr = A_PM_CTRL,
801 .reset = 0x7,
802 .ro = 0x8,
803 },{ .name = "RST_CTRL", .decode.addr = A_RST_CTRL,
804 .reset = 0x6f,
805 },{ .name = "DBG_CTRL", .decode.addr = A_DBG_CTRL,
806 },{ .name = "PL_LINK_CTRL_STATUS", .decode.addr = A_PL_LINK_CTRL_STATUS,
807 .rsvd = 0xf000,
808 .ro = 0x40ffff,
809 },{ .name = "DIR_LTSSM", .decode.addr = A_DIR_LTSSM,
810 },{ .name = "EP_CTRL", .decode.addr = A_EP_CTRL,
811 .ro = 0x1,
812 },{ .name = "RP_CTRL", .decode.addr = A_RP_CTRL,
813 },{ .name = "PCIE_STATUS", .decode.addr = A_PCIE_STATUS,
814 .ro = 0x3,
815
816 .reset = R_PCIE_STATUS_PHY_RDY_MASK | R_PCIE_STATUS_PCIE_LINK_UP_MASK,
817 },{ .name = "MISC_CTRL", .decode.addr = A_MISC_CTRL,
818 },{ .name = "ISR", .decode.addr = A_ISR,
819 .w1c = 0x3,
820 .post_write = isr_postw,
821 },{ .name = "IMR", .decode.addr = A_IMR,
822 .reset = 0x3,
823 .ro = 0x3,
824 },{ .name = "IER", .decode.addr = A_IER,
825 .pre_write = ier_prew,
826 },{ .name = "IDR", .decode.addr = A_IDR,
827 .pre_write = idr_prew,
828 },{ .name = "ECO_0", .decode.addr = A_ECO_0,
829 },{ .name = "ECO_1", .decode.addr = A_ECO_1,
830 .reset = 0xffffffff,
831 },{ .name = "CB", .decode.addr = A_CB,
832 .reset = 0x1,
833 }
834};
835
836static void pcie_attrib_reset(DeviceState *dev)
837{
838 PCIE_ATTRIB *s = XILINX_PCIE_ATTRIB(dev);
839 unsigned int i;
840
841 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
842 dep_register_reset(&s->regs_info[i]);
843 }
844
845 imr_update_irq(s);
846}
847
848static uint64_t pcie_attrib_read(void *opaque, hwaddr addr, unsigned size)
849{
850 PCIE_ATTRIB *s = XILINX_PCIE_ATTRIB(opaque);
851 DepRegisterInfo *r = &s->regs_info[addr / 4];
852
853 if (!r->data) {
854 qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
855 object_get_canonical_path(OBJECT(s)),
856 addr);
857 return 0;
858 }
859 return dep_register_read(r);
860}
861
862static void pcie_attrib_write(void *opaque, hwaddr addr, uint64_t value,
863 unsigned size)
864{
865 PCIE_ATTRIB *s = XILINX_PCIE_ATTRIB(opaque);
866 DepRegisterInfo *r = &s->regs_info[addr / 4];
867
868 if (!r->data) {
869 qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
870 object_get_canonical_path(OBJECT(s)),
871 addr, value);
872 return;
873 }
874 dep_register_write(r, value, ~0);
875}
876
877static const MemoryRegionOps pcie_attrib_ops = {
878 .read = pcie_attrib_read,
879 .write = pcie_attrib_write,
880 .endianness = DEVICE_LITTLE_ENDIAN,
881 .valid = {
882 .min_access_size = 4,
883 .max_access_size = 4,
884 },
885};
886
887static void pcie_attrib_realize(DeviceState *dev, Error **errp)
888{
889 PCIE_ATTRIB *s = XILINX_PCIE_ATTRIB(dev);
890 const char *prefix = object_get_canonical_path(OBJECT(dev));
891 unsigned int i;
892
893 for (i = 0; i < ARRAY_SIZE(pcie_attrib_regs_info); ++i) {
894 DepRegisterInfo *r;
895
896 r = &s->regs_info[pcie_attrib_regs_info[i].decode.addr / 4];
897 *r = (DepRegisterInfo) {
898 .data = (uint8_t *)&s->regs[
899 pcie_attrib_regs_info[i].decode.addr / 4],
900 .data_size = sizeof(uint32_t),
901 .access = &pcie_attrib_regs_info[i],
902 .debug = XILINX_PCIE_ATTRIB_ERR_DEBUG,
903 .prefix = prefix,
904 .opaque = s,
905 };
906 }
907}
908
909static void pcie_attrib_init(Object *obj)
910{
911 PCIE_ATTRIB *s = XILINX_PCIE_ATTRIB(obj);
912 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
913
914 memory_region_init_io(&s->iomem, obj, &pcie_attrib_ops, s,
915 TYPE_XILINX_PCIE_ATTRIB, R_MAX * 4);
916 sysbus_init_mmio(sbd, &s->iomem);
917 sysbus_init_irq(sbd, &s->irq_imr);
918}
919
920static const VMStateDescription vmstate_pcie_attrib = {
921 .name = TYPE_XILINX_PCIE_ATTRIB,
922 .version_id = 1,
923 .minimum_version_id = 1,
924 .minimum_version_id_old = 1,
925 .fields = (VMStateField[]) {
926 VMSTATE_UINT32_ARRAY(regs, PCIE_ATTRIB, R_MAX),
927 VMSTATE_END_OF_LIST(),
928 }
929};
930
931static void pcie_attrib_class_init(ObjectClass *klass, void *data)
932{
933 DeviceClass *dc = DEVICE_CLASS(klass);
934
935 dc->reset = pcie_attrib_reset;
936 dc->realize = pcie_attrib_realize;
937 dc->vmsd = &vmstate_pcie_attrib;
938}
939
940static const TypeInfo pcie_attrib_info = {
941 .name = TYPE_XILINX_PCIE_ATTRIB,
942 .parent = TYPE_SYS_BUS_DEVICE,
943 .instance_size = sizeof(PCIE_ATTRIB),
944 .class_init = pcie_attrib_class_init,
945 .instance_init = pcie_attrib_init,
946};
947
948static void pcie_attrib_register_types(void)
949{
950 type_register_static(&pcie_attrib_info);
951}
952
953type_init(pcie_attrib_register_types)
954
