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14#include "qemu/osdep.h"
15#include "qemu-common.h"
16#include "cpu.h"
17#include "s390-pci-inst.h"
18#include "s390-pci-bus.h"
19#include "exec/memory-internal.h"
20#include "qemu/error-report.h"
21#include "sysemu/hw_accel.h"
22
23#ifndef DEBUG_S390PCI_INST
24#define DEBUG_S390PCI_INST 0
25#endif
26
27#define DPRINTF(fmt, ...) \
28 do { \
29 if (DEBUG_S390PCI_INST) { \
30 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \
31 } \
32 } while (0)
33
34static void s390_set_status_code(CPUS390XState *env,
35 uint8_t r, uint64_t status_code)
36{
37 env->regs[r] &= ~0xff000000ULL;
38 env->regs[r] |= (status_code & 0xff) << 24;
39}
40
41static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc)
42{
43 S390PCIBusDevice *pbdev = NULL;
44 S390pciState *s = s390_get_phb();
45 uint32_t res_code, initial_l2, g_l2;
46 int rc, i;
47 uint64_t resume_token;
48
49 rc = 0;
50 if (lduw_p(&rrb->request.hdr.len) != 32) {
51 res_code = CLP_RC_LEN;
52 rc = -EINVAL;
53 goto out;
54 }
55
56 if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) {
57 res_code = CLP_RC_FMT;
58 rc = -EINVAL;
59 goto out;
60 }
61
62 if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 ||
63 ldq_p(&rrb->request.reserved1) != 0) {
64 res_code = CLP_RC_RESNOT0;
65 rc = -EINVAL;
66 goto out;
67 }
68
69 resume_token = ldq_p(&rrb->request.resume_token);
70
71 if (resume_token) {
72 pbdev = s390_pci_find_dev_by_idx(s, resume_token);
73 if (!pbdev) {
74 res_code = CLP_RC_LISTPCI_BADRT;
75 rc = -EINVAL;
76 goto out;
77 }
78 } else {
79 pbdev = s390_pci_find_next_avail_dev(s, NULL);
80 }
81
82 if (lduw_p(&rrb->response.hdr.len) < 48) {
83 res_code = CLP_RC_8K;
84 rc = -EINVAL;
85 goto out;
86 }
87
88 initial_l2 = lduw_p(&rrb->response.hdr.len);
89 if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry)
90 != 0) {
91 res_code = CLP_RC_LEN;
92 rc = -EINVAL;
93 *cc = 3;
94 goto out;
95 }
96
97 stl_p(&rrb->response.fmt, 0);
98 stq_p(&rrb->response.reserved1, 0);
99 stl_p(&rrb->response.mdd, FH_MASK_SHM);
100 stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS);
101 rrb->response.flags = UID_CHECKING_ENABLED;
102 rrb->response.entry_size = sizeof(ClpFhListEntry);
103
104 i = 0;
105 g_l2 = LIST_PCI_HDR_LEN;
106 while (g_l2 < initial_l2 && pbdev) {
107 stw_p(&rrb->response.fh_list[i].device_id,
108 pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID));
109 stw_p(&rrb->response.fh_list[i].vendor_id,
110 pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID));
111
112 stl_p(&rrb->response.fh_list[i].config,
113 pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31);
114 stl_p(&rrb->response.fh_list[i].fid, pbdev->fid);
115 stl_p(&rrb->response.fh_list[i].fh, pbdev->fh);
116
117 g_l2 += sizeof(ClpFhListEntry);
118
119 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n",
120 g_l2,
121 lduw_p(&rrb->response.fh_list[i].vendor_id),
122 lduw_p(&rrb->response.fh_list[i].device_id),
123 ldl_p(&rrb->response.fh_list[i].fid),
124 ldl_p(&rrb->response.fh_list[i].fh));
125 pbdev = s390_pci_find_next_avail_dev(s, pbdev);
126 i++;
127 }
128
129 if (!pbdev) {
130 resume_token = 0;
131 } else {
132 resume_token = pbdev->fh & FH_MASK_INDEX;
133 }
134 stq_p(&rrb->response.resume_token, resume_token);
135 stw_p(&rrb->response.hdr.len, g_l2);
136 stw_p(&rrb->response.hdr.rsp, CLP_RC_OK);
137out:
138 if (rc) {
139 DPRINTF("list pci failed rc 0x%x\n", rc);
140 stw_p(&rrb->response.hdr.rsp, res_code);
141 }
142 return rc;
143}
144
145int clp_service_call(S390CPU *cpu, uint8_t r2)
146{
147 ClpReqHdr *reqh;
148 ClpRspHdr *resh;
149 S390PCIBusDevice *pbdev;
150 uint32_t req_len;
151 uint32_t res_len;
152 uint8_t buffer[4096 * 2];
153 uint8_t cc = 0;
154 CPUS390XState *env = &cpu->env;
155 S390pciState *s = s390_get_phb();
156 int i;
157
158 cpu_synchronize_state(CPU(cpu));
159
160 if (env->psw.mask & PSW_MASK_PSTATE) {
161 program_interrupt(env, PGM_PRIVILEGED, 4);
162 return 0;
163 }
164
165 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) {
166 return 0;
167 }
168 reqh = (ClpReqHdr *)buffer;
169 req_len = lduw_p(&reqh->len);
170 if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) {
171 program_interrupt(env, PGM_OPERAND, 4);
172 return 0;
173 }
174
175 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
176 req_len + sizeof(*resh))) {
177 return 0;
178 }
179 resh = (ClpRspHdr *)(buffer + req_len);
180 res_len = lduw_p(&resh->len);
181 if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) {
182 program_interrupt(env, PGM_OPERAND, 4);
183 return 0;
184 }
185 if ((req_len + res_len) > 8192) {
186 program_interrupt(env, PGM_OPERAND, 4);
187 return 0;
188 }
189
190 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer,
191 req_len + res_len)) {
192 return 0;
193 }
194
195 if (req_len != 32) {
196 stw_p(&resh->rsp, CLP_RC_LEN);
197 goto out;
198 }
199
200 switch (lduw_p(&reqh->cmd)) {
201 case CLP_LIST_PCI: {
202 ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer;
203 list_pci(rrb, &cc);
204 break;
205 }
206 case CLP_SET_PCI_FN: {
207 ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh;
208 ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh;
209
210 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh));
211 if (!pbdev) {
212 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH);
213 goto out;
214 }
215
216 switch (reqsetpci->oc) {
217 case CLP_SET_ENABLE_PCI_FN:
218 switch (reqsetpci->ndas) {
219 case 0:
220 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS);
221 goto out;
222 case 1:
223 break;
224 default:
225 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES);
226 goto out;
227 }
228
229 if (pbdev->fh & FH_MASK_ENABLE) {
230 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
231 goto out;
232 }
233
234 pbdev->fh |= FH_MASK_ENABLE;
235 pbdev->state = ZPCI_FS_ENABLED;
236 stl_p(&ressetpci->fh, pbdev->fh);
237 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
238 break;
239 case CLP_SET_DISABLE_PCI_FN:
240 if (!(pbdev->fh & FH_MASK_ENABLE)) {
241 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
242 goto out;
243 }
244 device_reset(DEVICE(pbdev));
245 pbdev->fh &= ~FH_MASK_ENABLE;
246 pbdev->state = ZPCI_FS_DISABLED;
247 stl_p(&ressetpci->fh, pbdev->fh);
248 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK);
249 break;
250 default:
251 DPRINTF("unknown set pci command\n");
252 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP);
253 break;
254 }
255 break;
256 }
257 case CLP_QUERY_PCI_FN: {
258 ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh;
259 ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh;
260
261 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh));
262 if (!pbdev) {
263 DPRINTF("query pci no pci dev\n");
264 stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH);
265 goto out;
266 }
267
268 for (i = 0; i < PCI_BAR_COUNT; i++) {
269 uint32_t data = pci_get_long(pbdev->pdev->config +
270 PCI_BASE_ADDRESS_0 + (i * 4));
271
272 stl_p(&resquery->bar[i], data);
273 resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ?
274 ctz64(pbdev->pdev->io_regions[i].size) : 0;
275 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i,
276 ldl_p(&resquery->bar[i]),
277 pbdev->pdev->io_regions[i].size,
278 resquery->bar_size[i]);
279 }
280
281 stq_p(&resquery->sdma, ZPCI_SDMA_ADDR);
282 stq_p(&resquery->edma, ZPCI_EDMA_ADDR);
283 stl_p(&resquery->fid, pbdev->fid);
284 stw_p(&resquery->pchid, 0);
285 stw_p(&resquery->ug, 1);
286 stl_p(&resquery->uid, pbdev->uid);
287 stw_p(&resquery->hdr.rsp, CLP_RC_OK);
288 break;
289 }
290 case CLP_QUERY_PCI_FNGRP: {
291 ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh;
292 resgrp->fr = 1;
293 stq_p(&resgrp->dasm, 0);
294 stq_p(&resgrp->msia, ZPCI_MSI_ADDR);
295 stw_p(&resgrp->mui, 0);
296 stw_p(&resgrp->i, 128);
297 resgrp->version = 0;
298
299 stw_p(&resgrp->hdr.rsp, CLP_RC_OK);
300 break;
301 }
302 default:
303 DPRINTF("unknown clp command\n");
304 stw_p(&resh->rsp, CLP_RC_CMD);
305 break;
306 }
307
308out:
309 if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer,
310 req_len + res_len)) {
311 return 0;
312 }
313 setcc(cpu, cc);
314 return 0;
315}
316
317int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
318{
319 CPUS390XState *env = &cpu->env;
320 S390PCIBusDevice *pbdev;
321 uint64_t offset;
322 uint64_t data;
323 MemoryRegion *mr;
324 MemTxResult result;
325 uint8_t len;
326 uint32_t fh;
327 uint8_t pcias;
328
329 cpu_synchronize_state(CPU(cpu));
330
331 if (env->psw.mask & PSW_MASK_PSTATE) {
332 program_interrupt(env, PGM_PRIVILEGED, 4);
333 return 0;
334 }
335
336 if (r2 & 0x1) {
337 program_interrupt(env, PGM_SPECIFICATION, 4);
338 return 0;
339 }
340
341 fh = env->regs[r2] >> 32;
342 pcias = (env->regs[r2] >> 16) & 0xf;
343 len = env->regs[r2] & 0xf;
344 offset = env->regs[r2 + 1];
345
346 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
347 if (!pbdev) {
348 DPRINTF("pcilg no pci dev\n");
349 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
350 return 0;
351 }
352
353 switch (pbdev->state) {
354 case ZPCI_FS_RESERVED:
355 case ZPCI_FS_STANDBY:
356 case ZPCI_FS_DISABLED:
357 case ZPCI_FS_PERMANENT_ERROR:
358 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
359 return 0;
360 case ZPCI_FS_ERROR:
361 setcc(cpu, ZPCI_PCI_LS_ERR);
362 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
363 return 0;
364 default:
365 break;
366 }
367
368 if (pcias < 6) {
369 if ((8 - (offset & 0x7)) < len) {
370 program_interrupt(env, PGM_OPERAND, 4);
371 return 0;
372 }
373 mr = pbdev->pdev->io_regions[pcias].memory;
374 result = memory_region_dispatch_read(mr, offset, &data, len,
375 MEMTXATTRS_UNSPECIFIED);
376 if (result != MEMTX_OK) {
377 program_interrupt(env, PGM_OPERAND, 4);
378 return 0;
379 }
380 } else if (pcias == 15) {
381 if ((4 - (offset & 0x3)) < len) {
382 program_interrupt(env, PGM_OPERAND, 4);
383 return 0;
384 }
385 data = pci_host_config_read_common(
386 pbdev->pdev, offset, pci_config_size(pbdev->pdev), len);
387
388 switch (len) {
389 case 1:
390 break;
391 case 2:
392 data = bswap16(data);
393 break;
394 case 4:
395 data = bswap32(data);
396 break;
397 case 8:
398 data = bswap64(data);
399 break;
400 default:
401 program_interrupt(env, PGM_OPERAND, 4);
402 return 0;
403 }
404 } else {
405 DPRINTF("invalid space\n");
406 setcc(cpu, ZPCI_PCI_LS_ERR);
407 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
408 return 0;
409 }
410
411 env->regs[r1] = data;
412 setcc(cpu, ZPCI_PCI_LS_OK);
413 return 0;
414}
415
416static int trap_msix(S390PCIBusDevice *pbdev, uint64_t offset, uint8_t pcias)
417{
418 if (pbdev->msix.available && pbdev->msix.table_bar == pcias &&
419 offset >= pbdev->msix.table_offset &&
420 offset < (pbdev->msix.table_offset +
421 pbdev->msix.entries * PCI_MSIX_ENTRY_SIZE)) {
422 return 1;
423 } else {
424 return 0;
425 }
426}
427
428int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
429{
430 CPUS390XState *env = &cpu->env;
431 uint64_t offset, data;
432 S390PCIBusDevice *pbdev;
433 MemoryRegion *mr;
434 MemTxResult result;
435 uint8_t len;
436 uint32_t fh;
437 uint8_t pcias;
438
439 cpu_synchronize_state(CPU(cpu));
440
441 if (env->psw.mask & PSW_MASK_PSTATE) {
442 program_interrupt(env, PGM_PRIVILEGED, 4);
443 return 0;
444 }
445
446 if (r2 & 0x1) {
447 program_interrupt(env, PGM_SPECIFICATION, 4);
448 return 0;
449 }
450
451 fh = env->regs[r2] >> 32;
452 pcias = (env->regs[r2] >> 16) & 0xf;
453 len = env->regs[r2] & 0xf;
454 offset = env->regs[r2 + 1];
455
456 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
457 if (!pbdev) {
458 DPRINTF("pcistg no pci dev\n");
459 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
460 return 0;
461 }
462
463 switch (pbdev->state) {
464 case ZPCI_FS_RESERVED:
465 case ZPCI_FS_STANDBY:
466 case ZPCI_FS_DISABLED:
467 case ZPCI_FS_PERMANENT_ERROR:
468 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
469 return 0;
470 case ZPCI_FS_ERROR:
471 setcc(cpu, ZPCI_PCI_LS_ERR);
472 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED);
473 return 0;
474 default:
475 break;
476 }
477
478 data = env->regs[r1];
479 if (pcias < 6) {
480 if ((8 - (offset & 0x7)) < len) {
481 program_interrupt(env, PGM_OPERAND, 4);
482 return 0;
483 }
484
485 if (trap_msix(pbdev, offset, pcias)) {
486 offset = offset - pbdev->msix.table_offset;
487 mr = &pbdev->pdev->msix_table_mmio;
488 } else {
489 mr = pbdev->pdev->io_regions[pcias].memory;
490 }
491
492 result = memory_region_dispatch_write(mr, offset, data, len,
493 MEMTXATTRS_UNSPECIFIED);
494 if (result != MEMTX_OK) {
495 program_interrupt(env, PGM_OPERAND, 4);
496 return 0;
497 }
498 } else if (pcias == 15) {
499 if ((4 - (offset & 0x3)) < len) {
500 program_interrupt(env, PGM_OPERAND, 4);
501 return 0;
502 }
503 switch (len) {
504 case 1:
505 break;
506 case 2:
507 data = bswap16(data);
508 break;
509 case 4:
510 data = bswap32(data);
511 break;
512 case 8:
513 data = bswap64(data);
514 break;
515 default:
516 program_interrupt(env, PGM_OPERAND, 4);
517 return 0;
518 }
519
520 pci_host_config_write_common(pbdev->pdev, offset,
521 pci_config_size(pbdev->pdev),
522 data, len);
523 } else {
524 DPRINTF("pcistg invalid space\n");
525 setcc(cpu, ZPCI_PCI_LS_ERR);
526 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS);
527 return 0;
528 }
529
530 setcc(cpu, ZPCI_PCI_LS_OK);
531 return 0;
532}
533
534int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2)
535{
536 CPUS390XState *env = &cpu->env;
537 uint32_t fh;
538 S390PCIBusDevice *pbdev;
539 S390PCIIOMMU *iommu;
540 hwaddr start, end;
541 IOMMUTLBEntry entry;
542 IOMMUMemoryRegion *iommu_mr;
543 IOMMUMemoryRegionClass *imrc;
544
545 cpu_synchronize_state(CPU(cpu));
546
547 if (env->psw.mask & PSW_MASK_PSTATE) {
548 program_interrupt(env, PGM_PRIVILEGED, 4);
549 goto out;
550 }
551
552 if (r2 & 0x1) {
553 program_interrupt(env, PGM_SPECIFICATION, 4);
554 goto out;
555 }
556
557 fh = env->regs[r1] >> 32;
558 start = env->regs[r2];
559 end = start + env->regs[r2 + 1];
560
561 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
562 if (!pbdev) {
563 DPRINTF("rpcit no pci dev\n");
564 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
565 goto out;
566 }
567
568 switch (pbdev->state) {
569 case ZPCI_FS_RESERVED:
570 case ZPCI_FS_STANDBY:
571 case ZPCI_FS_DISABLED:
572 case ZPCI_FS_PERMANENT_ERROR:
573 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
574 return 0;
575 case ZPCI_FS_ERROR:
576 setcc(cpu, ZPCI_PCI_LS_ERR);
577 s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER);
578 return 0;
579 default:
580 break;
581 }
582
583 iommu = pbdev->iommu;
584 if (!iommu->g_iota) {
585 pbdev->state = ZPCI_FS_ERROR;
586 setcc(cpu, ZPCI_PCI_LS_ERR);
587 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES);
588 s390_pci_generate_error_event(ERR_EVENT_INVALAS, pbdev->fh, pbdev->fid,
589 start, 0);
590 goto out;
591 }
592
593 if (end < iommu->pba || start > iommu->pal) {
594 pbdev->state = ZPCI_FS_ERROR;
595 setcc(cpu, ZPCI_PCI_LS_ERR);
596 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES);
597 s390_pci_generate_error_event(ERR_EVENT_OORANGE, pbdev->fh, pbdev->fid,
598 start, 0);
599 goto out;
600 }
601
602 iommu_mr = &iommu->iommu_mr;
603 imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
604
605 while (start < end) {
606 entry = imrc->translate(iommu_mr, start, IOMMU_NONE);
607
608 if (!entry.translated_addr) {
609 pbdev->state = ZPCI_FS_ERROR;
610 setcc(cpu, ZPCI_PCI_LS_ERR);
611 s390_set_status_code(env, r1, ZPCI_PCI_ST_INSUF_RES);
612 s390_pci_generate_error_event(ERR_EVENT_SERR, pbdev->fh, pbdev->fid,
613 start, ERR_EVENT_Q_BIT);
614 goto out;
615 }
616
617 memory_region_notify_iommu(iommu_mr, entry);
618 start += entry.addr_mask + 1;
619 }
620
621 setcc(cpu, ZPCI_PCI_LS_OK);
622out:
623 return 0;
624}
625
626int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
627 uint8_t ar)
628{
629 CPUS390XState *env = &cpu->env;
630 S390PCIBusDevice *pbdev;
631 MemoryRegion *mr;
632 MemTxResult result;
633 int i;
634 uint32_t fh;
635 uint8_t pcias;
636 uint8_t len;
637 uint8_t buffer[128];
638
639 if (env->psw.mask & PSW_MASK_PSTATE) {
640 program_interrupt(env, PGM_PRIVILEGED, 6);
641 return 0;
642 }
643
644 fh = env->regs[r1] >> 32;
645 pcias = (env->regs[r1] >> 16) & 0xf;
646 len = env->regs[r1] & 0xff;
647
648 if (pcias > 5) {
649 DPRINTF("pcistb invalid space\n");
650 setcc(cpu, ZPCI_PCI_LS_ERR);
651 s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS);
652 return 0;
653 }
654
655 switch (len) {
656 case 16:
657 case 32:
658 case 64:
659 case 128:
660 break;
661 default:
662 program_interrupt(env, PGM_SPECIFICATION, 6);
663 return 0;
664 }
665
666 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
667 if (!pbdev) {
668 DPRINTF("pcistb no pci dev fh 0x%x\n", fh);
669 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
670 return 0;
671 }
672
673 switch (pbdev->state) {
674 case ZPCI_FS_RESERVED:
675 case ZPCI_FS_STANDBY:
676 case ZPCI_FS_DISABLED:
677 case ZPCI_FS_PERMANENT_ERROR:
678 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
679 return 0;
680 case ZPCI_FS_ERROR:
681 setcc(cpu, ZPCI_PCI_LS_ERR);
682 s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED);
683 return 0;
684 default:
685 break;
686 }
687
688 mr = pbdev->pdev->io_regions[pcias].memory;
689 if (!memory_region_access_valid(mr, env->regs[r3], len, true)) {
690 program_interrupt(env, PGM_OPERAND, 6);
691 return 0;
692 }
693
694 if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) {
695 return 0;
696 }
697
698 for (i = 0; i < len / 8; i++) {
699 result = memory_region_dispatch_write(mr, env->regs[r3] + i * 8,
700 ldq_p(buffer + i * 8), 8,
701 MEMTXATTRS_UNSPECIFIED);
702 if (result != MEMTX_OK) {
703 program_interrupt(env, PGM_OPERAND, 6);
704 return 0;
705 }
706 }
707
708 setcc(cpu, ZPCI_PCI_LS_OK);
709 return 0;
710}
711
712static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib)
713{
714 int ret, len;
715 uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data));
716
717 pbdev->routes.adapter.adapter_id = css_get_adapter_id(
718 CSS_IO_ADAPTER_PCI, isc);
719 pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t));
720 len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long);
721 pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len);
722
723 ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
724 if (ret) {
725 goto out;
726 }
727
728 ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator);
729 if (ret) {
730 goto out;
731 }
732
733 pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb);
734 pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data));
735 pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv);
736 pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data));
737 pbdev->isc = isc;
738 pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data));
739 pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data));
740
741 DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
742 return 0;
743out:
744 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
745 release_indicator(&pbdev->routes.adapter, pbdev->indicator);
746 pbdev->summary_ind = NULL;
747 pbdev->indicator = NULL;
748 return ret;
749}
750
751int pci_dereg_irqs(S390PCIBusDevice *pbdev)
752{
753 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind);
754 release_indicator(&pbdev->routes.adapter, pbdev->indicator);
755
756 pbdev->summary_ind = NULL;
757 pbdev->indicator = NULL;
758 pbdev->routes.adapter.summary_addr = 0;
759 pbdev->routes.adapter.summary_offset = 0;
760 pbdev->routes.adapter.ind_addr = 0;
761 pbdev->routes.adapter.ind_offset = 0;
762 pbdev->isc = 0;
763 pbdev->noi = 0;
764 pbdev->sum = 0;
765
766 DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id);
767 return 0;
768}
769
770static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib)
771{
772 uint64_t pba = ldq_p(&fib.pba);
773 uint64_t pal = ldq_p(&fib.pal);
774 uint64_t g_iota = ldq_p(&fib.iota);
775 uint8_t dt = (g_iota >> 2) & 0x7;
776 uint8_t t = (g_iota >> 11) & 0x1;
777
778 if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) {
779 program_interrupt(env, PGM_OPERAND, 6);
780 return -EINVAL;
781 }
782
783
784 if (!(dt == ZPCI_IOTA_RTTO && t)) {
785 error_report("unsupported ioat dt %d t %d", dt, t);
786 program_interrupt(env, PGM_OPERAND, 6);
787 return -EINVAL;
788 }
789
790 iommu->pba = pba;
791 iommu->pal = pal;
792 iommu->g_iota = g_iota;
793
794 s390_pci_iommu_enable(iommu);
795
796 return 0;
797}
798
799void pci_dereg_ioat(S390PCIIOMMU *iommu)
800{
801 s390_pci_iommu_disable(iommu);
802 iommu->pba = 0;
803 iommu->pal = 0;
804 iommu->g_iota = 0;
805}
806
807int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar)
808{
809 CPUS390XState *env = &cpu->env;
810 uint8_t oc, dmaas;
811 uint32_t fh;
812 ZpciFib fib;
813 S390PCIBusDevice *pbdev;
814 uint64_t cc = ZPCI_PCI_LS_OK;
815
816 if (env->psw.mask & PSW_MASK_PSTATE) {
817 program_interrupt(env, PGM_PRIVILEGED, 6);
818 return 0;
819 }
820
821 oc = env->regs[r1] & 0xff;
822 dmaas = (env->regs[r1] >> 16) & 0xff;
823 fh = env->regs[r1] >> 32;
824
825 if (fiba & 0x7) {
826 program_interrupt(env, PGM_SPECIFICATION, 6);
827 return 0;
828 }
829
830 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh);
831 if (!pbdev) {
832 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh);
833 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
834 return 0;
835 }
836
837 switch (pbdev->state) {
838 case ZPCI_FS_RESERVED:
839 case ZPCI_FS_STANDBY:
840 case ZPCI_FS_DISABLED:
841 case ZPCI_FS_PERMANENT_ERROR:
842 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
843 return 0;
844 default:
845 break;
846 }
847
848 if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
849 return 0;
850 }
851
852 if (fib.fmt != 0) {
853 program_interrupt(env, PGM_OPERAND, 6);
854 return 0;
855 }
856
857 switch (oc) {
858 case ZPCI_MOD_FC_REG_INT:
859 if (pbdev->summary_ind) {
860 cc = ZPCI_PCI_LS_ERR;
861 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
862 } else if (reg_irqs(env, pbdev, fib)) {
863 cc = ZPCI_PCI_LS_ERR;
864 s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL);
865 }
866 break;
867 case ZPCI_MOD_FC_DEREG_INT:
868 if (!pbdev->summary_ind) {
869 cc = ZPCI_PCI_LS_ERR;
870 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
871 } else {
872 pci_dereg_irqs(pbdev);
873 }
874 break;
875 case ZPCI_MOD_FC_REG_IOAT:
876 if (dmaas != 0) {
877 cc = ZPCI_PCI_LS_ERR;
878 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
879 } else if (pbdev->iommu->enabled) {
880 cc = ZPCI_PCI_LS_ERR;
881 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
882 } else if (reg_ioat(env, pbdev->iommu, fib)) {
883 cc = ZPCI_PCI_LS_ERR;
884 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
885 }
886 break;
887 case ZPCI_MOD_FC_DEREG_IOAT:
888 if (dmaas != 0) {
889 cc = ZPCI_PCI_LS_ERR;
890 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
891 } else if (!pbdev->iommu->enabled) {
892 cc = ZPCI_PCI_LS_ERR;
893 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
894 } else {
895 pci_dereg_ioat(pbdev->iommu);
896 }
897 break;
898 case ZPCI_MOD_FC_REREG_IOAT:
899 if (dmaas != 0) {
900 cc = ZPCI_PCI_LS_ERR;
901 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL);
902 } else if (!pbdev->iommu->enabled) {
903 cc = ZPCI_PCI_LS_ERR;
904 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
905 } else {
906 pci_dereg_ioat(pbdev->iommu);
907 if (reg_ioat(env, pbdev->iommu, fib)) {
908 cc = ZPCI_PCI_LS_ERR;
909 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES);
910 }
911 }
912 break;
913 case ZPCI_MOD_FC_RESET_ERROR:
914 switch (pbdev->state) {
915 case ZPCI_FS_BLOCKED:
916 case ZPCI_FS_ERROR:
917 pbdev->state = ZPCI_FS_ENABLED;
918 break;
919 default:
920 cc = ZPCI_PCI_LS_ERR;
921 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
922 }
923 break;
924 case ZPCI_MOD_FC_RESET_BLOCK:
925 switch (pbdev->state) {
926 case ZPCI_FS_ERROR:
927 pbdev->state = ZPCI_FS_BLOCKED;
928 break;
929 default:
930 cc = ZPCI_PCI_LS_ERR;
931 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE);
932 }
933 break;
934 case ZPCI_MOD_FC_SET_MEASURE:
935 pbdev->fmb_addr = ldq_p(&fib.fmb_addr);
936 break;
937 default:
938 program_interrupt(&cpu->env, PGM_OPERAND, 6);
939 cc = ZPCI_PCI_LS_ERR;
940 }
941
942 setcc(cpu, cc);
943 return 0;
944}
945
946int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar)
947{
948 CPUS390XState *env = &cpu->env;
949 uint8_t dmaas;
950 uint32_t fh;
951 ZpciFib fib;
952 S390PCIBusDevice *pbdev;
953 uint32_t data;
954 uint64_t cc = ZPCI_PCI_LS_OK;
955
956 if (env->psw.mask & PSW_MASK_PSTATE) {
957 program_interrupt(env, PGM_PRIVILEGED, 6);
958 return 0;
959 }
960
961 fh = env->regs[r1] >> 32;
962 dmaas = (env->regs[r1] >> 16) & 0xff;
963
964 if (dmaas) {
965 setcc(cpu, ZPCI_PCI_LS_ERR);
966 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS);
967 return 0;
968 }
969
970 if (fiba & 0x7) {
971 program_interrupt(env, PGM_SPECIFICATION, 6);
972 return 0;
973 }
974
975 pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX);
976 if (!pbdev) {
977 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
978 return 0;
979 }
980
981 memset(&fib, 0, sizeof(fib));
982
983 switch (pbdev->state) {
984 case ZPCI_FS_RESERVED:
985 case ZPCI_FS_STANDBY:
986 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
987 return 0;
988 case ZPCI_FS_DISABLED:
989 if (fh & FH_MASK_ENABLE) {
990 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE);
991 return 0;
992 }
993 goto out;
994
995
996 case ZPCI_FS_ERROR:
997 fib.fc |= 0x20;
998 case ZPCI_FS_BLOCKED:
999 fib.fc |= 0x40;
1000 case ZPCI_FS_ENABLED:
1001 fib.fc |= 0x80;
1002 if (pbdev->iommu->enabled) {
1003 fib.fc |= 0x10;
1004 }
1005 if (!(fh & FH_MASK_ENABLE)) {
1006 env->regs[r1] |= 1ULL << 63;
1007 }
1008 break;
1009 case ZPCI_FS_PERMANENT_ERROR:
1010 setcc(cpu, ZPCI_PCI_LS_ERR);
1011 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR);
1012 return 0;
1013 }
1014
1015 stq_p(&fib.pba, pbdev->iommu->pba);
1016 stq_p(&fib.pal, pbdev->iommu->pal);
1017 stq_p(&fib.iota, pbdev->iommu->g_iota);
1018 stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr);
1019 stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr);
1020 stq_p(&fib.fmb_addr, pbdev->fmb_addr);
1021
1022 data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) |
1023 ((uint32_t)pbdev->routes.adapter.ind_offset << 8) |
1024 ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset;
1025 stl_p(&fib.data, data);
1026
1027out:
1028 if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) {
1029 return 0;
1030 }
1031
1032 setcc(cpu, cc);
1033 return 0;
1034}
1035
