LXR qemu/target/microblaze/helper.c

   1/*
   2 *  MicroBlaze helper routines.
   3 *
   4 *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
   5 *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "cpu.h"
  23#include "exec/exec-all.h"
  24#include "qemu/host-utils.h"
  25#include "exec/log.h"
  26
  27#define D(x)
  28
  29#if defined(CONFIG_USER_ONLY)
  30
  31void mb_cpu_do_interrupt(CPUState *cs)
  32{
  33    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  34    CPUMBState *env = &cpu->env;
  35
  36    cs->exception_index = -1;
  37    env->res_addr = RES_ADDR_NONE;
  38    env->regs[14] = env->sregs[SR_PC];
  39}
  40
  41int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  42                            int mmu_idx)
  43{
  44    cs->exception_index = 0xaa;
  45    cpu_dump_state(cs, stderr, fprintf, 0);
  46    return 1;
  47}
  48
  49#else /* !CONFIG_USER_ONLY */
  50
  51int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  52                            int mmu_idx)
  53{
  54    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  55    CPUMBState *env = &cpu->env;
  56    unsigned int hit;
  57    unsigned int mmu_available;
  58    int r = 1;
  59    int prot;
  60
  61    mmu_available = 0;
  62    if (cpu->cfg.use_mmu) {
  63        mmu_available = 1;
  64        if ((cpu->cfg.pvr == C_PVR_FULL) &&
  65            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
  66            mmu_available = 0;
  67        }
  68    }
  69
  70    /* Translate if the MMU is available and enabled.  */
  71    if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
  72        target_ulong vaddr, paddr;
  73        struct microblaze_mmu_lookup lu;
  74
  75        hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
  76        if (hit) {
  77            vaddr = address & TARGET_PAGE_MASK;
  78            paddr = lu.paddr + vaddr - lu.vaddr;
  79
  80            qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n",
  81                    mmu_idx, vaddr, paddr, lu.prot);
  82            tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
  83            r = 0;
  84        } else {
  85            env->sregs[SR_EAR] = address;
  86            qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n",
  87                                        mmu_idx, address);
  88
  89            switch (lu.err) {
  90                case ERR_PROT:
  91                    env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
  92                    env->sregs[SR_ESR] |= (rw == 1) << 10;
  93                    break;
  94                case ERR_MISS:
  95                    env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
  96                    env->sregs[SR_ESR] |= (rw == 1) << 10;
  97                    break;
  98                default:
  99                    abort();
 100                    break;
 101            }
 102
 103            if (cs->exception_index == EXCP_MMU) {
 104                cpu_abort(cs, "recursive faults\n");
 105            }
 106
 107            /* TLB miss.  */
 108            cs->exception_index = EXCP_MMU;
 109        }
 110    } else {
 111        /* MMU disabled or not available.  */
 112        address &= TARGET_PAGE_MASK;
 113        prot = PAGE_BITS;
 114        tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
 115        r = 0;
 116    }
 117    return r;
 118}
 119
 120#include "hw/remote-port.h"
 121
 122void mb_cpu_do_interrupt(CPUState *cs)
 123{
 124    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 125    CPUMBState *env = &cpu->env;
 126    uint32_t t;
 127
 128    /* IMM flag cannot propagate across a branch and into the dslot.  */
 129    assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
 130    assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
 131/*    assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions.  */
 132    if (env->res_addr != RES_ADDR_NONE) {
 133        env->res_addr = RES_ADDR_NONE;
 134    }
 135    switch (cs->exception_index) {
 136        case EXCP_HW_EXCP:
 137            if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
 138                qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system without exceptions!\n");
 139                return;
 140            }
 141
 142            env->regs[17] = env->sregs[SR_PC] + 4;
 143            env->sregs[SR_ESR] &= ~(1 << 12);
 144
 145            /* Exception breaks branch + dslot sequence?  */
 146            if (env->iflags & D_FLAG) {
 147                env->sregs[SR_ESR] |= 1 << 12 ;
 148                env->sregs[SR_BTR] = env->btarget;
 149            }
 150
 151            /* Disable the MMU.  */
 152            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 153            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 154            env->sregs[SR_MSR] |= t;
 155            /* Exception in progress.  */
 156            env->sregs[SR_MSR] |= MSR_EIP;
 157
 158            qemu_log_mask(CPU_LOG_INT,
 159                          "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
 160                          env->sregs[SR_PC], env->sregs[SR_EAR],
 161                          env->sregs[SR_ESR], env->iflags);
 162            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 163            env->iflags &= ~(IMM_FLAG | D_FLAG);
 164            env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
 165            break;
 166
 167        case EXCP_MMU:
 168            env->regs[17] = env->sregs[SR_PC];
 169
 170            env->sregs[SR_ESR] &= ~(1 << 12);
 171            /* Exception breaks branch + dslot sequence?  */
 172            if (env->iflags & D_FLAG) {
 173                D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
 174                env->sregs[SR_ESR] |= 1 << 12 ;
 175                env->sregs[SR_BTR] = env->btarget;
 176
 177                /* Reexecute the branch.  */
 178                env->regs[17] -= 4;
 179                /* was the branch immprefixed?.  */
 180                if (env->bimm) {
 181                    qemu_log_mask(CPU_LOG_INT,
 182                                  "bimm exception at pc=%x iflags=%x\n",
 183                                  env->sregs[SR_PC], env->iflags);
 184                    env->regs[17] -= 4;
 185                    log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 186                }
 187            } else if (env->iflags & IMM_FLAG) {
 188                D(qemu_log("IMM_FLAG set at exception\n"));
 189                env->regs[17] -= 4;
 190            }
 191
 192            /* Disable the MMU.  */
 193            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 194            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 195            env->sregs[SR_MSR] |= t;
 196            /* Exception in progress.  */
 197            env->sregs[SR_MSR] |= MSR_EIP;
 198
 199            qemu_log_mask(CPU_LOG_INT,
 200                          "exception at pc=%x ear=%x iflags=%x\n",
 201                          env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
 202            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 203            env->iflags &= ~(IMM_FLAG | D_FLAG);
 204            env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
 205            break;
 206
 207        case EXCP_IRQ:
 208            assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
 209            assert(env->sregs[SR_MSR] & MSR_IE);
 210            assert(!(env->iflags & D_FLAG));
 211
 212            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 213
 214#if 0
 215#include "disas/disas.h"
 216
 217/* Useful instrumentation when debugging interrupt issues in either
 218   the models or in sw.  */
 219            {
 220                const char *sym;
 221
 222                sym = lookup_symbol(env->sregs[SR_PC]);
 223                if (sym
 224                    && (!strcmp("netif_rx", sym)
 225                        || !strcmp("process_backlog", sym))) {
 226
 227                    qemu_log(
 228                         "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
 229                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
 230                         sym);
 231
 232                    log_cpu_state(cs, 0);
 233                }
 234            }
 235#endif
 236            qemu_log_mask(CPU_LOG_INT,
 237                         "interrupt at pc=%x msr=%x %x iflags=%x\n",
 238                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
 239
 240            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
 241                                    | MSR_UM | MSR_IE);
 242            env->sregs[SR_MSR] |= t;
 243
 244            env->regs[14] = env->sregs[SR_PC];
 245            env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10;
 246            //log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 247            break;
 248
 249        case EXCP_BREAK:
 250        case EXCP_HW_BREAK:
 251            assert(!(env->iflags & IMM_FLAG));
 252            assert(!(env->iflags & D_FLAG));
 253            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 254            qemu_log_mask(CPU_LOG_INT,
 255                        "break at pc=%x msr=%x %x iflags=%x\n",
 256                        env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
 257            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 258            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 259            env->sregs[SR_MSR] |= t;
 260            env->sregs[SR_MSR] |= MSR_BIP;
 261            if (cs->exception_index == EXCP_HW_BREAK) {
 262                env->regs[16] = env->sregs[SR_PC];
 263                env->sregs[SR_MSR] |= MSR_BIP;
 264                env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18;
 265            } else
 266                env->sregs[SR_PC] = env->btarget;
 267            break;
 268        default:
 269            cpu_abort(cs, "unhandled exception type=%d\n",
 270                      cs->exception_index);
 271            break;
 272    }
 273}
 274
 275hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 276{
 277    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 278    CPUMBState *env = &cpu->env;
 279    target_ulong vaddr, paddr = 0;
 280    struct microblaze_mmu_lookup lu;
 281    unsigned int hit;
 282
 283    if (env->sregs[SR_MSR] & MSR_VM) {
 284        hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
 285        if (hit) {
 286            vaddr = addr & TARGET_PAGE_MASK;
 287            paddr = lu.paddr + vaddr - lu.vaddr;
 288        } else
 289            paddr = 0; /* ???.  */
 290    } else
 291        paddr = addr & TARGET_PAGE_MASK;
 292
 293    return paddr;
 294}
 295#endif
 296
 297bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 298{
 299    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 300    CPUMBState *env = &cpu->env;
 301
 302    if ((interrupt_request & CPU_INTERRUPT_HARD)
 303        && (env->sregs[SR_MSR] & MSR_IE)
 304        && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
 305        && !(env->iflags & (D_FLAG | IMM_FLAG))) {
 306        cs->exception_index = EXCP_IRQ;
 307        mb_cpu_do_interrupt(cs);
 308        return true;
 309    }
 310    return false;
 311}
 312