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20#include "qemu/osdep.h"
21#include "qapi/error.h"
22#include "hw/sysbus.h"
23#include "hw/arm/arm.h"
24#include "hw/devices.h"
25#include "hw/loader.h"
26#include "net/net.h"
27#include "sysemu/kvm.h"
28#include "sysemu/sysemu.h"
29#include "hw/boards.h"
30#include "sysemu/block-backend.h"
31#include "exec/address-spaces.h"
32#include "qemu/error-report.h"
33#include "hw/char/pl011.h"
34#include "hw/ide/ahci.h"
35#include "hw/cpu/a9mpcore.h"
36#include "hw/cpu/a15mpcore.h"
37#include "qemu/log.h"
38
39#define SMP_BOOT_ADDR 0x100
40#define SMP_BOOT_REG 0x40
41#define MPCORE_PERIPHBASE 0xfff10000
42
43#define MVBAR_ADDR 0x200
44#define BOARD_SETUP_ADDR (MVBAR_ADDR + 8 * sizeof(uint32_t))
45
46#define NIRQ_GIC 160
47
48
49
50static void hb_write_board_setup(ARMCPU *cpu,
51 const struct arm_boot_info *info)
52{
53 arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
54}
55
56static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
57{
58 int n;
59 uint32_t smpboot[] = {
60 0xee100fb0,
61 0xe210000f,
62 0xe3a03040,
63 0xe0830200,
64 0xe59f2024,
65 0xe3a01001,
66 0xe5821100,
67 0xe3a010ff,
68 0xe5821104,
69 0xf57ff04f,
70 0xe320f003,
71 0xe5901000,
72 0xe1110001,
73 0x0afffffb,
74 0xe12fff11,
75 MPCORE_PERIPHBASE
76 };
77 for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
78 smpboot[n] = tswap32(smpboot[n]);
79 }
80 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
81}
82
83static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
84{
85 CPUARMState *env = &cpu->env;
86
87 switch (info->nb_cpus) {
88 case 4:
89 address_space_stl_notdirty(&address_space_memory,
90 SMP_BOOT_REG + 0x30, 0,
91 MEMTXATTRS_UNSPECIFIED, NULL);
92 case 3:
93 address_space_stl_notdirty(&address_space_memory,
94 SMP_BOOT_REG + 0x20, 0,
95 MEMTXATTRS_UNSPECIFIED, NULL);
96 case 2:
97 address_space_stl_notdirty(&address_space_memory,
98 SMP_BOOT_REG + 0x10, 0,
99 MEMTXATTRS_UNSPECIFIED, NULL);
100 env->regs[15] = SMP_BOOT_ADDR;
101 break;
102 default:
103 break;
104 }
105}
106
107#define NUM_REGS 0x200
108static void hb_regs_write(void *opaque, hwaddr offset,
109 uint64_t value, unsigned size)
110{
111 uint32_t *regs = opaque;
112
113 if (offset == 0xf00) {
114 if (value == 1 || value == 2) {
115 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
116 } else if (value == 3) {
117 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
118 }
119 }
120
121 if (offset / 4 >= NUM_REGS) {
122 qemu_log_mask(LOG_GUEST_ERROR,
123 "highbank: bad write offset 0x%" HWADDR_PRIx "\n", offset);
124 return;
125 }
126 regs[offset / 4] = value;
127}
128
129static uint64_t hb_regs_read(void *opaque, hwaddr offset,
130 unsigned size)
131{
132 uint32_t value;
133 uint32_t *regs = opaque;
134
135 if (offset / 4 >= NUM_REGS) {
136 qemu_log_mask(LOG_GUEST_ERROR,
137 "highbank: bad read offset 0x%" HWADDR_PRIx "\n", offset);
138 return 0;
139 }
140 value = regs[offset / 4];
141
142 if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
143 value |= 0x30000000;
144 }
145
146 return value;
147}
148
149static const MemoryRegionOps hb_mem_ops = {
150 .read = hb_regs_read,
151 .write = hb_regs_write,
152 .endianness = DEVICE_NATIVE_ENDIAN,
153};
154
155#define TYPE_HIGHBANK_REGISTERS "highbank-regs"
156#define HIGHBANK_REGISTERS(obj) \
157 OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
158
159typedef struct {
160
161 SysBusDevice parent_obj;
162
163
164 MemoryRegion iomem;
165 uint32_t regs[NUM_REGS];
166} HighbankRegsState;
167
168static VMStateDescription vmstate_highbank_regs = {
169 .name = "highbank-regs",
170 .version_id = 0,
171 .minimum_version_id = 0,
172 .fields = (VMStateField[]) {
173 VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
174 VMSTATE_END_OF_LIST(),
175 },
176};
177
178static void highbank_regs_reset(DeviceState *dev)
179{
180 HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
181
182 s->regs[0x40] = 0x05F20121;
183 s->regs[0x41] = 0x2;
184 s->regs[0x42] = 0x05F30121;
185 s->regs[0x43] = 0x05F40121;
186}
187
188static void highbank_regs_init(Object *obj)
189{
190 HighbankRegsState *s = HIGHBANK_REGISTERS(obj);
191 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
192
193 memory_region_init_io(&s->iomem, obj, &hb_mem_ops, s->regs,
194 "highbank_regs", 0x1000);
195 sysbus_init_mmio(dev, &s->iomem);
196}
197
198static void highbank_regs_class_init(ObjectClass *klass, void *data)
199{
200 DeviceClass *dc = DEVICE_CLASS(klass);
201
202 dc->desc = "Calxeda Highbank registers";
203 dc->vmsd = &vmstate_highbank_regs;
204 dc->reset = highbank_regs_reset;
205}
206
207static const TypeInfo highbank_regs_info = {
208 .name = TYPE_HIGHBANK_REGISTERS,
209 .parent = TYPE_SYS_BUS_DEVICE,
210 .instance_size = sizeof(HighbankRegsState),
211 .instance_init = highbank_regs_init,
212 .class_init = highbank_regs_class_init,
213};
214
215static void highbank_regs_register_types(void)
216{
217 type_register_static(&highbank_regs_info);
218}
219
220type_init(highbank_regs_register_types)
221
222static struct arm_boot_info highbank_binfo;
223
224enum cxmachines {
225 CALXEDA_HIGHBANK,
226 CALXEDA_MIDWAY,
227};
228
229
230
231
232
233
234
235static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
236{
237 ram_addr_t ram_size = machine->ram_size;
238 const char *kernel_filename = machine->kernel_filename;
239 const char *kernel_cmdline = machine->kernel_cmdline;
240 const char *initrd_filename = machine->initrd_filename;
241 DeviceState *dev = NULL;
242 SysBusDevice *busdev;
243 qemu_irq pic[128];
244 int n;
245 qemu_irq cpu_irq[4];
246 qemu_irq cpu_fiq[4];
247 MemoryRegion *sysram;
248 MemoryRegion *dram;
249 MemoryRegion *sysmem;
250 char *sysboot_filename;
251
252 switch (machine_id) {
253 case CALXEDA_HIGHBANK:
254 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
255 break;
256 case CALXEDA_MIDWAY:
257 machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
258 break;
259 default:
260 assert(0);
261 }
262
263 for (n = 0; n < smp_cpus; n++) {
264 Object *cpuobj;
265 ARMCPU *cpu;
266
267 cpuobj = object_new(machine->cpu_type);
268 cpu = ARM_CPU(cpuobj);
269
270 object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,
271 "psci-conduit", &error_abort);
272
273 if (n) {
274
275 object_property_set_bool(cpuobj, true,
276 "start-powered-off", &error_abort);
277 }
278
279 if (object_property_find(cpuobj, "reset-cbar", NULL)) {
280 object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
281 "reset-cbar", &error_abort);
282 }
283 object_property_set_bool(cpuobj, true, "realized", &error_fatal);
284 cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
285 cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
286 }
287
288 sysmem = get_system_memory();
289 dram = g_new(MemoryRegion, 1);
290 memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
291
292 memory_region_add_subregion(sysmem, 0, dram);
293
294 sysram = g_new(MemoryRegion, 1);
295 memory_region_init_ram_nomigrate(sysram, NULL, "highbank.sysram", 0x8000,
296 &error_fatal);
297 memory_region_add_subregion(sysmem, 0xfff88000, sysram);
298 if (bios_name != NULL) {
299 sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
300 if (sysboot_filename != NULL) {
301 if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
302 error_report("Unable to load %s", bios_name);
303 exit(1);
304 }
305 g_free(sysboot_filename);
306 } else {
307 error_report("Unable to find %s", bios_name);
308 exit(1);
309 }
310 }
311
312 switch (machine_id) {
313 case CALXEDA_HIGHBANK:
314 dev = qdev_create(NULL, "l2x0");
315 qdev_init_nofail(dev);
316 busdev = SYS_BUS_DEVICE(dev);
317 sysbus_mmio_map(busdev, 0, 0xfff12000);
318
319 dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
320 break;
321 case CALXEDA_MIDWAY:
322 dev = qdev_create(NULL, TYPE_A15MPCORE_PRIV);
323 break;
324 }
325 qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
326 qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
327 qdev_init_nofail(dev);
328 busdev = SYS_BUS_DEVICE(dev);
329 sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
330 for (n = 0; n < smp_cpus; n++) {
331 sysbus_connect_irq(busdev, n, cpu_irq[n]);
332 sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
333 }
334
335 for (n = 0; n < 128; n++) {
336 pic[n] = qdev_get_gpio_in(dev, n);
337 }
338
339 dev = qdev_create(NULL, "sp804");
340 qdev_prop_set_uint32(dev, "freq0", 150000000);
341 qdev_prop_set_uint32(dev, "freq1", 150000000);
342 qdev_init_nofail(dev);
343 busdev = SYS_BUS_DEVICE(dev);
344 sysbus_mmio_map(busdev, 0, 0xfff34000);
345 sysbus_connect_irq(busdev, 0, pic[18]);
346 pl011_create(0xfff36000, pic[20], serial_hds[0]);
347
348 dev = qdev_create(NULL, TYPE_HIGHBANK_REGISTERS);
349 qdev_init_nofail(dev);
350 busdev = SYS_BUS_DEVICE(dev);
351 sysbus_mmio_map(busdev, 0, 0xfff3c000);
352
353 sysbus_create_simple("pl061", 0xfff30000, pic[14]);
354 sysbus_create_simple("pl061", 0xfff31000, pic[15]);
355 sysbus_create_simple("pl061", 0xfff32000, pic[16]);
356 sysbus_create_simple("pl061", 0xfff33000, pic[17]);
357 sysbus_create_simple("pl031", 0xfff35000, pic[19]);
358 sysbus_create_simple("pl022", 0xfff39000, pic[23]);
359
360 sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]);
361
362 if (nd_table[0].used) {
363 qemu_check_nic_model(&nd_table[0], "xgmac");
364 dev = qdev_create(NULL, "xgmac");
365 qdev_set_nic_properties(dev, &nd_table[0]);
366 qdev_init_nofail(dev);
367 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
368 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
369 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
370 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
371
372 qemu_check_nic_model(&nd_table[1], "xgmac");
373 dev = qdev_create(NULL, "xgmac");
374 qdev_set_nic_properties(dev, &nd_table[1]);
375 qdev_init_nofail(dev);
376 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
377 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
378 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
379 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
380 }
381
382
383
384 highbank_binfo.ram_size = ram_size;
385 highbank_binfo.kernel_filename = kernel_filename;
386 highbank_binfo.kernel_cmdline = kernel_cmdline;
387 highbank_binfo.initrd_filename = initrd_filename;
388
389
390
391
392 highbank_binfo.board_id = -1;
393 highbank_binfo.nb_cpus = smp_cpus;
394 highbank_binfo.loader_start = 0;
395 highbank_binfo.write_secondary_boot = hb_write_secondary;
396 highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
397 if (!kvm_enabled()) {
398 highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
399 highbank_binfo.write_board_setup = hb_write_board_setup;
400 highbank_binfo.secure_board_setup = true;
401 } else {
402 warn_report("cannot load built-in Monitor support "
403 "if KVM is enabled. Some guests (such as Linux) "
404 "may not boot.");
405 }
406
407 arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
408}
409
410static void highbank_init(MachineState *machine)
411{
412 calxeda_init(machine, CALXEDA_HIGHBANK);
413}
414
415static void midway_init(MachineState *machine)
416{
417 calxeda_init(machine, CALXEDA_MIDWAY);
418}
419
420static void highbank_class_init(ObjectClass *oc, void *data)
421{
422 MachineClass *mc = MACHINE_CLASS(oc);
423
424 mc->desc = "Calxeda Highbank (ECX-1000)";
425 mc->init = highbank_init;
426 mc->block_default_type = IF_IDE;
427 mc->units_per_default_bus = 1;
428 mc->max_cpus = 4;
429 mc->ignore_memory_transaction_failures = true;
430}
431
432static const TypeInfo highbank_type = {
433 .name = MACHINE_TYPE_NAME("highbank"),
434 .parent = TYPE_MACHINE,
435 .class_init = highbank_class_init,
436};
437
438static void midway_class_init(ObjectClass *oc, void *data)
439{
440 MachineClass *mc = MACHINE_CLASS(oc);
441
442 mc->desc = "Calxeda Midway (ECX-2000)";
443 mc->init = midway_init;
444 mc->block_default_type = IF_IDE;
445 mc->units_per_default_bus = 1;
446 mc->max_cpus = 4;
447 mc->ignore_memory_transaction_failures = true;
448}
449
450static const TypeInfo midway_type = {
451 .name = MACHINE_TYPE_NAME("midway"),
452 .parent = TYPE_MACHINE,
453 .class_init = midway_class_init,
454};
455
456static void calxeda_machines_init(void)
457{
458 type_register_static(&highbank_type);
459 type_register_static(&midway_type);
460}
461
462type_init(calxeda_machines_init)
463