LXR qemu/hw/dma/puv3

   1/*
   2 * DMA device simulation in PKUnity SoC
   3 *
   4 * Copyright (C) 2010-2012 Guan Xuetao
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation, or any later version.
   9 * See the COPYING file in the top-level directory.
  10 */
  11#include "qemu/osdep.h"
  12#include "hw/hw.h"
  13#include "hw/sysbus.h"
  14
  15#undef DEBUG_PUV3
  16#include "hw/unicore32/puv3.h"
  17
  18#define PUV3_DMA_CH_NR          (6)
  19#define PUV3_DMA_CH_MASK        (0xff)
  20#define PUV3_DMA_CH(offset)     ((offset) >> 8)
  21
  22#define TYPE_PUV3_DMA "puv3_dma"
  23#define PUV3_DMA(obj) OBJECT_CHECK(PUV3DMAState, (obj), TYPE_PUV3_DMA)
  24
  25typedef struct PUV3DMAState {
  26    SysBusDevice parent_obj;
  27
  28    MemoryRegion iomem;
  29    uint32_t reg_CFG[PUV3_DMA_CH_NR];
  30} PUV3DMAState;
  31
  32static uint64_t puv3_dma_read(void *opaque, hwaddr offset,
  33        unsigned size)
  34{
  35    PUV3DMAState *s = opaque;
  36    uint32_t ret = 0;
  37
  38    assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
  39
  40    switch (offset & PUV3_DMA_CH_MASK) {
  41    case 0x10:
  42        ret = s->reg_CFG[PUV3_DMA_CH(offset)];
  43        break;
  44    default:
  45        DPRINTF("Bad offset 0x%x\n", offset);
  46    }
  47    DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  48
  49    return ret;
  50}
  51
  52static void puv3_dma_write(void *opaque, hwaddr offset,
  53        uint64_t value, unsigned size)
  54{
  55    PUV3DMAState *s = opaque;
  56
  57    assert(PUV3_DMA_CH(offset) < PUV3_DMA_CH_NR);
  58
  59    switch (offset & PUV3_DMA_CH_MASK) {
  60    case 0x10:
  61        s->reg_CFG[PUV3_DMA_CH(offset)] = value;
  62        break;
  63    default:
  64        DPRINTF("Bad offset 0x%x\n", offset);
  65    }
  66    DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  67}
  68
  69static const MemoryRegionOps puv3_dma_ops = {
  70    .read = puv3_dma_read,
  71    .write = puv3_dma_write,
  72    .impl = {
  73        .min_access_size = 4,
  74        .max_access_size = 4,
  75    },
  76    .endianness = DEVICE_NATIVE_ENDIAN,
  77};
  78
  79static int puv3_dma_init(SysBusDevice *dev)
  80{
  81    PUV3DMAState *s = PUV3_DMA(dev);
  82    int i;
  83
  84    for (i = 0; i < PUV3_DMA_CH_NR; i++) {
  85        s->reg_CFG[i] = 0x0;
  86    }
  87
  88    memory_region_init_io(&s->iomem, OBJECT(s), &puv3_dma_ops, s, "puv3_dma",
  89            PUV3_REGS_OFFSET);
  90    sysbus_init_mmio(dev, &s->iomem);
  91
  92    return 0;
  93}
  94
  95static void puv3_dma_class_init(ObjectClass *klass, void *data)
  96{
  97    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
  98
  99    sdc->init = puv3_dma_init;
 100}
 101
 102static const TypeInfo puv3_dma_info = {
 103    .name = TYPE_PUV3_DMA,
 104    .parent = TYPE_SYS_BUS_DEVICE,
 105    .instance_size = sizeof(PUV3DMAState),
 106    .class_init = puv3_dma_class_init,
 107};
 108
 109static void puv3_dma_register_type(void)
 110{
 111    type_register_static(&puv3_dma_info);
 112}
 113
 114type_init(puv3_dma_register_type)
 115