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63#include "qemu/osdep.h"
64#include "hw/hw.h"
65#include "hw/pci/msi.h"
66#include "hw/i386/pc.h"
67#include "hw/pci/pci.h"
68#include "hw/isa/isa.h"
69#include "sysemu/block-backend.h"
70#include "sysemu/dma.h"
71#include "hw/ide/pci.h"
72#include "hw/ide/ahci_internal.h"
73
74#define ICH9_MSI_CAP_OFFSET 0x80
75#define ICH9_SATA_CAP_OFFSET 0xA8
76
77#define ICH9_IDP_BAR 4
78#define ICH9_MEM_BAR 5
79
80#define ICH9_IDP_INDEX 0x10
81#define ICH9_IDP_INDEX_LOG2 0x04
82
83static const VMStateDescription vmstate_ich9_ahci = {
84 .name = "ich9_ahci",
85 .version_id = 1,
86 .fields = (VMStateField[]) {
87 VMSTATE_PCI_DEVICE(parent_obj, AHCIPCIState),
88 VMSTATE_AHCI(ahci, AHCIPCIState),
89 VMSTATE_END_OF_LIST()
90 },
91};
92
93static void pci_ich9_reset(DeviceState *dev)
94{
95 AHCIPCIState *d = ICH_AHCI(dev);
96
97 ahci_reset(&d->ahci);
98}
99
100static void pci_ich9_ahci_init(Object *obj)
101{
102 struct AHCIPCIState *d = ICH_AHCI(obj);
103
104 ahci_init(&d->ahci, DEVICE(obj));
105}
106
107static void pci_ich9_ahci_realize(PCIDevice *dev, Error **errp)
108{
109 struct AHCIPCIState *d;
110 int sata_cap_offset;
111 uint8_t *sata_cap;
112 d = ICH_AHCI(dev);
113 int ret;
114
115 ahci_realize(&d->ahci, DEVICE(dev), pci_get_address_space(dev), 6);
116
117 pci_config_set_prog_interface(dev->config, AHCI_PROGMODE_MAJOR_REV_1);
118
119 dev->config[PCI_CACHE_LINE_SIZE] = 0x08;
120 dev->config[PCI_LATENCY_TIMER] = 0x00;
121 pci_config_set_interrupt_pin(dev->config, 1);
122
123
124 dev->config[0x90] = 1 << 6;
125
126 d->ahci.irq = pci_allocate_irq(dev);
127
128 pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
129 &d->ahci.idp);
130 pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY,
131 &d->ahci.mem);
132
133 sata_cap_offset = pci_add_capability(dev, PCI_CAP_ID_SATA,
134 ICH9_SATA_CAP_OFFSET, SATA_CAP_SIZE,
135 errp);
136 if (sata_cap_offset < 0) {
137 return;
138 }
139
140 sata_cap = dev->config + sata_cap_offset;
141 pci_set_word(sata_cap + SATA_CAP_REV, 0x10);
142 pci_set_long(sata_cap + SATA_CAP_BAR,
143 (ICH9_IDP_BAR + 0x4) | (ICH9_IDP_INDEX_LOG2 << 4));
144 d->ahci.idp_offset = ICH9_IDP_INDEX;
145
146
147
148
149 ret = msi_init(dev, ICH9_MSI_CAP_OFFSET, 1, true, false, NULL);
150
151
152 assert(!ret || ret == -ENOTSUP);
153}
154
155static void pci_ich9_uninit(PCIDevice *dev)
156{
157 struct AHCIPCIState *d;
158 d = ICH_AHCI(dev);
159
160 msi_uninit(dev);
161 ahci_uninit(&d->ahci);
162 qemu_free_irq(d->ahci.irq);
163}
164
165static void ich_ahci_class_init(ObjectClass *klass, void *data)
166{
167 DeviceClass *dc = DEVICE_CLASS(klass);
168 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
169
170 k->realize = pci_ich9_ahci_realize;
171 k->exit = pci_ich9_uninit;
172 k->vendor_id = PCI_VENDOR_ID_INTEL;
173 k->device_id = PCI_DEVICE_ID_INTEL_82801IR;
174 k->revision = 0x02;
175 k->class_id = PCI_CLASS_STORAGE_SATA;
176 dc->vmsd = &vmstate_ich9_ahci;
177 dc->reset = pci_ich9_reset;
178 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
179}
180
181static const TypeInfo ich_ahci_info = {
182 .name = TYPE_ICH9_AHCI,
183 .parent = TYPE_PCI_DEVICE,
184 .instance_size = sizeof(AHCIPCIState),
185 .instance_init = pci_ich9_ahci_init,
186 .class_init = ich_ahci_class_init,
187 .interfaces = (InterfaceInfo[]) {
188 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
189 { },
190 },
191};
192
193static void ich_ahci_register_types(void)
194{
195 type_register_static(&ich_ahci_info);
196}
197
198type_init(ich_ahci_register_types)
199
