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17#include "qemu/osdep.h"
18#include "hw/hw.h"
19#include "qemu/timer.h"
20#include "hw/sysbus.h"
21#include "hw/fdt_generic_devices.h"
22#include "sysemu/sysemu.h"
23#include "qom/cpu.h"
24#include "qapi/error.h"
25#include "qemu/log.h"
26
27#ifdef CONFIG_FDT
28#include "qemu/config-file.h"
29#endif
30
31#ifndef ZYNQ_SLCR_ERR_DEBUG
32#define ZYNQ_SLCR_ERR_DEBUG 0
33#endif
34
35#define DB_PRINT(...) do { \
36 if (ZYNQ_SLCR_ERR_DEBUG) { \
37 fprintf(stderr, ": %s: ", __func__); \
38 fprintf(stderr, ## __VA_ARGS__); \
39 } \
40 } while (0);
41
42#define XILINX_LOCK_KEY 0x767b
43#define XILINX_UNLOCK_KEY 0xdf0d
44
45#define R_PSS_RST_CTRL_SOFT_RST 0x1
46
47enum {
48 SCL = 0x000 / 4,
49 LOCK,
50 UNLOCK,
51 LOCKSTA,
52
53 ARM_PLL_CTRL = 0x100 / 4,
54 DDR_PLL_CTRL,
55 IO_PLL_CTRL,
56 PLL_STATUS,
57 ARM_PLL_CFG,
58 DDR_PLL_CFG,
59 IO_PLL_CFG,
60
61 ARM_CLK_CTRL = 0x120 / 4,
62 DDR_CLK_CTRL,
63 DCI_CLK_CTRL,
64 APER_CLK_CTRL,
65 USB0_CLK_CTRL,
66 USB1_CLK_CTRL,
67 GEM0_RCLK_CTRL,
68 GEM1_RCLK_CTRL,
69 GEM0_CLK_CTRL,
70 GEM1_CLK_CTRL,
71 SMC_CLK_CTRL,
72 LQSPI_CLK_CTRL,
73 SDIO_CLK_CTRL,
74 UART_CLK_CTRL,
75 SPI_CLK_CTRL,
76 CAN_CLK_CTRL,
77 CAN_MIOCLK_CTRL,
78 DBG_CLK_CTRL,
79 PCAP_CLK_CTRL,
80 TOPSW_CLK_CTRL,
81
82#define FPGA_CTRL_REGS(n, start) \
83 FPGA ## n ## _CLK_CTRL = (start) / 4, \
84 FPGA ## n ## _THR_CTRL, \
85 FPGA ## n ## _THR_CNT, \
86 FPGA ## n ## _THR_STA,
87 FPGA_CTRL_REGS(0, 0x170)
88 FPGA_CTRL_REGS(1, 0x180)
89 FPGA_CTRL_REGS(2, 0x190)
90 FPGA_CTRL_REGS(3, 0x1a0)
91
92 BANDGAP_TRIP = 0x1b8 / 4,
93 PLL_PREDIVISOR = 0x1c0 / 4,
94 CLK_621_TRUE,
95
96 PSS_RST_CTRL = 0x200 / 4,
97 DDR_RST_CTRL,
98 TOPSW_RESET_CTRL,
99 DMAC_RST_CTRL,
100 USB_RST_CTRL,
101 GEM_RST_CTRL,
102 SDIO_RST_CTRL,
103 SPI_RST_CTRL,
104 CAN_RST_CTRL,
105 I2C_RST_CTRL,
106 UART_RST_CTRL,
107 GPIO_RST_CTRL,
108 LQSPI_RST_CTRL,
109 SMC_RST_CTRL,
110 OCM_RST_CTRL,
111 FPGA_RST_CTRL = 0x240 / 4,
112 A9_CPU_RST_CTRL,
113
114 RS_AWDT_CTRL = 0x24c / 4,
115 RST_REASON,
116
117 REBOOT_STATUS = 0x258 / 4,
118 BOOT_MODE,
119
120 APU_CTRL = 0x300 / 4,
121 WDT_CLK_SEL,
122
123 TZ_DMA_NS = 0x440 / 4,
124 TZ_DMA_IRQ_NS,
125 TZ_DMA_PERIPH_NS,
126
127 PSS_IDCODE = 0x530 / 4,
128
129 DDR_URGENT = 0x600 / 4,
130 DDR_CAL_START = 0x60c / 4,
131 DDR_REF_START = 0x614 / 4,
132 DDR_CMD_STA,
133 DDR_URGENT_SEL,
134 DDR_DFI_STATUS,
135
136 MIO = 0x700 / 4,
137#define MIO_LENGTH 54
138
139 MIO_LOOPBACK = 0x804 / 4,
140 MIO_MST_TRI0,
141 MIO_MST_TRI1,
142
143 SD0_WP_CD_SEL = 0x830 / 4,
144 SD1_WP_CD_SEL,
145
146 LVL_SHFTR_EN = 0x900 / 4,
147 OCM_CFG = 0x910 / 4,
148
149 CPU_RAM = 0xa00 / 4,
150
151 IOU = 0xa30 / 4,
152
153 DMAC_RAM = 0xa50 / 4,
154
155 AFI0 = 0xa60 / 4,
156 AFI1 = AFI0 + 3,
157 AFI2 = AFI1 + 3,
158 AFI3 = AFI2 + 3,
159#define AFI_LENGTH 3
160
161 OCM = 0xa90 / 4,
162
163 DEVCI_RAM = 0xaa0 / 4,
164
165 CSG_RAM = 0xab0 / 4,
166
167 GPIOB_CTRL = 0xb00 / 4,
168 GPIOB_CFG_CMOS18,
169 GPIOB_CFG_CMOS25,
170 GPIOB_CFG_CMOS33,
171 GPIOB_CFG_HSTL = 0xb14 / 4,
172 GPIOB_DRVR_BIAS_CTRL,
173
174 DDRIOB = 0xb40 / 4,
175#define DDRIOB_LENGTH 14
176};
177
178#define ZYNQ_SLCR_MMIO_SIZE 0x1000
179#define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4)
180
181#define ZYNQ_SLCR_NUM_CPUS 2
182
183#define FPGA_RST_VALID_BITS 0x01f33F0F
184
185
186
187#define FPGA_RST_INVERT_BITS 0x0000000F
188#define A9_CPU_RST_CTRL_RST_SHIFT 0
189
190#define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
191#define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)
192
193typedef struct ZynqSLCRState {
194 SysBusDevice parent_obj;
195
196 MemoryRegion iomem;
197 qemu_irq cpu_resets[ZYNQ_SLCR_NUM_CPUS];
198
199
200 qemu_irq fpga_resets[17];
201
202 uint32_t regs[ZYNQ_SLCR_NUM_REGS];
203} ZynqSLCRState;
204
205
206static void zynq_slcr_set_qspi(ZynqSLCRState *s, void *fdt)
207{
208 int i;
209 Error *errp = NULL;
210 char node_path[DT_PATH_LENGTH];
211
212 memset(node_path, 0, sizeof(node_path));
213
214
215 if (qemu_devtree_node_by_compatible(fdt, node_path,
216 "xlnx,zynq-qspi-1.0")) {
217 DB_PRINT("DT, PS7 QSPI node not found\n");
218 return ;
219 }
220
221
222
223
224
225 if (qemu_devtree_get_num_children(fdt, node_path, 1)) {
226 DB_PRINT("DT, PS7 QSPI: child node found\n");
227
228 for (i = 1; i <= 6; i++) {
229 s->regs[MIO+i] = 0x00000202;
230 }
231
232
233 if (qemu_fdt_getprop_cell(fdt, node_path, "is-dual", 0,
234 false, &errp) == 1) {
235 DB_PRINT("DT, PS QSPI is in dual\n");
236
237 s->regs[MIO+0] = 0x00000202;
238
239
240 for (i = 9; i <= 13; i++) {
241 s->regs[MIO+i] = 0x00000202;
242 }
243 }
244 }
245}
246
247static void zynq_slcr_fdt_config(ZynqSLCRState *s)
248{
249#ifdef CONFIG_FDT
250 QemuOpts *machine_opts;
251 const char *dtb_filename;
252 int fdt_size;
253 void *fdt = NULL;
254
255
256 machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
257 if (machine_opts) {
258 dtb_filename = qemu_opt_get(machine_opts, "dtb");
259 } else {
260 dtb_filename = NULL;
261 }
262
263 if (dtb_filename) {
264 fdt = load_device_tree(dtb_filename, &fdt_size);
265 }
266
267 if (!fdt) {
268 return;
269 }
270
271 zynq_slcr_set_qspi(s, fdt);
272#endif
273
274 return;
275}
276
277static void zynq_slcr_update_fpga_resets(ZynqSLCRState *s)
278{
279 uint32_t val = s->regs[FPGA_RST_CTRL];
280
281 val ^= FPGA_RST_INVERT_BITS;
282 int out_idx = 0;
283 int i;
284
285
286 for (i = 0; i < 32; i++) {
287 bool rst = extract32(val, i, 1);
288 bool valid = extract32(FPGA_RST_VALID_BITS, i, 1);
289
290
291 if (!valid) {
292 continue;
293 }
294
295 assert(out_idx < ARRAY_SIZE(s->fpga_resets));
296 qemu_set_irq(s->fpga_resets[out_idx], rst);
297 out_idx++;
298 }
299}
300
301static void zynq_slcr_reset(DeviceState *d)
302{
303 ZynqSLCRState *s = ZYNQ_SLCR(d);
304 int i, boot_mode;
305 QemuOpts *opts = qemu_find_opts_singleton("boot-opts");
306
307 DB_PRINT("RESET\n");
308
309 boot_mode = qemu_opt_get_number(opts, "mode", 0);
310
311 s->regs[LOCKSTA] = 1;
312
313 s->regs[ARM_PLL_CTRL] = 0x0001A008;
314 s->regs[DDR_PLL_CTRL] = 0x0001A008;
315 s->regs[IO_PLL_CTRL] = 0x0001A008;
316 s->regs[PLL_STATUS] = 0x0000003F;
317 s->regs[ARM_PLL_CFG] = 0x00014000;
318 s->regs[DDR_PLL_CFG] = 0x00014000;
319 s->regs[IO_PLL_CFG] = 0x00014000;
320
321
322 s->regs[ARM_CLK_CTRL] = 0x1F000200;
323 s->regs[DDR_CLK_CTRL] = 0x18400003;
324 s->regs[DCI_CLK_CTRL] = 0x01E03201;
325 s->regs[APER_CLK_CTRL] = 0x01ed044d;
326 s->regs[USB0_CLK_CTRL] = s->regs[USB1_CLK_CTRL] = 0x00101941;
327 s->regs[GEM0_RCLK_CTRL] = s->regs[GEM1_RCLK_CTRL] = 0x00000001;
328 s->regs[GEM0_CLK_CTRL] = s->regs[GEM1_CLK_CTRL] = 0x00003C01;
329 s->regs[SMC_CLK_CTRL] = 0x00003C01;
330 s->regs[LQSPI_CLK_CTRL] = 0x00002821;
331 s->regs[SDIO_CLK_CTRL] = 0x00001E03;
332 s->regs[UART_CLK_CTRL] = 0x00003F03;
333 s->regs[SPI_CLK_CTRL] = 0x00003F03;
334 s->regs[CAN_CLK_CTRL] = 0x00501903;
335 s->regs[DBG_CLK_CTRL] = 0x00000F03;
336 s->regs[PCAP_CLK_CTRL] = 0x00000F01;
337
338
339 s->regs[FPGA0_CLK_CTRL] = s->regs[FPGA1_CLK_CTRL] = s->regs[FPGA2_CLK_CTRL]
340 = s->regs[FPGA3_CLK_CTRL] = 0x00101800;
341 s->regs[FPGA0_THR_STA] = s->regs[FPGA1_THR_STA] = s->regs[FPGA2_THR_STA]
342 = s->regs[FPGA3_THR_STA] = 0x00010000;
343
344
345 s->regs[BANDGAP_TRIP] = 0x0000001F;
346 s->regs[PLL_PREDIVISOR] = 0x00000001;
347 s->regs[CLK_621_TRUE] = 0x00000001;
348
349
350 s->regs[FPGA_RST_CTRL] = 0x01F33F0F;
351 s->regs[RST_REASON] = 0x00000040;
352
353 s->regs[BOOT_MODE] = boot_mode;
354
355
356 for (i = 0; i < 54; i++) {
357 s->regs[MIO + i] = 0x00001601;
358 }
359 for (i = 2; i <= 8; i++) {
360 s->regs[MIO + i] = 0x00000601;
361 }
362
363 s->regs[MIO_MST_TRI0] = s->regs[MIO_MST_TRI1] = 0xFFFFFFFF;
364
365 s->regs[CPU_RAM + 0] = s->regs[CPU_RAM + 1] = s->regs[CPU_RAM + 3]
366 = s->regs[CPU_RAM + 4] = s->regs[CPU_RAM + 7]
367 = 0x00010101;
368 s->regs[CPU_RAM + 2] = s->regs[CPU_RAM + 5] = 0x01010101;
369 s->regs[CPU_RAM + 6] = 0x00000001;
370
371 s->regs[IOU + 0] = s->regs[IOU + 1] = s->regs[IOU + 2] = s->regs[IOU + 3]
372 = 0x09090909;
373 s->regs[IOU + 4] = s->regs[IOU + 5] = 0x00090909;
374 s->regs[IOU + 6] = 0x00000909;
375
376 s->regs[DMAC_RAM] = 0x00000009;
377
378 s->regs[AFI0 + 0] = s->regs[AFI0 + 1] = 0x09090909;
379 s->regs[AFI1 + 0] = s->regs[AFI1 + 1] = 0x09090909;
380 s->regs[AFI2 + 0] = s->regs[AFI2 + 1] = 0x09090909;
381 s->regs[AFI3 + 0] = s->regs[AFI3 + 1] = 0x09090909;
382 s->regs[AFI0 + 2] = s->regs[AFI1 + 2] = s->regs[AFI2 + 2]
383 = s->regs[AFI3 + 2] = 0x00000909;
384
385 s->regs[OCM + 0] = 0x01010101;
386 s->regs[OCM + 1] = s->regs[OCM + 2] = 0x09090909;
387
388 s->regs[DEVCI_RAM] = 0x00000909;
389 s->regs[CSG_RAM] = 0x00000001;
390
391 s->regs[DDRIOB + 0] = s->regs[DDRIOB + 1] = s->regs[DDRIOB + 2]
392 = s->regs[DDRIOB + 3] = 0x00000e00;
393 s->regs[DDRIOB + 4] = s->regs[DDRIOB + 5] = s->regs[DDRIOB + 6]
394 = 0x00000e00;
395 s->regs[DDRIOB + 12] = 0x00000021;
396
397 zynq_slcr_fdt_config(s);
398 zynq_slcr_update_fpga_resets(s);
399}
400
401
402static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
403{
404 switch (offset) {
405 case LOCK:
406 case UNLOCK:
407 case DDR_CAL_START:
408 case DDR_REF_START:
409 return !rnw;
410 case LOCKSTA:
411 case FPGA0_THR_STA:
412 case FPGA1_THR_STA:
413 case FPGA2_THR_STA:
414 case FPGA3_THR_STA:
415 case BOOT_MODE:
416 case PSS_IDCODE:
417 case DDR_CMD_STA:
418 case DDR_DFI_STATUS:
419 case PLL_STATUS:
420 return rnw;
421 case SCL:
422 case ARM_PLL_CTRL ... IO_PLL_CTRL:
423 case ARM_PLL_CFG ... IO_PLL_CFG:
424 case ARM_CLK_CTRL ... TOPSW_CLK_CTRL:
425 case FPGA0_CLK_CTRL ... FPGA0_THR_CNT:
426 case FPGA1_CLK_CTRL ... FPGA1_THR_CNT:
427 case FPGA2_CLK_CTRL ... FPGA2_THR_CNT:
428 case FPGA3_CLK_CTRL ... FPGA3_THR_CNT:
429 case BANDGAP_TRIP:
430 case PLL_PREDIVISOR:
431 case CLK_621_TRUE:
432 case PSS_RST_CTRL ... A9_CPU_RST_CTRL:
433 case RS_AWDT_CTRL:
434 case RST_REASON:
435 case REBOOT_STATUS:
436 case APU_CTRL:
437 case WDT_CLK_SEL:
438 case TZ_DMA_NS ... TZ_DMA_PERIPH_NS:
439 case DDR_URGENT:
440 case DDR_URGENT_SEL:
441 case MIO ... MIO + MIO_LENGTH - 1:
442 case MIO_LOOPBACK ... MIO_MST_TRI1:
443 case SD0_WP_CD_SEL:
444 case SD1_WP_CD_SEL:
445 case LVL_SHFTR_EN:
446 case OCM_CFG:
447 case CPU_RAM:
448 case IOU:
449 case DMAC_RAM:
450 case AFI0 ... AFI3 + AFI_LENGTH - 1:
451 case OCM:
452 case DEVCI_RAM:
453 case CSG_RAM:
454 case GPIOB_CTRL ... GPIOB_CFG_CMOS33:
455 case GPIOB_CFG_HSTL:
456 case GPIOB_DRVR_BIAS_CTRL:
457 case DDRIOB ... DDRIOB + DDRIOB_LENGTH - 1:
458 return true;
459 default:
460 return false;
461 }
462}
463
464static uint64_t zynq_slcr_read(void *opaque, hwaddr offset,
465 unsigned size)
466{
467 ZynqSLCRState *s = opaque;
468 offset /= 4;
469 uint32_t ret = s->regs[offset];
470
471 if (!zynq_slcr_check_offset(offset, true)) {
472 qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to "
473 " addr %" HWADDR_PRIx "\n", offset * 4);
474 }
475
476 DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset * 4, ret);
477 return ret;
478}
479
480static void zynq_slcr_write(void *opaque, hwaddr offset,
481 uint64_t val, unsigned size)
482{
483 ZynqSLCRState *s = (ZynqSLCRState *)opaque;
484 offset /= 4;
485 int i;
486
487 DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val);
488
489 if (!zynq_slcr_check_offset(offset, false)) {
490 qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid write access to "
491 "addr %" HWADDR_PRIx "\n", offset * 4);
492 return;
493 }
494
495 switch (offset) {
496 case SCL:
497 s->regs[SCL] = val & 0x1;
498 return;
499 case LOCK:
500 if ((val & 0xFFFF) == XILINX_LOCK_KEY) {
501 DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
502 (unsigned)val & 0xFFFF);
503 s->regs[LOCKSTA] = 1;
504 } else {
505 DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
506 (int)offset, (unsigned)val & 0xFFFF);
507 }
508 return;
509 case UNLOCK:
510 if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {
511 DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
512 (unsigned)val & 0xFFFF);
513 s->regs[LOCKSTA] = 0;
514 } else {
515 DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
516 (int)offset, (unsigned)val & 0xFFFF);
517 }
518 return;
519 }
520
521 if (s->regs[LOCKSTA]) {
522 qemu_log_mask(LOG_GUEST_ERROR,
523 "SCLR registers are locked. Unlock them first\n");
524 return;
525 }
526 s->regs[offset] = val;
527
528 switch (offset) {
529 case PSS_RST_CTRL:
530 if (val & R_PSS_RST_CTRL_SOFT_RST) {
531 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
532 }
533 break;
534 case A9_CPU_RST_CTRL:
535 for (i = 0; i < ZYNQ_SLCR_NUM_CPUS; ++i) {
536 bool rst = extract32(val, A9_CPU_RST_CTRL_RST_SHIFT + i, 1);
537
538 qemu_set_irq(s->cpu_resets[i], rst);
539 DB_PRINT("%sresetting cpu %d\n", rst ? "" : "un-", i);
540 }
541 break;
542 case FPGA_RST_CTRL:
543
544 s->regs[offset] &= FPGA_RST_VALID_BITS;
545 zynq_slcr_update_fpga_resets(s);
546 break;
547 }
548}
549
550static const MemoryRegionOps slcr_ops = {
551 .read = zynq_slcr_read,
552 .write = zynq_slcr_write,
553 .endianness = DEVICE_NATIVE_ENDIAN,
554};
555
556static void zynq_slcr_realize(DeviceState *dev, Error **errp)
557{
558 int i;
559 CPUState *env = first_cpu;
560
561
562 for (i = 0; i < fdt_generic_num_cpus && i < ZYNQ_SLCR_NUM_CPUS; ++i) {
563 Object *cpu_obj = OBJECT(env);
564 if (!cpu_obj->parent) {
565 char *cpu_child_name = g_strdup_printf("cpu-%d\n", i);
566 object_property_add_child(qdev_get_machine(), cpu_child_name,
567 cpu_obj, &error_abort);
568 }
569 qdev_connect_gpio_out(dev, i,
570 qdev_get_gpio_in_named(DEVICE(env), "reset", 0));
571 env = CPU_NEXT(env);
572 }
573}
574
575static void zynq_slcr_init(Object *obj)
576{
577 ZynqSLCRState *s = ZYNQ_SLCR(obj);
578
579 memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr",
580 ZYNQ_SLCR_MMIO_SIZE);
581 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
582
583 qdev_init_gpio_out(DEVICE(obj), s->cpu_resets, ZYNQ_SLCR_NUM_CPUS);
584 qdev_init_gpio_out(DEVICE(obj), s->fpga_resets, ARRAY_SIZE(s->fpga_resets));
585}
586
587static const VMStateDescription vmstate_zynq_slcr = {
588 .name = "zynq_slcr",
589 .version_id = 2,
590 .minimum_version_id = 2,
591 .fields = (VMStateField[]) {
592 VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS),
593 VMSTATE_END_OF_LIST()
594 }
595};
596
597static void zynq_slcr_class_init(ObjectClass *klass, void *data)
598{
599 DeviceClass *dc = DEVICE_CLASS(klass);
600
601 dc->vmsd = &vmstate_zynq_slcr;
602 dc->reset = zynq_slcr_reset;
603 dc->realize = zynq_slcr_realize;
604}
605
606static const TypeInfo zynq_slcr_info = {
607 .class_init = zynq_slcr_class_init,
608 .name = TYPE_ZYNQ_SLCR,
609 .parent = TYPE_SYS_BUS_DEVICE,
610 .instance_size = sizeof(ZynqSLCRState),
611 .instance_init = zynq_slcr_init,
612};
613
614static void zynq_slcr_register_types(void)
615{
616 type_register_static(&zynq_slcr_info);
617}
618
619type_init(zynq_slcr_register_types)
620
