qemu/hw/intc/openpic_kvm.c
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   1/*
   2 * KVM in-kernel OpenPIC
   3 *
   4 * Copyright 2013 Freescale Semiconductor, Inc.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "qapi/error.h"
  27#include "qemu-common.h"
  28#include "cpu.h"
  29#include <sys/ioctl.h>
  30#include "exec/address-spaces.h"
  31#include "hw/hw.h"
  32#include "hw/ppc/openpic.h"
  33#include "hw/pci/msi.h"
  34#include "hw/sysbus.h"
  35#include "sysemu/kvm.h"
  36#include "qemu/log.h"
  37
  38#define GCR_RESET        0x80000000
  39
  40#define KVM_OPENPIC(obj) \
  41    OBJECT_CHECK(KVMOpenPICState, (obj), TYPE_KVM_OPENPIC)
  42
  43typedef struct KVMOpenPICState {
  44    /*< private >*/
  45    SysBusDevice parent_obj;
  46    /*< public >*/
  47
  48    MemoryRegion mem;
  49    MemoryListener mem_listener;
  50    uint32_t fd;
  51    uint32_t model;
  52    hwaddr mapped;
  53} KVMOpenPICState;
  54
  55static void kvm_openpic_set_irq(void *opaque, int n_IRQ, int level)
  56{
  57    kvm_set_irq(kvm_state, n_IRQ, level);
  58}
  59
  60static void kvm_openpic_write(void *opaque, hwaddr addr, uint64_t val,
  61                              unsigned size)
  62{
  63    KVMOpenPICState *opp = opaque;
  64    struct kvm_device_attr attr;
  65    uint32_t val32 = val;
  66    int ret;
  67
  68    attr.group = KVM_DEV_MPIC_GRP_REGISTER;
  69    attr.attr = addr;
  70    attr.addr = (uint64_t)(unsigned long)&val32;
  71
  72    ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
  73    if (ret < 0) {
  74        qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
  75                      strerror(errno), attr.attr);
  76    }
  77}
  78
  79static void kvm_openpic_reset(DeviceState *d)
  80{
  81    KVMOpenPICState *opp = KVM_OPENPIC(d);
  82
  83    /* Trigger the GCR.RESET bit to reset the PIC */
  84    kvm_openpic_write(opp, 0x1020, GCR_RESET, sizeof(uint32_t));
  85}
  86
  87static uint64_t kvm_openpic_read(void *opaque, hwaddr addr, unsigned size)
  88{
  89    KVMOpenPICState *opp = opaque;
  90    struct kvm_device_attr attr;
  91    uint32_t val = 0xdeadbeef;
  92    int ret;
  93
  94    attr.group = KVM_DEV_MPIC_GRP_REGISTER;
  95    attr.attr = addr;
  96    attr.addr = (uint64_t)(unsigned long)&val;
  97
  98    ret = ioctl(opp->fd, KVM_GET_DEVICE_ATTR, &attr);
  99    if (ret < 0) {
 100        qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
 101                      strerror(errno), attr.attr);
 102        return 0;
 103    }
 104
 105    return val;
 106}
 107
 108static const MemoryRegionOps kvm_openpic_mem_ops = {
 109    .write = kvm_openpic_write,
 110    .read  = kvm_openpic_read,
 111    .endianness = DEVICE_BIG_ENDIAN,
 112    .impl = {
 113        .min_access_size = 4,
 114        .max_access_size = 4,
 115    },
 116};
 117
 118static void kvm_openpic_region_add(MemoryListener *listener,
 119                                   MemoryRegionSection *section)
 120{
 121    KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
 122                                        mem_listener);
 123    struct kvm_device_attr attr;
 124    uint64_t reg_base;
 125    int ret;
 126
 127    if (section->fv != address_space_to_flatview(&address_space_memory)) {
 128        abort();
 129    }
 130
 131    /* Ignore events on regions that are not us */
 132    if (section->mr != &opp->mem) {
 133        return;
 134    }
 135
 136    if (opp->mapped) {
 137        /*
 138         * We can only map the MPIC once. Since we are already mapped,
 139         * the best we can do is ignore new maps.
 140         */
 141        return;
 142    }
 143
 144    reg_base = section->offset_within_address_space;
 145    opp->mapped = reg_base;
 146
 147    attr.group = KVM_DEV_MPIC_GRP_MISC;
 148    attr.attr = KVM_DEV_MPIC_BASE_ADDR;
 149    attr.addr = (uint64_t)(unsigned long)&reg_base;
 150
 151    ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
 152    if (ret < 0) {
 153        fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
 154                strerror(errno), reg_base);
 155    }
 156}
 157
 158static void kvm_openpic_region_del(MemoryListener *listener,
 159                                   MemoryRegionSection *section)
 160{
 161    KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
 162                                        mem_listener);
 163    struct kvm_device_attr attr;
 164    uint64_t reg_base = 0;
 165    int ret;
 166
 167    /* Ignore events on regions that are not us */
 168    if (section->mr != &opp->mem) {
 169        return;
 170    }
 171
 172    if (section->offset_within_address_space != opp->mapped) {
 173        /*
 174         * We can only map the MPIC once. This mapping was a secondary
 175         * one that we couldn't fulfill. Ignore it.
 176         */
 177        return;
 178    }
 179    opp->mapped = 0;
 180
 181    attr.group = KVM_DEV_MPIC_GRP_MISC;
 182    attr.attr = KVM_DEV_MPIC_BASE_ADDR;
 183    attr.addr = (uint64_t)(unsigned long)&reg_base;
 184
 185    ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
 186    if (ret < 0) {
 187        fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
 188                strerror(errno), reg_base);
 189    }
 190}
 191
 192static void kvm_openpic_init(Object *obj)
 193{
 194    KVMOpenPICState *opp = KVM_OPENPIC(obj);
 195
 196    memory_region_init_io(&opp->mem, OBJECT(opp), &kvm_openpic_mem_ops, opp,
 197                          "kvm-openpic", 0x40000);
 198}
 199
 200static void kvm_openpic_realize(DeviceState *dev, Error **errp)
 201{
 202    SysBusDevice *d = SYS_BUS_DEVICE(dev);
 203    KVMOpenPICState *opp = KVM_OPENPIC(dev);
 204    KVMState *s = kvm_state;
 205    int kvm_openpic_model;
 206    struct kvm_create_device cd = {0};
 207    int ret, i;
 208
 209    if (!kvm_check_extension(s, KVM_CAP_DEVICE_CTRL)) {
 210        error_setg(errp, "Kernel is lacking Device Control API");
 211        return;
 212    }
 213
 214    switch (opp->model) {
 215    case OPENPIC_MODEL_FSL_MPIC_20:
 216        kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_20;
 217        break;
 218
 219    case OPENPIC_MODEL_FSL_MPIC_42:
 220        kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_42;
 221        break;
 222
 223    default:
 224        error_setg(errp, "Unsupported OpenPIC model %" PRIu32, opp->model);
 225        return;
 226    }
 227
 228    cd.type = kvm_openpic_model;
 229    ret = kvm_vm_ioctl(s, KVM_CREATE_DEVICE, &cd);
 230    if (ret < 0) {
 231        error_setg(errp, "Can't create device %d: %s",
 232                   cd.type, strerror(errno));
 233        return;
 234    }
 235    opp->fd = cd.fd;
 236
 237    sysbus_init_mmio(d, &opp->mem);
 238    qdev_init_gpio_in(dev, kvm_openpic_set_irq, OPENPIC_MAX_IRQ);
 239
 240    opp->mem_listener.region_add = kvm_openpic_region_add;
 241    opp->mem_listener.region_del = kvm_openpic_region_del;
 242    memory_listener_register(&opp->mem_listener, &address_space_memory);
 243
 244    /* indicate pic capabilities */
 245    msi_nonbroken = true;
 246    kvm_kernel_irqchip = true;
 247    kvm_async_interrupts_allowed = true;
 248
 249    /* set up irq routing */
 250    kvm_init_irq_routing(kvm_state);
 251    for (i = 0; i < 256; ++i) {
 252        kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
 253    }
 254
 255    kvm_msi_via_irqfd_allowed = true;
 256    kvm_gsi_routing_allowed = true;
 257
 258    kvm_irqchip_commit_routes(s);
 259}
 260
 261int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs)
 262{
 263    KVMOpenPICState *opp = KVM_OPENPIC(d);
 264
 265    return kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_MPIC, 0, opp->fd,
 266                               kvm_arch_vcpu_id(cs));
 267}
 268
 269static Property kvm_openpic_properties[] = {
 270    DEFINE_PROP_UINT32("model", KVMOpenPICState, model,
 271                       OPENPIC_MODEL_FSL_MPIC_20),
 272    DEFINE_PROP_END_OF_LIST(),
 273};
 274
 275static void kvm_openpic_class_init(ObjectClass *oc, void *data)
 276{
 277    DeviceClass *dc = DEVICE_CLASS(oc);
 278
 279    dc->realize = kvm_openpic_realize;
 280    dc->props = kvm_openpic_properties;
 281    dc->reset = kvm_openpic_reset;
 282    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
 283}
 284
 285static const TypeInfo kvm_openpic_info = {
 286    .name          = TYPE_KVM_OPENPIC,
 287    .parent        = TYPE_SYS_BUS_DEVICE,
 288    .instance_size = sizeof(KVMOpenPICState),
 289    .instance_init = kvm_openpic_init,
 290    .class_init    = kvm_openpic_class_init,
 291};
 292
 293static void kvm_openpic_register_types(void)
 294{
 295    type_register_static(&kvm_openpic_info);
 296}
 297
 298type_init(kvm_openpic_register_types)
 299