qemu/hw/scsi/vmw_pvscsi.c
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   1/*
   2 * QEMU VMWARE PVSCSI paravirtual SCSI bus
   3 *
   4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
   5 *
   6 * Developed by Daynix Computing LTD (http://www.daynix.com)
   7 *
   8 * Based on implementation by Paolo Bonzini
   9 * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html
  10 *
  11 * Authors:
  12 * Paolo Bonzini <pbonzini@redhat.com>
  13 * Dmitry Fleytman <dmitry@daynix.com>
  14 * Yan Vugenfirer <yan@daynix.com>
  15 *
  16 * This work is licensed under the terms of the GNU GPL, version 2.
  17 * See the COPYING file in the top-level directory.
  18 *
  19 * NOTE about MSI-X:
  20 * MSI-X support has been removed for the moment because it leads Windows OS
  21 * to crash on startup. The crash happens because Windows driver requires
  22 * MSI-X shared memory to be part of the same BAR used for rings state
  23 * registers, etc. This is not supported by QEMU infrastructure so separate
  24 * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs.
  25 *
  26 */
  27
  28#include "qemu/osdep.h"
  29#include "qapi/error.h"
  30#include "hw/scsi/scsi.h"
  31#include "scsi/constants.h"
  32#include "hw/pci/msi.h"
  33#include "vmw_pvscsi.h"
  34#include "trace.h"
  35
  36
  37#define PVSCSI_USE_64BIT         (true)
  38#define PVSCSI_PER_VECTOR_MASK   (false)
  39
  40#define PVSCSI_MAX_DEVS                   (64)
  41#define PVSCSI_MSIX_NUM_VECTORS           (1)
  42
  43#define PVSCSI_MAX_SG_ELEM                2048
  44
  45#define PVSCSI_MAX_CMD_DATA_WORDS \
  46    (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t))
  47
  48#define RS_GET_FIELD(m, field) \
  49    (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
  50                 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field)))
  51#define RS_SET_FIELD(m, field, val) \
  52    (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
  53                 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), val))
  54
  55typedef struct PVSCSIClass {
  56    PCIDeviceClass parent_class;
  57    DeviceRealize parent_dc_realize;
  58} PVSCSIClass;
  59
  60#define TYPE_PVSCSI "pvscsi"
  61#define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI)
  62
  63#define PVSCSI_DEVICE_CLASS(klass) \
  64    OBJECT_CLASS_CHECK(PVSCSIClass, (klass), TYPE_PVSCSI)
  65#define PVSCSI_DEVICE_GET_CLASS(obj) \
  66    OBJECT_GET_CLASS(PVSCSIClass, (obj), TYPE_PVSCSI)
  67
  68/* Compatibility flags for migration */
  69#define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT 0
  70#define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION \
  71    (1 << PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT)
  72#define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1
  73#define PVSCSI_COMPAT_DISABLE_PCIE \
  74    (1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT)
  75
  76#define PVSCSI_USE_OLD_PCI_CONFIGURATION(s) \
  77    ((s)->compat_flags & PVSCSI_COMPAT_OLD_PCI_CONFIGURATION)
  78#define PVSCSI_MSI_OFFSET(s) \
  79    (PVSCSI_USE_OLD_PCI_CONFIGURATION(s) ? 0x50 : 0x7c)
  80#define PVSCSI_EXP_EP_OFFSET (0x40)
  81
  82typedef struct PVSCSIRingInfo {
  83    uint64_t            rs_pa;
  84    uint32_t            txr_len_mask;
  85    uint32_t            rxr_len_mask;
  86    uint32_t            msg_len_mask;
  87    uint64_t            req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
  88    uint64_t            cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
  89    uint64_t            msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES];
  90    uint64_t            consumed_ptr;
  91    uint64_t            filled_cmp_ptr;
  92    uint64_t            filled_msg_ptr;
  93} PVSCSIRingInfo;
  94
  95typedef struct PVSCSISGState {
  96    hwaddr elemAddr;
  97    hwaddr dataAddr;
  98    uint32_t resid;
  99} PVSCSISGState;
 100
 101typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList;
 102
 103typedef struct {
 104    PCIDevice parent_obj;
 105    MemoryRegion io_space;
 106    SCSIBus bus;
 107    QEMUBH *completion_worker;
 108    PVSCSIRequestList pending_queue;
 109    PVSCSIRequestList completion_queue;
 110
 111    uint64_t reg_interrupt_status;        /* Interrupt status register value */
 112    uint64_t reg_interrupt_enabled;       /* Interrupt mask register value   */
 113    uint64_t reg_command_status;          /* Command status register value   */
 114
 115    /* Command data adoption mechanism */
 116    uint64_t curr_cmd;                   /* Last command arrived             */
 117    uint32_t curr_cmd_data_cntr;         /* Amount of data for last command  */
 118
 119    /* Collector for current command data */
 120    uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS];
 121
 122    uint8_t rings_info_valid;            /* Whether data rings initialized   */
 123    uint8_t msg_ring_info_valid;         /* Whether message ring initialized */
 124    uint8_t use_msg;                     /* Whether to use message ring      */
 125
 126    uint8_t msi_used;                    /* For migration compatibility      */
 127    PVSCSIRingInfo rings;                /* Data transfer rings manager      */
 128    uint32_t resetting;                  /* Reset in progress                */
 129
 130    uint32_t compat_flags;
 131} PVSCSIState;
 132
 133typedef struct PVSCSIRequest {
 134    SCSIRequest *sreq;
 135    PVSCSIState *dev;
 136    uint8_t sense_key;
 137    uint8_t completed;
 138    int lun;
 139    QEMUSGList sgl;
 140    PVSCSISGState sg;
 141    struct PVSCSIRingReqDesc req;
 142    struct PVSCSIRingCmpDesc cmp;
 143    QTAILQ_ENTRY(PVSCSIRequest) next;
 144} PVSCSIRequest;
 145
 146/* Integer binary logarithm */
 147static int
 148pvscsi_log2(uint32_t input)
 149{
 150    int log = 0;
 151    assert(input > 0);
 152    while (input >> ++log) {
 153    }
 154    return log;
 155}
 156
 157static void
 158pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri)
 159{
 160    int i;
 161    uint32_t txr_len_log2, rxr_len_log2;
 162    uint32_t req_ring_size, cmp_ring_size;
 163    m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT;
 164
 165    req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
 166    cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
 167    txr_len_log2 = pvscsi_log2(req_ring_size - 1);
 168    rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1);
 169
 170    m->txr_len_mask = MASK(txr_len_log2);
 171    m->rxr_len_mask = MASK(rxr_len_log2);
 172
 173    m->consumed_ptr = 0;
 174    m->filled_cmp_ptr = 0;
 175
 176    for (i = 0; i < ri->reqRingNumPages; i++) {
 177        m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT;
 178    }
 179
 180    for (i = 0; i < ri->cmpRingNumPages; i++) {
 181        m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT;
 182    }
 183
 184    RS_SET_FIELD(m, reqProdIdx, 0);
 185    RS_SET_FIELD(m, reqConsIdx, 0);
 186    RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2);
 187
 188    RS_SET_FIELD(m, cmpProdIdx, 0);
 189    RS_SET_FIELD(m, cmpConsIdx, 0);
 190    RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2);
 191
 192    trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2);
 193
 194    /* Flush ring state page changes */
 195    smp_wmb();
 196}
 197
 198static int
 199pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri)
 200{
 201    int i;
 202    uint32_t len_log2;
 203    uint32_t ring_size;
 204
 205    if (!ri->numPages || ri->numPages > PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES) {
 206        return -1;
 207    }
 208    ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
 209    len_log2 = pvscsi_log2(ring_size - 1);
 210
 211    m->msg_len_mask = MASK(len_log2);
 212
 213    m->filled_msg_ptr = 0;
 214
 215    for (i = 0; i < ri->numPages; i++) {
 216        m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT;
 217    }
 218
 219    RS_SET_FIELD(m, msgProdIdx, 0);
 220    RS_SET_FIELD(m, msgConsIdx, 0);
 221    RS_SET_FIELD(m, msgNumEntriesLog2, len_log2);
 222
 223    trace_pvscsi_ring_init_msg(len_log2);
 224
 225    /* Flush ring state page changes */
 226    smp_wmb();
 227
 228    return 0;
 229}
 230
 231static void
 232pvscsi_ring_cleanup(PVSCSIRingInfo *mgr)
 233{
 234    mgr->rs_pa = 0;
 235    mgr->txr_len_mask = 0;
 236    mgr->rxr_len_mask = 0;
 237    mgr->msg_len_mask = 0;
 238    mgr->consumed_ptr = 0;
 239    mgr->filled_cmp_ptr = 0;
 240    mgr->filled_msg_ptr = 0;
 241    memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa));
 242    memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa));
 243    memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa));
 244}
 245
 246static hwaddr
 247pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr)
 248{
 249    uint32_t ready_ptr = RS_GET_FIELD(mgr, reqProdIdx);
 250    uint32_t ring_size = PVSCSI_MAX_NUM_PAGES_REQ_RING
 251                            * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
 252
 253    if (ready_ptr != mgr->consumed_ptr
 254        && ready_ptr - mgr->consumed_ptr < ring_size) {
 255        uint32_t next_ready_ptr =
 256            mgr->consumed_ptr++ & mgr->txr_len_mask;
 257        uint32_t next_ready_page =
 258            next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
 259        uint32_t inpage_idx =
 260            next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
 261
 262        return mgr->req_ring_pages_pa[next_ready_page] +
 263               inpage_idx * sizeof(PVSCSIRingReqDesc);
 264    } else {
 265        return 0;
 266    }
 267}
 268
 269static void
 270pvscsi_ring_flush_req(PVSCSIRingInfo *mgr)
 271{
 272    RS_SET_FIELD(mgr, reqConsIdx, mgr->consumed_ptr);
 273}
 274
 275static hwaddr
 276pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr)
 277{
 278    /*
 279     * According to Linux driver code it explicitly verifies that number
 280     * of requests being processed by device is less then the size of
 281     * completion queue, so device may omit completion queue overflow
 282     * conditions check. We assume that this is true for other (Windows)
 283     * drivers as well.
 284     */
 285
 286    uint32_t free_cmp_ptr =
 287        mgr->filled_cmp_ptr++ & mgr->rxr_len_mask;
 288    uint32_t free_cmp_page =
 289        free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
 290    uint32_t inpage_idx =
 291        free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
 292    return mgr->cmp_ring_pages_pa[free_cmp_page] +
 293           inpage_idx * sizeof(PVSCSIRingCmpDesc);
 294}
 295
 296static hwaddr
 297pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr)
 298{
 299    uint32_t free_msg_ptr =
 300        mgr->filled_msg_ptr++ & mgr->msg_len_mask;
 301    uint32_t free_msg_page =
 302        free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
 303    uint32_t inpage_idx =
 304        free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
 305    return mgr->msg_ring_pages_pa[free_msg_page] +
 306           inpage_idx * sizeof(PVSCSIRingMsgDesc);
 307}
 308
 309static void
 310pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr)
 311{
 312    /* Flush descriptor changes */
 313    smp_wmb();
 314
 315    trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr);
 316
 317    RS_SET_FIELD(mgr, cmpProdIdx, mgr->filled_cmp_ptr);
 318}
 319
 320static bool
 321pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr)
 322{
 323    uint32_t prodIdx = RS_GET_FIELD(mgr, msgProdIdx);
 324    uint32_t consIdx = RS_GET_FIELD(mgr, msgConsIdx);
 325
 326    return (prodIdx - consIdx) < (mgr->msg_len_mask + 1);
 327}
 328
 329static void
 330pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr)
 331{
 332    /* Flush descriptor changes */
 333    smp_wmb();
 334
 335    trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr);
 336
 337    RS_SET_FIELD(mgr, msgProdIdx, mgr->filled_msg_ptr);
 338}
 339
 340static void
 341pvscsi_reset_state(PVSCSIState *s)
 342{
 343    s->curr_cmd = PVSCSI_CMD_FIRST;
 344    s->curr_cmd_data_cntr = 0;
 345    s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 346    s->reg_interrupt_status = 0;
 347    pvscsi_ring_cleanup(&s->rings);
 348    s->rings_info_valid = FALSE;
 349    s->msg_ring_info_valid = FALSE;
 350    QTAILQ_INIT(&s->pending_queue);
 351    QTAILQ_INIT(&s->completion_queue);
 352}
 353
 354static void
 355pvscsi_update_irq_status(PVSCSIState *s)
 356{
 357    PCIDevice *d = PCI_DEVICE(s);
 358    bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status;
 359
 360    trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled,
 361                                  s->reg_interrupt_status);
 362
 363    if (msi_enabled(d)) {
 364        if (should_raise) {
 365            trace_pvscsi_update_irq_msi();
 366            msi_notify(d, PVSCSI_VECTOR_COMPLETION);
 367        }
 368        return;
 369    }
 370
 371    pci_set_irq(d, !!should_raise);
 372}
 373
 374static void
 375pvscsi_raise_completion_interrupt(PVSCSIState *s)
 376{
 377    s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0;
 378
 379    /* Memory barrier to flush interrupt status register changes*/
 380    smp_wmb();
 381
 382    pvscsi_update_irq_status(s);
 383}
 384
 385static void
 386pvscsi_raise_message_interrupt(PVSCSIState *s)
 387{
 388    s->reg_interrupt_status |= PVSCSI_INTR_MSG_0;
 389
 390    /* Memory barrier to flush interrupt status register changes*/
 391    smp_wmb();
 392
 393    pvscsi_update_irq_status(s);
 394}
 395
 396static void
 397pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc)
 398{
 399    hwaddr cmp_descr_pa;
 400
 401    cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings);
 402    trace_pvscsi_cmp_ring_put(cmp_descr_pa);
 403    cpu_physical_memory_write(cmp_descr_pa, (void *)cmp_desc,
 404                              sizeof(*cmp_desc));
 405}
 406
 407static void
 408pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc)
 409{
 410    hwaddr msg_descr_pa;
 411
 412    msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings);
 413    trace_pvscsi_msg_ring_put(msg_descr_pa);
 414    cpu_physical_memory_write(msg_descr_pa, (void *)msg_desc,
 415                              sizeof(*msg_desc));
 416}
 417
 418static void
 419pvscsi_process_completion_queue(void *opaque)
 420{
 421    PVSCSIState *s = opaque;
 422    PVSCSIRequest *pvscsi_req;
 423    bool has_completed = false;
 424
 425    while (!QTAILQ_EMPTY(&s->completion_queue)) {
 426        pvscsi_req = QTAILQ_FIRST(&s->completion_queue);
 427        QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next);
 428        pvscsi_cmp_ring_put(s, &pvscsi_req->cmp);
 429        g_free(pvscsi_req);
 430        has_completed = true;
 431    }
 432
 433    if (has_completed) {
 434        pvscsi_ring_flush_cmp(&s->rings);
 435        pvscsi_raise_completion_interrupt(s);
 436    }
 437}
 438
 439static void
 440pvscsi_reset_adapter(PVSCSIState *s)
 441{
 442    s->resetting++;
 443    qbus_reset_all_fn(&s->bus);
 444    s->resetting--;
 445    pvscsi_process_completion_queue(s);
 446    assert(QTAILQ_EMPTY(&s->pending_queue));
 447    pvscsi_reset_state(s);
 448}
 449
 450static void
 451pvscsi_schedule_completion_processing(PVSCSIState *s)
 452{
 453    /* Try putting more complete requests on the ring. */
 454    if (!QTAILQ_EMPTY(&s->completion_queue)) {
 455        qemu_bh_schedule(s->completion_worker);
 456    }
 457}
 458
 459static void
 460pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r)
 461{
 462    assert(!r->completed);
 463
 464    trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen,
 465                                  r->sense_key);
 466    if (r->sreq != NULL) {
 467        scsi_req_unref(r->sreq);
 468        r->sreq = NULL;
 469    }
 470    r->completed = 1;
 471    QTAILQ_REMOVE(&s->pending_queue, r, next);
 472    QTAILQ_INSERT_TAIL(&s->completion_queue, r, next);
 473    pvscsi_schedule_completion_processing(s);
 474}
 475
 476static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r)
 477{
 478    PVSCSIRequest *req = r->hba_private;
 479
 480    trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size);
 481
 482    return &req->sgl;
 483}
 484
 485static void
 486pvscsi_get_next_sg_elem(PVSCSISGState *sg)
 487{
 488    struct PVSCSISGElement elem;
 489
 490    cpu_physical_memory_read(sg->elemAddr, (void *)&elem, sizeof(elem));
 491    if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) {
 492        /*
 493            * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in
 494            * header file but its value is unknown. This flag requires
 495            * additional processing, so we put warning here to catch it
 496            * some day and make proper implementation
 497            */
 498        trace_pvscsi_get_next_sg_elem(elem.flags);
 499    }
 500
 501    sg->elemAddr += sizeof(elem);
 502    sg->dataAddr = elem.addr;
 503    sg->resid = elem.length;
 504}
 505
 506static void
 507pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len)
 508{
 509    r->cmp.senseLen = MIN(r->req.senseLen, len);
 510    r->sense_key = sense[(sense[0] & 2) ? 1 : 2];
 511    cpu_physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen);
 512}
 513
 514static void
 515pvscsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid)
 516{
 517    PVSCSIRequest *pvscsi_req = req->hba_private;
 518    PVSCSIState *s;
 519
 520    if (!pvscsi_req) {
 521        trace_pvscsi_command_complete_not_found(req->tag);
 522        return;
 523    }
 524    s = pvscsi_req->dev;
 525
 526    if (resid) {
 527        /* Short transfer.  */
 528        trace_pvscsi_command_complete_data_run();
 529        pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN;
 530    }
 531
 532    pvscsi_req->cmp.scsiStatus = status;
 533    if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) {
 534        uint8_t sense[SCSI_SENSE_BUF_SIZE];
 535        int sense_len =
 536            scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense));
 537
 538        trace_pvscsi_command_complete_sense_len(sense_len);
 539        pvscsi_write_sense(pvscsi_req, sense, sense_len);
 540    }
 541    qemu_sglist_destroy(&pvscsi_req->sgl);
 542    pvscsi_complete_request(s, pvscsi_req);
 543}
 544
 545static void
 546pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type)
 547{
 548    if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) {
 549        PVSCSIMsgDescDevStatusChanged msg = {0};
 550
 551        msg.type = msg_type;
 552        msg.bus = dev->channel;
 553        msg.target = dev->id;
 554        msg.lun[1] = dev->lun;
 555
 556        pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg);
 557        pvscsi_ring_flush_msg(&s->rings);
 558        pvscsi_raise_message_interrupt(s);
 559    }
 560}
 561
 562static void
 563pvscsi_hotplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
 564{
 565    PVSCSIState *s = PVSCSI(hotplug_dev);
 566
 567    pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_ADDED);
 568}
 569
 570static void
 571pvscsi_hot_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
 572{
 573    PVSCSIState *s = PVSCSI(hotplug_dev);
 574
 575    pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_REMOVED);
 576    qdev_simple_device_unplug_cb(hotplug_dev, dev, errp);
 577}
 578
 579static void
 580pvscsi_request_cancelled(SCSIRequest *req)
 581{
 582    PVSCSIRequest *pvscsi_req = req->hba_private;
 583    PVSCSIState *s = pvscsi_req->dev;
 584
 585    if (pvscsi_req->completed) {
 586        return;
 587    }
 588
 589   if (pvscsi_req->dev->resetting) {
 590       pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET;
 591    } else {
 592       pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE;
 593    }
 594
 595    pvscsi_complete_request(s, pvscsi_req);
 596}
 597
 598static SCSIDevice*
 599pvscsi_device_find(PVSCSIState *s, int channel, int target,
 600                   uint8_t *requested_lun, uint8_t *target_lun)
 601{
 602    if (requested_lun[0] || requested_lun[2] || requested_lun[3] ||
 603        requested_lun[4] || requested_lun[5] || requested_lun[6] ||
 604        requested_lun[7] || (target > PVSCSI_MAX_DEVS)) {
 605        return NULL;
 606    } else {
 607        *target_lun = requested_lun[1];
 608        return scsi_device_find(&s->bus, channel, target, *target_lun);
 609    }
 610}
 611
 612static PVSCSIRequest *
 613pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d,
 614                                struct PVSCSIRingReqDesc *descr)
 615{
 616    PVSCSIRequest *pvscsi_req;
 617    uint8_t lun;
 618
 619    pvscsi_req = g_malloc0(sizeof(*pvscsi_req));
 620    pvscsi_req->dev = s;
 621    pvscsi_req->req = *descr;
 622    pvscsi_req->cmp.context = pvscsi_req->req.context;
 623    QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next);
 624
 625    *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun);
 626    if (*d) {
 627        pvscsi_req->lun = lun;
 628    }
 629
 630    return pvscsi_req;
 631}
 632
 633static void
 634pvscsi_convert_sglist(PVSCSIRequest *r)
 635{
 636    uint32_t chunk_size, elmcnt = 0;
 637    uint64_t data_length = r->req.dataLen;
 638    PVSCSISGState sg = r->sg;
 639    while (data_length && elmcnt < PVSCSI_MAX_SG_ELEM) {
 640        while (!sg.resid && elmcnt++ < PVSCSI_MAX_SG_ELEM) {
 641            pvscsi_get_next_sg_elem(&sg);
 642            trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr,
 643                                        r->sg.resid);
 644        }
 645        chunk_size = MIN(data_length, sg.resid);
 646        if (chunk_size) {
 647            qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size);
 648        }
 649
 650        sg.dataAddr += chunk_size;
 651        data_length -= chunk_size;
 652        sg.resid -= chunk_size;
 653    }
 654}
 655
 656static void
 657pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r)
 658{
 659    PCIDevice *d = PCI_DEVICE(s);
 660
 661    pci_dma_sglist_init(&r->sgl, d, 1);
 662    if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
 663        pvscsi_convert_sglist(r);
 664    } else {
 665        qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen);
 666    }
 667}
 668
 669static void
 670pvscsi_process_request_descriptor(PVSCSIState *s,
 671                                  struct PVSCSIRingReqDesc *descr)
 672{
 673    SCSIDevice *d;
 674    PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr);
 675    int64_t n;
 676
 677    trace_pvscsi_process_req_descr(descr->cdb[0], descr->context);
 678
 679    if (!d) {
 680        r->cmp.hostStatus = BTSTAT_SELTIMEO;
 681        trace_pvscsi_process_req_descr_unknown_device();
 682        pvscsi_complete_request(s, r);
 683        return;
 684    }
 685
 686    if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
 687        r->sg.elemAddr = descr->dataAddr;
 688    }
 689
 690    r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, r);
 691    if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV &&
 692        (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) {
 693        r->cmp.hostStatus = BTSTAT_BADMSG;
 694        trace_pvscsi_process_req_descr_invalid_dir();
 695        scsi_req_cancel(r->sreq);
 696        return;
 697    }
 698    if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV &&
 699        (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) {
 700        r->cmp.hostStatus = BTSTAT_BADMSG;
 701        trace_pvscsi_process_req_descr_invalid_dir();
 702        scsi_req_cancel(r->sreq);
 703        return;
 704    }
 705
 706    pvscsi_build_sglist(s, r);
 707    n = scsi_req_enqueue(r->sreq);
 708
 709    if (n) {
 710        scsi_req_continue(r->sreq);
 711    }
 712}
 713
 714static void
 715pvscsi_process_io(PVSCSIState *s)
 716{
 717    PVSCSIRingReqDesc descr;
 718    hwaddr next_descr_pa;
 719
 720    assert(s->rings_info_valid);
 721    while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) {
 722
 723        /* Only read after production index verification */
 724        smp_rmb();
 725
 726        trace_pvscsi_process_io(next_descr_pa);
 727        cpu_physical_memory_read(next_descr_pa, &descr, sizeof(descr));
 728        pvscsi_process_request_descriptor(s, &descr);
 729    }
 730
 731    pvscsi_ring_flush_req(&s->rings);
 732}
 733
 734static void
 735pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc)
 736{
 737    int i;
 738    trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN);
 739
 740    trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages);
 741    for (i = 0; i < rc->reqRingNumPages; i++) {
 742        trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]);
 743    }
 744
 745    trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages);
 746    for (i = 0; i < rc->cmpRingNumPages; i++) {
 747        trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->cmpRingPPNs[i]);
 748    }
 749}
 750
 751static uint64_t
 752pvscsi_on_cmd_config(PVSCSIState *s)
 753{
 754    trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG");
 755    return PVSCSI_COMMAND_PROCESSING_FAILED;
 756}
 757
 758static uint64_t
 759pvscsi_on_cmd_unplug(PVSCSIState *s)
 760{
 761    trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG");
 762    return PVSCSI_COMMAND_PROCESSING_FAILED;
 763}
 764
 765static uint64_t
 766pvscsi_on_issue_scsi(PVSCSIState *s)
 767{
 768    trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI");
 769    return PVSCSI_COMMAND_PROCESSING_FAILED;
 770}
 771
 772static uint64_t
 773pvscsi_on_cmd_setup_rings(PVSCSIState *s)
 774{
 775    PVSCSICmdDescSetupRings *rc =
 776        (PVSCSICmdDescSetupRings *) s->curr_cmd_data;
 777
 778    trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS");
 779
 780    if (!rc->reqRingNumPages
 781        || rc->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES
 782        || !rc->cmpRingNumPages
 783        || rc->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES) {
 784        return PVSCSI_COMMAND_PROCESSING_FAILED;
 785    }
 786
 787    pvscsi_dbg_dump_tx_rings_config(rc);
 788    pvscsi_ring_init_data(&s->rings, rc);
 789
 790    s->rings_info_valid = TRUE;
 791    return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 792}
 793
 794static uint64_t
 795pvscsi_on_cmd_abort(PVSCSIState *s)
 796{
 797    PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data;
 798    PVSCSIRequest *r, *next;
 799
 800    trace_pvscsi_on_cmd_abort(cmd->context, cmd->target);
 801
 802    QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) {
 803        if (r->req.context == cmd->context) {
 804            break;
 805        }
 806    }
 807    if (r) {
 808        assert(!r->completed);
 809        r->cmp.hostStatus = BTSTAT_ABORTQUEUE;
 810        scsi_req_cancel(r->sreq);
 811    }
 812
 813    return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 814}
 815
 816static uint64_t
 817pvscsi_on_cmd_unknown(PVSCSIState *s)
 818{
 819    trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]);
 820    return PVSCSI_COMMAND_PROCESSING_FAILED;
 821}
 822
 823static uint64_t
 824pvscsi_on_cmd_reset_device(PVSCSIState *s)
 825{
 826    uint8_t target_lun = 0;
 827    struct PVSCSICmdDescResetDevice *cmd =
 828        (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data;
 829    SCSIDevice *sdev;
 830
 831    sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun);
 832
 833    trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev);
 834
 835    if (sdev != NULL) {
 836        s->resetting++;
 837        device_reset(&sdev->qdev);
 838        s->resetting--;
 839        return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 840    }
 841
 842    return PVSCSI_COMMAND_PROCESSING_FAILED;
 843}
 844
 845static uint64_t
 846pvscsi_on_cmd_reset_bus(PVSCSIState *s)
 847{
 848    trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS");
 849
 850    s->resetting++;
 851    qbus_reset_all_fn(&s->bus);
 852    s->resetting--;
 853    return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 854}
 855
 856static uint64_t
 857pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s)
 858{
 859    PVSCSICmdDescSetupMsgRing *rc =
 860        (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data;
 861
 862    trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING");
 863
 864    if (!s->use_msg) {
 865        return PVSCSI_COMMAND_PROCESSING_FAILED;
 866    }
 867
 868    if (s->rings_info_valid) {
 869        if (pvscsi_ring_init_msg(&s->rings, rc) < 0) {
 870            return PVSCSI_COMMAND_PROCESSING_FAILED;
 871        }
 872        s->msg_ring_info_valid = TRUE;
 873    }
 874    return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t);
 875}
 876
 877static uint64_t
 878pvscsi_on_cmd_adapter_reset(PVSCSIState *s)
 879{
 880    trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET");
 881
 882    pvscsi_reset_adapter(s);
 883    return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 884}
 885
 886static const struct {
 887    int       data_size;
 888    uint64_t  (*handler_fn)(PVSCSIState *s);
 889} pvscsi_commands[] = {
 890    [PVSCSI_CMD_FIRST] = {
 891        .data_size = 0,
 892        .handler_fn = pvscsi_on_cmd_unknown,
 893    },
 894
 895    /* Not implemented, data size defined based on what arrives on windows */
 896    [PVSCSI_CMD_CONFIG] = {
 897        .data_size = 6 * sizeof(uint32_t),
 898        .handler_fn = pvscsi_on_cmd_config,
 899    },
 900
 901    /* Command not implemented, data size is unknown */
 902    [PVSCSI_CMD_ISSUE_SCSI] = {
 903        .data_size = 0,
 904        .handler_fn = pvscsi_on_issue_scsi,
 905    },
 906
 907    /* Command not implemented, data size is unknown */
 908    [PVSCSI_CMD_DEVICE_UNPLUG] = {
 909        .data_size = 0,
 910        .handler_fn = pvscsi_on_cmd_unplug,
 911    },
 912
 913    [PVSCSI_CMD_SETUP_RINGS] = {
 914        .data_size = sizeof(PVSCSICmdDescSetupRings),
 915        .handler_fn = pvscsi_on_cmd_setup_rings,
 916    },
 917
 918    [PVSCSI_CMD_RESET_DEVICE] = {
 919        .data_size = sizeof(struct PVSCSICmdDescResetDevice),
 920        .handler_fn = pvscsi_on_cmd_reset_device,
 921    },
 922
 923    [PVSCSI_CMD_RESET_BUS] = {
 924        .data_size = 0,
 925        .handler_fn = pvscsi_on_cmd_reset_bus,
 926    },
 927
 928    [PVSCSI_CMD_SETUP_MSG_RING] = {
 929        .data_size = sizeof(PVSCSICmdDescSetupMsgRing),
 930        .handler_fn = pvscsi_on_cmd_setup_msg_ring,
 931    },
 932
 933    [PVSCSI_CMD_ADAPTER_RESET] = {
 934        .data_size = 0,
 935        .handler_fn = pvscsi_on_cmd_adapter_reset,
 936    },
 937
 938    [PVSCSI_CMD_ABORT_CMD] = {
 939        .data_size = sizeof(struct PVSCSICmdDescAbortCmd),
 940        .handler_fn = pvscsi_on_cmd_abort,
 941    },
 942};
 943
 944static void
 945pvscsi_do_command_processing(PVSCSIState *s)
 946{
 947    size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
 948
 949    assert(s->curr_cmd < PVSCSI_CMD_LAST);
 950    if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) {
 951        s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s);
 952        s->curr_cmd = PVSCSI_CMD_FIRST;
 953        s->curr_cmd_data_cntr   = 0;
 954    }
 955}
 956
 957static void
 958pvscsi_on_command_data(PVSCSIState *s, uint32_t value)
 959{
 960    size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
 961
 962    assert(bytes_arrived < sizeof(s->curr_cmd_data));
 963    s->curr_cmd_data[s->curr_cmd_data_cntr++] = value;
 964
 965    pvscsi_do_command_processing(s);
 966}
 967
 968static void
 969pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id)
 970{
 971    if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) {
 972        s->curr_cmd = cmd_id;
 973    } else {
 974        s->curr_cmd = PVSCSI_CMD_FIRST;
 975        trace_pvscsi_on_cmd_unknown(cmd_id);
 976    }
 977
 978    s->curr_cmd_data_cntr = 0;
 979    s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA;
 980
 981    pvscsi_do_command_processing(s);
 982}
 983
 984static void
 985pvscsi_io_write(void *opaque, hwaddr addr,
 986                uint64_t val, unsigned size)
 987{
 988    PVSCSIState *s = opaque;
 989
 990    switch (addr) {
 991    case PVSCSI_REG_OFFSET_COMMAND:
 992        pvscsi_on_command(s, val);
 993        break;
 994
 995    case PVSCSI_REG_OFFSET_COMMAND_DATA:
 996        pvscsi_on_command_data(s, (uint32_t) val);
 997        break;
 998
 999    case PVSCSI_REG_OFFSET_INTR_STATUS:
1000        trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val);
1001        s->reg_interrupt_status &= ~val;
1002        pvscsi_update_irq_status(s);
1003        pvscsi_schedule_completion_processing(s);
1004        break;
1005
1006    case PVSCSI_REG_OFFSET_INTR_MASK:
1007        trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val);
1008        s->reg_interrupt_enabled = val;
1009        pvscsi_update_irq_status(s);
1010        break;
1011
1012    case PVSCSI_REG_OFFSET_KICK_NON_RW_IO:
1013        trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val);
1014        pvscsi_process_io(s);
1015        break;
1016
1017    case PVSCSI_REG_OFFSET_KICK_RW_IO:
1018        trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val);
1019        pvscsi_process_io(s);
1020        break;
1021
1022    case PVSCSI_REG_OFFSET_DEBUG:
1023        trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val);
1024        break;
1025
1026    default:
1027        trace_pvscsi_io_write_unknown(addr, size, val);
1028        break;
1029    }
1030
1031}
1032
1033static uint64_t
1034pvscsi_io_read(void *opaque, hwaddr addr, unsigned size)
1035{
1036    PVSCSIState *s = opaque;
1037
1038    switch (addr) {
1039    case PVSCSI_REG_OFFSET_INTR_STATUS:
1040        trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS",
1041                             s->reg_interrupt_status);
1042        return s->reg_interrupt_status;
1043
1044    case PVSCSI_REG_OFFSET_INTR_MASK:
1045        trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK",
1046                             s->reg_interrupt_status);
1047        return s->reg_interrupt_enabled;
1048
1049    case PVSCSI_REG_OFFSET_COMMAND_STATUS:
1050        trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS",
1051                             s->reg_interrupt_status);
1052        return s->reg_command_status;
1053
1054    default:
1055        trace_pvscsi_io_read_unknown(addr, size);
1056        return 0;
1057    }
1058}
1059
1060
1061static void
1062pvscsi_init_msi(PVSCSIState *s)
1063{
1064    int res;
1065    PCIDevice *d = PCI_DEVICE(s);
1066
1067    res = msi_init(d, PVSCSI_MSI_OFFSET(s), PVSCSI_MSIX_NUM_VECTORS,
1068                   PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK, NULL);
1069    if (res < 0) {
1070        trace_pvscsi_init_msi_fail(res);
1071        s->msi_used = false;
1072    } else {
1073        s->msi_used = true;
1074    }
1075}
1076
1077static void
1078pvscsi_cleanup_msi(PVSCSIState *s)
1079{
1080    PCIDevice *d = PCI_DEVICE(s);
1081
1082    msi_uninit(d);
1083}
1084
1085static const MemoryRegionOps pvscsi_ops = {
1086        .read = pvscsi_io_read,
1087        .write = pvscsi_io_write,
1088        .endianness = DEVICE_LITTLE_ENDIAN,
1089        .impl = {
1090                .min_access_size = 4,
1091                .max_access_size = 4,
1092        },
1093};
1094
1095static const struct SCSIBusInfo pvscsi_scsi_info = {
1096        .tcq = true,
1097        .max_target = PVSCSI_MAX_DEVS,
1098        .max_channel = 0,
1099        .max_lun = 0,
1100
1101        .get_sg_list = pvscsi_get_sg_list,
1102        .complete = pvscsi_command_complete,
1103        .cancel = pvscsi_request_cancelled,
1104};
1105
1106static void
1107pvscsi_realizefn(PCIDevice *pci_dev, Error **errp)
1108{
1109    PVSCSIState *s = PVSCSI(pci_dev);
1110
1111    trace_pvscsi_state("init");
1112
1113    /* PCI subsystem ID, subsystem vendor ID, revision */
1114    if (PVSCSI_USE_OLD_PCI_CONFIGURATION(s)) {
1115        pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 0x1000);
1116    } else {
1117        pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1118                     PCI_VENDOR_ID_VMWARE);
1119        pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1120                     PCI_DEVICE_ID_VMWARE_PVSCSI);
1121        pci_config_set_revision(pci_dev->config, 0x2);
1122    }
1123
1124    /* PCI latency timer = 255 */
1125    pci_dev->config[PCI_LATENCY_TIMER] = 0xff;
1126
1127    /* Interrupt pin A */
1128    pci_config_set_interrupt_pin(pci_dev->config, 1);
1129
1130    memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s,
1131                          "pvscsi-io", PVSCSI_MEM_SPACE_SIZE);
1132    pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space);
1133
1134    pvscsi_init_msi(s);
1135
1136    if (pci_is_express(pci_dev) && pci_bus_is_express(pci_dev->bus)) {
1137        pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET);
1138    }
1139
1140    s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s);
1141
1142    scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
1143                 &pvscsi_scsi_info, NULL);
1144    /* override default SCSI bus hotplug-handler, with pvscsi's one */
1145    qbus_set_hotplug_handler(BUS(&s->bus), DEVICE(s), &error_abort);
1146    pvscsi_reset_state(s);
1147}
1148
1149static void
1150pvscsi_uninit(PCIDevice *pci_dev)
1151{
1152    PVSCSIState *s = PVSCSI(pci_dev);
1153
1154    trace_pvscsi_state("uninit");
1155    qemu_bh_delete(s->completion_worker);
1156
1157    pvscsi_cleanup_msi(s);
1158}
1159
1160static void
1161pvscsi_reset(DeviceState *dev)
1162{
1163    PCIDevice *d = PCI_DEVICE(dev);
1164    PVSCSIState *s = PVSCSI(d);
1165
1166    trace_pvscsi_state("reset");
1167    pvscsi_reset_adapter(s);
1168}
1169
1170static int
1171pvscsi_pre_save(void *opaque)
1172{
1173    PVSCSIState *s = (PVSCSIState *) opaque;
1174
1175    trace_pvscsi_state("presave");
1176
1177    assert(QTAILQ_EMPTY(&s->pending_queue));
1178    assert(QTAILQ_EMPTY(&s->completion_queue));
1179
1180    return 0;
1181}
1182
1183static int
1184pvscsi_post_load(void *opaque, int version_id)
1185{
1186    trace_pvscsi_state("postload");
1187    return 0;
1188}
1189
1190static bool pvscsi_vmstate_need_pcie_device(void *opaque)
1191{
1192    PVSCSIState *s = PVSCSI(opaque);
1193
1194    return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE);
1195}
1196
1197static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id)
1198{
1199    return !pvscsi_vmstate_need_pcie_device(opaque);
1200}
1201
1202static const VMStateDescription vmstate_pvscsi_pcie_device = {
1203    .name = "pvscsi/pcie",
1204    .needed = pvscsi_vmstate_need_pcie_device,
1205    .fields = (VMStateField[]) {
1206        VMSTATE_PCI_DEVICE(parent_obj, PVSCSIState),
1207        VMSTATE_END_OF_LIST()
1208    }
1209};
1210
1211static const VMStateDescription vmstate_pvscsi = {
1212    .name = "pvscsi",
1213    .version_id = 0,
1214    .minimum_version_id = 0,
1215    .pre_save = pvscsi_pre_save,
1216    .post_load = pvscsi_post_load,
1217    .fields = (VMStateField[]) {
1218        VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState,
1219                            pvscsi_vmstate_test_pci_device, 0,
1220                            vmstate_pci_device, PCIDevice),
1221        VMSTATE_UINT8(msi_used, PVSCSIState),
1222        VMSTATE_UINT32(resetting, PVSCSIState),
1223        VMSTATE_UINT64(reg_interrupt_status, PVSCSIState),
1224        VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState),
1225        VMSTATE_UINT64(reg_command_status, PVSCSIState),
1226        VMSTATE_UINT64(curr_cmd, PVSCSIState),
1227        VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState),
1228        VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState,
1229                             ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)),
1230        VMSTATE_UINT8(rings_info_valid, PVSCSIState),
1231        VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState),
1232        VMSTATE_UINT8(use_msg, PVSCSIState),
1233
1234        VMSTATE_UINT64(rings.rs_pa, PVSCSIState),
1235        VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState),
1236        VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState),
1237        VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState,
1238                             PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1239        VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState,
1240                             PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1241        VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState),
1242        VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState),
1243
1244        VMSTATE_END_OF_LIST()
1245    },
1246    .subsections = (const VMStateDescription*[]) {
1247        &vmstate_pvscsi_pcie_device,
1248        NULL
1249    }
1250};
1251
1252static Property pvscsi_properties[] = {
1253    DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
1254    DEFINE_PROP_BIT("x-old-pci-configuration", PVSCSIState, compat_flags,
1255                    PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false),
1256    DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags,
1257                    PVSCSI_COMPAT_DISABLE_PCIE_BIT, false),
1258    DEFINE_PROP_END_OF_LIST(),
1259};
1260
1261static void pvscsi_realize(DeviceState *qdev, Error **errp)
1262{
1263    PVSCSIClass *pvs_c = PVSCSI_DEVICE_GET_CLASS(qdev);
1264    PCIDevice *pci_dev = PCI_DEVICE(qdev);
1265    PVSCSIState *s = PVSCSI(qdev);
1266
1267    if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) {
1268        pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1269    }
1270
1271    pvs_c->parent_dc_realize(qdev, errp);
1272}
1273
1274static void pvscsi_class_init(ObjectClass *klass, void *data)
1275{
1276    DeviceClass *dc = DEVICE_CLASS(klass);
1277    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1278    PVSCSIClass *pvs_k = PVSCSI_DEVICE_CLASS(klass);
1279    HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
1280
1281    k->realize = pvscsi_realizefn;
1282    k->exit = pvscsi_uninit;
1283    k->vendor_id = PCI_VENDOR_ID_VMWARE;
1284    k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI;
1285    k->class_id = PCI_CLASS_STORAGE_SCSI;
1286    k->subsystem_id = 0x1000;
1287    pvs_k->parent_dc_realize = dc->realize;
1288    dc->realize = pvscsi_realize;
1289    dc->reset = pvscsi_reset;
1290    dc->vmsd = &vmstate_pvscsi;
1291    dc->props = pvscsi_properties;
1292    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1293    hc->unplug = pvscsi_hot_unplug;
1294    hc->plug = pvscsi_hotplug;
1295}
1296
1297static const TypeInfo pvscsi_info = {
1298    .name          = TYPE_PVSCSI,
1299    .parent        = TYPE_PCI_DEVICE,
1300    .class_size    = sizeof(PVSCSIClass),
1301    .instance_size = sizeof(PVSCSIState),
1302    .class_init    = pvscsi_class_init,
1303    .interfaces = (InterfaceInfo[]) {
1304        { TYPE_HOTPLUG_HANDLER },
1305        { INTERFACE_PCIE_DEVICE },
1306        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1307        { }
1308    }
1309};
1310
1311static void
1312pvscsi_register_types(void)
1313{
1314    type_register_static(&pvscsi_info);
1315}
1316
1317type_init(pvscsi_register_types);
1318