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28#include "qemu/osdep.h"
29#include "qapi/error.h"
30#include "qemu-common.h"
31#include "cpu.h"
32#include "sysemu/sysemu.h"
33#include "hw/boards.h"
34#include "hw/loader.h"
35#include "elf.h"
36#include "exec/memory.h"
37#include "exec/address-spaces.h"
38#include "hw/char/serial.h"
39#include "net/net.h"
40#include "hw/sysbus.h"
41#include "hw/block/flash.h"
42#include "sysemu/block-backend.h"
43#include "chardev/char.h"
44#include "sysemu/device_tree.h"
45#include "qemu/error-report.h"
46#include "bootparam.h"
47
48typedef struct LxBoardDesc {
49 hwaddr flash_base;
50 size_t flash_size;
51 size_t flash_boot_base;
52 size_t flash_sector_size;
53 size_t sram_size;
54} LxBoardDesc;
55
56typedef struct Lx60FpgaState {
57 MemoryRegion iomem;
58 uint32_t leds;
59 uint32_t switches;
60} Lx60FpgaState;
61
62static void lx60_fpga_reset(void *opaque)
63{
64 Lx60FpgaState *s = opaque;
65
66 s->leds = 0;
67 s->switches = 0;
68}
69
70static uint64_t lx60_fpga_read(void *opaque, hwaddr addr,
71 unsigned size)
72{
73 Lx60FpgaState *s = opaque;
74
75 switch (addr) {
76 case 0x0:
77 return 0x09272011;
78
79 case 0x4:
80 return 10000000;
81
82 case 0x8:
83 return s->leds;
84
85 case 0xc:
86 return s->switches;
87 }
88 return 0;
89}
90
91static void lx60_fpga_write(void *opaque, hwaddr addr,
92 uint64_t val, unsigned size)
93{
94 Lx60FpgaState *s = opaque;
95
96 switch (addr) {
97 case 0x8:
98 s->leds = val;
99 break;
100
101 case 0x10:
102 if (val == 0xdead) {
103 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
104 }
105 break;
106 }
107}
108
109static const MemoryRegionOps lx60_fpga_ops = {
110 .read = lx60_fpga_read,
111 .write = lx60_fpga_write,
112 .endianness = DEVICE_NATIVE_ENDIAN,
113};
114
115static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space,
116 hwaddr base)
117{
118 Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState));
119
120 memory_region_init_io(&s->iomem, NULL, &lx60_fpga_ops, s,
121 "lx60.fpga", 0x10000);
122 memory_region_add_subregion(address_space, base, &s->iomem);
123 lx60_fpga_reset(s);
124 qemu_register_reset(lx60_fpga_reset, s);
125 return s;
126}
127
128static void lx60_net_init(MemoryRegion *address_space,
129 hwaddr base,
130 hwaddr descriptors,
131 hwaddr buffers,
132 qemu_irq irq, NICInfo *nd)
133{
134 DeviceState *dev;
135 SysBusDevice *s;
136 MemoryRegion *ram;
137
138 dev = qdev_create(NULL, "open_eth");
139 qdev_set_nic_properties(dev, nd);
140 qdev_init_nofail(dev);
141
142 s = SYS_BUS_DEVICE(dev);
143 sysbus_connect_irq(s, 0, irq);
144 memory_region_add_subregion(address_space, base,
145 sysbus_mmio_get_region(s, 0));
146 memory_region_add_subregion(address_space, descriptors,
147 sysbus_mmio_get_region(s, 1));
148
149 ram = g_malloc(sizeof(*ram));
150 memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16384,
151 &error_fatal);
152 vmstate_register_ram_global(ram);
153 memory_region_add_subregion(address_space, buffers, ram);
154}
155
156static pflash_t *xtfpga_flash_init(MemoryRegion *address_space,
157 const LxBoardDesc *board,
158 DriveInfo *dinfo, int be)
159{
160 SysBusDevice *s;
161 DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
162
163 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
164 &error_abort);
165 qdev_prop_set_uint32(dev, "num-blocks",
166 board->flash_size / board->flash_sector_size);
167 qdev_prop_set_uint64(dev, "sector-length", board->flash_sector_size);
168 qdev_prop_set_uint8(dev, "width", 2);
169 qdev_prop_set_bit(dev, "big-endian", be);
170 qdev_prop_set_string(dev, "name", "lx60.io.flash");
171 qdev_init_nofail(dev);
172 s = SYS_BUS_DEVICE(dev);
173 memory_region_add_subregion(address_space, board->flash_base,
174 sysbus_mmio_get_region(s, 0));
175 return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
176}
177
178static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
179{
180 XtensaCPU *cpu = opaque;
181
182 return cpu_get_phys_page_debug(CPU(cpu), addr);
183}
184
185static void lx60_reset(void *opaque)
186{
187 XtensaCPU *cpu = opaque;
188
189 cpu_reset(CPU(cpu));
190}
191
192static uint64_t lx60_io_read(void *opaque, hwaddr addr,
193 unsigned size)
194{
195 return 0;
196}
197
198static void lx60_io_write(void *opaque, hwaddr addr,
199 uint64_t val, unsigned size)
200{
201}
202
203static const MemoryRegionOps lx60_io_ops = {
204 .read = lx60_io_read,
205 .write = lx60_io_write,
206 .endianness = DEVICE_NATIVE_ENDIAN,
207};
208
209static void lx_init(const LxBoardDesc *board, MachineState *machine)
210{
211#ifdef TARGET_WORDS_BIGENDIAN
212 int be = 1;
213#else
214 int be = 0;
215#endif
216 MemoryRegion *system_memory = get_system_memory();
217 XtensaCPU *cpu = NULL;
218 CPUXtensaState *env = NULL;
219 MemoryRegion *ram, *rom, *system_io;
220 DriveInfo *dinfo;
221 pflash_t *flash = NULL;
222 QemuOpts *machine_opts = qemu_get_machine_opts();
223 const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
224 const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
225 const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
226 const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
227 int n;
228
229 for (n = 0; n < smp_cpus; n++) {
230 cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
231 env = &cpu->env;
232
233 env->sregs[PRID] = n;
234 qemu_register_reset(lx60_reset, cpu);
235
236
237
238 cpu_reset(CPU(cpu));
239 }
240
241 ram = g_malloc(sizeof(*ram));
242 memory_region_init_ram(ram, NULL, "lx60.dram", machine->ram_size,
243 &error_fatal);
244 memory_region_add_subregion(system_memory, 0, ram);
245
246 system_io = g_malloc(sizeof(*system_io));
247 memory_region_init_io(system_io, NULL, &lx60_io_ops, NULL, "lx60.io",
248 224 * 1024 * 1024);
249 memory_region_add_subregion(system_memory, 0xf0000000, system_io);
250 lx60_fpga_init(system_io, 0x0d020000);
251 if (nd_table[0].used) {
252 lx60_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
253 xtensa_get_extint(env, 1), nd_table);
254 }
255
256 if (!serial_hds[0]) {
257 serial_hds[0] = qemu_chr_new("serial0", "null");
258 }
259
260 serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0),
261 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
262
263 dinfo = drive_get(IF_PFLASH, 0, 0);
264 if (dinfo) {
265 flash = xtfpga_flash_init(system_io, board, dinfo, be);
266 }
267
268
269 if (kernel_filename) {
270 uint32_t entry_point = env->pc;
271 size_t bp_size = 3 * get_tag_size(0);
272 uint32_t tagptr = 0xfe000000 + board->sram_size;
273 uint32_t cur_tagptr;
274 BpMemInfo memory_location = {
275 .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
276 .start = tswap32(0),
277 .end = tswap32(machine->ram_size),
278 };
279 uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
280 machine->ram_size : 0x08000000;
281 uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
282
283 rom = g_malloc(sizeof(*rom));
284 memory_region_init_ram(rom, NULL, "lx60.sram", board->sram_size,
285 &error_fatal);
286 memory_region_add_subregion(system_memory, 0xfe000000, rom);
287
288 if (kernel_cmdline) {
289 bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
290 }
291 if (dtb_filename) {
292 bp_size += get_tag_size(sizeof(uint32_t));
293 }
294 if (initrd_filename) {
295 bp_size += get_tag_size(sizeof(BpMemInfo));
296 }
297
298
299 tagptr = (tagptr - bp_size) & ~0xff;
300 cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
301 cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
302 sizeof(memory_location), &memory_location);
303
304 if (kernel_cmdline) {
305 cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
306 strlen(kernel_cmdline) + 1, kernel_cmdline);
307 }
308#ifdef CONFIG_FDT
309 if (dtb_filename) {
310 int fdt_size;
311 void *fdt = load_device_tree(dtb_filename, &fdt_size);
312 uint32_t dtb_addr = tswap32(cur_lowmem);
313
314 if (!fdt) {
315 error_report("could not load DTB '%s'", dtb_filename);
316 exit(EXIT_FAILURE);
317 }
318
319 cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
320 cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
321 sizeof(dtb_addr), &dtb_addr);
322 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096);
323 }
324#else
325 if (dtb_filename) {
326 error_report("could not load DTB '%s': "
327 "FDT support is not configured in QEMU",
328 dtb_filename);
329 exit(EXIT_FAILURE);
330 }
331#endif
332 if (initrd_filename) {
333 BpMemInfo initrd_location = { 0 };
334 int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
335 lowmem_end - cur_lowmem);
336
337 if (initrd_size < 0) {
338 initrd_size = load_image_targphys(initrd_filename,
339 cur_lowmem,
340 lowmem_end - cur_lowmem);
341 }
342 if (initrd_size < 0) {
343 error_report("could not load initrd '%s'", initrd_filename);
344 exit(EXIT_FAILURE);
345 }
346 initrd_location.start = tswap32(cur_lowmem);
347 initrd_location.end = tswap32(cur_lowmem + initrd_size);
348 cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
349 sizeof(initrd_location), &initrd_location);
350 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096);
351 }
352 cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
353 env->regs[2] = tagptr;
354
355 uint64_t elf_entry;
356 uint64_t elf_lowaddr;
357 int success = load_elf(kernel_filename, translate_phys_addr, cpu,
358 &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0);
359 if (success > 0) {
360 entry_point = elf_entry;
361 } else {
362 hwaddr ep;
363 int is_linux;
364 success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
365 translate_phys_addr, cpu);
366 if (success > 0 && is_linux) {
367 entry_point = ep;
368 } else {
369 error_report("could not load kernel '%s'",
370 kernel_filename);
371 exit(EXIT_FAILURE);
372 }
373 }
374 if (entry_point != env->pc) {
375 static const uint8_t jx_a0[] = {
376#ifdef TARGET_WORDS_BIGENDIAN
377 0x0a, 0, 0,
378#else
379 0xa0, 0, 0,
380#endif
381 };
382 env->regs[0] = entry_point;
383 cpu_physical_memory_write(env->pc, jx_a0, sizeof(jx_a0));
384 }
385 } else {
386 if (flash) {
387 MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
388 MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
389
390 memory_region_init_alias(flash_io, NULL, "lx60.flash",
391 flash_mr, board->flash_boot_base,
392 board->flash_size - board->flash_boot_base < 0x02000000 ?
393 board->flash_size - board->flash_boot_base : 0x02000000);
394 memory_region_add_subregion(system_memory, 0xfe000000,
395 flash_io);
396 }
397 }
398}
399
400static void xtensa_lx60_init(MachineState *machine)
401{
402 static const LxBoardDesc lx60_board = {
403 .flash_base = 0x08000000,
404 .flash_size = 0x00400000,
405 .flash_sector_size = 0x10000,
406 .sram_size = 0x20000,
407 };
408 lx_init(&lx60_board, machine);
409}
410
411static void xtensa_lx200_init(MachineState *machine)
412{
413 static const LxBoardDesc lx200_board = {
414 .flash_base = 0x08000000,
415 .flash_size = 0x01000000,
416 .flash_sector_size = 0x20000,
417 .sram_size = 0x2000000,
418 };
419 lx_init(&lx200_board, machine);
420}
421
422static void xtensa_ml605_init(MachineState *machine)
423{
424 static const LxBoardDesc ml605_board = {
425 .flash_base = 0x08000000,
426 .flash_size = 0x01000000,
427 .flash_sector_size = 0x20000,
428 .sram_size = 0x2000000,
429 };
430 lx_init(&ml605_board, machine);
431}
432
433static void xtensa_kc705_init(MachineState *machine)
434{
435 static const LxBoardDesc kc705_board = {
436 .flash_base = 0x00000000,
437 .flash_size = 0x08000000,
438 .flash_boot_base = 0x06000000,
439 .flash_sector_size = 0x20000,
440 .sram_size = 0x2000000,
441 };
442 lx_init(&kc705_board, machine);
443}
444
445static void xtensa_lx60_class_init(ObjectClass *oc, void *data)
446{
447 MachineClass *mc = MACHINE_CLASS(oc);
448
449 mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
450 mc->init = xtensa_lx60_init;
451 mc->max_cpus = 4;
452 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
453}
454
455static const TypeInfo xtensa_lx60_type = {
456 .name = MACHINE_TYPE_NAME("lx60"),
457 .parent = TYPE_MACHINE,
458 .class_init = xtensa_lx60_class_init,
459};
460
461static void xtensa_lx200_class_init(ObjectClass *oc, void *data)
462{
463 MachineClass *mc = MACHINE_CLASS(oc);
464
465 mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
466 mc->init = xtensa_lx200_init;
467 mc->max_cpus = 4;
468 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
469}
470
471static const TypeInfo xtensa_lx200_type = {
472 .name = MACHINE_TYPE_NAME("lx200"),
473 .parent = TYPE_MACHINE,
474 .class_init = xtensa_lx200_class_init,
475};
476
477static void xtensa_ml605_class_init(ObjectClass *oc, void *data)
478{
479 MachineClass *mc = MACHINE_CLASS(oc);
480
481 mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
482 mc->init = xtensa_ml605_init;
483 mc->max_cpus = 4;
484 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
485}
486
487static const TypeInfo xtensa_ml605_type = {
488 .name = MACHINE_TYPE_NAME("ml605"),
489 .parent = TYPE_MACHINE,
490 .class_init = xtensa_ml605_class_init,
491};
492
493static void xtensa_kc705_class_init(ObjectClass *oc, void *data)
494{
495 MachineClass *mc = MACHINE_CLASS(oc);
496
497 mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
498 mc->init = xtensa_kc705_init;
499 mc->max_cpus = 4;
500 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
501}
502
503static const TypeInfo xtensa_kc705_type = {
504 .name = MACHINE_TYPE_NAME("kc705"),
505 .parent = TYPE_MACHINE,
506 .class_init = xtensa_kc705_class_init,
507};
508
509static void xtensa_lx_machines_init(void)
510{
511 type_register_static(&xtensa_lx60_type);
512 type_register_static(&xtensa_lx200_type);
513 type_register_static(&xtensa_ml605_type);
514 type_register_static(&xtensa_kc705_type);
515}
516
517type_init(xtensa_lx_machines_init)
518
