LXR qemu/target/microblaze/cpu.h

   1/*
   2 *  MicroBlaze virtual CPU header
   3 *
   4 *  Copyright (c) 2009 Edgar E. Iglesias
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#ifndef MICROBLAZE_CPU_H
  21#define MICROBLAZE_CPU_H
  22
  23#include "qemu-common.h"
  24#include "cpu-qom.h"
  25
  26#define TARGET_LONG_BITS 64
  27
  28#define CPUArchState struct CPUMBState
  29
  30#include "exec/cpu-defs.h"
  31#include "fpu/softfloat.h"
  32struct CPUMBState;
  33typedef struct CPUMBState CPUMBState;
  34#if !defined(CONFIG_USER_ONLY)
  35#include "mmu.h"
  36#endif
  37
  38#define EXCP_MMU        1
  39#define EXCP_IRQ        2
  40#define EXCP_BREAK      3
  41#define EXCP_HW_BREAK   4
  42#define EXCP_HW_EXCP    5
  43
  44/* MicroBlaze-specific interrupt pending bits.  */
  45#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
  46
  47/* Meanings of the MBCPU object's two inbound GPIO lines */
  48#define MB_CPU_IRQ 0
  49#define MB_CPU_FIR 1
  50
  51/* Register aliases. R0 - R15 */
  52#define R_SP     1
  53#define SR_PC    0
  54#define SR_MSR   1
  55#define SR_EAR   3
  56#define SR_ESR   5
  57#define SR_FSR   7
  58#define SR_BTR   0xb
  59#define SR_EDR   0xd
  60
  61/* MSR flags.  */
  62#define MSR_PVR_SHIFT 10
  63
  64#define MSR_BE  (1<<0) /* 0x001 */
  65#define MSR_IE  (1<<1) /* 0x002 */
  66#define MSR_C   (1<<2) /* 0x004 */
  67#define MSR_BIP (1<<3) /* 0x008 */
  68#define MSR_FSL (1<<4) /* 0x010 */
  69#define MSR_ICE (1<<5) /* 0x020 */
  70#define MSR_DZ  (1<<6) /* 0x040 */
  71#define MSR_DCE (1<<7) /* 0x080 */
  72#define MSR_EE  (1<<8) /* 0x100 */
  73#define MSR_EIP (1<<9) /* 0x200 */
  74#define MSR_PVR (1 << MSR_PVR_SHIFT)
  75#define MSR_CC  (1<<31)
  76
  77/* Machine State Register (MSR) Fields */
  78#define MSR_UM (1<<11) /* User Mode */
  79#define MSR_UMS        (1<<12) /* User Mode Save */
  80#define MSR_VM (1<<13) /* Virtual Mode */
  81#define MSR_VMS        (1<<14) /* Virtual Mode Save */
  82
  83#define MSR_KERNEL      MSR_EE|MSR_VM
  84//#define MSR_USER     MSR_KERNEL|MSR_UM|MSR_IE
  85#define MSR_KERNEL_VMS  MSR_EE|MSR_VMS
  86//#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
  87
  88/* Exception State Register (ESR) Fields */
  89#define          ESR_DIZ       (1<<11) /* Zone Protection */
  90#define          ESR_S         (1<<10) /* Store instruction */
  91
  92#define          ESR_ESS_FSL_OFFSET     5
  93
  94#define          ESR_EC_FSL             0
  95#define          ESR_EC_UNALIGNED_DATA  1
  96#define          ESR_EC_ILLEGAL_OP      2
  97#define          ESR_EC_INSN_BUS        3
  98#define          ESR_EC_DATA_BUS        4
  99#define          ESR_EC_DIVZERO         5
 100#define          ESR_EC_FPU             6
 101#define          ESR_EC_PRIVINSN        7
 102#define          ESR_EC_STACKPROT       7  /* Same as PRIVINSN.  */
 103#define          ESR_EC_DATA_STORAGE    8
 104#define          ESR_EC_INSN_STORAGE    9
 105#define          ESR_EC_DATA_TLB        10
 106#define          ESR_EC_INSN_TLB        11
 107#define          ESR_EC_MASK            31
 108
 109/* Floating Point Status Register (FSR) Bits */
 110#define FSR_IO          (1<<4) /* Invalid operation */
 111#define FSR_DZ          (1<<3) /* Divide-by-zero */
 112#define FSR_OF          (1<<2) /* Overflow */
 113#define FSR_UF          (1<<1) /* Underflow */
 114#define FSR_DO          (1<<0) /* Denormalized operand error */
 115
 116/* Version reg.  */
 117/* Basic PVR mask */
 118#define PVR0_PVR_FULL_MASK              0x80000000
 119#define PVR0_USE_BARREL_MASK            0x40000000
 120#define PVR0_USE_DIV_MASK               0x20000000
 121#define PVR0_USE_HW_MUL_MASK            0x10000000
 122#define PVR0_USE_FPU_MASK               0x08000000
 123#define PVR0_USE_EXC_MASK               0x04000000
 124#define PVR0_USE_ICACHE_MASK            0x02000000
 125#define PVR0_USE_DCACHE_MASK            0x01000000
 126#define PVR0_USE_MMU_MASK               0x00800000
 127#define PVR0_USE_BTC                    0x00400000
 128#define PVR0_ENDI_MASK                  0x00200000
 129#define PVR0_FAULT                      0x00100000
 130#define PVR0_VERSION_MASK               0x0000FF00
 131#define PVR0_USER1_MASK                 0x000000FF
 132#define PVR0_SPROT_MASK                 0x00000001
 133
 134#define PVR0_VERSION_SHIFT              8
 135
 136/* User 2 PVR mask */
 137#define PVR1_USER2_MASK                 0xFFFFFFFF
 138
 139/* Configuration PVR masks */
 140#define PVR2_D_OPB_MASK                 0x80000000
 141#define PVR2_D_LMB_MASK                 0x40000000
 142#define PVR2_I_OPB_MASK                 0x20000000
 143#define PVR2_I_LMB_MASK                 0x10000000
 144#define PVR2_INTERRUPT_IS_EDGE_MASK     0x08000000
 145#define PVR2_EDGE_IS_POSITIVE_MASK      0x04000000
 146#define PVR2_D_PLB_MASK                 0x02000000      /* new */
 147#define PVR2_I_PLB_MASK                 0x01000000      /* new */
 148#define PVR2_INTERCONNECT               0x00800000      /* new */
 149#define PVR2_USE_EXTEND_FSL             0x00080000      /* new */
 150#define PVR2_USE_FSL_EXC                0x00040000      /* new */
 151#define PVR2_USE_MSR_INSTR              0x00020000
 152#define PVR2_USE_PCMP_INSTR             0x00010000
 153#define PVR2_AREA_OPTIMISED             0x00008000
 154#define PVR2_USE_BARREL_MASK            0x00004000
 155#define PVR2_USE_DIV_MASK               0x00002000
 156#define PVR2_USE_HW_MUL_MASK            0x00001000
 157#define PVR2_USE_FPU_MASK               0x00000800
 158#define PVR2_USE_MUL64_MASK             0x00000400
 159#define PVR2_USE_FPU2_MASK              0x00000200      /* new */
 160#define PVR2_USE_IPLBEXC                0x00000100
 161#define PVR2_USE_DPLBEXC                0x00000080
 162#define PVR2_OPCODE_0x0_ILL_MASK        0x00000040
 163#define PVR2_UNALIGNED_EXC_MASK         0x00000020
 164#define PVR2_ILL_OPCODE_EXC_MASK        0x00000010
 165#define PVR2_IOPB_BUS_EXC_MASK          0x00000008
 166#define PVR2_DOPB_BUS_EXC_MASK          0x00000004
 167#define PVR2_DIV_ZERO_EXC_MASK          0x00000002
 168#define PVR2_FPU_EXC_MASK               0x00000001
 169
 170/* Debug and exception PVR masks */
 171#define PVR3_DEBUG_ENABLED_MASK         0x80000000
 172#define PVR3_NUMBER_OF_PC_BRK_MASK      0x1E000000
 173#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
 174#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
 175#define PVR3_FSL_LINKS_MASK             0x00000380
 176
 177/* ICache config PVR masks */
 178#define PVR4_USE_ICACHE_MASK            0x80000000
 179#define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000
 180#define PVR4_ICACHE_USE_FSL_MASK        0x02000000
 181#define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000
 182#define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000
 183#define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000
 184
 185/* DCache config PVR masks */
 186#define PVR5_USE_DCACHE_MASK            0x80000000
 187#define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000
 188#define PVR5_DCACHE_USE_FSL_MASK        0x02000000
 189#define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000
 190#define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000
 191#define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000
 192#define PVR5_DCACHE_WRITEBACK_MASK      0x00004000
 193
 194/* ICache base address PVR mask */
 195#define PVR6_ICACHE_BASEADDR_MASK       0xFFFFFFFF
 196
 197/* ICache high address PVR mask */
 198#define PVR7_ICACHE_HIGHADDR_MASK       0xFFFFFFFF
 199
 200/* DCache base address PVR mask */
 201#define PVR8_DCACHE_BASEADDR_MASK       0xFFFFFFFF
 202
 203/* DCache high address PVR mask */
 204#define PVR9_DCACHE_HIGHADDR_MASK       0xFFFFFFFF
 205
 206/* Target family PVR mask */
 207#define PVR10_TARGET_FAMILY_MASK        0xFF000000
 208#define PVR10_ASIZE_SHIFT               18
 209
 210/* MMU descrtiption */
 211#define PVR11_USE_MMU                   0xC0000000
 212#define PVR11_MMU_ITLB_SIZE             0x38000000
 213#define PVR11_MMU_DTLB_SIZE             0x07000000
 214#define PVR11_MMU_TLB_ACCESS            0x00C00000
 215#define PVR11_MMU_ZONES                 0x003E0000
 216/* MSR Reset value PVR mask */
 217#define PVR11_MSR_RESET_VALUE_MASK      0x000007FF
 218
 219#define C_PVR_NONE                      0
 220#define C_PVR_BASIC                     1
 221#define C_PVR_FULL                      2
 222
 223/* CPU flags.  */
 224
 225/* Condition codes.  */
 226#define CC_GE  5
 227#define CC_GT  4
 228#define CC_LE  3
 229#define CC_LT  2
 230#define CC_NE  1
 231#define CC_EQ  0
 232
 233#define NB_MMU_MODES    3
 234#undef NB_MEM_ATTR
 235#define NB_MEM_ATTR     1
 236
 237#define STREAM_EXCEPTION (1 << 0)
 238#define STREAM_ATOMIC    (1 << 1)
 239#define STREAM_TEST      (1 << 2)
 240#define STREAM_CONTROL   (1 << 3)
 241#define STREAM_NONBLOCK  (1 << 4)
 242
 243struct CPUMBState {
 244    uint32_t debug;
 245    uint32_t btaken;
 246    uint32_t btarget;
 247    uint32_t bimm;
 248
 249    uint32_t imm;
 250    uint32_t regs[32];
 251    uint64_t sregs[14];
 252    float_status fp_status;
 253    /* Stack protectors. Yes, it's a hw feature.  */
 254    uint32_t slr, shr;
 255
 256    /* lwx/swx reserved address */
 257#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
 258    target_ulong res_addr;
 259    uint32_t res_val;
 260
 261    /* Internal flags.  */
 262#define IMM_FLAG        4
 263#define MSR_EE_FLAG     (1 << 8)
 264#define DRTI_FLAG       (1 << 16)
 265#define DRTE_FLAG       (1 << 17)
 266#define DRTB_FLAG       (1 << 18)
 267#define D_FLAG          (1 << 19)  /* Bit in ESR.  */
 268/* TB dependent CPUMBState.  */
 269#define IFLAGS_TB_MASK  (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
 270    uint32_t iflags;
 271    uint32_t wakeup;
 272
 273#if !defined(CONFIG_USER_ONLY)
 274    /* Unified MMU.  */
 275    struct microblaze_mmu mmu;
 276#endif
 277
 278    /* Fields up to this point are cleared by a CPU reset */
 279    struct {} end_reset_fields;
 280
 281    CPU_COMMON
 282
 283    /* These fields are preserved on reset.  */
 284
 285    struct {
 286        uint32_t regs[13];
 287    } pvr;
 288
 289    /* MicroBlaze does not have state that affects the memory attributes so
 290     * we end up only needing one instance.  */
 291    MemTxAttrs *memattr_p;
 292};
 293
 294/**
 295 * MicroBlazeCPU:
 296 * @env: #CPUMBState
 297 *
 298 * A MicroBlaze CPU.
 299 */
 300struct MicroBlazeCPU {
 301    /*< private >*/
 302    CPUState parent_obj;
 303
 304    /*< public >*/
 305    qemu_irq mb_sleep;
 306
 307    /* Microblaze Configuration Settings */
 308    struct {
 309        bool stackprot;
 310        uint32_t base_vectors;
 311        uint8_t addr_size;
 312        uint8_t use_fpu;
 313        uint8_t use_hw_mul;
 314        bool use_barrel;
 315        bool use_div;
 316        bool use_msr_instr;
 317        bool use_pcmp_instr;
 318        bool use_mmu;
 319        bool dcache_writeback;
 320        bool endi;
 321        char *version;
 322        uint8_t pvr;
 323    } cfg;
 324
 325    CPUMBState env;
 326};
 327
 328static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env)
 329{
 330    return container_of(env, MicroBlazeCPU, env);
 331}
 332
 333#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e))
 334
 335#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
 336
 337void mb_cpu_do_interrupt(CPUState *cs);
 338bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
 339void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 340                       int flags);
 341hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 342int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 343int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 344
 345void mb_tcg_init(void);
 346/* you can call this signal handler from your SIGBUS and SIGSEGV
 347   signal handlers to inform the virtual CPU of exceptions. non zero
 348   is returned if the signal was handled by the virtual CPU.  */
 349int cpu_mb_signal_handler(int host_signum, void *pinfo,
 350                          void *puc);
 351
 352/* FIXME: MB uses variable pages down to 1K but linux only uses 4k.  */
 353#define TARGET_PAGE_BITS 12
 354
 355#define TARGET_PHYS_ADDR_SPACE_BITS 64
 356#define TARGET_VIRT_ADDR_SPACE_BITS 64
 357
 358#define cpu_init(cpu_model) cpu_generic_init(TYPE_MICROBLAZE_CPU, cpu_model)
 359
 360#define cpu_signal_handler cpu_mb_signal_handler
 361
 362/* MMU modes definitions */
 363#define MMU_MODE0_SUFFIX _nommu
 364#define MMU_MODE1_SUFFIX _kernel
 365#define MMU_MODE2_SUFFIX _user
 366#define MMU_NOMMU_IDX   0
 367#define MMU_KERNEL_IDX  1
 368#define MMU_USER_IDX    2
 369/* See NB_MMU_MODES further up the file.  */
 370
 371static inline int cpu_mmu_index (CPUMBState *env, bool ifetch)
 372{
 373        /* Are we in nommu mode?.  */
 374        if (!(env->sregs[SR_MSR] & MSR_VM))
 375            return MMU_NOMMU_IDX;
 376
 377        if (env->sregs[SR_MSR] & MSR_UM)
 378            return MMU_USER_IDX;
 379        return MMU_KERNEL_IDX;
 380}
 381
 382int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 383                            int mmu_idx);
 384
 385#include "exec/cpu-all.h"
 386
 387static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
 388                                        target_ulong *cs_base, uint32_t *flags)
 389{
 390    *pc = env->sregs[SR_PC];
 391    *cs_base = 0;
 392    *flags = (env->iflags & IFLAGS_TB_MASK) |
 393                 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
 394}
 395
 396#if !defined(CONFIG_USER_ONLY)
 397void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 398                              bool is_write, bool is_exec, int is_asi,
 399                              unsigned size);
 400#endif
 401
 402#endif
 403