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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/mips/mips.h"
28#include "hw/mips/cpudevs.h"
29#include "hw/i386/pc.h"
30#include "hw/char/serial.h"
31#include "hw/isa/isa.h"
32#include "hw/block/fdc.h"
33#include "sysemu/sysemu.h"
34#include "sysemu/arch_init.h"
35#include "hw/boards.h"
36#include "net/net.h"
37#include "hw/scsi/esp.h"
38#include "hw/mips/bios.h"
39#include "hw/loader.h"
40#include "hw/timer/mc146818rtc.h"
41#include "hw/timer/i8254.h"
42#include "hw/audio/pcspk.h"
43#include "sysemu/block-backend.h"
44#include "hw/sysbus.h"
45#include "exec/address-spaces.h"
46#include "sysemu/qtest.h"
47#include "qemu/error-report.h"
48#include "qemu/help_option.h"
49
50enum jazz_model_e
51{
52 JAZZ_MAGNUM,
53 JAZZ_PICA61,
54};
55
56static void main_cpu_reset(void *opaque)
57{
58 MIPSCPU *cpu = opaque;
59
60 cpu_reset(CPU(cpu));
61}
62
63static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
64{
65 uint8_t val;
66 address_space_read(&address_space_memory, 0x90000071,
67 MEMTXATTRS_UNSPECIFIED, &val, 1);
68 return val;
69}
70
71static void rtc_write(void *opaque, hwaddr addr,
72 uint64_t val, unsigned size)
73{
74 uint8_t buf = val & 0xff;
75 address_space_write(&address_space_memory, 0x90000071,
76 MEMTXATTRS_UNSPECIFIED, &buf, 1);
77}
78
79static const MemoryRegionOps rtc_ops = {
80 .read = rtc_read,
81 .write = rtc_write,
82 .endianness = DEVICE_NATIVE_ENDIAN,
83};
84
85static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
86 unsigned size)
87{
88
89
90 return 0xff;
91}
92
93static void dma_dummy_write(void *opaque, hwaddr addr,
94 uint64_t val, unsigned size)
95{
96
97
98}
99
100static const MemoryRegionOps dma_dummy_ops = {
101 .read = dma_dummy_read,
102 .write = dma_dummy_write,
103 .endianness = DEVICE_NATIVE_ENDIAN,
104};
105
106#define MAGNUM_BIOS_SIZE_MAX 0x7e000
107#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
108
109static CPUUnassignedAccess real_do_unassigned_access;
110static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr,
111 bool is_write, bool is_exec,
112 int opaque, unsigned size)
113{
114 if (!is_exec) {
115
116 return;
117 }
118 (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size);
119}
120
121static void mips_jazz_init(MachineState *machine,
122 enum jazz_model_e jazz_model)
123{
124 MemoryRegion *address_space = get_system_memory();
125 char *filename;
126 int bios_size, n;
127 MIPSCPU *cpu;
128 CPUClass *cc;
129 CPUMIPSState *env;
130 qemu_irq *i8259;
131 rc4030_dma *dmas;
132 IOMMUMemoryRegion *rc4030_dma_mr;
133 MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
134 MemoryRegion *isa_io = g_new(MemoryRegion, 1);
135 MemoryRegion *rtc = g_new(MemoryRegion, 1);
136 MemoryRegion *i8042 = g_new(MemoryRegion, 1);
137 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
138 NICInfo *nd;
139 DeviceState *dev, *rc4030;
140 SysBusDevice *sysbus;
141 ISABus *isa_bus;
142 ISADevice *pit;
143 DriveInfo *fds[MAX_FD];
144 qemu_irq esp_reset, dma_enable;
145 MemoryRegion *ram = g_new(MemoryRegion, 1);
146 MemoryRegion *bios = g_new(MemoryRegion, 1);
147 MemoryRegion *bios2 = g_new(MemoryRegion, 1);
148
149
150 cpu = MIPS_CPU(cpu_create(machine->cpu_type));
151 env = &cpu->env;
152 qemu_register_reset(main_cpu_reset, cpu);
153
154
155
156
157
158
159
160
161 cc = CPU_GET_CLASS(cpu);
162 real_do_unassigned_access = cc->do_unassigned_access;
163 cc->do_unassigned_access = mips_jazz_do_unassigned_access;
164
165
166 memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
167 machine->ram_size);
168 memory_region_add_subregion(address_space, 0, ram);
169
170 memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
171 &error_fatal);
172 memory_region_set_readonly(bios, true);
173 memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
174 0, MAGNUM_BIOS_SIZE);
175 memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
176 memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
177
178
179 if (bios_name == NULL)
180 bios_name = BIOS_FILENAME;
181 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
182 if (filename) {
183 bios_size = load_image_targphys(filename, 0xfff00000LL,
184 MAGNUM_BIOS_SIZE);
185 g_free(filename);
186 } else {
187 bios_size = -1;
188 }
189 if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
190 error_report("Could not load MIPS bios '%s'", bios_name);
191 exit(1);
192 }
193
194
195 cpu_mips_irq_init_cpu(cpu);
196 cpu_mips_clock_init(cpu);
197
198
199 rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
200 sysbus = SYS_BUS_DEVICE(rc4030);
201 sysbus_connect_irq(sysbus, 0, env->irq[6]);
202 sysbus_connect_irq(sysbus, 1, env->irq[3]);
203 memory_region_add_subregion(address_space, 0x80000000,
204 sysbus_mmio_get_region(sysbus, 0));
205 memory_region_add_subregion(address_space, 0xf0000000,
206 sysbus_mmio_get_region(sysbus, 1));
207 memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
208 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
209
210
211 memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
212 memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
213 memory_region_add_subregion(address_space, 0x90000000, isa_io);
214 memory_region_add_subregion(address_space, 0x91000000, isa_mem);
215 isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
216
217
218 i8259 = i8259_init(isa_bus, env->irq[4]);
219 isa_bus_irqs(isa_bus, i8259);
220 DMA_init(isa_bus, 0);
221 pit = pit_init(isa_bus, 0x40, 0, NULL);
222 pcspk_init(isa_bus, pit);
223
224
225 switch (jazz_model) {
226 case JAZZ_MAGNUM:
227 dev = qdev_create(NULL, "sysbus-g364");
228 qdev_init_nofail(dev);
229 sysbus = SYS_BUS_DEVICE(dev);
230 sysbus_mmio_map(sysbus, 0, 0x60080000);
231 sysbus_mmio_map(sysbus, 1, 0x40000000);
232 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
233 {
234
235 MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
236 memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
237 &error_fatal);
238 memory_region_set_readonly(rom_mr, true);
239 uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
240 memory_region_add_subregion(address_space, 0x60000000, rom_mr);
241 rom[0] = 0x10;
242 }
243 break;
244 case JAZZ_PICA61:
245 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
246 break;
247 default:
248 break;
249 }
250
251
252 for (n = 0; n < nb_nics; n++) {
253 nd = &nd_table[n];
254 if (!nd->model)
255 nd->model = g_strdup("dp83932");
256 if (strcmp(nd->model, "dp83932") == 0) {
257 qemu_check_nic_model(nd, "dp83932");
258
259 dev = qdev_create(NULL, "dp8393x");
260 qdev_set_nic_properties(dev, nd);
261 qdev_prop_set_uint8(dev, "it_shift", 2);
262 qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
263 qdev_init_nofail(dev);
264 sysbus = SYS_BUS_DEVICE(dev);
265 sysbus_mmio_map(sysbus, 0, 0x80001000);
266 sysbus_mmio_map(sysbus, 1, 0x8000b000);
267 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
268 break;
269 } else if (is_help_option(nd->model)) {
270 fprintf(stderr, "qemu: Supported NICs: dp83932\n");
271 exit(1);
272 } else {
273 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
274 exit(1);
275 }
276 }
277
278
279 esp_init(0x80002000, 0,
280 rc4030_dma_read, rc4030_dma_write, dmas[0],
281 qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
282
283
284 for (n = 0; n < MAX_FD; n++) {
285 fds[n] = drive_get(IF_FLOPPY, 0, n);
286 }
287
288 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
289
290
291 rtc_init(isa_bus, 1980, NULL);
292 memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
293 memory_region_add_subregion(address_space, 0x80004000, rtc);
294
295
296 i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
297 i8042, 0x1000, 0x1);
298 memory_region_add_subregion(address_space, 0x80005000, i8042);
299
300
301 if (serial_hds[0]) {
302 serial_mm_init(address_space, 0x80006000, 0,
303 qdev_get_gpio_in(rc4030, 8), 8000000/16,
304 serial_hds[0], DEVICE_NATIVE_ENDIAN);
305 }
306 if (serial_hds[1]) {
307 serial_mm_init(address_space, 0x80007000, 0,
308 qdev_get_gpio_in(rc4030, 9), 8000000/16,
309 serial_hds[1], DEVICE_NATIVE_ENDIAN);
310 }
311
312
313 if (parallel_hds[0])
314 parallel_mm_init(address_space, 0x80008000, 0,
315 qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
316
317
318
319
320 dev = qdev_create(NULL, "ds1225y");
321 qdev_init_nofail(dev);
322 sysbus = SYS_BUS_DEVICE(dev);
323 sysbus_mmio_map(sysbus, 0, 0x80009000);
324
325
326 sysbus_create_simple("jazz-led", 0x8000f000, NULL);
327}
328
329static
330void mips_magnum_init(MachineState *machine)
331{
332 mips_jazz_init(machine, JAZZ_MAGNUM);
333}
334
335static
336void mips_pica61_init(MachineState *machine)
337{
338 mips_jazz_init(machine, JAZZ_PICA61);
339}
340
341static void mips_magnum_class_init(ObjectClass *oc, void *data)
342{
343 MachineClass *mc = MACHINE_CLASS(oc);
344
345 mc->desc = "MIPS Magnum";
346 mc->init = mips_magnum_init;
347 mc->block_default_type = IF_SCSI;
348 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
349}
350
351static const TypeInfo mips_magnum_type = {
352 .name = MACHINE_TYPE_NAME("magnum"),
353 .parent = TYPE_MACHINE,
354 .class_init = mips_magnum_class_init,
355};
356
357static void mips_pica61_class_init(ObjectClass *oc, void *data)
358{
359 MachineClass *mc = MACHINE_CLASS(oc);
360
361 mc->desc = "Acer Pica 61";
362 mc->init = mips_pica61_init;
363 mc->block_default_type = IF_SCSI;
364 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
365}
366
367static const TypeInfo mips_pica61_type = {
368 .name = MACHINE_TYPE_NAME("pica61"),
369 .parent = TYPE_MACHINE,
370 .class_init = mips_pica61_class_init,
371};
372
373static void mips_jazz_machine_init(void)
374{
375 type_register_static(&mips_magnum_type);
376 type_register_static(&mips_pica61_type);
377}
378
379type_init(mips_jazz_machine_init)
380
