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26#ifndef ARM_TCG_TARGET_H
27#define ARM_TCG_TARGET_H
28
29
30#ifndef __ARM_ARCH
31# if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
32 || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
33 || defined(__ARM_ARCH_7EM__)
34# define __ARM_ARCH 7
35# elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
36 || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \
37 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__)
38# define __ARM_ARCH 6
39# elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) \
40 || defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \
41 || defined(__ARM_ARCH_5TEJ__)
42# define __ARM_ARCH 5
43# else
44# define __ARM_ARCH 4
45# endif
46#endif
47
48extern int arm_arch;
49
50#if defined(__ARM_ARCH_5T__) \
51 || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__)
52# define use_armv5t_instructions 1
53#else
54# define use_armv5t_instructions use_armv6_instructions
55#endif
56
57#define use_armv6_instructions (__ARM_ARCH >= 6 || arm_arch >= 6)
58#define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7)
59
60#undef TCG_TARGET_STACK_GROWSUP
61#define TCG_TARGET_INSN_UNIT_SIZE 4
62#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
63
64typedef enum {
65 TCG_REG_R0 = 0,
66 TCG_REG_R1,
67 TCG_REG_R2,
68 TCG_REG_R3,
69 TCG_REG_R4,
70 TCG_REG_R5,
71 TCG_REG_R6,
72 TCG_REG_R7,
73 TCG_REG_R8,
74 TCG_REG_R9,
75 TCG_REG_R10,
76 TCG_REG_R11,
77 TCG_REG_R12,
78 TCG_REG_R13,
79 TCG_REG_R14,
80 TCG_REG_PC,
81} TCGReg;
82
83#define TCG_TARGET_NB_REGS 16
84
85#ifdef __ARM_ARCH_EXT_IDIV__
86#define use_idiv_instructions 1
87#else
88extern bool use_idiv_instructions;
89#endif
90
91
92
93#define TCG_REG_CALL_STACK TCG_REG_R13
94#define TCG_TARGET_STACK_ALIGN 8
95#define TCG_TARGET_CALL_ALIGN_ARGS 1
96#define TCG_TARGET_CALL_STACK_OFFSET 0
97
98
99#define TCG_TARGET_HAS_ext8s_i32 1
100#define TCG_TARGET_HAS_ext16s_i32 1
101#define TCG_TARGET_HAS_ext8u_i32 0
102#define TCG_TARGET_HAS_ext16u_i32 1
103#define TCG_TARGET_HAS_bswap16_i32 1
104#define TCG_TARGET_HAS_bswap32_i32 1
105#define TCG_TARGET_HAS_not_i32 1
106#define TCG_TARGET_HAS_neg_i32 1
107#define TCG_TARGET_HAS_rot_i32 1
108#define TCG_TARGET_HAS_andc_i32 1
109#define TCG_TARGET_HAS_orc_i32 0
110#define TCG_TARGET_HAS_eqv_i32 0
111#define TCG_TARGET_HAS_nand_i32 0
112#define TCG_TARGET_HAS_nor_i32 0
113#define TCG_TARGET_HAS_clz_i32 use_armv5t_instructions
114#define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions
115#define TCG_TARGET_HAS_ctpop_i32 0
116#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
117#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
118#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
119#define TCG_TARGET_HAS_movcond_i32 1
120#define TCG_TARGET_HAS_mulu2_i32 1
121#define TCG_TARGET_HAS_muls2_i32 1
122#define TCG_TARGET_HAS_muluh_i32 0
123#define TCG_TARGET_HAS_mulsh_i32 0
124#define TCG_TARGET_HAS_div_i32 use_idiv_instructions
125#define TCG_TARGET_HAS_rem_i32 0
126#define TCG_TARGET_HAS_goto_ptr 1
127#define TCG_TARGET_HAS_direct_jump 0
128
129enum {
130 TCG_AREG0 = TCG_REG_R6,
131};
132
133#define TCG_TARGET_DEFAULT_MO (0)
134
135static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
136{
137 __builtin___clear_cache((char *) start, (char *) stop);
138}
139
140
141void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
142
143#ifdef CONFIG_SOFTMMU
144#define TCG_TARGET_NEED_LDST_LABELS
145#endif
146#define TCG_TARGET_NEED_POOL_LABELS
147
148#endif
149