LXR qemu/include/exec/memattrs.h

   1/*
   2 * Memory transaction attributes
   3 *
   4 * Copyright (c) 2015 Linaro Limited.
   5 *
   6 * Authors:
   7 *  Peter Maydell <peter.maydell@linaro.org>
   8 *
   9 * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10 * See the COPYING file in the top-level directory.
  11 *
  12 */
  13
  14#ifndef MEMATTRS_H
  15#define MEMATTRS_H
  16
  17#include "qom/object.h"
  18#include "qapi/visitor-impl.h"
  19
  20/* Every memory transaction has associated with it a set of
  21 * attributes. Some of these are generic (such as the ID of
  22 * the bus master); some are specific to a particular kind of
  23 * bus (such as the ARM Secure/NonSecure bit). We define them
  24 * all as non-overlapping bitfields in a single struct to avoid
  25 * confusion if different parts of QEMU used the same bit for
  26 * different semantics.
  27 */
  28typedef struct MemTxAttrs {
  29    Object parent_obj;
  30    /* Bus masters which don't specify any attributes will get this
  31     * (via the MEMTXATTRS_UNSPECIFIED constant), so that we can
  32     * distinguish "all attributes deliberately clear" from
  33     * "didn't specify" if necessary.
  34     */
  35    unsigned int unspecified:1;
  36    /* ARM/AMBA: TrustZone Secure access
  37     * x86: System Management Mode access
  38     */
  39    unsigned int secure:1;
  40    /* Memory access is usermode (unprivileged) */
  41    unsigned int user:1;
  42    /* Memory access request from the debugger */
  43    unsigned int debug:1;
  44    /* Requester ID (for MSI for example) */
  45    unsigned int requester_id:16;
  46} MemTxAttrs;
  47
  48/* Bus masters which don't specify any attributes will get this,
  49 * which has all attribute bits clear except the topmost one
  50 * (so that we can distinguish "all attributes deliberately clear"
  51 * from "didn't specify" if necessary).
  52 */
  53#define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified = 1 })
  54
  55/* New-style MMIO accessors can indicate that the transaction failed.
  56 * A zero (MEMTX_OK) response means success; anything else is a failure
  57 * of some kind. The memory subsystem will bitwise-OR together results
  58 * if it is synthesizing an operation from multiple smaller accesses.
  59 */
  60#define MEMTX_OK 0
  61#define MEMTX_ERROR             (1U << 0) /* device returned an error */
  62#define MEMTX_DECODE_ERROR      (1U << 1) /* nothing at that address */
  63typedef uint32_t MemTxResult;
  64
  65void cpu_set_mr(Object *obj, Visitor *v, void *opaque,
  66                const char *name, Error **errp);
  67
  68#endif
  69