1/* 2 * ARM GIC support 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21#ifndef HW_ARM_GIC_COMMON_H 22#define HW_ARM_GIC_COMMON_H 23 24#include "hw/sysbus.h" 25 26/* Maximum number of possible interrupts, determined by the GIC architecture */ 27#define GIC_MAXIRQ 1020 28/* First 32 are private to each CPU (SGIs and PPIs). */ 29#define GIC_INTERNAL 32 30#define GIC_NR_SGIS 16 31/* Maximum number of possible CPU interfaces, determined by GIC architecture */ 32/* Include a vCPU interface per CPU. */ 33#define GIC_N_REALCPU 8 34#define GIC_NCPU (GIC_N_REALCPU * 2) 35 36#define MAX_NR_GROUP_PRIO 256 37#define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32) 38#define GICV_NR_LR 4 39 40typedef struct gic_irq_state { 41 /* The enable bits are only banked for per-cpu interrupts. */ 42 uint8_t enabled; 43 uint8_t pending; 44 uint8_t active; 45 uint8_t level; 46 bool model; /* 0 = N:N, 1 = 1:N */ 47 bool edge_trigger; /* true: edge-triggered, false: level-triggered */ 48 bool group; 49} gic_irq_state; 50 51typedef struct GICState { 52 /*< private >*/ 53 SysBusDevice parent_obj; 54 /*< public >*/ 55 56 qemu_irq parent_irq[GIC_NCPU]; 57 qemu_irq parent_fiq[GIC_NCPU]; 58 qemu_irq parent_virq[GIC_NCPU]; 59 qemu_irq parent_vfiq[GIC_NCPU]; 60 qemu_irq maint[GIC_N_REALCPU]; 61 62 bool enabled; 63 bool enabled_grp0; 64 65 struct { 66 bool enable_grp[2]; 67 bool ack_ctl; 68 bool fiq_en; 69 bool eoirmode; 70 bool eoirmode_ns; 71 } gicc_ctrl[GIC_NCPU]; 72 73 uint32_t ctrl[GIC_NCPU]; 74 75 /* GICD_CTLR; for a GIC with the security extensions the NS banked version 76 * of this register is just an alias of bit 1 of the S banked version. 77 */ 78 uint32_t ctlr; 79 /* GICC_CTLR; again, the NS banked version is just aliases of bits of 80 * the S banked register, so our state only needs to store the S version. 81 */ 82 uint32_t cpu_ctlr[GIC_NCPU]; 83 84 gic_irq_state irq_state[GIC_MAXIRQ]; 85 uint8_t irq_target[GIC_MAXIRQ]; 86 uint8_t priority1[GIC_INTERNAL][GIC_NCPU]; 87 uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL]; 88 uint16_t last_active[GIC_MAXIRQ][GIC_NCPU]; 89 /* For each SGI on the target CPU, we store 8 bits 90 * indicating which source CPUs have made this SGI 91 * pending on the target CPU. These correspond to 92 * the bytes in the GIC_SPENDSGIR* registers as 93 * read by the target CPU. 94 */ 95 uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU]; 96 97 uint16_t priority_mask[GIC_NCPU]; 98 uint16_t running_irq[GIC_NCPU]; 99 uint16_t running_priority[GIC_NCPU]; 100 uint16_t current_pending[GIC_NCPU]; 101 102 /* We present the GICv2 without security extensions to a guest and 103 * therefore the guest can configure the GICC_CTLR to configure group 1 104 * binary point in the abpr. 105 */ 106 uint8_t bpr[GIC_NCPU]; 107 uint8_t abpr[GIC_NCPU]; 108 109 /* The Interface Identification Register. 110 * This is implementation defined 111 */ 112 uint32_t c_iidr; 113 114 /* The APR is implementation defined, so we choose a layout identical to 115 * the KVM ABI layout for QEMU's implementation of the gic: 116 * If an interrupt for preemption level X is active, then 117 * APRn[X mod 32] == 0b1, where n = X / 32 118 * otherwise the bit is clear. 119 * 120 * TODO: rewrite the interrupt acknowlege/complete routines to use 121 * the APR registers to track the necessary information to update 122 * s->running_priority[] on interrupt completion (ie completely remove 123 * last_active[][] and running_irq[]). This will be necessary if we ever 124 * want to support TCG<->KVM migration, or TCG guests which can 125 * do power management involving powering down and restarting 126 * the GIC. 127 */ 128 /* We don't use all of this space but we allocate all of it. */ 129 uint32_t apr[GIC_NR_APRS][GIC_NCPU]; 130 uint32_t apr_guard[32]; 131 132 struct { 133 uint32_t hcr[GIC_N_REALCPU]; 134 uint32_t vtr[GIC_N_REALCPU]; 135 uint32_t misr[GIC_N_REALCPU]; 136 uint64_t eisr[GIC_N_REALCPU]; 137 uint64_t elrsr[GIC_N_REALCPU]; 138 uint32_t apr[GIC_N_REALCPU]; 139 uint32_t lr[GIC_N_REALCPU][GICV_NR_LR]; 140 141 uint32_t pending_prio[GIC_N_REALCPU]; 142 uint8_t pending_lrn[GIC_N_REALCPU]; 143 } gich; 144 145 uint32_t num_cpu; 146 147 MemoryRegion iomem; /* Distributor */ 148 /* This is just so we can have an opaque pointer which identifies 149 * both this GIC and which CPU interface we should be accessing. 150 */ 151 struct GICState *backref[GIC_NCPU]; 152 MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ 153 MemoryRegion hypiomem[GIC_NCPU + 1]; /* Virtual control interfaces */ 154 MemoryRegion vcpuiomem; /* Virtual CPU interface */ 155 uint32_t map_stride; 156 uint32_t num_irq; 157 uint32_t revision; 158 bool security_extn; 159 bool irq_reset_nonsecure; 160 bool disable_linux_gic_init; 161 int dev_fd; /* kvm device fd if backed by kvm vgic support */ 162} GICState; 163 164#define TYPE_ARM_GIC_COMMON "arm_gic_common" 165#define ARM_GIC_COMMON(obj) \ 166 OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON) 167#define ARM_GIC_COMMON_CLASS(klass) \ 168 OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON) 169#define ARM_GIC_COMMON_GET_CLASS(obj) \ 170 OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON) 171 172typedef struct ARMGICCommonClass { 173 /*< private >*/ 174 SysBusDeviceClass parent_class; 175 /*< public >*/ 176 177 void (*pre_save)(GICState *s); 178 void (*post_load)(GICState *s); 179} ARMGICCommonClass; 180 181void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler, 182 const MemoryRegionOps *ops); 183 184#endif 185