LXR qemu/target/xtensa/overlay

   1/*
   2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3 * All rights reserved.
   4 *
   5 * Redistribution and use in source and binary forms, with or without
   6 * modification, are permitted provided that the following conditions are met:
   7 *     * Redistributions of source code must retain the above copyright
   8 *       notice, this list of conditions and the following disclaimer.
   9 *     * Redistributions in binary form must reproduce the above copyright
  10 *       notice, this list of conditions and the following disclaimer in the
  11 *       documentation and/or other materials provided with the distribution.
  12 *     * Neither the name of the Open Source and Linux Lab nor the
  13 *       names of its contributors may be used to endorse or promote products
  14 *       derived from this software without specific prior written permission.
  15 *
  16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 */
  27
  28#define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
  29        a1, a2, a3, a4, a5, a6) \
  30    { .targno = (no), .type = (typ), .group = (grp), .size = (sz) },
  31#define XTREG_END { .targno = -1 },
  32
  33#ifndef XCHAL_HAVE_DEPBITS
  34#define XCHAL_HAVE_DEPBITS 0
  35#endif
  36
  37#ifndef XCHAL_HAVE_DIV32
  38#define XCHAL_HAVE_DIV32 0
  39#endif
  40
  41#ifndef XCHAL_UNALIGNED_LOAD_HW
  42#define XCHAL_UNALIGNED_LOAD_HW 0
  43#endif
  44
  45#ifndef XCHAL_HAVE_VECBASE
  46#define XCHAL_HAVE_VECBASE 0
  47#define XCHAL_VECBASE_RESET_VADDR 0
  48#endif
  49
  50#ifndef XCHAL_RESET_VECTOR0_VADDR
  51#define XCHAL_RESET_VECTOR0_VADDR XCHAL_RESET_VECTOR_VADDR
  52#endif
  53
  54#ifndef XCHAL_RESET_VECTOR1_VADDR
  55#define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR
  56#endif
  57
  58#ifndef XCHAL_HW_MIN_VERSION
  59#define XCHAL_HW_MIN_VERSION 0
  60#endif
  61
  62#ifndef XCHAL_LOOP_BUFFER_SIZE
  63#define XCHAL_LOOP_BUFFER_SIZE 0
  64#endif
  65
  66#ifndef XCHAL_HAVE_EXTERN_REGS
  67#define XCHAL_HAVE_EXTERN_REGS 0
  68#endif
  69
  70#define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
  71
  72#define XTENSA_OPTIONS ( \
  73    XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
  74    XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
  75    XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
  76    XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
  77    XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
  78    XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
  79    XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
  80    XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
  81    XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
  82    XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
  83    XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
  84    XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
  85    XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
  86    XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
  87    XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
  88    XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
  89    XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
  90    XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
  91        XTENSA_OPTION_ATOMCTL) | \
  92    XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
  93    /* Interrupts and exceptions */ \
  94    XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
  95    XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
  96    XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
  97        XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
  98    XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
  99    XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
 100        XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
 101    XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
 102    /* Local memory, TODO */ \
 103    XCHAL_OPTION(XCHAL_ICACHE_SIZE, XTENSA_OPTION_ICACHE) | \
 104    XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
 105            XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
 106    XCHAL_OPTION(XCHAL_DCACHE_SIZE, XTENSA_OPTION_DCACHE) | \
 107    XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
 108            XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
 109    XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
 110    /* Memory protection and translation */ \
 111    XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
 112            XTENSA_OPTION_REGION_PROTECTION) | \
 113    XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
 114            XTENSA_OPTION_REGION_TRANSLATION) | \
 115    XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
 116    XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
 117    /* Other, TODO */ \
 118    XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
 119    XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\
 120    XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \
 121    XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \
 122    XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID) | \
 123    XCHAL_OPTION(XCHAL_HAVE_EXTERN_REGS, XTENSA_OPTION_EXTERN_REGS))
 124
 125#ifndef XCHAL_WINDOW_OF4_VECOFS
 126#define XCHAL_WINDOW_OF4_VECOFS         0x00000000
 127#define XCHAL_WINDOW_UF4_VECOFS         0x00000040
 128#define XCHAL_WINDOW_OF8_VECOFS         0x00000080
 129#define XCHAL_WINDOW_UF8_VECOFS         0x000000C0
 130#define XCHAL_WINDOW_OF12_VECOFS        0x00000100
 131#define XCHAL_WINDOW_UF12_VECOFS        0x00000140
 132#endif
 133
 134#if XCHAL_HAVE_WINDOWED
 135#define WINDOW_VECTORS \
 136   [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
 137       XCHAL_WINDOW_VECTORS_VADDR, \
 138   [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
 139       XCHAL_WINDOW_VECTORS_VADDR, \
 140   [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
 141       XCHAL_WINDOW_VECTORS_VADDR, \
 142   [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
 143       XCHAL_WINDOW_VECTORS_VADDR, \
 144   [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
 145       XCHAL_WINDOW_VECTORS_VADDR, \
 146   [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
 147       XCHAL_WINDOW_VECTORS_VADDR,
 148#else
 149#define WINDOW_VECTORS
 150#endif
 151
 152#define EXCEPTION_VECTORS { \
 153        [EXC_RESET0] = XCHAL_RESET_VECTOR0_VADDR, \
 154        [EXC_RESET1] = XCHAL_RESET_VECTOR1_VADDR, \
 155        WINDOW_VECTORS \
 156        [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
 157        [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
 158        [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
 159        [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
 160    }
 161
 162#define INTERRUPT_VECTORS { \
 163        0, \
 164        0, \
 165        XCHAL_INTLEVEL2_VECTOR_VADDR, \
 166        XCHAL_INTLEVEL3_VECTOR_VADDR, \
 167        XCHAL_INTLEVEL4_VECTOR_VADDR, \
 168        XCHAL_INTLEVEL5_VECTOR_VADDR, \
 169        XCHAL_INTLEVEL6_VECTOR_VADDR, \
 170        XCHAL_INTLEVEL7_VECTOR_VADDR, \
 171    }
 172
 173#define LEVEL_MASKS { \
 174        [1] = XCHAL_INTLEVEL1_MASK, \
 175        [2] = XCHAL_INTLEVEL2_MASK, \
 176        [3] = XCHAL_INTLEVEL3_MASK, \
 177        [4] = XCHAL_INTLEVEL4_MASK, \
 178        [5] = XCHAL_INTLEVEL5_MASK, \
 179        [6] = XCHAL_INTLEVEL6_MASK, \
 180        [7] = XCHAL_INTLEVEL7_MASK, \
 181    }
 182
 183#define INTTYPE_MASKS { \
 184        [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
 185        [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
 186        [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
 187    }
 188
 189#define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
 190#define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
 191#define XTHAL_INTTYPE_NMI INTTYPE_NMI
 192#define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
 193#define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
 194#define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
 195#define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
 196#define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
 197#define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING
 198
 199
 200#define INTERRUPT(i) { \
 201        .level = XCHAL_INT ## i ## _LEVEL, \
 202        .inttype = XCHAL_INT ## i ## _TYPE, \
 203    }
 204
 205#define INTERRUPTS { \
 206        [0] = INTERRUPT(0), \
 207        [1] = INTERRUPT(1), \
 208        [2] = INTERRUPT(2), \
 209        [3] = INTERRUPT(3), \
 210        [4] = INTERRUPT(4), \
 211        [5] = INTERRUPT(5), \
 212        [6] = INTERRUPT(6), \
 213        [7] = INTERRUPT(7), \
 214        [8] = INTERRUPT(8), \
 215        [9] = INTERRUPT(9), \
 216        [10] = INTERRUPT(10), \
 217        [11] = INTERRUPT(11), \
 218        [12] = INTERRUPT(12), \
 219        [13] = INTERRUPT(13), \
 220        [14] = INTERRUPT(14), \
 221        [15] = INTERRUPT(15), \
 222        [16] = INTERRUPT(16), \
 223        [17] = INTERRUPT(17), \
 224        [18] = INTERRUPT(18), \
 225        [19] = INTERRUPT(19), \
 226        [20] = INTERRUPT(20), \
 227        [21] = INTERRUPT(21), \
 228        [22] = INTERRUPT(22), \
 229        [23] = INTERRUPT(23), \
 230        [24] = INTERRUPT(24), \
 231        [25] = INTERRUPT(25), \
 232        [26] = INTERRUPT(26), \
 233        [27] = INTERRUPT(27), \
 234        [28] = INTERRUPT(28), \
 235        [29] = INTERRUPT(29), \
 236        [30] = INTERRUPT(30), \
 237        [31] = INTERRUPT(31), \
 238    }
 239
 240#define TIMERINTS { \
 241        [0] = XCHAL_TIMER0_INTERRUPT, \
 242        [1] = XCHAL_TIMER1_INTERRUPT, \
 243        [2] = XCHAL_TIMER2_INTERRUPT, \
 244    }
 245
 246#define EXTINTS { \
 247        [0] = XCHAL_EXTINT0_NUM, \
 248        [1] = XCHAL_EXTINT1_NUM, \
 249        [2] = XCHAL_EXTINT2_NUM, \
 250        [3] = XCHAL_EXTINT3_NUM, \
 251        [4] = XCHAL_EXTINT4_NUM, \
 252        [5] = XCHAL_EXTINT5_NUM, \
 253        [6] = XCHAL_EXTINT6_NUM, \
 254        [7] = XCHAL_EXTINT7_NUM, \
 255        [8] = XCHAL_EXTINT8_NUM, \
 256        [9] = XCHAL_EXTINT9_NUM, \
 257        [10] = XCHAL_EXTINT10_NUM, \
 258        [11] = XCHAL_EXTINT11_NUM, \
 259        [12] = XCHAL_EXTINT12_NUM, \
 260        [13] = XCHAL_EXTINT13_NUM, \
 261        [14] = XCHAL_EXTINT14_NUM, \
 262        [15] = XCHAL_EXTINT15_NUM, \
 263        [16] = XCHAL_EXTINT16_NUM, \
 264        [17] = XCHAL_EXTINT17_NUM, \
 265        [18] = XCHAL_EXTINT18_NUM, \
 266        [19] = XCHAL_EXTINT19_NUM, \
 267        [20] = XCHAL_EXTINT20_NUM, \
 268        [21] = XCHAL_EXTINT21_NUM, \
 269        [22] = XCHAL_EXTINT22_NUM, \
 270        [23] = XCHAL_EXTINT23_NUM, \
 271        [24] = XCHAL_EXTINT24_NUM, \
 272        [25] = XCHAL_EXTINT25_NUM, \
 273        [26] = XCHAL_EXTINT26_NUM, \
 274        [27] = XCHAL_EXTINT27_NUM, \
 275        [28] = XCHAL_EXTINT28_NUM, \
 276        [29] = XCHAL_EXTINT29_NUM, \
 277        [30] = XCHAL_EXTINT30_NUM, \
 278        [31] = XCHAL_EXTINT31_NUM, \
 279    }
 280
 281#define EXCEPTIONS_SECTION \
 282    .excm_level = XCHAL_EXCM_LEVEL, \
 283    .vecbase = XCHAL_VECBASE_RESET_VADDR, \
 284    .exception_vector = EXCEPTION_VECTORS
 285
 286#define INTERRUPTS_SECTION \
 287    .ninterrupt = XCHAL_NUM_INTERRUPTS, \
 288    .nlevel = XCHAL_NUM_INTLEVELS, \
 289    .interrupt_vector = INTERRUPT_VECTORS, \
 290    .level_mask = LEVEL_MASKS, \
 291    .inttype_mask = INTTYPE_MASKS, \
 292    .interrupt = INTERRUPTS, \
 293    .nccompare = XCHAL_NUM_TIMERS, \
 294    .timerint = TIMERINTS, \
 295    .nextint = XCHAL_NUM_EXTINTERRUPTS, \
 296    .extint = EXTINTS
 297
 298#if XCHAL_HAVE_PTP_MMU
 299
 300#define TLB_TEMPLATE(ways, refill_way_size, way56) { \
 301        .nways = ways, \
 302        .way_size = { \
 303            (refill_way_size), (refill_way_size), \
 304            (refill_way_size), (refill_way_size), \
 305            4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
 306        }, \
 307        .varway56 = (way56), \
 308        .nrefillentries = (refill_way_size) * 4, \
 309    }
 310
 311#define ITLB(varway56) \
 312    TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
 313
 314#define DTLB(varway56) \
 315    TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
 316
 317#define TLB_SECTION \
 318    .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
 319    .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
 320
 321#ifndef XCHAL_SYSROM0_PADDR
 322#define XCHAL_SYSROM0_PADDR 0xfe000000
 323#define XCHAL_SYSROM0_SIZE  0x02000000
 324#endif
 325
 326#ifndef XCHAL_SYSRAM0_PADDR
 327#define XCHAL_SYSRAM0_PADDR 0x00000000
 328#define XCHAL_SYSRAM0_SIZE  0x08000000
 329#endif
 330
 331#elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
 332
 333#define TLB_TEMPLATE { \
 334        .nways = 1, \
 335        .way_size = { \
 336            8, \
 337        } \
 338    }
 339
 340#define TLB_SECTION \
 341    .itlb = TLB_TEMPLATE, \
 342    .dtlb = TLB_TEMPLATE
 343
 344#ifndef XCHAL_SYSROM0_PADDR
 345#define XCHAL_SYSROM0_PADDR 0x60000000
 346#define XCHAL_SYSROM0_SIZE  0x04000000
 347#endif
 348
 349#ifndef XCHAL_SYSRAM0_PADDR
 350#define XCHAL_SYSRAM0_PADDR 0x50000000
 351#define XCHAL_SYSRAM0_SIZE  0x04000000
 352#endif
 353
 354#else
 355
 356#ifndef XCHAL_SYSROM0_PADDR
 357#define XCHAL_SYSROM0_PADDR 0x60000000
 358#define XCHAL_SYSROM0_SIZE  0x04000000
 359#endif
 360
 361#ifndef XCHAL_SYSRAM0_PADDR
 362#define XCHAL_SYSRAM0_PADDR 0x50000000
 363#define XCHAL_SYSRAM0_SIZE  0x04000000
 364#endif
 365
 366#endif
 367
 368#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
 369#define REGISTER_CORE(core) \
 370    static void __attribute__((constructor)) register_core(void) \
 371    { \
 372        static XtensaConfigList node = { \
 373            .config = &core, \
 374        }; \
 375        xtensa_finalize_config(&core); \
 376        xtensa_register_core(&node); \
 377    }
 378#else
 379#define REGISTER_CORE(core)
 380#endif
 381
 382#define DEBUG_SECTION \
 383    .debug_level = XCHAL_DEBUGLEVEL, \
 384    .nibreak = XCHAL_NUM_IBREAK, \
 385    .ndbreak = XCHAL_NUM_DBREAK
 386
 387#define CACHE_SECTION \
 388    .icache_ways = XCHAL_ICACHE_WAYS, \
 389    .dcache_ways = XCHAL_DCACHE_WAYS, \
 390    .memctl_mask = \
 391        (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \
 392        (XCHAL_DCACHE_SIZE ? \
 393         MEMCTL_DALLOCWAYS_MASK | MEMCTL_DUSEWAYS_MASK : 0) | \
 394        MEMCTL_ISNP | MEMCTL_DSNP | \
 395        (XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0)
 396
 397#define MEM_LOCATION(name, n) \
 398    { \
 399        .addr = XCHAL_ ## name ## n ## _PADDR, \
 400        .size = XCHAL_ ## name ## n ## _SIZE, \
 401    }
 402
 403#define MEM_SECTIONS(name) \
 404    MEM_LOCATION(name, 0), \
 405    MEM_LOCATION(name, 1), \
 406    MEM_LOCATION(name, 2), \
 407    MEM_LOCATION(name, 3)
 408
 409#define MEM_SECTION(name) \
 410    .num = XCHAL_NUM_ ## name, \
 411    .location = { \
 412        MEM_SECTIONS(name) \
 413    }
 414
 415#define SYSMEM_SECTION(name) \
 416    .num = 1, \
 417    .location = { \
 418        { \
 419            .addr = XCHAL_ ## name ## 0_PADDR, \
 420            .size = XCHAL_ ## name ## 0_SIZE, \
 421        } \
 422    }
 423
 424#define LOCAL_MEMORIES_SECTION \
 425    .instrom = { \
 426        MEM_SECTION(INSTROM) \
 427    }, \
 428    .instram = { \
 429        MEM_SECTION(INSTRAM) \
 430    }, \
 431    .datarom = { \
 432        MEM_SECTION(DATAROM) \
 433    }, \
 434    .dataram = { \
 435        MEM_SECTION(DATARAM) \
 436    }, \
 437    .sysrom = { \
 438        SYSMEM_SECTION(SYSROM) \
 439    }, \
 440    .sysram = { \
 441        SYSMEM_SECTION(SYSRAM) \
 442    }
 443
 444#define CONFIG_SECTION \
 445    .configid = { \
 446        XCHAL_HW_CONFIGID0, \
 447        XCHAL_HW_CONFIGID1, \
 448    }
 449
 450#define DEFAULT_SECTIONS \
 451    .options = XTENSA_OPTIONS, \
 452    .nareg = XCHAL_NUM_AREGS, \
 453    .ndepc = (XCHAL_XEA_VERSION >= 2), \
 454    EXCEPTIONS_SECTION, \
 455    INTERRUPTS_SECTION, \
 456    TLB_SECTION, \
 457    DEBUG_SECTION, \
 458    CACHE_SECTION, \
 459    LOCAL_MEMORIES_SECTION, \
 460    CONFIG_SECTION
 461
 462
 463#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
 464#define XCHAL_INTLEVEL2_VECTOR_VADDR 0
 465#endif
 466#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
 467#define XCHAL_INTLEVEL3_VECTOR_VADDR 0
 468#endif
 469#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
 470#define XCHAL_INTLEVEL4_VECTOR_VADDR 0
 471#endif
 472#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
 473#define XCHAL_INTLEVEL5_VECTOR_VADDR 0
 474#endif
 475#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
 476#define XCHAL_INTLEVEL6_VECTOR_VADDR 0
 477#endif
 478#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
 479#define XCHAL_INTLEVEL7_VECTOR_VADDR 0
 480#endif
 481
 482
 483#if XCHAL_NUM_INTERRUPTS <= 0
 484#define XCHAL_INT0_LEVEL 0
 485#define XCHAL_INT0_TYPE 0
 486#endif
 487#if XCHAL_NUM_INTERRUPTS <= 1
 488#define XCHAL_INT1_LEVEL 0
 489#define XCHAL_INT1_TYPE 0
 490#endif
 491#if XCHAL_NUM_INTERRUPTS <= 2
 492#define XCHAL_INT2_LEVEL 0
 493#define XCHAL_INT2_TYPE 0
 494#endif
 495#if XCHAL_NUM_INTERRUPTS <= 3
 496#define XCHAL_INT3_LEVEL 0
 497#define XCHAL_INT3_TYPE 0
 498#endif
 499#if XCHAL_NUM_INTERRUPTS <= 4
 500#define XCHAL_INT4_LEVEL 0
 501#define XCHAL_INT4_TYPE 0
 502#endif
 503#if XCHAL_NUM_INTERRUPTS <= 5
 504#define XCHAL_INT5_LEVEL 0
 505#define XCHAL_INT5_TYPE 0
 506#endif
 507#if XCHAL_NUM_INTERRUPTS <= 6
 508#define XCHAL_INT6_LEVEL 0
 509#define XCHAL_INT6_TYPE 0
 510#endif
 511#if XCHAL_NUM_INTERRUPTS <= 7
 512#define XCHAL_INT7_LEVEL 0
 513#define XCHAL_INT7_TYPE 0
 514#endif
 515#if XCHAL_NUM_INTERRUPTS <= 8
 516#define XCHAL_INT8_LEVEL 0
 517#define XCHAL_INT8_TYPE 0
 518#endif
 519#if XCHAL_NUM_INTERRUPTS <= 9
 520#define XCHAL_INT9_LEVEL 0
 521#define XCHAL_INT9_TYPE 0
 522#endif
 523#if XCHAL_NUM_INTERRUPTS <= 10
 524#define XCHAL_INT10_LEVEL 0
 525#define XCHAL_INT10_TYPE 0
 526#endif
 527#if XCHAL_NUM_INTERRUPTS <= 11
 528#define XCHAL_INT11_LEVEL 0
 529#define XCHAL_INT11_TYPE 0
 530#endif
 531#if XCHAL_NUM_INTERRUPTS <= 12
 532#define XCHAL_INT12_LEVEL 0
 533#define XCHAL_INT12_TYPE 0
 534#endif
 535#if XCHAL_NUM_INTERRUPTS <= 13
 536#define XCHAL_INT13_LEVEL 0
 537#define XCHAL_INT13_TYPE 0
 538#endif
 539#if XCHAL_NUM_INTERRUPTS <= 14
 540#define XCHAL_INT14_LEVEL 0
 541#define XCHAL_INT14_TYPE 0
 542#endif
 543#if XCHAL_NUM_INTERRUPTS <= 15
 544#define XCHAL_INT15_LEVEL 0
 545#define XCHAL_INT15_TYPE 0
 546#endif
 547#if XCHAL_NUM_INTERRUPTS <= 16
 548#define XCHAL_INT16_LEVEL 0
 549#define XCHAL_INT16_TYPE 0
 550#endif
 551#if XCHAL_NUM_INTERRUPTS <= 17
 552#define XCHAL_INT17_LEVEL 0
 553#define XCHAL_INT17_TYPE 0
 554#endif
 555#if XCHAL_NUM_INTERRUPTS <= 18
 556#define XCHAL_INT18_LEVEL 0
 557#define XCHAL_INT18_TYPE 0
 558#endif
 559#if XCHAL_NUM_INTERRUPTS <= 19
 560#define XCHAL_INT19_LEVEL 0
 561#define XCHAL_INT19_TYPE 0
 562#endif
 563#if XCHAL_NUM_INTERRUPTS <= 20
 564#define XCHAL_INT20_LEVEL 0
 565#define XCHAL_INT20_TYPE 0
 566#endif
 567#if XCHAL_NUM_INTERRUPTS <= 21
 568#define XCHAL_INT21_LEVEL 0
 569#define XCHAL_INT21_TYPE 0
 570#endif
 571#if XCHAL_NUM_INTERRUPTS <= 22
 572#define XCHAL_INT22_LEVEL 0
 573#define XCHAL_INT22_TYPE 0
 574#endif
 575#if XCHAL_NUM_INTERRUPTS <= 23
 576#define XCHAL_INT23_LEVEL 0
 577#define XCHAL_INT23_TYPE 0
 578#endif
 579#if XCHAL_NUM_INTERRUPTS <= 24
 580#define XCHAL_INT24_LEVEL 0
 581#define XCHAL_INT24_TYPE 0
 582#endif
 583#if XCHAL_NUM_INTERRUPTS <= 25
 584#define XCHAL_INT25_LEVEL 0
 585#define XCHAL_INT25_TYPE 0
 586#endif
 587#if XCHAL_NUM_INTERRUPTS <= 26
 588#define XCHAL_INT26_LEVEL 0
 589#define XCHAL_INT26_TYPE 0
 590#endif
 591#if XCHAL_NUM_INTERRUPTS <= 27
 592#define XCHAL_INT27_LEVEL 0
 593#define XCHAL_INT27_TYPE 0
 594#endif
 595#if XCHAL_NUM_INTERRUPTS <= 28
 596#define XCHAL_INT28_LEVEL 0
 597#define XCHAL_INT28_TYPE 0
 598#endif
 599#if XCHAL_NUM_INTERRUPTS <= 29
 600#define XCHAL_INT29_LEVEL 0
 601#define XCHAL_INT29_TYPE 0
 602#endif
 603#if XCHAL_NUM_INTERRUPTS <= 30
 604#define XCHAL_INT30_LEVEL 0
 605#define XCHAL_INT30_TYPE 0
 606#endif
 607#if XCHAL_NUM_INTERRUPTS <= 31
 608#define XCHAL_INT31_LEVEL 0
 609#define XCHAL_INT31_TYPE 0
 610#endif
 611
 612
 613#if XCHAL_NUM_EXTINTERRUPTS <= 0
 614#define XCHAL_EXTINT0_NUM 0
 615#endif
 616#if XCHAL_NUM_EXTINTERRUPTS <= 1
 617#define XCHAL_EXTINT1_NUM 0
 618#endif
 619#if XCHAL_NUM_EXTINTERRUPTS <= 2
 620#define XCHAL_EXTINT2_NUM 0
 621#endif
 622#if XCHAL_NUM_EXTINTERRUPTS <= 3
 623#define XCHAL_EXTINT3_NUM 0
 624#endif
 625#if XCHAL_NUM_EXTINTERRUPTS <= 4
 626#define XCHAL_EXTINT4_NUM 0
 627#endif
 628#if XCHAL_NUM_EXTINTERRUPTS <= 5
 629#define XCHAL_EXTINT5_NUM 0
 630#endif
 631#if XCHAL_NUM_EXTINTERRUPTS <= 6
 632#define XCHAL_EXTINT6_NUM 0
 633#endif
 634#if XCHAL_NUM_EXTINTERRUPTS <= 7
 635#define XCHAL_EXTINT7_NUM 0
 636#endif
 637#if XCHAL_NUM_EXTINTERRUPTS <= 8
 638#define XCHAL_EXTINT8_NUM 0
 639#endif
 640#if XCHAL_NUM_EXTINTERRUPTS <= 9
 641#define XCHAL_EXTINT9_NUM 0
 642#endif
 643#if XCHAL_NUM_EXTINTERRUPTS <= 10
 644#define XCHAL_EXTINT10_NUM 0
 645#endif
 646#if XCHAL_NUM_EXTINTERRUPTS <= 11
 647#define XCHAL_EXTINT11_NUM 0
 648#endif
 649#if XCHAL_NUM_EXTINTERRUPTS <= 12
 650#define XCHAL_EXTINT12_NUM 0
 651#endif
 652#if XCHAL_NUM_EXTINTERRUPTS <= 13
 653#define XCHAL_EXTINT13_NUM 0
 654#endif
 655#if XCHAL_NUM_EXTINTERRUPTS <= 14
 656#define XCHAL_EXTINT14_NUM 0
 657#endif
 658#if XCHAL_NUM_EXTINTERRUPTS <= 15
 659#define XCHAL_EXTINT15_NUM 0
 660#endif
 661#if XCHAL_NUM_EXTINTERRUPTS <= 16
 662#define XCHAL_EXTINT16_NUM 0
 663#endif
 664#if XCHAL_NUM_EXTINTERRUPTS <= 17
 665#define XCHAL_EXTINT17_NUM 0
 666#endif
 667#if XCHAL_NUM_EXTINTERRUPTS <= 18
 668#define XCHAL_EXTINT18_NUM 0
 669#endif
 670#if XCHAL_NUM_EXTINTERRUPTS <= 19
 671#define XCHAL_EXTINT19_NUM 0
 672#endif
 673#if XCHAL_NUM_EXTINTERRUPTS <= 20
 674#define XCHAL_EXTINT20_NUM 0
 675#endif
 676#if XCHAL_NUM_EXTINTERRUPTS <= 21
 677#define XCHAL_EXTINT21_NUM 0
 678#endif
 679#if XCHAL_NUM_EXTINTERRUPTS <= 22
 680#define XCHAL_EXTINT22_NUM 0
 681#endif
 682#if XCHAL_NUM_EXTINTERRUPTS <= 23
 683#define XCHAL_EXTINT23_NUM 0
 684#endif
 685#if XCHAL_NUM_EXTINTERRUPTS <= 24
 686#define XCHAL_EXTINT24_NUM 0
 687#endif
 688#if XCHAL_NUM_EXTINTERRUPTS <= 25
 689#define XCHAL_EXTINT25_NUM 0
 690#endif
 691#if XCHAL_NUM_EXTINTERRUPTS <= 26
 692#define XCHAL_EXTINT26_NUM 0
 693#endif
 694#if XCHAL_NUM_EXTINTERRUPTS <= 27
 695#define XCHAL_EXTINT27_NUM 0
 696#endif
 697#if XCHAL_NUM_EXTINTERRUPTS <= 28
 698#define XCHAL_EXTINT28_NUM 0
 699#endif
 700#if XCHAL_NUM_EXTINTERRUPTS <= 29
 701#define XCHAL_EXTINT29_NUM 0
 702#endif
 703#if XCHAL_NUM_EXTINTERRUPTS <= 30
 704#define XCHAL_EXTINT30_NUM 0
 705#endif
 706#if XCHAL_NUM_EXTINTERRUPTS <= 31
 707#define XCHAL_EXTINT31_NUM 0
 708#endif
 709
 710
 711#define XTHAL_TIMER_UNCONFIGURED 0
 712
 713#if XCHAL_NUM_INSTROM < 1
 714#define XCHAL_INSTROM0_PADDR 0
 715#define XCHAL_INSTROM0_SIZE 0
 716#endif
 717#if XCHAL_NUM_INSTROM < 2
 718#define XCHAL_INSTROM1_PADDR 0
 719#define XCHAL_INSTROM1_SIZE 0
 720#endif
 721#if XCHAL_NUM_INSTROM < 3
 722#define XCHAL_INSTROM2_PADDR 0
 723#define XCHAL_INSTROM2_SIZE 0
 724#endif
 725#if XCHAL_NUM_INSTROM < 4
 726#define XCHAL_INSTROM3_PADDR 0
 727#define XCHAL_INSTROM3_SIZE 0
 728#endif
 729#if XCHAL_NUM_INSTROM > MAX_NMEMORY
 730#error XCHAL_NUM_INSTROM > MAX_NMEMORY
 731#endif
 732
 733#if XCHAL_NUM_INSTRAM < 1
 734#define XCHAL_INSTRAM0_PADDR 0
 735#define XCHAL_INSTRAM0_SIZE 0
 736#endif
 737#if XCHAL_NUM_INSTRAM < 2
 738#define XCHAL_INSTRAM1_PADDR 0
 739#define XCHAL_INSTRAM1_SIZE 0
 740#endif
 741#if XCHAL_NUM_INSTRAM < 3
 742#define XCHAL_INSTRAM2_PADDR 0
 743#define XCHAL_INSTRAM2_SIZE 0
 744#endif
 745#if XCHAL_NUM_INSTRAM < 4
 746#define XCHAL_INSTRAM3_PADDR 0
 747#define XCHAL_INSTRAM3_SIZE 0
 748#endif
 749#if XCHAL_NUM_INSTRAM > MAX_NMEMORY
 750#error XCHAL_NUM_INSTRAM > MAX_NMEMORY
 751#endif
 752
 753#if XCHAL_NUM_DATAROM < 1
 754#define XCHAL_DATAROM0_PADDR 0
 755#define XCHAL_DATAROM0_SIZE 0
 756#endif
 757#if XCHAL_NUM_DATAROM < 2
 758#define XCHAL_DATAROM1_PADDR 0
 759#define XCHAL_DATAROM1_SIZE 0
 760#endif
 761#if XCHAL_NUM_DATAROM < 3
 762#define XCHAL_DATAROM2_PADDR 0
 763#define XCHAL_DATAROM2_SIZE 0
 764#endif
 765#if XCHAL_NUM_DATAROM < 4
 766#define XCHAL_DATAROM3_PADDR 0
 767#define XCHAL_DATAROM3_SIZE 0
 768#endif
 769#if XCHAL_NUM_DATAROM > MAX_NMEMORY
 770#error XCHAL_NUM_DATAROM > MAX_NMEMORY
 771#endif
 772
 773#if XCHAL_NUM_DATARAM < 1
 774#define XCHAL_DATARAM0_PADDR 0
 775#define XCHAL_DATARAM0_SIZE 0
 776#endif
 777#if XCHAL_NUM_DATARAM < 2
 778#define XCHAL_DATARAM1_PADDR 0
 779#define XCHAL_DATARAM1_SIZE 0
 780#endif
 781#if XCHAL_NUM_DATARAM < 3
 782#define XCHAL_DATARAM2_PADDR 0
 783#define XCHAL_DATARAM2_SIZE 0
 784#endif
 785#if XCHAL_NUM_DATARAM < 4
 786#define XCHAL_DATARAM3_PADDR 0
 787#define XCHAL_DATARAM3_SIZE 0
 788#endif
 789#if XCHAL_NUM_DATARAM > MAX_NMEMORY
 790#error XCHAL_NUM_DATARAM > MAX_NMEMORY
 791#endif
 792