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24#ifndef HW_ARM_GICV3_COMMON_H
25#define HW_ARM_GICV3_COMMON_H
26
27#include "hw/sysbus.h"
28#include "hw/intc/arm_gic_common.h"
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34
35#define GICV3_MAXIRQ 1020
36#define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL)
37
38#define GICV3_REDIST_SIZE 0x20000
39
40
41#define GICV3_TARGETLIST_BITS 16
42
43
44#define GICV3_LR_MAX 16
45
46
47#define GIC_MIN_BPR 0
48
49#define GIC_MIN_BPR_NS (GIC_MIN_BPR + 1)
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64
65#define GICV3_BMP_SIZE DIV_ROUND_UP(GICV3_MAXIRQ, 32)
66
67#define GIC_DECLARE_BITMAP(name) \
68 uint32_t name[GICV3_BMP_SIZE]
69
70#define GIC_BIT_MASK(nr) (1U << ((nr) % 32))
71#define GIC_BIT_WORD(nr) ((nr) / 32)
72
73static inline void gic_bmp_set_bit(int nr, uint32_t *addr)
74{
75 uint32_t mask = GIC_BIT_MASK(nr);
76 uint32_t *p = addr + GIC_BIT_WORD(nr);
77
78 *p |= mask;
79}
80
81static inline void gic_bmp_clear_bit(int nr, uint32_t *addr)
82{
83 uint32_t mask = GIC_BIT_MASK(nr);
84 uint32_t *p = addr + GIC_BIT_WORD(nr);
85
86 *p &= ~mask;
87}
88
89static inline int gic_bmp_test_bit(int nr, const uint32_t *addr)
90{
91 return 1U & (addr[GIC_BIT_WORD(nr)] >> (nr & 31));
92}
93
94static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val)
95{
96 uint32_t mask = GIC_BIT_MASK(nr);
97 uint32_t *p = addr + GIC_BIT_WORD(nr);
98
99 *p &= ~mask;
100 *p |= (val & 1U) << (nr % 32);
101}
102
103
104static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr)
105{
106 return addr + GIC_BIT_WORD(nr);
107}
108
109typedef struct GICv3State GICv3State;
110typedef struct GICv3CPUState GICv3CPUState;
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129
130#define GICV3_G0 0
131#define GICV3_G1 1
132#define GICV3_G1NS 2
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138
139#define GICV3_S 0
140#define GICV3_NS 1
141
142typedef struct {
143 int irq;
144 uint8_t prio;
145 int grp;
146} PendingIrq;
147
148struct GICv3CPUState {
149 GICv3State *gic;
150 CPUState *cpu;
151 qemu_irq parent_irq;
152 qemu_irq parent_fiq;
153 qemu_irq parent_virq;
154 qemu_irq parent_vfiq;
155 qemu_irq maintenance_irq;
156
157
158 uint32_t level;
159
160 uint32_t gicr_ctlr;
161 uint64_t gicr_typer;
162 uint32_t gicr_statusr[2];
163 uint32_t gicr_waker;
164 uint64_t gicr_propbaser;
165 uint64_t gicr_pendbaser;
166
167 uint32_t gicr_igroupr0;
168 uint32_t gicr_ienabler0;
169 uint32_t gicr_ipendr0;
170 uint32_t gicr_iactiver0;
171 uint32_t edge_trigger;
172 uint32_t gicr_igrpmodr0;
173 uint32_t gicr_nsacr;
174 uint8_t gicr_ipriorityr[GIC_INTERNAL];
175
176
177 uint64_t icc_sre_el1;
178 uint64_t icc_ctlr_el1[2];
179 uint64_t icc_pmr_el1;
180 uint64_t icc_bpr[3];
181 uint64_t icc_apr[3][4];
182 uint64_t icc_igrpen[3];
183 uint64_t icc_ctlr_el3;
184
185
186 uint64_t ich_apr[3][4];
187 uint64_t ich_hcr_el2;
188 uint64_t ich_lr_el2[GICV3_LR_MAX];
189 uint64_t ich_vmcr_el2;
190
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195
196 int num_list_regs;
197 int vpribits;
198 int vprebits;
199
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204 PendingIrq hppi;
205
206 bool seenbetter;
207};
208
209struct GICv3State {
210
211 SysBusDevice parent_obj;
212
213
214 MemoryRegion iomem_dist;
215 MemoryRegion *iomem_redist;
216 uint32_t *redist_region_count;
217 uint32_t nb_redist_regions;
218
219 uint32_t num_cpu;
220 uint32_t num_irq;
221 uint32_t revision;
222 bool security_extn;
223 bool irq_reset_nonsecure;
224 bool gicd_no_migration_shift_bug;
225
226 int dev_fd;
227 Error *migration_blocker;
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234 uint32_t gicd_ctlr;
235 uint32_t gicd_statusr[2];
236 GIC_DECLARE_BITMAP(group);
237 GIC_DECLARE_BITMAP(grpmod);
238 GIC_DECLARE_BITMAP(enabled);
239 GIC_DECLARE_BITMAP(pending);
240 GIC_DECLARE_BITMAP(active);
241 GIC_DECLARE_BITMAP(level);
242 GIC_DECLARE_BITMAP(edge_trigger);
243 uint8_t gicd_ipriority[GICV3_MAXIRQ];
244 uint64_t gicd_irouter[GICV3_MAXIRQ];
245
246
247
248 GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ];
249 uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)];
250
251 GICv3CPUState *cpu;
252};
253
254#define GICV3_BITMAP_ACCESSORS(BMP) \
255 static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq) \
256 { \
257 gic_bmp_set_bit(irq, s->BMP); \
258 } \
259 static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq) \
260 { \
261 return gic_bmp_test_bit(irq, s->BMP); \
262 } \
263 static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \
264 { \
265 gic_bmp_clear_bit(irq, s->BMP); \
266 } \
267 static inline void gicv3_gicd_##BMP##_replace(GICv3State *s, \
268 int irq, int value) \
269 { \
270 gic_bmp_replace_bit(irq, s->BMP, value); \
271 }
272
273GICV3_BITMAP_ACCESSORS(group)
274GICV3_BITMAP_ACCESSORS(grpmod)
275GICV3_BITMAP_ACCESSORS(enabled)
276GICV3_BITMAP_ACCESSORS(pending)
277GICV3_BITMAP_ACCESSORS(active)
278GICV3_BITMAP_ACCESSORS(level)
279GICV3_BITMAP_ACCESSORS(edge_trigger)
280
281#define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
282#define ARM_GICV3_COMMON(obj) \
283 OBJECT_CHECK(GICv3State, (obj), TYPE_ARM_GICV3_COMMON)
284#define ARM_GICV3_COMMON_CLASS(klass) \
285 OBJECT_CLASS_CHECK(ARMGICv3CommonClass, (klass), TYPE_ARM_GICV3_COMMON)
286#define ARM_GICV3_COMMON_GET_CLASS(obj) \
287 OBJECT_GET_CLASS(ARMGICv3CommonClass, (obj), TYPE_ARM_GICV3_COMMON)
288
289typedef struct ARMGICv3CommonClass {
290
291 SysBusDeviceClass parent_class;
292
293
294 void (*pre_save)(GICv3State *s);
295 void (*post_load)(GICv3State *s);
296} ARMGICv3CommonClass;
297
298void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
299 const MemoryRegionOps *ops, Error **errp);
300
301#endif
302