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21#ifndef HW_ARM_SMMU_INTERNAL_H
22#define HW_ARM_SMMU_INTERNAL_H
23
24#define TBI0(tbi) ((tbi) & 0x1)
25#define TBI1(tbi) ((tbi) & 0x2 >> 1)
26
27
28
29#define ARM_LPAE_PTE_TYPE_SHIFT 0
30#define ARM_LPAE_PTE_TYPE_MASK 0x3
31
32#define ARM_LPAE_PTE_TYPE_BLOCK 1
33#define ARM_LPAE_PTE_TYPE_TABLE 3
34
35#define ARM_LPAE_L3_PTE_TYPE_RESERVED 1
36#define ARM_LPAE_L3_PTE_TYPE_PAGE 3
37
38#define ARM_LPAE_PTE_VALID (1 << 0)
39
40#define PTE_ADDRESS(pte, shift) \
41 (extract64(pte, shift, 47 - shift + 1) << shift)
42
43#define is_invalid_pte(pte) (!(pte & ARM_LPAE_PTE_VALID))
44
45#define is_reserved_pte(pte, level) \
46 ((level == 3) && \
47 ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_RESERVED))
48
49#define is_block_pte(pte, level) \
50 ((level < 3) && \
51 ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_BLOCK))
52
53#define is_table_pte(pte, level) \
54 ((level < 3) && \
55 ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_TABLE))
56
57#define is_page_pte(pte, level) \
58 ((level == 3) && \
59 ((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_PAGE))
60
61
62
63#define PTE_AP(pte) \
64 (extract64(pte, 6, 2))
65
66#define PTE_APTABLE(pte) \
67 (extract64(pte, 61, 2))
68
69
70
71
72
73#define is_permission_fault(ap, perm) \
74 (((perm) & IOMMU_WO) && ((ap) & 0x2))
75
76#define PTE_AP_TO_PERM(ap) \
77 (IOMMU_ACCESS_FLAG(true, !((ap) & 0x2)))
78
79
80
81static inline int level_shift(int level, int granule_sz)
82{
83 return granule_sz + (3 - level) * (granule_sz - 3);
84}
85
86static inline uint64_t level_page_mask(int level, int granule_sz)
87{
88 return ~(MAKE_64BIT_MASK(0, level_shift(level, granule_sz)));
89}
90
91static inline
92uint64_t iova_level_offset(uint64_t iova, int inputsize,
93 int level, int gsz)
94{
95 return ((iova & MAKE_64BIT_MASK(0, inputsize)) >> level_shift(level, gsz)) &
96 MAKE_64BIT_MASK(0, gsz - 3);
97}
98
99#endif
100