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26#include "qemu/osdep.h"
27#include "hw/pci/pci.h"
28#include "migration/vmstate.h"
29#include "qemu/module.h"
30#include "sysemu/block-backend.h"
31#include "sysemu/blockdev.h"
32#include "sysemu/dma.h"
33
34#include "hw/ide/pci.h"
35#include "trace.h"
36
37static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
38{
39 BMDMAState *bm = opaque;
40 uint32_t val;
41
42 if (size != 1) {
43 return ((uint64_t)1 << (size * 8)) - 1;
44 }
45
46 switch(addr & 3) {
47 case 0:
48 val = bm->cmd;
49 break;
50 case 2:
51 val = bm->status;
52 break;
53 default:
54 val = 0xff;
55 break;
56 }
57
58 trace_bmdma_read(addr, val);
59 return val;
60}
61
62static void bmdma_write(void *opaque, hwaddr addr,
63 uint64_t val, unsigned size)
64{
65 BMDMAState *bm = opaque;
66
67 if (size != 1) {
68 return;
69 }
70
71 trace_bmdma_write(addr, val);
72
73 switch(addr & 3) {
74 case 0:
75 bmdma_cmd_writeb(bm, val);
76 break;
77 case 2:
78 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
79 break;
80 }
81}
82
83static const MemoryRegionOps piix_bmdma_ops = {
84 .read = bmdma_read,
85 .write = bmdma_write,
86};
87
88static void bmdma_setup_bar(PCIIDEState *d)
89{
90 int i;
91
92 memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16);
93 for(i = 0;i < 2; i++) {
94 BMDMAState *bm = &d->bmdma[i];
95
96 memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm,
97 "piix-bmdma", 4);
98 memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
99 memory_region_init_io(&bm->addr_ioport, OBJECT(d),
100 &bmdma_addr_ioport_ops, bm, "bmdma", 4);
101 memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
102 }
103}
104
105static void piix_ide_reset(DeviceState *dev)
106{
107 PCIIDEState *d = PCI_IDE(dev);
108 PCIDevice *pd = PCI_DEVICE(d);
109 uint8_t *pci_conf = pd->config;
110 int i;
111
112 for (i = 0; i < 2; i++) {
113 ide_bus_reset(&d->bus[i]);
114 }
115
116
117 pci_conf[PCI_COMMAND] = 0x00;
118
119 pci_conf[PCI_COMMAND + 1] = 0x00;
120
121 pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
122 pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
123 pci_conf[0x20] = 0x01;
124}
125
126static void pci_piix_init_ports(PCIIDEState *d) {
127 static const struct {
128 int iobase;
129 int iobase2;
130 int isairq;
131 } port_info[] = {
132 {0x1f0, 0x3f6, 14},
133 {0x170, 0x376, 15},
134 };
135 int i;
136
137 for (i = 0; i < 2; i++) {
138 ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
139 ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
140 port_info[i].iobase2);
141 ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
142
143 bmdma_init(&d->bus[i], &d->bmdma[i], d);
144 d->bmdma[i].bus = &d->bus[i];
145 ide_register_restart_cb(&d->bus[i]);
146 }
147}
148
149static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
150{
151 PCIIDEState *d = PCI_IDE(dev);
152 uint8_t *pci_conf = dev->config;
153
154 pci_conf[PCI_CLASS_PROG] = 0x80;
155
156 bmdma_setup_bar(d);
157 pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
158
159 vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d);
160
161 pci_piix_init_ports(d);
162}
163
164int pci_piix3_xen_ide_unplug(DeviceState *dev, bool aux)
165{
166 PCIIDEState *pci_ide;
167 DriveInfo *di;
168 int i;
169 IDEDevice *idedev;
170
171 pci_ide = PCI_IDE(dev);
172
173 for (i = aux ? 1 : 0; i < 4; i++) {
174 di = drive_get_by_index(IF_IDE, i);
175 if (di != NULL && !di->media_cd) {
176 BlockBackend *blk = blk_by_legacy_dinfo(di);
177 DeviceState *ds = blk_get_attached_dev(blk);
178
179 blk_drain(blk);
180 blk_flush(blk);
181
182 if (ds) {
183 blk_detach_dev(blk, ds);
184 }
185 pci_ide->bus[di->bus].ifs[di->unit].blk = NULL;
186 if (!(i % 2)) {
187 idedev = pci_ide->bus[di->bus].master;
188 } else {
189 idedev = pci_ide->bus[di->bus].slave;
190 }
191 idedev->conf.blk = NULL;
192 monitor_remove_blk(blk);
193 blk_unref(blk);
194 }
195 }
196 qdev_reset_all(dev);
197 return 0;
198}
199
200static void pci_piix_ide_exitfn(PCIDevice *dev)
201{
202 PCIIDEState *d = PCI_IDE(dev);
203 unsigned i;
204
205 for (i = 0; i < 2; ++i) {
206 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
207 memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
208 }
209}
210
211
212static void piix3_ide_class_init(ObjectClass *klass, void *data)
213{
214 DeviceClass *dc = DEVICE_CLASS(klass);
215 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
216
217 dc->reset = piix_ide_reset;
218 k->realize = pci_piix_ide_realize;
219 k->exit = pci_piix_ide_exitfn;
220 k->vendor_id = PCI_VENDOR_ID_INTEL;
221 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
222 k->class_id = PCI_CLASS_STORAGE_IDE;
223 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
224 dc->hotpluggable = false;
225}
226
227static const TypeInfo piix3_ide_info = {
228 .name = "piix3-ide",
229 .parent = TYPE_PCI_IDE,
230 .class_init = piix3_ide_class_init,
231};
232
233static const TypeInfo piix3_ide_xen_info = {
234 .name = "piix3-ide-xen",
235 .parent = TYPE_PCI_IDE,
236 .class_init = piix3_ide_class_init,
237};
238
239
240static void piix4_ide_class_init(ObjectClass *klass, void *data)
241{
242 DeviceClass *dc = DEVICE_CLASS(klass);
243 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
244
245 dc->reset = piix_ide_reset;
246 k->realize = pci_piix_ide_realize;
247 k->exit = pci_piix_ide_exitfn;
248 k->vendor_id = PCI_VENDOR_ID_INTEL;
249 k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
250 k->class_id = PCI_CLASS_STORAGE_IDE;
251 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
252 dc->hotpluggable = false;
253}
254
255static const TypeInfo piix4_ide_info = {
256 .name = "piix4-ide",
257 .parent = TYPE_PCI_IDE,
258 .class_init = piix4_ide_class_init,
259};
260
261static void piix_ide_register_types(void)
262{
263 type_register_static(&piix3_ide_info);
264 type_register_static(&piix3_ide_xen_info);
265 type_register_static(&piix4_ide_info);
266}
267
268type_init(piix_ide_register_types)
269
