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25#include "qemu/osdep.h"
26#include "hw/sysbus.h"
27#include "hw/irq.h"
28#include "hw/ptimer.h"
29#include "hw/qdev-properties.h"
30#include "qemu/log.h"
31#include "qemu/module.h"
32#include "qemu/bitops.h"
33#include "hw/ssi/xilinx_spips.h"
34#include "qapi/error.h"
35#include "hw/register.h"
36#include "sysemu/dma.h"
37#include "migration/blocker.h"
38#include "migration/vmstate.h"
39
40#ifndef XILINX_SPIPS_ERR_DEBUG
41#define XILINX_SPIPS_ERR_DEBUG 0
42#endif
43
44#define DB_PRINT_L(level, ...) do { \
45 if (XILINX_SPIPS_ERR_DEBUG > (level)) { \
46 fprintf(stderr, ": %s: ", __func__); \
47 fprintf(stderr, ## __VA_ARGS__); \
48 } \
49} while (0)
50
51
52#define R_CONFIG (0x00 / 4)
53#define IFMODE (1U << 31)
54#define R_CONFIG_ENDIAN (1 << 26)
55#define MODEFAIL_GEN_EN (1 << 17)
56#define MAN_START_COM (1 << 16)
57#define MAN_START_EN (1 << 15)
58#define MANUAL_CS (1 << 14)
59#define CS (0xF << 10)
60#define CS_SHIFT (10)
61#define PERI_SEL (1 << 9)
62#define REF_CLK (1 << 8)
63#define FIFO_WIDTH (3 << 6)
64#define BAUD_RATE_DIV (7 << 3)
65#define CLK_PH (1 << 2)
66#define CLK_POL (1 << 1)
67#define MODE_SEL (1 << 0)
68#define R_CONFIG_RSVD (0x7bf40000)
69
70
71#define R_INTR_STATUS (0x04 / 4)
72#define R_INTR_STATUS_RESET (0x104)
73#define R_INTR_EN (0x08 / 4)
74#define R_INTR_DIS (0x0C / 4)
75#define R_INTR_MASK (0x10 / 4)
76#define IXR_TX_FIFO_UNDERFLOW (1 << 6)
77
78#define IXR_RX_FIFO_EMPTY (1 << 11)
79#define IXR_GENERIC_FIFO_FULL (1 << 10)
80#define IXR_GENERIC_FIFO_NOT_FULL (1 << 9)
81#define IXR_TX_FIFO_EMPTY (1 << 8)
82#define IXR_GENERIC_FIFO_EMPTY (1 << 7)
83#define IXR_RX_FIFO_FULL (1 << 5)
84#define IXR_RX_FIFO_NOT_EMPTY (1 << 4)
85#define IXR_TX_FIFO_FULL (1 << 3)
86#define IXR_TX_FIFO_NOT_FULL (1 << 2)
87#define IXR_TX_FIFO_MODE_FAIL (1 << 1)
88#define IXR_RX_FIFO_OVERFLOW (1 << 0)
89#define IXR_ALL ((1 << 13) - 1)
90#define GQSPI_IXR_MASK 0xFBE
91#define IXR_SELF_CLEAR \
92(IXR_GENERIC_FIFO_EMPTY \
93| IXR_GENERIC_FIFO_FULL \
94| IXR_GENERIC_FIFO_NOT_FULL \
95| IXR_TX_FIFO_EMPTY \
96| IXR_TX_FIFO_FULL \
97| IXR_TX_FIFO_NOT_FULL \
98| IXR_RX_FIFO_EMPTY \
99| IXR_RX_FIFO_FULL \
100| IXR_RX_FIFO_NOT_EMPTY)
101
102#define R_EN (0x14 / 4)
103#define R_DELAY (0x18 / 4)
104#define R_TX_DATA (0x1C / 4)
105#define R_RX_DATA (0x20 / 4)
106#define R_SLAVE_IDLE_COUNT (0x24 / 4)
107#define R_TX_THRES (0x28 / 4)
108#define R_RX_THRES (0x2C / 4)
109#define R_GPIO (0x30 / 4)
110#define R_LPBK_DLY_ADJ (0x38 / 4)
111#define R_LPBK_DLY_ADJ_RESET (0x33)
112#define R_IOU_TAPDLY_BYPASS (0x3C / 4)
113#define R_TXD1 (0x80 / 4)
114#define R_TXD2 (0x84 / 4)
115#define R_TXD3 (0x88 / 4)
116
117#define R_LQSPI_CFG (0xa0 / 4)
118#define R_LQSPI_CFG_RESET 0x03A002EB
119#define LQSPI_CFG_LQ_MODE (1U << 31)
120#define LQSPI_CFG_TWO_MEM (1 << 30)
121#define LQSPI_CFG_SEP_BUS (1 << 29)
122#define LQSPI_CFG_U_PAGE (1 << 28)
123#define LQSPI_CFG_ADDR4 (1 << 27)
124#define LQSPI_CFG_MODE_EN (1 << 25)
125#define LQSPI_CFG_MODE_WIDTH 8
126#define LQSPI_CFG_MODE_SHIFT 16
127#define LQSPI_CFG_DUMMY_WIDTH 3
128#define LQSPI_CFG_DUMMY_SHIFT 8
129#define LQSPI_CFG_INST_CODE 0xFF
130
131#define R_CMND (0xc0 / 4)
132 #define R_CMND_RXFIFO_DRAIN (1 << 19)
133 FIELD(CMND, PARTIAL_BYTE_LEN, 16, 3)
134#define R_CMND_EXT_ADD (1 << 15)
135 FIELD(CMND, RX_DISCARD, 8, 7)
136 FIELD(CMND, DUMMY_CYCLES, 2, 6)
137#define R_CMND_DMA_EN (1 << 1)
138#define R_CMND_PUSH_WAIT (1 << 0)
139#define R_TRANSFER_SIZE (0xc4 / 4)
140#define R_LQSPI_STS (0xA4 / 4)
141#define LQSPI_STS_WR_RECVD (1 << 1)
142
143#define R_DUMMY_CYCLE_EN (0xC8 / 4)
144#define R_ECO (0xF8 / 4)
145#define R_MOD_ID (0xFC / 4)
146
147#define R_GQSPI_SELECT (0x144 / 4)
148 FIELD(GQSPI_SELECT, GENERIC_QSPI_EN, 0, 1)
149#define R_GQSPI_ISR (0x104 / 4)
150#define R_GQSPI_IER (0x108 / 4)
151#define R_GQSPI_IDR (0x10c / 4)
152#define R_GQSPI_IMR (0x110 / 4)
153#define R_GQSPI_IMR_RESET (0xfbe)
154#define R_GQSPI_TX_THRESH (0x128 / 4)
155#define R_GQSPI_RX_THRESH (0x12c / 4)
156#define R_GQSPI_GPIO (0x130 / 4)
157#define R_GQSPI_LPBK_DLY_ADJ (0x138 / 4)
158#define R_GQSPI_LPBK_DLY_ADJ_RESET (0x33)
159#define R_GQSPI_CNFG (0x100 / 4)
160 FIELD(GQSPI_CNFG, MODE_EN, 30, 2)
161 FIELD(GQSPI_CNFG, GEN_FIFO_START_MODE, 29, 1)
162 FIELD(GQSPI_CNFG, GEN_FIFO_START, 28, 1)
163 FIELD(GQSPI_CNFG, ENDIAN, 26, 1)
164
165 FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1)
166
167 FIELD(GQSPI_CNFG, BR, 3, 3)
168 FIELD(GQSPI_CNFG, CPH, 2, 1)
169 FIELD(GQSPI_CNFG, CPL, 1, 1)
170#define R_GQSPI_GEN_FIFO (0x140 / 4)
171#define R_GQSPI_TXD (0x11c / 4)
172#define R_GQSPI_RXD (0x120 / 4)
173#define R_GQSPI_FIFO_CTRL (0x14c / 4)
174 FIELD(GQSPI_FIFO_CTRL, RX_FIFO_RESET, 2, 1)
175 FIELD(GQSPI_FIFO_CTRL, TX_FIFO_RESET, 1, 1)
176 FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1)
177#define R_GQSPI_GFIFO_THRESH (0x150 / 4)
178#define R_GQSPI_DATA_STS (0x15c / 4)
179
180
181
182
183#define R_GQSPI_GF_SNAPSHOT (0x160 / 4)
184 FIELD(GQSPI_GF_SNAPSHOT, POLL, 19, 1)
185 FIELD(GQSPI_GF_SNAPSHOT, STRIPE, 18, 1)
186 FIELD(GQSPI_GF_SNAPSHOT, RECIEVE, 17, 1)
187 FIELD(GQSPI_GF_SNAPSHOT, TRANSMIT, 16, 1)
188 FIELD(GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT, 14, 2)
189 FIELD(GQSPI_GF_SNAPSHOT, CHIP_SELECT, 12, 2)
190 FIELD(GQSPI_GF_SNAPSHOT, SPI_MODE, 10, 2)
191 FIELD(GQSPI_GF_SNAPSHOT, EXPONENT, 9, 1)
192 FIELD(GQSPI_GF_SNAPSHOT, DATA_XFER, 8, 1)
193 FIELD(GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA, 0, 8)
194#define R_GQSPI_MOD_ID (0x1fc / 4)
195#define R_GQSPI_MOD_ID_RESET (0x10a0000)
196
197#define R_QSPIDMA_DST_CTRL (0x80c / 4)
198#define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00)
199#define R_QSPIDMA_DST_I_MASK (0x820 / 4)
200#define R_QSPIDMA_DST_I_MASK_RESET (0xfe)
201#define R_QSPIDMA_DST_CTRL2 (0x824 / 4)
202#define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8)
203
204
205#define RXFF_A (128)
206#define TXFF_A (128)
207
208#define RXFF_A_Q (64 * 4)
209#define TXFF_A_Q (64 * 4)
210
211
212#define LQSPI_ADDRESS_BITS 24
213#define LQSPI_HACK_CHUNK_SIZE (1 * 1024 * 1024)
214
215#define SNOOP_CHECKING 0xFF
216#define SNOOP_ADDR 0xF0
217#define SNOOP_NONE 0xEE
218#define SNOOP_STRIPING 0
219
220#define MIN_NUM_BUSSES 1
221#define MAX_NUM_BUSSES 2
222
223static inline int num_effective_busses(XilinxSPIPS *s)
224{
225 return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
226 s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
227}
228
229static void xilinx_spips_update_cs(XilinxSPIPS *s, int field)
230{
231 int i;
232
233 for (i = 0; i < s->num_cs * s->num_busses; i++) {
234 bool old_state = s->cs_lines_state[i];
235 bool new_state = field & (1 << i);
236
237 if (old_state != new_state) {
238 s->cs_lines_state[i] = new_state;
239 s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD);
240 DB_PRINT_L(1, "%sselecting slave %d\n", new_state ? "" : "de", i);
241 }
242 qemu_set_irq(s->cs_lines[i], !new_state);
243 }
244 if (!(field & ((1 << (s->num_cs * s->num_busses)) - 1))) {
245 s->snoop_state = SNOOP_CHECKING;
246 s->cmd_dummies = 0;
247 s->link_state = 1;
248 s->link_state_next = 1;
249 s->link_state_next_when = 0;
250 DB_PRINT_L(1, "moving to snoop check state\n");
251 }
252}
253
254static void xlnx_zynqmp_qspips_update_cs_lines(XlnxZynqMPQSPIPS *s)
255{
256 if (s->regs[R_GQSPI_GF_SNAPSHOT]) {
257 int field = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, CHIP_SELECT);
258 bool upper_cs_sel = field & (1 << 1);
259 bool lower_cs_sel = field & 1;
260 bool bus0_enabled;
261 bool bus1_enabled;
262 uint8_t buses;
263 int cs = 0;
264
265 buses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
266 bus0_enabled = buses & 1;
267 bus1_enabled = buses & (1 << 1);
268
269 if (bus0_enabled && bus1_enabled) {
270 if (lower_cs_sel) {
271 cs |= 1;
272 }
273 if (upper_cs_sel) {
274 cs |= 1 << 3;
275 }
276 } else if (bus0_enabled) {
277 if (lower_cs_sel) {
278 cs |= 1;
279 }
280 if (upper_cs_sel) {
281 cs |= 1 << 1;
282 }
283 } else if (bus1_enabled) {
284 if (lower_cs_sel) {
285 cs |= 1 << 2;
286 }
287 if (upper_cs_sel) {
288 cs |= 1 << 3;
289 }
290 }
291 xilinx_spips_update_cs(XILINX_SPIPS(s), cs);
292 }
293}
294
295static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
296{
297 int field;
298
299 if (object_dynamic_cast(OBJECT(s), TYPE_XILINX_QSPIPS)) {
300 field = !extract32(s->regs[R_CONFIG], CS_SHIFT, 1);
301 } else {
302 field = ~((s->regs[R_CONFIG] & CS) >> CS_SHIFT);
303 }
304
305
306 if (num_effective_busses(s) == 2) {
307
308 field &= 0x1;
309 field |= field << 3;
310
311 } else if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM &&
312 s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE) {
313
314 field &= 0x1;
315
316 field <<= 1;
317 }
318
319 if (!(s->regs[R_CONFIG] & MANUAL_CS) &&
320 fifo8_is_empty(&s->tx_fifo)) {
321 field = 0;
322 }
323 xilinx_spips_update_cs(s, field);
324}
325
326static void xilinx_spips_update_ixr(XilinxSPIPS *s)
327{
328 if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
329 s->regs[R_INTR_STATUS] &= ~IXR_SELF_CLEAR;
330 s->regs[R_INTR_STATUS] |=
331 (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
332 (s->rx_fifo.num >= s->regs[R_RX_THRES] ?
333 IXR_RX_FIFO_NOT_EMPTY : 0) |
334 (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
335 (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
336 }
337 int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
338 IXR_ALL);
339 if (new_irqline != s->irqline) {
340 s->irqline = new_irqline;
341 qemu_set_irq(s->irq, s->irqline);
342 }
343}
344
345static void xlnx_zynqmp_qspips_update_ixr(XlnxZynqMPQSPIPS *s)
346{
347 uint32_t gqspi_int;
348 int new_irqline;
349
350 s->regs[R_GQSPI_ISR] &= ~IXR_SELF_CLEAR;
351 s->regs[R_GQSPI_ISR] |=
352 (fifo32_is_empty(&s->fifo_g) ? IXR_GENERIC_FIFO_EMPTY : 0) |
353 (fifo32_is_full(&s->fifo_g) ? IXR_GENERIC_FIFO_FULL : 0) |
354 (s->fifo_g.fifo.num < s->regs[R_GQSPI_GFIFO_THRESH] ?
355 IXR_GENERIC_FIFO_NOT_FULL : 0) |
356 (fifo8_is_empty(&s->rx_fifo_g) ? IXR_RX_FIFO_EMPTY : 0) |
357 (fifo8_is_full(&s->rx_fifo_g) ? IXR_RX_FIFO_FULL : 0) |
358 (s->rx_fifo_g.num >= s->regs[R_GQSPI_RX_THRESH] ?
359 IXR_RX_FIFO_NOT_EMPTY : 0) |
360 (fifo8_is_empty(&s->tx_fifo_g) ? IXR_TX_FIFO_EMPTY : 0) |
361 (fifo8_is_full(&s->tx_fifo_g) ? IXR_TX_FIFO_FULL : 0) |
362 (s->tx_fifo_g.num < s->regs[R_GQSPI_TX_THRESH] ?
363 IXR_TX_FIFO_NOT_FULL : 0);
364
365
366 gqspi_int = (~s->regs[R_GQSPI_IMR]) & s->regs[R_GQSPI_ISR] & GQSPI_IXR_MASK;
367 new_irqline = !!(gqspi_int & IXR_ALL);
368
369
370 if (new_irqline != s->gqspi_irqline) {
371 s->gqspi_irqline = new_irqline;
372 qemu_set_irq(XILINX_SPIPS(s)->irq, s->gqspi_irqline);
373 }
374}
375
376static void xilinx_spips_reset(DeviceState *d)
377{
378 XilinxSPIPS *s = XILINX_SPIPS(d);
379
380 memset(s->regs, 0, sizeof(s->regs));
381
382 fifo8_reset(&s->rx_fifo);
383 fifo8_reset(&s->rx_fifo);
384
385 s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
386 s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
387 s->regs[R_TX_THRES] = 1;
388 s->regs[R_RX_THRES] = 1;
389
390 s->regs[R_MOD_ID] = 0x01090106;
391 s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
392 s->link_state = 1;
393 s->link_state_next = 1;
394 s->link_state_next_when = 0;
395 s->snoop_state = SNOOP_CHECKING;
396 s->cmd_dummies = 0;
397 s->man_start_com = false;
398 xilinx_spips_update_ixr(s);
399 xilinx_spips_update_cs_lines(s);
400}
401
402static void xlnx_zynqmp_qspips_reset(DeviceState *d)
403{
404 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(d);
405
406 xilinx_spips_reset(d);
407
408 memset(s->regs, 0, sizeof(s->regs));
409
410 fifo8_reset(&s->rx_fifo_g);
411 fifo8_reset(&s->rx_fifo_g);
412 fifo32_reset(&s->fifo_g);
413 s->regs[R_INTR_STATUS] = R_INTR_STATUS_RESET;
414 s->regs[R_GPIO] = 1;
415 s->regs[R_LPBK_DLY_ADJ] = R_LPBK_DLY_ADJ_RESET;
416 s->regs[R_GQSPI_GFIFO_THRESH] = 0x10;
417 s->regs[R_MOD_ID] = 0x01090101;
418 s->regs[R_GQSPI_IMR] = R_GQSPI_IMR_RESET;
419 s->regs[R_GQSPI_TX_THRESH] = 1;
420 s->regs[R_GQSPI_RX_THRESH] = 1;
421 s->regs[R_GQSPI_GPIO] = 1;
422 s->regs[R_GQSPI_LPBK_DLY_ADJ] = R_GQSPI_LPBK_DLY_ADJ_RESET;
423 s->regs[R_GQSPI_MOD_ID] = R_GQSPI_MOD_ID_RESET;
424 s->man_start_com_g = false;
425 s->gqspi_irqline = 0;
426 xlnx_zynqmp_qspips_update_ixr(s);
427}
428
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432
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437
438
439static inline void stripe8(uint8_t *x, int num, bool dir)
440{
441 uint8_t r[MAX_NUM_BUSSES];
442 int idx[2] = {0, 0};
443 int bit[2] = {0, 7};
444 int d = dir;
445
446 assert(num <= MAX_NUM_BUSSES);
447 memset(r, 0, sizeof(uint8_t) * num);
448
449 for (idx[0] = 0; idx[0] < num; ++idx[0]) {
450 for (bit[0] = 7; bit[0] >= 0; bit[0]--) {
451 r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0;
452 idx[1] = (idx[1] + 1) % num;
453 if (!idx[1]) {
454 bit[1]--;
455 }
456 }
457 }
458 memcpy(x, r, sizeof(uint8_t) * num);
459}
460
461static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQSPIPS *s)
462{
463 while (s->regs[R_GQSPI_DATA_STS] || !fifo32_is_empty(&s->fifo_g)) {
464 uint8_t tx_rx[2] = { 0 };
465 int num_stripes = 1;
466 uint8_t busses;
467 int i;
468
469 if (!s->regs[R_GQSPI_DATA_STS]) {
470 uint8_t imm;
471
472 s->regs[R_GQSPI_GF_SNAPSHOT] = fifo32_pop(&s->fifo_g);
473 DB_PRINT_L(0, "GQSPI command: %x\n", s->regs[R_GQSPI_GF_SNAPSHOT]);
474 if (!s->regs[R_GQSPI_GF_SNAPSHOT]) {
475 DB_PRINT_L(0, "Dummy GQSPI Delay Command Entry, Do nothing");
476 continue;
477 }
478 xlnx_zynqmp_qspips_update_cs_lines(s);
479
480 imm = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA);
481 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) {
482
483 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) ||
484 ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) {
485 s->regs[R_GQSPI_DATA_STS] = 1;
486
487 } else {
488 s->regs[R_GQSPI_DATA_STS] = 0;
489 }
490 } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, EXPONENT)) {
491 if (imm > 31) {
492 qemu_log_mask(LOG_UNIMP, "QSPI exponential transfer too"
493 " long - 2 ^ %" PRId8 " requested\n", imm);
494 }
495 s->regs[R_GQSPI_DATA_STS] = 1ul << imm;
496 } else {
497 s->regs[R_GQSPI_DATA_STS] = imm;
498 }
499 }
500
501 if (!s->regs[R_GQSPI_DATA_STS]) {
502 continue;
503 }
504 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE) &&
505 fifo8_is_full(&s->rx_fifo_g)) {
506
507 return;
508 }
509 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, STRIPE) &&
510 (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT) ||
511 ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))) {
512 num_stripes = 2;
513 }
514 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) {
515 tx_rx[0] = ARRAY_FIELD_EX32(s->regs,
516 GQSPI_GF_SNAPSHOT, IMMEDIATE_DATA);
517 } else if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)) {
518 for (i = 0; i < num_stripes; ++i) {
519 if (!fifo8_is_empty(&s->tx_fifo_g)) {
520 tx_rx[i] = fifo8_pop(&s->tx_fifo_g);
521 s->tx_fifo_g_align++;
522 } else {
523 return;
524 }
525 }
526 }
527 if (num_stripes == 1) {
528
529 tx_rx[1] = tx_rx[0];
530 }
531 busses = ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_BUS_SELECT);
532 for (i = 0; i < 2; ++i) {
533 DB_PRINT_L(1, "bus %d tx = %02x\n", i, tx_rx[i]);
534 tx_rx[i] = ssi_transfer(XILINX_SPIPS(s)->spi[i], tx_rx[i]);
535 DB_PRINT_L(1, "bus %d rx = %02x\n", i, tx_rx[i]);
536 }
537 if (s->regs[R_GQSPI_DATA_STS] > 1 &&
538 busses == 0x3 && num_stripes == 2) {
539 s->regs[R_GQSPI_DATA_STS] -= 2;
540 } else if (s->regs[R_GQSPI_DATA_STS] > 0) {
541 s->regs[R_GQSPI_DATA_STS]--;
542 }
543 if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE)) {
544 for (i = 0; i < 2; ++i) {
545 if (busses & (1 << i)) {
546 DB_PRINT_L(1, "bus %d push_byte = %02x\n", i, tx_rx[i]);
547 fifo8_push(&s->rx_fifo_g, tx_rx[i]);
548 s->rx_fifo_g_align++;
549 }
550 }
551 }
552 if (!s->regs[R_GQSPI_DATA_STS]) {
553 for (; s->tx_fifo_g_align % 4; s->tx_fifo_g_align++) {
554 fifo8_pop(&s->tx_fifo_g);
555 }
556 for (; s->rx_fifo_g_align % 4; s->rx_fifo_g_align++) {
557 fifo8_push(&s->rx_fifo_g, 0);
558 }
559 }
560 }
561}
562
563static int xilinx_spips_num_dummies(XilinxQSPIPS *qs, uint8_t command)
564{
565 if (!qs) {
566
567 return -1;
568 }
569
570 switch (command) {
571 case READ:
572 case PP:
573 case DPP:
574 case QPP:
575 case ERASE_4K:
576 case ERASE_32K:
577 case ERASE_SEC:
578 case READ_4:
579 case PP_4:
580 case QPP_4:
581 case ERASE4_4K:
582 case ERASE4_32K:
583 case ERASE4_SEC:
584 return 0;
585 case FAST_READ:
586 case DOR:
587 case QOR:
588 case FAST_READ_4:
589 case DOR_4:
590 case QOR_4:
591 return 1;
592 case DIOR:
593 case DIOR_4:
594 return 2;
595 case QIOR:
596 case QIOR_4:
597 return 4;
598 case JEDEC_READ:
599 default:
600 return -1;
601 }
602}
603
604static inline uint8_t get_addr_length(XilinxSPIPS *s, uint8_t cmd)
605{
606 switch (cmd) {
607 case PP_4:
608 case QPP_4:
609 case READ_4:
610 case QIOR_4:
611 case FAST_READ_4:
612 case DOR_4:
613 case QOR_4:
614 case DIOR_4:
615 case ERASE4_4K:
616 case ERASE4_32K:
617 case ERASE4_SEC:
618 return 4;
619 default:
620 return (s->regs[R_CMND] & R_CMND_EXT_ADD) ? 4 : 3;
621 }
622}
623
624static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
625{
626 int debug_level = 0;
627 XilinxQSPIPS *q = (XilinxQSPIPS *) object_dynamic_cast(OBJECT(s),
628 TYPE_XILINX_QSPIPS);
629
630 for (;;) {
631 int i;
632 uint8_t tx = 0;
633 uint8_t tx_rx[MAX_NUM_BUSSES] = { 0 };
634 uint8_t dummy_cycles = 0;
635 uint8_t addr_length;
636
637 if (fifo8_is_empty(&s->tx_fifo)) {
638 xilinx_spips_update_ixr(s);
639 return;
640 } else if (s->snoop_state == SNOOP_STRIPING) {
641 for (i = 0; i < num_effective_busses(s); ++i) {
642 tx_rx[i] = fifo8_pop(&s->tx_fifo);
643 }
644 stripe8(tx_rx, num_effective_busses(s), false);
645 } else if ( s->snoop_state == SNOOP_NONE ||
646 s->snoop_state >= SNOOP_ADDR) {
647 tx = fifo8_pop(&s->tx_fifo);
648 for (i = 0; i < num_effective_busses(s); ++i) {
649 tx_rx[i] = tx;
650 }
651 } else {
652
653
654 tx = fifo8_pop(&s->tx_fifo);
655 dummy_cycles = 8 / s->link_state;
656 }
657
658 for (i = 0; i < num_effective_busses(s); ++i) {
659 int bus = num_effective_busses(s) - 1 - i;
660 if (dummy_cycles) {
661 int d;
662 for (d = 0; d < dummy_cycles; ++d) {
663 tx_rx[0] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[0]);
664 }
665 } else {
666 DB_PRINT_L(debug_level, "tx = %02x\n", tx_rx[i]);
667 tx_rx[i] = ssi_transfer(s->spi[bus], (uint32_t)tx_rx[i]);
668 DB_PRINT_L(debug_level, "rx = %02x\n", tx_rx[i]);
669 }
670 }
671
672 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) {
673 DB_PRINT_L(debug_level, "dircarding drained rx byte\n");
674
675 } else if (s->rx_discard) {
676 DB_PRINT_L(debug_level, "dircarding discarded rx byte\n");
677 s->rx_discard -= 8 / s->link_state;
678 } else if (fifo8_is_full(&s->rx_fifo)) {
679 s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
680 DB_PRINT_L(0, "rx FIFO overflow");
681 } else if (s->snoop_state == SNOOP_STRIPING) {
682 stripe8(tx_rx, num_effective_busses(s), true);
683 for (i = 0; i < num_effective_busses(s); ++i) {
684 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]);
685 DB_PRINT_L(debug_level, "pushing striped rx byte\n");
686 }
687 } else {
688 DB_PRINT_L(debug_level, "pushing unstriped rx byte\n");
689 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]);
690 }
691
692 if (s->link_state_next_when) {
693 s->link_state_next_when--;
694 if (!s->link_state_next_when) {
695 s->link_state = s->link_state_next;
696 }
697 }
698
699 DB_PRINT_L(debug_level, "initial snoop state: %x\n",
700 (unsigned)s->snoop_state);
701 switch (s->snoop_state) {
702 case (SNOOP_CHECKING):
703
704 s->cmd_dummies = xilinx_spips_num_dummies(q, tx);
705 addr_length = get_addr_length(s, tx);
706 if (s->cmd_dummies < 0) {
707 s->snoop_state = SNOOP_NONE;
708 } else {
709 s->snoop_state = SNOOP_ADDR + addr_length - 1;
710 }
711 switch (tx) {
712 case DPP:
713 case DOR:
714 case DOR_4:
715 s->link_state_next = 2;
716 s->link_state_next_when = addr_length + s->cmd_dummies;
717 break;
718 case QPP:
719 case QPP_4:
720 case QOR:
721 case QOR_4:
722 s->link_state_next = 4;
723 s->link_state_next_when = addr_length + s->cmd_dummies;
724 break;
725 case DIOR:
726 case DIOR_4:
727 s->link_state = 2;
728 break;
729 case QIOR:
730 case QIOR_4:
731 s->link_state = 4;
732 break;
733 }
734 break;
735 case (SNOOP_ADDR):
736
737
738 if (s->cmd_dummies < 0) {
739 s->snoop_state = SNOOP_NONE;
740 } else {
741 s->snoop_state = s->cmd_dummies;
742 }
743 break;
744 case (SNOOP_STRIPING):
745 case (SNOOP_NONE):
746
747 if (!debug_level) {
748 DB_PRINT_L(0, "squelching debug info ....\n");
749 debug_level = 1;
750 }
751 break;
752 default:
753 s->snoop_state--;
754 }
755 DB_PRINT_L(debug_level, "final snoop state: %x\n",
756 (unsigned)s->snoop_state);
757 }
758}
759
760static inline void tx_data_bytes(Fifo8 *fifo, uint32_t value, int num, bool be)
761{
762 int i;
763 for (i = 0; i < num && !fifo8_is_full(fifo); ++i) {
764 if (be) {
765 fifo8_push(fifo, (uint8_t)(value >> 24));
766 value <<= 8;
767 } else {
768 fifo8_push(fifo, (uint8_t)value);
769 value >>= 8;
770 }
771 }
772}
773
774static void xilinx_spips_check_zero_pump(XilinxSPIPS *s)
775{
776 if (!s->regs[R_TRANSFER_SIZE]) {
777 return;
778 }
779 if (!fifo8_is_empty(&s->tx_fifo) && s->regs[R_CMND] & R_CMND_PUSH_WAIT) {
780 return;
781 }
782
783
784
785
786 while (s->regs[R_TRANSFER_SIZE] &&
787 s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) {
788
789 tx_data_bytes(&s->tx_fifo, 0, 4, false);
790 s->regs[R_TRANSFER_SIZE] &= ~0x03ull;
791 s->regs[R_TRANSFER_SIZE] -= 4;
792 }
793}
794
795static void xilinx_spips_check_flush(XilinxSPIPS *s)
796{
797 if (s->man_start_com ||
798 (!fifo8_is_empty(&s->tx_fifo) &&
799 !(s->regs[R_CONFIG] & MAN_START_EN))) {
800 xilinx_spips_check_zero_pump(s);
801 xilinx_spips_flush_txfifo(s);
802 }
803 if (fifo8_is_empty(&s->tx_fifo) && !s->regs[R_TRANSFER_SIZE]) {
804 s->man_start_com = false;
805 }
806 xilinx_spips_update_ixr(s);
807}
808
809static void xlnx_zynqmp_qspips_check_flush(XlnxZynqMPQSPIPS *s)
810{
811 bool gqspi_has_work = s->regs[R_GQSPI_DATA_STS] ||
812 !fifo32_is_empty(&s->fifo_g);
813
814 if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) {
815 if (s->man_start_com_g || (gqspi_has_work &&
816 !ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE))) {
817 xlnx_zynqmp_qspips_flush_fifo_g(s);
818 }
819 } else {
820 xilinx_spips_check_flush(XILINX_SPIPS(s));
821 }
822 if (!gqspi_has_work) {
823 s->man_start_com_g = false;
824 }
825 xlnx_zynqmp_qspips_update_ixr(s);
826}
827
828static inline int rx_data_bytes(Fifo8 *fifo, uint8_t *value, int max)
829{
830 int i;
831
832 for (i = 0; i < max && !fifo8_is_empty(fifo); ++i) {
833 value[i] = fifo8_pop(fifo);
834 }
835 return max - i;
836}
837
838static const void *pop_buf(Fifo8 *fifo, uint32_t max, uint32_t *num)
839{
840 void *ret;
841
842 if (max == 0 || max > fifo->num) {
843 abort();
844 }
845 *num = MIN(fifo->capacity - fifo->head, max);
846 ret = &fifo->data[fifo->head];
847 fifo->head += *num;
848 fifo->head %= fifo->capacity;
849 fifo->num -= *num;
850 return ret;
851}
852
853static void xlnx_zynqmp_qspips_notify(void *opaque)
854{
855 XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(opaque);
856 XilinxSPIPS *s = XILINX_SPIPS(rq);
857 Fifo8 *recv_fifo;
858
859 if (ARRAY_FIELD_EX32(rq->regs, GQSPI_SELECT, GENERIC_QSPI_EN)) {
860 if (!(ARRAY_FIELD_EX32(rq->regs, GQSPI_CNFG, MODE_EN) == 2)) {
861 return;
862 }
863 recv_fifo = &rq->rx_fifo_g;
864 } else {
865 if (!(s->regs[R_CMND] & R_CMND_DMA_EN)) {
866 return;
867 }
868 recv_fifo = &s->rx_fifo;
869 }
870 while (recv_fifo->num >= 4
871 && stream_can_push(rq->dma, xlnx_zynqmp_qspips_notify, rq))
872 {
873 size_t ret;
874 uint32_t num;
875 const void *rxd;
876 int len;
877
878 len = recv_fifo->num >= rq->dma_burst_size ? rq->dma_burst_size :
879 recv_fifo->num;
880 rxd = pop_buf(recv_fifo, len, &num);
881
882 memcpy(rq->dma_buf, rxd, num);
883
884 ret = stream_push(rq->dma, rq->dma_buf, num, false);
885 assert(ret == num);
886 xlnx_zynqmp_qspips_check_flush(rq);
887 }
888}
889
890static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
891 unsigned size)
892{
893 XilinxSPIPS *s = opaque;
894 uint32_t mask = ~0;
895 uint32_t ret;
896 uint8_t rx_buf[4];
897 int shortfall;
898
899 addr >>= 2;
900 switch (addr) {
901 case R_CONFIG:
902 mask = ~(R_CONFIG_RSVD | MAN_START_COM);
903 break;
904 case R_INTR_STATUS:
905 ret = s->regs[addr] & IXR_ALL;
906 s->regs[addr] = 0;
907 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
908 xilinx_spips_update_ixr(s);
909 return ret;
910 case R_INTR_MASK:
911 mask = IXR_ALL;
912 break;
913 case R_EN:
914 mask = 0x1;
915 break;
916 case R_SLAVE_IDLE_COUNT:
917 mask = 0xFF;
918 break;
919 case R_MOD_ID:
920 mask = 0x01FFFFFF;
921 break;
922 case R_INTR_EN:
923 case R_INTR_DIS:
924 case R_TX_DATA:
925 mask = 0;
926 break;
927 case R_RX_DATA:
928 memset(rx_buf, 0, sizeof(rx_buf));
929 shortfall = rx_data_bytes(&s->rx_fifo, rx_buf, s->num_txrx_bytes);
930 ret = s->regs[R_CONFIG] & R_CONFIG_ENDIAN ?
931 cpu_to_be32(*(uint32_t *)rx_buf) :
932 cpu_to_le32(*(uint32_t *)rx_buf);
933 if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) {
934 ret <<= 8 * shortfall;
935 }
936 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
937 xilinx_spips_check_flush(s);
938 xilinx_spips_update_ixr(s);
939 return ret;
940 }
941 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4,
942 s->regs[addr] & mask);
943 return s->regs[addr] & mask;
944
945}
946
947static uint64_t xlnx_zynqmp_qspips_read(void *opaque,
948 hwaddr addr, unsigned size)
949{
950 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque);
951 uint32_t reg = addr / 4;
952 uint32_t ret;
953 uint8_t rx_buf[4];
954 int shortfall;
955
956 if (reg <= R_MOD_ID) {
957 return xilinx_spips_read(opaque, addr, size);
958 } else {
959 switch (reg) {
960 case R_GQSPI_RXD:
961 if (fifo8_is_empty(&s->rx_fifo_g)) {
962 qemu_log_mask(LOG_GUEST_ERROR,
963 "Read from empty GQSPI RX FIFO\n");
964 return 0;
965 }
966 memset(rx_buf, 0, sizeof(rx_buf));
967 shortfall = rx_data_bytes(&s->rx_fifo_g, rx_buf,
968 XILINX_SPIPS(s)->num_txrx_bytes);
969 ret = ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN) ?
970 cpu_to_be32(*(uint32_t *)rx_buf) :
971 cpu_to_le32(*(uint32_t *)rx_buf);
972 if (!ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN)) {
973 ret <<= 8 * shortfall;
974 }
975 xlnx_zynqmp_qspips_check_flush(s);
976 xlnx_zynqmp_qspips_update_ixr(s);
977 return ret;
978 default:
979 return s->regs[reg];
980 }
981 }
982}
983
984static void xilinx_spips_write(void *opaque, hwaddr addr,
985 uint64_t value, unsigned size)
986{
987 int mask = ~0;
988 XilinxSPIPS *s = opaque;
989 bool try_flush = true;
990
991 DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
992 addr >>= 2;
993 switch (addr) {
994 case R_CONFIG:
995 mask = ~(R_CONFIG_RSVD | MAN_START_COM);
996 if ((value & MAN_START_COM) && (s->regs[R_CONFIG] & MAN_START_EN)) {
997 s->man_start_com = true;
998 }
999 break;
1000 case R_INTR_STATUS:
1001 mask = IXR_ALL;
1002 s->regs[R_INTR_STATUS] &= ~(mask & value);
1003 goto no_reg_update;
1004 case R_INTR_DIS:
1005 mask = IXR_ALL;
1006 s->regs[R_INTR_MASK] &= ~(mask & value);
1007 goto no_reg_update;
1008 case R_INTR_EN:
1009 mask = IXR_ALL;
1010 s->regs[R_INTR_MASK] |= mask & value;
1011 goto no_reg_update;
1012 case R_EN:
1013 mask = 0x1;
1014 break;
1015 case R_SLAVE_IDLE_COUNT:
1016 mask = 0xFF;
1017 break;
1018 case R_RX_DATA:
1019 case R_INTR_MASK:
1020 case R_MOD_ID:
1021 mask = 0;
1022 break;
1023 case R_TX_DATA:
1024 tx_data_bytes(&s->tx_fifo, (uint32_t)value, s->num_txrx_bytes,
1025 s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
1026 goto no_reg_update;
1027 case R_TXD1:
1028 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 1,
1029 s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
1030 goto no_reg_update;
1031 case R_TXD2:
1032 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 2,
1033 s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
1034 goto no_reg_update;
1035 case R_TXD3:
1036 tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3,
1037 s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
1038 goto no_reg_update;
1039
1040 case R_GPIO:
1041 case R_LPBK_DLY_ADJ:
1042 case R_IOU_TAPDLY_BYPASS:
1043 case R_DUMMY_CYCLE_EN:
1044 case R_ECO:
1045 try_flush = false;
1046 break;
1047 }
1048 s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
1049no_reg_update:
1050 if (try_flush) {
1051 xilinx_spips_update_cs_lines(s);
1052 xilinx_spips_check_flush(s);
1053 xilinx_spips_update_cs_lines(s);
1054 xilinx_spips_update_ixr(s);
1055 }
1056}
1057
1058static const MemoryRegionOps spips_ops = {
1059 .read = xilinx_spips_read,
1060 .write = xilinx_spips_write,
1061 .endianness = DEVICE_LITTLE_ENDIAN,
1062};
1063
1064static void xilinx_qspips_invalidate_mmio_ptr(XilinxQSPIPS *q)
1065{
1066 q->lqspi_cached_addr = ~0ULL;
1067}
1068
1069static void xilinx_qspips_write(void *opaque, hwaddr addr,
1070 uint64_t value, unsigned size)
1071{
1072 XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
1073 XilinxSPIPS *s = XILINX_SPIPS(opaque);
1074
1075 uint32_t lqspi_cfg_old = s->regs[R_LQSPI_CFG];
1076
1077 xilinx_spips_write(opaque, addr, value, size);
1078 addr >>= 2;
1079
1080 if (addr == R_LQSPI_CFG &&
1081 ((lqspi_cfg_old ^ value) & ~LQSPI_CFG_U_PAGE)) {
1082 q->lqspi_cached_addr = ~0ULL;
1083 if (q->lqspi_size) {
1084 uint32_t src = q->lqspi_src;
1085 uint32_t dst = q->lqspi_dst;
1086 uint32_t btt = q->lqspi_size;
1087
1088 assert(!(btt % LQSPI_HACK_CHUNK_SIZE));
1089 fprintf(stderr, "QEMU: Syncing LQSPI - this may be slow "
1090 "(1 \".\" / MByte):");
1091
1092 while (btt) {
1093 uint8_t lqspi_hack_buf[LQSPI_HACK_CHUNK_SIZE];
1094 dma_memory_read(q->hack_as, src, lqspi_hack_buf,
1095 LQSPI_HACK_CHUNK_SIZE);
1096 dma_memory_write(q->hack_as, dst, lqspi_hack_buf,
1097 LQSPI_HACK_CHUNK_SIZE);
1098 fprintf(stderr, ".");
1099 btt -= LQSPI_HACK_CHUNK_SIZE;
1100 src += LQSPI_HACK_CHUNK_SIZE;
1101 dst += LQSPI_HACK_CHUNK_SIZE;
1102 }
1103 fprintf(stderr, "\n");
1104 }
1105 }
1106 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) {
1107 fifo8_reset(&s->rx_fifo);
1108 }
1109 if (s->regs[R_CMND] & R_CMND_RXFIFO_DRAIN) {
1110 fifo8_reset(&s->rx_fifo);
1111 }
1112}
1113
1114static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr,
1115 uint64_t value, unsigned size)
1116{
1117 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(opaque);
1118 uint32_t reg = addr / 4;
1119
1120 if (reg <= R_MOD_ID) {
1121 xilinx_qspips_write(opaque, addr, value, size);
1122 } else {
1123 switch (reg) {
1124 case R_GQSPI_CNFG:
1125 if (FIELD_EX32(value, GQSPI_CNFG, GEN_FIFO_START) &&
1126 ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, GEN_FIFO_START_MODE)) {
1127 s->man_start_com_g = true;
1128 }
1129 s->regs[reg] = value & ~(R_GQSPI_CNFG_GEN_FIFO_START_MASK);
1130 break;
1131 case R_GQSPI_GEN_FIFO:
1132 if (!fifo32_is_full(&s->fifo_g)) {
1133 fifo32_push(&s->fifo_g, value);
1134 }
1135 break;
1136 case R_GQSPI_TXD:
1137 tx_data_bytes(&s->tx_fifo_g, (uint32_t)value, 4,
1138 ARRAY_FIELD_EX32(s->regs, GQSPI_CNFG, ENDIAN));
1139 break;
1140 case R_GQSPI_FIFO_CTRL:
1141 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET)) {
1142 fifo32_reset(&s->fifo_g);
1143 }
1144 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, TX_FIFO_RESET)) {
1145 fifo8_reset(&s->tx_fifo_g);
1146 }
1147 if (FIELD_EX32(value, GQSPI_FIFO_CTRL, RX_FIFO_RESET)) {
1148 fifo8_reset(&s->rx_fifo_g);
1149 }
1150 break;
1151 case R_GQSPI_IDR:
1152 s->regs[R_GQSPI_IMR] |= value;
1153 break;
1154 case R_GQSPI_IER:
1155 s->regs[R_GQSPI_IMR] &= ~value;
1156 break;
1157 case R_GQSPI_ISR:
1158 s->regs[R_GQSPI_ISR] &= ~value;
1159 break;
1160 case R_GQSPI_IMR:
1161 case R_GQSPI_RXD:
1162 case R_GQSPI_GF_SNAPSHOT:
1163 case R_GQSPI_MOD_ID:
1164 break;
1165 default:
1166 s->regs[reg] = value;
1167 break;
1168 }
1169 xlnx_zynqmp_qspips_update_cs_lines(s);
1170 xlnx_zynqmp_qspips_check_flush(s);
1171 xlnx_zynqmp_qspips_update_cs_lines(s);
1172 xlnx_zynqmp_qspips_update_ixr(s);
1173 }
1174 xlnx_zynqmp_qspips_notify(s);
1175}
1176
1177static const MemoryRegionOps qspips_ops = {
1178 .read = xilinx_spips_read,
1179 .write = xilinx_qspips_write,
1180 .endianness = DEVICE_LITTLE_ENDIAN,
1181};
1182
1183static const MemoryRegionOps xlnx_zynqmp_qspips_ops = {
1184 .read = xlnx_zynqmp_qspips_read,
1185 .write = xlnx_zynqmp_qspips_write,
1186 .endianness = DEVICE_LITTLE_ENDIAN,
1187};
1188
1189#define LQSPI_CACHE_SIZE 1024
1190
1191static void lqspi_load_cache(void *opaque, hwaddr addr)
1192{
1193 XilinxQSPIPS *q = opaque;
1194 XilinxSPIPS *s = opaque;
1195 int i;
1196 int flash_addr = ((addr & ~(LQSPI_CACHE_SIZE - 1))
1197 / num_effective_busses(s));
1198 int slave = flash_addr >> LQSPI_ADDRESS_BITS;
1199 int cache_entry = 0;
1200 uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE;
1201
1202 if (addr < q->lqspi_cached_addr ||
1203 addr >= q->lqspi_cached_addr + LQSPI_CACHE_SIZE) {
1204 xilinx_qspips_invalidate_mmio_ptr(q);
1205 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
1206 s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0;
1207
1208 DB_PRINT_L(0, "config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
1209
1210 fifo8_reset(&s->tx_fifo);
1211 fifo8_reset(&s->rx_fifo);
1212
1213
1214 DB_PRINT_L(0, "pushing read instruction: %02x\n",
1215 (unsigned)(uint8_t)(s->regs[R_LQSPI_CFG] &
1216 LQSPI_CFG_INST_CODE));
1217 fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
1218
1219 DB_PRINT_L(0, "pushing read address %06x\n", flash_addr);
1220 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) {
1221 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24));
1222 }
1223 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
1224 fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
1225 fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
1226
1227 if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
1228 fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
1229 LQSPI_CFG_MODE_SHIFT,
1230 LQSPI_CFG_MODE_WIDTH));
1231 }
1232
1233 for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
1234 LQSPI_CFG_DUMMY_WIDTH)); ++i) {
1235 DB_PRINT_L(0, "pushing dummy byte\n");
1236 fifo8_push(&s->tx_fifo, 0);
1237 }
1238 xilinx_spips_update_cs_lines(s);
1239 xilinx_spips_flush_txfifo(s);
1240 fifo8_reset(&s->rx_fifo);
1241
1242 DB_PRINT_L(0, "starting QSPI data read\n");
1243
1244 while (cache_entry < LQSPI_CACHE_SIZE) {
1245 for (i = 0; i < 64; ++i) {
1246 tx_data_bytes(&s->tx_fifo, 0, 1, false);
1247 }
1248 xilinx_spips_flush_txfifo(s);
1249 for (i = 0; i < 64; ++i) {
1250 rx_data_bytes(&s->rx_fifo, &q->lqspi_buf[cache_entry++], 1);
1251 }
1252 }
1253
1254 s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
1255 s->regs[R_LQSPI_STS] |= u_page_save;
1256 xilinx_spips_update_cs_lines(s);
1257
1258 q->lqspi_cached_addr = flash_addr * num_effective_busses(s);
1259 }
1260}
1261
1262static MemTxResult lqspi_read(void *opaque, hwaddr addr, uint64_t *value,
1263 unsigned size, MemTxAttrs attrs)
1264{
1265 XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
1266
1267 if (addr >= q->lqspi_cached_addr &&
1268 addr < q->lqspi_cached_addr + LQSPI_CACHE_SIZE) {
1269 uint8_t *retp = &q->lqspi_buf[addr - q->lqspi_cached_addr];
1270 if (size == 1) {
1271 *value = *retp;
1272 } else if (size == 2) {
1273 *value = cpu_to_le16(*(uint16_t *)retp);
1274 } else {
1275 *value = cpu_to_le32(*(uint32_t *)retp);
1276 }
1277 DB_PRINT_L(1, "addr: %08" HWADDR_PRIx ", data: %08" PRIx64 "\n",
1278 addr, *value);
1279 return MEMTX_OK;
1280 }
1281
1282 lqspi_load_cache(opaque, addr);
1283 return lqspi_read(opaque, addr, value, size, attrs);
1284}
1285
1286static MemTxResult lqspi_write(void *opaque, hwaddr offset, uint64_t value,
1287 unsigned size, MemTxAttrs attrs)
1288{
1289
1290
1291
1292
1293
1294 qemu_log_mask(LOG_GUEST_ERROR, "%s Unexpected %u-bit access to 0x%" PRIx64
1295 " (value: 0x%" PRIx64 "\n",
1296 __func__, size << 3, offset, value);
1297
1298 return MEMTX_ERROR;
1299}
1300
1301static const MemoryRegionOps lqspi_ops = {
1302 .read_with_attrs = lqspi_read,
1303 .write_with_attrs = lqspi_write,
1304 .endianness = DEVICE_NATIVE_ENDIAN,
1305 .impl = {
1306 .min_access_size = 1,
1307 .max_access_size = 4,
1308 },
1309 .valid = {
1310 .min_access_size = 1,
1311 .max_access_size = 4
1312 }
1313};
1314
1315static void xilinx_spips_realize(DeviceState *dev, Error **errp)
1316{
1317 XilinxSPIPS *s = XILINX_SPIPS(dev);
1318 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1319 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
1320 qemu_irq *cs;
1321 int i;
1322
1323 DB_PRINT_L(0, "realized spips\n");
1324
1325 if (s->num_busses > MAX_NUM_BUSSES) {
1326 error_setg(errp,
1327 "requested number of SPI busses %u exceeds maximum %d",
1328 s->num_busses, MAX_NUM_BUSSES);
1329 return;
1330 }
1331 if (s->num_busses < MIN_NUM_BUSSES) {
1332 error_setg(errp,
1333 "requested number of SPI busses %u is below minimum %d",
1334 s->num_busses, MIN_NUM_BUSSES);
1335 return;
1336 }
1337
1338 s->spi = g_new(SSIBus *, s->num_busses);
1339 for (i = 0; i < s->num_busses; ++i) {
1340 char bus_name[16];
1341 snprintf(bus_name, 16, "spi%d", i);
1342 s->spi[i] = ssi_create_bus(dev, bus_name);
1343 }
1344
1345 s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
1346 s->cs_lines_state = g_new0(bool, s->num_cs * s->num_busses);
1347 for (i = 0, cs = s->cs_lines; i < s->num_busses; ++i, cs += s->num_cs) {
1348 ssi_auto_connect_slaves(DEVICE(s), cs, s->spi[i]);
1349 }
1350
1351 sysbus_init_irq(sbd, &s->irq);
1352 qdev_init_gpio_out(dev, s->cs_lines, s->num_cs * s->num_busses);
1353
1354 memory_region_init_io(&s->iomem, OBJECT(s), xsc->reg_ops, s,
1355 "spi", XLNX_ZYNQMP_SPIPS_R_MAX * 4);
1356 sysbus_init_mmio(sbd, &s->iomem);
1357
1358 s->irqline = -1;
1359
1360 fifo8_create(&s->rx_fifo, xsc->rx_fifo_size);
1361 fifo8_create(&s->tx_fifo, xsc->tx_fifo_size);
1362}
1363
1364static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
1365{
1366 XilinxSPIPS *s = XILINX_SPIPS(dev);
1367 XilinxQSPIPS *q = XILINX_QSPIPS(dev);
1368 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1369
1370 DB_PRINT_L(0, "realized qspips\n");
1371
1372 s->num_busses = 2;
1373 s->num_cs = 2;
1374 s->num_txrx_bytes = 4;
1375
1376 xilinx_spips_realize(dev, errp);
1377 q->hack_as = q->hack_dma ? address_space_init_shareable(q->hack_dma,
1378 NULL) : &address_space_memory;
1379 memory_region_init_io(&s->mmlqspi, OBJECT(s), &lqspi_ops, s, "lqspi",
1380 (1 << LQSPI_ADDRESS_BITS) * 2);
1381 sysbus_init_mmio(sbd, &s->mmlqspi);
1382
1383 q->lqspi_cached_addr = ~0ULL;
1384}
1385
1386static void xlnx_zynqmp_qspips_realize(DeviceState *dev, Error **errp)
1387{
1388 XlnxZynqMPQSPIPS *s = XLNX_ZYNQMP_QSPIPS(dev);
1389 XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
1390
1391 if (s->dma_burst_size > QSPI_DMA_MAX_BURST_SIZE) {
1392 error_setg(errp,
1393 "qspi dma burst size %u exceeds maximum limit %d",
1394 s->dma_burst_size, QSPI_DMA_MAX_BURST_SIZE);
1395 return;
1396 }
1397 xilinx_qspips_realize(dev, errp);
1398 fifo8_create(&s->rx_fifo_g, xsc->rx_fifo_size);
1399 fifo8_create(&s->tx_fifo_g, xsc->tx_fifo_size);
1400 fifo32_create(&s->fifo_g, 32);
1401}
1402
1403static void xlnx_zynqmp_qspips_init(Object *obj)
1404{
1405 XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj);
1406
1407 object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE,
1408 (Object **)&rq->dma,
1409 object_property_allow_set_link,
1410 OBJ_PROP_LINK_STRONG);
1411}
1412
1413static int xilinx_spips_post_load(void *opaque, int version_id)
1414{
1415 xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
1416 xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
1417 return 0;
1418}
1419
1420static const VMStateDescription vmstate_xilinx_spips = {
1421 .name = "xilinx_spips",
1422 .version_id = 2,
1423 .minimum_version_id = 2,
1424 .post_load = xilinx_spips_post_load,
1425 .fields = (VMStateField[]) {
1426 VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
1427 VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
1428 VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, XLNX_SPIPS_R_MAX),
1429 VMSTATE_UINT8(snoop_state, XilinxSPIPS),
1430 VMSTATE_END_OF_LIST()
1431 }
1432};
1433
1434static int xlnx_zynqmp_qspips_post_load(void *opaque, int version_id)
1435{
1436 XlnxZynqMPQSPIPS *s = (XlnxZynqMPQSPIPS *)opaque;
1437 XilinxSPIPS *qs = XILINX_SPIPS(s);
1438
1439 if (ARRAY_FIELD_EX32(s->regs, GQSPI_SELECT, GENERIC_QSPI_EN) &&
1440 fifo8_is_empty(&qs->rx_fifo) && fifo8_is_empty(&qs->tx_fifo)) {
1441 xlnx_zynqmp_qspips_update_ixr(s);
1442 xlnx_zynqmp_qspips_update_cs_lines(s);
1443 }
1444 return 0;
1445}
1446
1447static const VMStateDescription vmstate_xilinx_qspips = {
1448 .name = "xilinx_qspips",
1449 .version_id = 1,
1450 .minimum_version_id = 1,
1451 .fields = (VMStateField[]) {
1452 VMSTATE_STRUCT(parent_obj, XilinxQSPIPS, 0,
1453 vmstate_xilinx_spips, XilinxSPIPS),
1454 VMSTATE_END_OF_LIST()
1455 }
1456};
1457
1458static const VMStateDescription vmstate_xlnx_zynqmp_qspips = {
1459 .name = "xlnx_zynqmp_qspips",
1460 .version_id = 1,
1461 .minimum_version_id = 1,
1462 .post_load = xlnx_zynqmp_qspips_post_load,
1463 .fields = (VMStateField[]) {
1464 VMSTATE_STRUCT(parent_obj, XlnxZynqMPQSPIPS, 0,
1465 vmstate_xilinx_qspips, XilinxQSPIPS),
1466 VMSTATE_FIFO8(tx_fifo_g, XlnxZynqMPQSPIPS),
1467 VMSTATE_FIFO8(rx_fifo_g, XlnxZynqMPQSPIPS),
1468 VMSTATE_FIFO32(fifo_g, XlnxZynqMPQSPIPS),
1469 VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPQSPIPS, XLNX_ZYNQMP_SPIPS_R_MAX),
1470 VMSTATE_END_OF_LIST()
1471 }
1472};
1473
1474static Property xilinx_zynqmp_qspips_properties[] = {
1475 DEFINE_PROP_UINT32("dma-burst-size", XlnxZynqMPQSPIPS, dma_burst_size, 64),
1476 DEFINE_PROP_END_OF_LIST(),
1477};
1478
1479static Property xilinx_qspips_properties[] = {
1480 DEFINE_PROP_UINT32("lqspi-size", XilinxQSPIPS, lqspi_size, 0),
1481 DEFINE_PROP_UINT32("lqspi-src", XilinxQSPIPS, lqspi_src, 0),
1482 DEFINE_PROP_UINT32("lqspi-dst", XilinxQSPIPS, lqspi_dst, 0),
1483
1484
1485
1486
1487 DEFINE_PROP_BOOL("x-mmio-exec", XilinxQSPIPS, mmio_execution_enabled,
1488 false),
1489 DEFINE_PROP_END_OF_LIST(),
1490};
1491
1492static Property xilinx_spips_properties[] = {
1493 DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
1494 DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
1495 DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
1496 DEFINE_PROP_END_OF_LIST(),
1497};
1498
1499static void xilinx_qspips_init(Object *obj)
1500{
1501 XilinxQSPIPS *q = XILINX_QSPIPS(obj);
1502
1503 object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
1504 (Object **)&q->hack_dma,
1505 qdev_prop_allow_set_link_before_realize,
1506 OBJ_PROP_LINK_STRONG);
1507}
1508
1509static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
1510{
1511 DeviceClass *dc = DEVICE_CLASS(klass);
1512 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
1513
1514 dc->realize = xilinx_qspips_realize;
1515 device_class_set_props(dc, xilinx_qspips_properties);
1516 xsc->reg_ops = &qspips_ops;
1517 xsc->rx_fifo_size = RXFF_A_Q;
1518 xsc->tx_fifo_size = TXFF_A_Q;
1519}
1520
1521static void xilinx_spips_class_init(ObjectClass *klass, void *data)
1522{
1523 DeviceClass *dc = DEVICE_CLASS(klass);
1524 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
1525
1526 dc->realize = xilinx_spips_realize;
1527 dc->reset = xilinx_spips_reset;
1528 device_class_set_props(dc, xilinx_spips_properties);
1529 dc->vmsd = &vmstate_xilinx_spips;
1530
1531 xsc->reg_ops = &spips_ops;
1532 xsc->rx_fifo_size = RXFF_A;
1533 xsc->tx_fifo_size = TXFF_A;
1534}
1535
1536static void xlnx_zynqmp_qspips_class_init(ObjectClass *klass, void * data)
1537{
1538 DeviceClass *dc = DEVICE_CLASS(klass);
1539 XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
1540
1541 dc->realize = xlnx_zynqmp_qspips_realize;
1542 dc->reset = xlnx_zynqmp_qspips_reset;
1543 dc->vmsd = &vmstate_xlnx_zynqmp_qspips;
1544 device_class_set_props(dc, xilinx_zynqmp_qspips_properties);
1545 xsc->reg_ops = &xlnx_zynqmp_qspips_ops;
1546 xsc->rx_fifo_size = RXFF_A_Q;
1547 xsc->tx_fifo_size = TXFF_A_Q;
1548}
1549
1550static const TypeInfo xilinx_spips_info = {
1551 .name = TYPE_XILINX_SPIPS,
1552 .parent = TYPE_SYS_BUS_DEVICE,
1553 .instance_size = sizeof(XilinxSPIPS),
1554 .class_init = xilinx_spips_class_init,
1555 .class_size = sizeof(XilinxSPIPSClass),
1556};
1557
1558static const TypeInfo xilinx_qspips_info = {
1559 .name = TYPE_XILINX_QSPIPS,
1560 .parent = TYPE_XILINX_SPIPS,
1561 .instance_size = sizeof(XilinxQSPIPS),
1562 .class_init = xilinx_qspips_class_init,
1563 .instance_init = xilinx_qspips_init,
1564};
1565
1566static const TypeInfo xlnx_zynqmp_qspips_info = {
1567 .name = TYPE_XLNX_ZYNQMP_QSPIPS,
1568 .parent = TYPE_XILINX_QSPIPS,
1569 .instance_size = sizeof(XlnxZynqMPQSPIPS),
1570 .instance_init = xlnx_zynqmp_qspips_init,
1571 .class_init = xlnx_zynqmp_qspips_class_init,
1572};
1573
1574static void xilinx_spips_register_types(void)
1575{
1576 type_register_static(&xilinx_spips_info);
1577 type_register_static(&xilinx_qspips_info);
1578 type_register_static(&xlnx_zynqmp_qspips_info);
1579}
1580
1581type_init(xilinx_spips_register_types)
1582
