1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#ifndef ARM_CPU_H
21#define ARM_CPU_H
22
23#include "kvm-consts.h"
24#include "hw/registerfields.h"
25#include "cpu-qom.h"
26#include "exec/cpu-defs.h"
27
28
29#define TCG_GUEST_DEFAULT_MO (0)
30
31#ifdef TARGET_AARCH64
32#define KVM_HAVE_MCE_INJECTION 1
33#endif
34
35#define EXCP_UDEF 1
36#define EXCP_SWI 2
37#define EXCP_PREFETCH_ABORT 3
38#define EXCP_DATA_ABORT 4
39#define EXCP_IRQ 5
40#define EXCP_FIQ 6
41#define EXCP_BKPT 7
42#define EXCP_EXCEPTION_EXIT 8
43#define EXCP_KERNEL_TRAP 9
44#define EXCP_HVC 11
45#define EXCP_HYP_TRAP 12
46#define EXCP_SMC 13
47#define EXCP_VIRQ 14
48#define EXCP_VFIQ 15
49#define EXCP_SEMIHOST 16
50#define EXCP_NOCP 17
51#define EXCP_INVSTATE 18
52#define EXCP_STKOF 19
53#define EXCP_LAZYFP 20
54#define EXCP_LSERR 21
55#define EXCP_UNALIGNED 22
56
57
58#define ARMV7M_EXCP_RESET 1
59#define ARMV7M_EXCP_NMI 2
60#define ARMV7M_EXCP_HARD 3
61#define ARMV7M_EXCP_MEM 4
62#define ARMV7M_EXCP_BUS 5
63#define ARMV7M_EXCP_USAGE 6
64#define ARMV7M_EXCP_SECURE 7
65#define ARMV7M_EXCP_SVC 11
66#define ARMV7M_EXCP_DEBUG 12
67#define ARMV7M_EXCP_PENDSV 14
68#define ARMV7M_EXCP_SYSTICK 15
69
70
71
72
73
74
75
76
77
78
79enum {
80 M_REG_NS = 0,
81 M_REG_S = 1,
82 M_REG_NUM_BANKS = 2,
83};
84
85
86#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
87#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
88#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
89
90
91
92
93
94
95
96#ifdef HOST_WORDS_BIGENDIAN
97#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
98#define offsetofhigh32(S, M) offsetof(S, M)
99#else
100#define offsetoflow32(S, M) offsetof(S, M)
101#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
102#endif
103
104
105#define ARM_CPU_IRQ 0
106#define ARM_CPU_FIQ 1
107#define ARM_CPU_VIRQ 2
108#define ARM_CPU_VFIQ 3
109
110#undef NB_MEM_ATTR
111#define NB_MEM_ATTR 2
112#define MEM_ATTR_NS 0
113#define MEM_ATTR_SEC 1
114
115
116
117
118
119#define TARGET_INSN_START_EXTRA_WORDS 2
120
121
122
123
124
125
126#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
127#define ARM_INSN_START_WORD2_SHIFT 14
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146typedef struct DynamicGDBXMLInfo {
147 char *desc;
148 int num;
149 union {
150 struct {
151 uint32_t *keys;
152 } cpregs;
153 } data;
154} DynamicGDBXMLInfo;
155
156
157typedef struct ARMGenericTimer {
158 uint64_t cval;
159 uint64_t ctl;
160} ARMGenericTimer;
161
162#define GTIMER_PHYS 0
163#define GTIMER_VIRT 1
164#define GTIMER_HYP 2
165#define GTIMER_SEC 3
166#define GTIMER_HYPVIRT 4
167#define NUM_GTIMERS 5
168
169typedef struct {
170 uint64_t raw_tcr;
171 uint32_t mask;
172 uint32_t base_mask;
173} TCR;
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201#ifdef TARGET_AARCH64
202# define ARM_MAX_VQ 16
203void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
204#else
205# define ARM_MAX_VQ 1
206static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
207#endif
208
209typedef struct ARMVectorReg {
210 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
211} ARMVectorReg;
212
213#ifdef TARGET_AARCH64
214
215typedef struct ARMPredicateReg {
216 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
217} ARMPredicateReg;
218
219
220typedef struct ARMPACKey {
221 uint64_t lo, hi;
222} ARMPACKey;
223#endif
224
225
226typedef struct CPUARMState {
227
228 uint32_t regs[16];
229
230
231
232
233
234
235 uint64_t xregs[32];
236 uint64_t pc;
237
238
239
240
241
242
243
244
245
246
247
248
249 uint32_t pstate;
250 uint32_t aarch64;
251
252
253 uint32_t hflags;
254
255
256
257
258 uint32_t uncached_cpsr;
259 uint32_t spsr;
260
261
262 uint64_t banked_spsr[8];
263 uint32_t banked_r13[8];
264 uint32_t banked_r14[8];
265
266
267 uint32_t usr_regs[5];
268 uint32_t fiq_regs[5];
269
270
271 uint32_t CF;
272 uint32_t VF;
273 uint32_t NF;
274 uint32_t ZF;
275 uint32_t QF;
276 uint32_t GE;
277 uint32_t thumb;
278 uint32_t condexec_bits;
279 uint32_t btype;
280 uint64_t daif;
281
282 uint64_t elr_el[4];
283 uint64_t sp_el[4];
284
285
286 struct {
287 uint32_t c0_cpuid;
288 union {
289 struct {
290 uint64_t _unused_csselr0;
291 uint64_t csselr_ns;
292 uint64_t _unused_csselr1;
293 uint64_t csselr_s;
294 };
295 uint64_t csselr_el[4];
296 };
297 union {
298 struct {
299 uint64_t _unused_sctlr;
300 uint64_t sctlr_ns;
301 uint64_t hsctlr;
302 uint64_t sctlr_s;
303 };
304 uint64_t sctlr_el[4];
305 };
306 uint64_t cpacr_el1;
307 uint64_t cptr_el[4];
308 uint32_t c1_xscaleauxcr;
309 uint64_t sder;
310 uint32_t nsacr;
311 union {
312 struct {
313 uint64_t _unused_ttbr0_0;
314 uint64_t ttbr0_ns;
315 uint64_t _unused_ttbr0_1;
316 uint64_t ttbr0_s;
317 };
318 uint64_t ttbr0_el[4];
319 };
320 union {
321 struct {
322 uint64_t _unused_ttbr1_0;
323 uint64_t ttbr1_ns;
324 uint64_t _unused_ttbr1_1;
325 uint64_t ttbr1_s;
326 };
327 uint64_t ttbr1_el[4];
328 };
329 uint64_t vttbr_el2;
330
331 TCR tcr_el[4];
332 TCR vtcr_el2;
333 uint32_t c2_data;
334 uint32_t c2_insn;
335 union {
336
337
338 struct {
339 uint64_t dacr_ns;
340 uint64_t dacr_s;
341 };
342 struct {
343 uint64_t dacr32_el2;
344 };
345 };
346 uint32_t pmsav5_data_ap;
347 uint32_t pmsav5_insn_ap;
348 uint64_t hcr_el2;
349 uint64_t scr_el3;
350 union {
351 struct {
352 uint64_t ifsr_ns;
353 uint64_t ifsr_s;
354 };
355 struct {
356 uint64_t ifsr32_el2;
357 };
358 };
359 union {
360 struct {
361 uint64_t _unused_dfsr;
362 uint64_t dfsr_ns;
363 uint64_t hsr;
364 uint64_t dfsr_s;
365 };
366 uint64_t esr_el[4];
367 };
368 uint32_t c6_region[8];
369 union {
370 struct {
371 uint64_t _unused_far0;
372#ifdef HOST_WORDS_BIGENDIAN
373 uint32_t ifar_ns;
374 uint32_t dfar_ns;
375 uint32_t ifar_s;
376 uint32_t dfar_s;
377#else
378 uint32_t dfar_ns;
379 uint32_t ifar_ns;
380 uint32_t dfar_s;
381 uint32_t ifar_s;
382#endif
383 uint64_t _unused_far3;
384 };
385 uint64_t far_el[4];
386 };
387 uint64_t hpfar_el2;
388 uint64_t hstr_el2;
389 union {
390 struct {
391 uint64_t _unused_par_0;
392 uint64_t par_ns;
393 uint64_t _unused_par_1;
394 uint64_t par_s;
395 };
396 uint64_t par_el[4];
397 };
398
399 uint32_t c9_insn;
400 uint32_t c9_data;
401 uint64_t c9_pmcr;
402 uint64_t c9_pmcnten;
403 uint64_t c9_pmovsr;
404 uint64_t c9_pmuserenr;
405 uint64_t c9_pmselr;
406 uint64_t c9_pminten;
407 uint32_t c9_pmxevtyper;
408 union {
409 struct {
410#ifdef HOST_WORDS_BIGENDIAN
411 uint64_t _unused_mair_0;
412 uint32_t mair1_ns;
413 uint32_t mair0_ns;
414 uint64_t _unused_mair_1;
415 uint32_t mair1_s;
416 uint32_t mair0_s;
417#else
418 uint64_t _unused_mair_0;
419 uint32_t mair0_ns;
420 uint32_t mair1_ns;
421 uint64_t _unused_mair_1;
422 uint32_t mair0_s;
423 uint32_t mair1_s;
424#endif
425 };
426 uint64_t mair_el[4];
427 };
428 union {
429 struct {
430 uint64_t _unused_vbar;
431 uint64_t vbar_ns;
432 uint64_t hvbar;
433 uint64_t vbar_s;
434 };
435 uint64_t vbar_el[4];
436 };
437 uint32_t mvbar;
438 struct {
439 uint32_t fcseidr_ns;
440 uint32_t fcseidr_s;
441 };
442 union {
443 struct {
444 uint64_t _unused_contextidr_0;
445 uint64_t contextidr_ns;
446 uint64_t _unused_contextidr_1;
447 uint64_t contextidr_s;
448 };
449 uint64_t contextidr_el[4];
450 };
451 union {
452 struct {
453 uint64_t tpidrurw_ns;
454 uint64_t tpidrprw_ns;
455 uint64_t htpidr;
456 uint64_t _tpidr_el3;
457 };
458 uint64_t tpidr_el[4];
459 };
460
461 uint64_t tpidrurw_s;
462 uint64_t tpidrprw_s;
463 uint64_t tpidruro_s;
464
465 union {
466 uint64_t tpidruro_ns;
467 uint64_t tpidrro_el[1];
468 };
469 uint64_t c14_cntfrq;
470 uint64_t c14_cntkctl;
471 uint32_t cnthctl_el2;
472 uint64_t cntvoff_el2;
473 ARMGenericTimer c14_timer[NUM_GTIMERS];
474 uint32_t c15_cpar;
475 uint32_t c15_ticonfig;
476 uint32_t c15_i_max;
477 uint32_t c15_i_min;
478 uint32_t c15_threadid;
479 uint32_t c15_config_base_address;
480 uint32_t c15_diagnostic;
481 uint32_t c15_power_diagnostic;
482 uint32_t c15_power_control;
483 uint64_t dbgbvr[16];
484 uint64_t dbgbcr[16];
485 uint64_t dbgwvr[16];
486 uint64_t dbgwcr[16];
487 uint64_t mdscr_el1;
488 uint64_t oslsr_el1;
489 uint64_t mdcr_el2;
490 uint64_t mdcr_el3;
491
492
493
494
495
496 uint64_t c15_ccnt;
497
498
499
500
501
502
503
504 uint64_t c15_ccnt_delta;
505 uint64_t c14_pmevcntr[31];
506 uint64_t c14_pmevcntr_delta[31];
507 uint64_t c14_pmevtyper[31];
508 uint64_t pmccfiltr_el0;
509 uint64_t vpidr_el2;
510 uint64_t vmpidr_el2;
511 } cp15;
512
513 struct {
514
515
516
517
518
519
520
521
522
523
524
525 uint32_t other_sp;
526 uint32_t other_ss_msp;
527 uint32_t other_ss_psp;
528 uint32_t vecbase[M_REG_NUM_BANKS];
529 uint32_t basepri[M_REG_NUM_BANKS];
530 uint32_t control[M_REG_NUM_BANKS];
531 uint32_t ccr[M_REG_NUM_BANKS];
532 uint32_t cfsr[M_REG_NUM_BANKS];
533 uint32_t hfsr;
534 uint32_t dfsr;
535 uint32_t sfsr;
536 uint32_t mmfar[M_REG_NUM_BANKS];
537 uint32_t bfar;
538 uint32_t sfar;
539 unsigned mpu_ctrl[M_REG_NUM_BANKS];
540 int exception;
541 uint32_t primask[M_REG_NUM_BANKS];
542 uint32_t faultmask[M_REG_NUM_BANKS];
543 uint32_t aircr;
544 uint32_t secure;
545 uint32_t csselr[M_REG_NUM_BANKS];
546 uint32_t scr[M_REG_NUM_BANKS];
547 uint32_t msplim[M_REG_NUM_BANKS];
548 uint32_t psplim[M_REG_NUM_BANKS];
549 uint32_t fpcar[M_REG_NUM_BANKS];
550 uint32_t fpccr[M_REG_NUM_BANKS];
551 uint32_t fpdscr[M_REG_NUM_BANKS];
552 uint32_t cpacr[M_REG_NUM_BANKS];
553 uint32_t nsacr;
554 } v7m;
555
556
557
558
559
560
561
562 struct {
563 uint32_t syndrome;
564 uint32_t fsr;
565 uint64_t vaddress;
566 uint32_t target_el;
567
568
569
570 } exception;
571
572
573 struct {
574 uint8_t pending;
575 uint8_t has_esr;
576 uint64_t esr;
577 } serror;
578
579
580 uint32_t irq_line_state;
581
582
583 uint32_t teecr;
584 uint32_t teehbr;
585
586
587 struct {
588 ARMVectorReg zregs[32];
589
590#ifdef TARGET_AARCH64
591
592#define FFR_PRED_NUM 16
593 ARMPredicateReg pregs[17];
594
595 ARMPredicateReg preg_tmp;
596#endif
597
598
599 uint32_t qc[4] QEMU_ALIGNED(16);
600 int vec_len;
601 int vec_stride;
602
603 uint32_t xregs[16];
604
605
606 uint32_t scratch[8];
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629 float_status fp_status;
630 float_status fp_status_f16;
631 float_status standard_fp_status;
632
633
634 uint64_t zcr_el[4];
635 } vfp;
636 uint64_t exclusive_addr;
637 uint64_t exclusive_val;
638 uint64_t exclusive_high;
639
640 uint32_t debug_ctx;
641
642
643 struct {
644 uint64_t regs[16];
645 uint64_t val;
646
647 uint32_t cregs[16];
648 } iwmmxt;
649
650#ifdef TARGET_AARCH64
651 struct {
652 ARMPACKey apia;
653 ARMPACKey apib;
654 ARMPACKey apda;
655 ARMPACKey apdb;
656 ARMPACKey apga;
657 } keys;
658#endif
659
660#if defined(CONFIG_USER_ONLY)
661
662 int eabi;
663#endif
664
665 struct CPUBreakpoint *cpu_breakpoint[16];
666 struct CPUWatchpoint *cpu_watchpoint[16];
667
668
669 struct {} end_reset_fields;
670
671
672 bool irq_wires[4];
673
674
675 uint64_t features;
676
677
678 bool vinithi;
679
680
681 struct {
682 uint32_t *drbar;
683 uint32_t *drsr;
684 uint32_t *dracr;
685 uint32_t rnr[M_REG_NUM_BANKS];
686 } pmsav7;
687
688 MemTxAttrs *memattr_ns;
689 MemTxAttrs *memattr_s;
690
691
692 struct {
693
694
695
696
697
698 uint32_t *rbar[M_REG_NUM_BANKS];
699 uint32_t *rlar[M_REG_NUM_BANKS];
700 uint32_t mair0[M_REG_NUM_BANKS];
701 uint32_t mair1[M_REG_NUM_BANKS];
702 } pmsav8;
703
704
705 struct {
706 uint32_t *rbar;
707 uint32_t *rlar;
708 uint32_t rnr;
709 uint32_t ctrl;
710 } sau;
711
712 void *nvic;
713 const struct arm_boot_info *boot_info;
714
715 void *gicv3state;
716} CPUARMState;
717
718enum {
719 DEBUG_CURRENT_EL = 0,
720 DEBUG_EL0 = 1,
721 DEBUG_EL1 = 2,
722 DEBUG_EL2 = 3,
723 DEBUG_EL3 = 4,
724 DEBUG_PHYS = 5,
725};
726
727static inline void set_feature(CPUARMState *env, int feature)
728{
729 env->features |= 1ULL << feature;
730}
731
732static inline void unset_feature(CPUARMState *env, int feature)
733{
734 env->features &= ~(1ULL << feature);
735}
736
737
738
739
740
741
742typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
743typedef struct ARMELChangeHook ARMELChangeHook;
744struct ARMELChangeHook {
745 ARMELChangeHookFn *hook;
746 void *opaque;
747 QLIST_ENTRY(ARMELChangeHook) node;
748};
749
750
751
752typedef enum ARMPSCIState {
753 PSCI_ON = 0,
754 PSCI_OFF = 1,
755 PSCI_ON_PENDING = 2
756} ARMPSCIState;
757
758typedef struct ARMISARegisters ARMISARegisters;
759
760
761
762
763
764
765
766struct ARMCPU {
767
768 CPUState parent_obj;
769
770
771 CPUNegativeOffsetState neg;
772 CPUARMState env;
773
774 bool is_in_wfi;
775
776
777 GHashTable *cp_regs;
778
779
780
781
782
783
784
785 uint64_t *cpreg_indexes;
786
787 uint64_t *cpreg_values;
788
789 int32_t cpreg_array_len;
790
791
792
793
794 uint64_t *cpreg_vmstate_indexes;
795 uint64_t *cpreg_vmstate_values;
796 int32_t cpreg_vmstate_array_len;
797
798 DynamicGDBXMLInfo dyn_sysreg_xml;
799 DynamicGDBXMLInfo dyn_svereg_xml;
800
801
802 QEMUTimer *gt_timer[NUM_GTIMERS];
803
804
805
806
807 QEMUTimer *pmu_timer;
808
809 qemu_irq gt_timer_outputs[NUM_GTIMERS];
810
811 qemu_irq gicv3_maintenance_interrupt;
812
813 qemu_irq pmu_interrupt;
814
815
816 qemu_irq wfi;
817
818
819 MemoryRegion *secure_memory;
820
821
822 Object *idau;
823
824
825 const char *dtb_compatible;
826
827
828
829
830
831 uint32_t psci_version;
832
833
834 bool start_powered_off;
835
836
837 ARMPSCIState power_state;
838
839
840 bool has_el2;
841
842 bool has_el3;
843
844 bool has_pmu;
845
846 bool has_vfp;
847
848 bool has_neon;
849
850 bool has_dsp;
851
852
853 bool has_mpu;
854
855 uint32_t pmsav7_dregion;
856
857 uint32_t sau_sregion;
858
859
860
861
862 uint32_t psci_conduit;
863
864
865 uint32_t init_svtor;
866
867
868
869
870 uint32_t kvm_target;
871
872
873 uint32_t kvm_init_features[7];
874
875
876
877
878 bool kvm_adjvtime;
879 bool kvm_vtime_dirty;
880 uint64_t kvm_vtime;
881
882
883 bool mp_is_up;
884
885
886
887
888 bool host_cpu_probe_failed;
889
890
891
892
893 int32_t core_count;
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912 struct ARMISARegisters {
913 uint32_t id_isar0;
914 uint32_t id_isar1;
915 uint32_t id_isar2;
916 uint32_t id_isar3;
917 uint32_t id_isar4;
918 uint32_t id_isar5;
919 uint32_t id_isar6;
920 uint32_t id_mmfr0;
921 uint32_t id_mmfr1;
922 uint32_t id_mmfr2;
923 uint32_t id_mmfr3;
924 uint32_t id_mmfr4;
925 uint32_t mvfr0;
926 uint32_t mvfr1;
927 uint32_t mvfr2;
928 uint32_t id_dfr0;
929 uint32_t dbgdidr;
930 uint64_t id_aa64isar0;
931 uint64_t id_aa64isar1;
932 uint64_t id_aa64pfr0;
933 uint64_t id_aa64pfr1;
934 uint64_t id_aa64mmfr0;
935 uint64_t id_aa64mmfr1;
936 uint64_t id_aa64mmfr2;
937 uint64_t id_aa64dfr0;
938 uint64_t id_aa64dfr1;
939 } isar;
940 uint64_t midr;
941 uint32_t revidr;
942 uint32_t reset_fpsid;
943 uint32_t ctr;
944 uint32_t reset_sctlr;
945 uint32_t id_pfr0;
946 uint32_t id_pfr1;
947 uint64_t pmceid0;
948 uint64_t pmceid1;
949 uint32_t id_afr0;
950 uint64_t id_aa64afr0;
951 uint64_t id_aa64afr1;
952 uint32_t clidr;
953 uint64_t mp_affinity;
954
955
956
957 uint64_t ccsidr[16];
958 uint64_t reset_cbar;
959 uint32_t reset_auxcr;
960 bool reset_hivecs;
961
962 uint32_t dcz_blocksize;
963 uint64_t rvbar;
964 int pe;
965
966
967 int gic_num_lrs;
968 int gic_vpribits;
969 int gic_vprebits;
970
971
972
973
974
975
976 bool cfgend;
977
978 MemoryRegion *mr_secure;
979
980 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
981 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
982
983 int32_t node_id;
984
985
986 uint8_t device_irq_level;
987
988
989 uint32_t sve_max_vq;
990
991
992
993
994
995
996
997
998
999
1000 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
1001 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
1002
1003
1004 uint64_t gt_cntfrq_hz;
1005};
1006
1007unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
1008
1009void arm_cpu_post_init(Object *obj);
1010
1011uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
1012
1013#ifndef CONFIG_USER_ONLY
1014extern const VMStateDescription vmstate_arm_cpu;
1015#endif
1016
1017void arm_cpu_do_interrupt(CPUState *cpu);
1018void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1019bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
1020
1021hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1022 MemTxAttrs *attrs);
1023
1024int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1025int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1026
1027
1028
1029
1030
1031int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
1032int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
1033
1034
1035
1036
1037
1038const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
1039
1040int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1041 int cpuid, void *opaque);
1042int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1043 int cpuid, void *opaque);
1044
1045#ifdef TARGET_AARCH64
1046int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1047int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1048void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1049void aarch64_sve_change_el(CPUARMState *env, int old_el,
1050 int new_el, bool el0_a64);
1051void aarch64_add_sve_properties(Object *obj);
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1063{
1064#ifdef HOST_WORDS_BIGENDIAN
1065 int i;
1066
1067 for (i = 0; i < nr; ++i) {
1068 dst[i] = bswap64(src[i]);
1069 }
1070
1071 return dst;
1072#else
1073 return src;
1074#endif
1075}
1076
1077#else
1078static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
1079static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1080 int n, bool a)
1081{ }
1082static inline void aarch64_add_sve_properties(Object *obj) { }
1083#endif
1084
1085#if !defined(CONFIG_TCG)
1086static inline target_ulong do_arm_semihosting(CPUARMState *env)
1087{
1088 g_assert_not_reached();
1089}
1090#else
1091target_ulong do_arm_semihosting(CPUARMState *env);
1092#endif
1093void aarch64_sync_32_to_64(CPUARMState *env);
1094void aarch64_sync_64_to_32(CPUARMState *env);
1095
1096int fp_exception_el(CPUARMState *env, int cur_el);
1097int sve_exception_el(CPUARMState *env, int cur_el);
1098uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
1099
1100static inline bool is_a64(CPUARMState *env)
1101{
1102 return env->aarch64;
1103}
1104
1105
1106
1107
1108int cpu_arm_signal_handler(int host_signum, void *pinfo,
1109 void *puc);
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119void pmu_op_start(CPUARMState *env);
1120void pmu_op_finish(CPUARMState *env);
1121
1122
1123
1124
1125void arm_pmu_timer_cb(void *opaque);
1126
1127
1128
1129
1130void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1131void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1132
1133
1134
1135
1136
1137
1138
1139
1140void pmu_init(ARMCPU *cpu);
1141
1142
1143
1144
1145
1146
1147
1148#define SCTLR_M (1U << 0)
1149#define SCTLR_A (1U << 1)
1150#define SCTLR_C (1U << 2)
1151#define SCTLR_W (1U << 3)
1152#define SCTLR_nTLSMD_32 (1U << 3)
1153#define SCTLR_SA (1U << 3)
1154#define SCTLR_P (1U << 4)
1155#define SCTLR_LSMAOE_32 (1U << 4)
1156#define SCTLR_SA0 (1U << 4)
1157#define SCTLR_D (1U << 5)
1158#define SCTLR_CP15BEN (1U << 5)
1159#define SCTLR_L (1U << 6)
1160#define SCTLR_nAA (1U << 6)
1161#define SCTLR_B (1U << 7)
1162#define SCTLR_ITD (1U << 7)
1163#define SCTLR_S (1U << 8)
1164#define SCTLR_SED (1U << 8)
1165#define SCTLR_R (1U << 9)
1166#define SCTLR_UMA (1U << 9)
1167#define SCTLR_F (1U << 10)
1168#define SCTLR_SW (1U << 10)
1169#define SCTLR_EnRCTX (1U << 10)
1170#define SCTLR_Z (1U << 11)
1171#define SCTLR_EOS (1U << 11)
1172#define SCTLR_I (1U << 12)
1173#define SCTLR_V (1U << 13)
1174#define SCTLR_EnDB (1U << 13)
1175#define SCTLR_RR (1U << 14)
1176#define SCTLR_DZE (1U << 14)
1177#define SCTLR_L4 (1U << 15)
1178#define SCTLR_UCT (1U << 15)
1179#define SCTLR_DT (1U << 16)
1180#define SCTLR_nTWI (1U << 16)
1181#define SCTLR_HA (1U << 17)
1182#define SCTLR_BR (1U << 17)
1183#define SCTLR_IT (1U << 18)
1184#define SCTLR_nTWE (1U << 18)
1185#define SCTLR_WXN (1U << 19)
1186#define SCTLR_ST (1U << 20)
1187#define SCTLR_UWXN (1U << 20)
1188#define SCTLR_FI (1U << 21)
1189#define SCTLR_IESB (1U << 21)
1190#define SCTLR_U (1U << 22)
1191#define SCTLR_EIS (1U << 22)
1192#define SCTLR_XP (1U << 23)
1193#define SCTLR_SPAN (1U << 23)
1194#define SCTLR_VE (1U << 24)
1195#define SCTLR_E0E (1U << 24)
1196#define SCTLR_EE (1U << 25)
1197#define SCTLR_L2 (1U << 26)
1198#define SCTLR_UCI (1U << 26)
1199#define SCTLR_NMFI (1U << 27)
1200#define SCTLR_EnDA (1U << 27)
1201#define SCTLR_TRE (1U << 28)
1202#define SCTLR_nTLSMD_64 (1U << 28)
1203#define SCTLR_AFE (1U << 29)
1204#define SCTLR_LSMAOE_64 (1U << 29)
1205#define SCTLR_TE (1U << 30)
1206#define SCTLR_EnIB (1U << 30)
1207#define SCTLR_EnIA (1U << 31)
1208#define SCTLR_BT0 (1ULL << 35)
1209#define SCTLR_BT1 (1ULL << 36)
1210#define SCTLR_ITFSB (1ULL << 37)
1211#define SCTLR_TCF0 (3ULL << 38)
1212#define SCTLR_TCF (3ULL << 40)
1213#define SCTLR_ATA0 (1ULL << 42)
1214#define SCTLR_ATA (1ULL << 43)
1215#define SCTLR_DSSBS (1ULL << 44)
1216
1217#define CPTR_TCPAC (1U << 31)
1218#define CPTR_TTA (1U << 20)
1219#define CPTR_TFP (1U << 10)
1220#define CPTR_TZ (1U << 8)
1221#define CPTR_EZ (1U << 8)
1222
1223#define MDCR_EPMAD (1U << 21)
1224#define MDCR_EDAD (1U << 20)
1225#define MDCR_SPME (1U << 17)
1226#define MDCR_HPMD (1U << 17)
1227#define MDCR_SDD (1U << 16)
1228#define MDCR_SPD (3U << 14)
1229#define MDCR_TDRA (1U << 11)
1230#define MDCR_TDOSA (1U << 10)
1231#define MDCR_TDA (1U << 9)
1232#define MDCR_TDE (1U << 8)
1233#define MDCR_HPME (1U << 7)
1234#define MDCR_TPM (1U << 6)
1235#define MDCR_TPMCR (1U << 5)
1236#define MDCR_HPMN (0x1fU)
1237
1238
1239#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1240
1241#define CPSR_M (0x1fU)
1242#define CPSR_T (1U << 5)
1243#define CPSR_F (1U << 6)
1244#define CPSR_I (1U << 7)
1245#define CPSR_A (1U << 8)
1246#define CPSR_E (1U << 9)
1247#define CPSR_IT_2_7 (0xfc00U)
1248#define CPSR_GE (0xfU << 16)
1249#define CPSR_IL (1U << 20)
1250#define CPSR_PAN (1U << 22)
1251#define CPSR_J (1U << 24)
1252#define CPSR_IT_0_1 (3U << 25)
1253#define CPSR_Q (1U << 27)
1254#define CPSR_V (1U << 28)
1255#define CPSR_C (1U << 29)
1256#define CPSR_Z (1U << 30)
1257#define CPSR_N (1U << 31)
1258#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1259#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1260
1261#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1262#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1263 | CPSR_NZCV)
1264
1265#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1266
1267#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1268
1269
1270#define XPSR_EXCP 0x1ffU
1271#define XPSR_SPREALIGN (1U << 9)
1272#define XPSR_IT_2_7 CPSR_IT_2_7
1273#define XPSR_GE CPSR_GE
1274#define XPSR_SFPA (1U << 20)
1275#define XPSR_T (1U << 24)
1276#define XPSR_IT_0_1 CPSR_IT_0_1
1277#define XPSR_Q CPSR_Q
1278#define XPSR_V CPSR_V
1279#define XPSR_C CPSR_C
1280#define XPSR_Z CPSR_Z
1281#define XPSR_N CPSR_N
1282#define XPSR_NZCV CPSR_NZCV
1283#define XPSR_IT CPSR_IT
1284
1285#define TTBCR_N (7U << 0)
1286#define TTBCR_T0SZ (7U << 0)
1287#define TTBCR_PD0 (1U << 4)
1288#define TTBCR_PD1 (1U << 5)
1289#define TTBCR_EPD0 (1U << 7)
1290#define TTBCR_IRGN0 (3U << 8)
1291#define TTBCR_ORGN0 (3U << 10)
1292#define TTBCR_SH0 (3U << 12)
1293#define TTBCR_T1SZ (3U << 16)
1294#define TTBCR_A1 (1U << 22)
1295#define TTBCR_EPD1 (1U << 23)
1296#define TTBCR_IRGN1 (3U << 24)
1297#define TTBCR_ORGN1 (3U << 26)
1298#define TTBCR_SH1 (1U << 28)
1299#define TTBCR_EAE (1U << 31)
1300
1301
1302
1303
1304
1305#define PSTATE_SP (1U)
1306#define PSTATE_M (0xFU)
1307#define PSTATE_nRW (1U << 4)
1308#define PSTATE_F (1U << 6)
1309#define PSTATE_I (1U << 7)
1310#define PSTATE_A (1U << 8)
1311#define PSTATE_D (1U << 9)
1312#define PSTATE_BTYPE (3U << 10)
1313#define PSTATE_IL (1U << 20)
1314#define PSTATE_SS (1U << 21)
1315#define PSTATE_PAN (1U << 22)
1316#define PSTATE_UAO (1U << 23)
1317#define PSTATE_V (1U << 28)
1318#define PSTATE_C (1U << 29)
1319#define PSTATE_Z (1U << 30)
1320#define PSTATE_N (1U << 31)
1321#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1322#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1323#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1324
1325#define PSTATE_MODE_EL3h 13
1326#define PSTATE_MODE_EL3t 12
1327#define PSTATE_MODE_EL2h 9
1328#define PSTATE_MODE_EL2t 8
1329#define PSTATE_MODE_EL1h 5
1330#define PSTATE_MODE_EL1t 4
1331#define PSTATE_MODE_EL0t 0
1332
1333
1334
1335
1336void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1337
1338
1339static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1340{
1341 return (el << 2) | handler;
1342}
1343
1344
1345
1346
1347
1348static inline uint32_t pstate_read(CPUARMState *env)
1349{
1350 int ZF;
1351
1352 ZF = (env->ZF == 0);
1353 return (env->NF & 0x80000000) | (ZF << 30)
1354 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1355 | env->pstate | env->daif | (env->btype << 10);
1356}
1357
1358static inline void pstate_write(CPUARMState *env, uint32_t val)
1359{
1360 env->ZF = (~val) & PSTATE_Z;
1361 env->NF = val;
1362 env->CF = (val >> 29) & 1;
1363 env->VF = (val << 3) & 0x80000000;
1364 env->daif = val & PSTATE_DAIF;
1365 env->btype = (val >> 10) & 3;
1366 env->pstate = val & ~CACHED_PSTATE_BITS;
1367}
1368
1369
1370uint32_t cpsr_read(CPUARMState *env);
1371
1372typedef enum CPSRWriteType {
1373 CPSRWriteByInstr = 0,
1374 CPSRWriteExceptionReturn = 1,
1375 CPSRWriteRaw = 2,
1376 CPSRWriteByGDBStub = 3,
1377} CPSRWriteType;
1378
1379
1380void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1381 CPSRWriteType write_type);
1382uint64_t mpidr_read_val(CPUARMState *env);
1383
1384
1385static inline uint32_t xpsr_read(CPUARMState *env)
1386{
1387 int ZF;
1388 ZF = (env->ZF == 0);
1389 return (env->NF & 0x80000000) | (ZF << 30)
1390 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1391 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1392 | ((env->condexec_bits & 0xfc) << 8)
1393 | (env->GE << 16)
1394 | env->v7m.exception;
1395}
1396
1397
1398static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1399{
1400 if (mask & XPSR_NZCV) {
1401 env->ZF = (~val) & XPSR_Z;
1402 env->NF = val;
1403 env->CF = (val >> 29) & 1;
1404 env->VF = (val << 3) & 0x80000000;
1405 }
1406 if (mask & XPSR_Q) {
1407 env->QF = ((val & XPSR_Q) != 0);
1408 }
1409 if (mask & XPSR_GE) {
1410 env->GE = (val & XPSR_GE) >> 16;
1411 }
1412#ifndef CONFIG_USER_ONLY
1413 if (mask & XPSR_T) {
1414 env->thumb = ((val & XPSR_T) != 0);
1415 }
1416 if (mask & XPSR_IT_0_1) {
1417 env->condexec_bits &= ~3;
1418 env->condexec_bits |= (val >> 25) & 3;
1419 }
1420 if (mask & XPSR_IT_2_7) {
1421 env->condexec_bits &= 3;
1422 env->condexec_bits |= (val >> 8) & 0xfc;
1423 }
1424 if (mask & XPSR_EXCP) {
1425
1426 write_v7m_exception(env, val & XPSR_EXCP);
1427 }
1428#endif
1429}
1430
1431#define HCR_VM (1ULL << 0)
1432#define HCR_SWIO (1ULL << 1)
1433#define HCR_PTW (1ULL << 2)
1434#define HCR_FMO (1ULL << 3)
1435#define HCR_IMO (1ULL << 4)
1436#define HCR_AMO (1ULL << 5)
1437#define HCR_VF (1ULL << 6)
1438#define HCR_VI (1ULL << 7)
1439#define HCR_VSE (1ULL << 8)
1440#define HCR_FB (1ULL << 9)
1441#define HCR_BSU_MASK (3ULL << 10)
1442#define HCR_DC (1ULL << 12)
1443#define HCR_TWI (1ULL << 13)
1444#define HCR_TWE (1ULL << 14)
1445#define HCR_TID0 (1ULL << 15)
1446#define HCR_TID1 (1ULL << 16)
1447#define HCR_TID2 (1ULL << 17)
1448#define HCR_TID3 (1ULL << 18)
1449#define HCR_TSC (1ULL << 19)
1450#define HCR_TIDCP (1ULL << 20)
1451#define HCR_TACR (1ULL << 21)
1452#define HCR_TSW (1ULL << 22)
1453#define HCR_TPCP (1ULL << 23)
1454#define HCR_TPU (1ULL << 24)
1455#define HCR_TTLB (1ULL << 25)
1456#define HCR_TVM (1ULL << 26)
1457#define HCR_TGE (1ULL << 27)
1458#define HCR_TDZ (1ULL << 28)
1459#define HCR_HCD (1ULL << 29)
1460#define HCR_TRVM (1ULL << 30)
1461#define HCR_RW (1ULL << 31)
1462#define HCR_CD (1ULL << 32)
1463#define HCR_ID (1ULL << 33)
1464#define HCR_E2H (1ULL << 34)
1465#define HCR_TLOR (1ULL << 35)
1466#define HCR_TERR (1ULL << 36)
1467#define HCR_TEA (1ULL << 37)
1468#define HCR_MIOCNCE (1ULL << 38)
1469
1470#define HCR_APK (1ULL << 40)
1471#define HCR_API (1ULL << 41)
1472#define HCR_NV (1ULL << 42)
1473#define HCR_NV1 (1ULL << 43)
1474#define HCR_AT (1ULL << 44)
1475#define HCR_NV2 (1ULL << 45)
1476#define HCR_FWB (1ULL << 46)
1477#define HCR_FIEN (1ULL << 47)
1478
1479#define HCR_TID4 (1ULL << 49)
1480#define HCR_TICAB (1ULL << 50)
1481#define HCR_AMVOFFEN (1ULL << 51)
1482#define HCR_TOCU (1ULL << 52)
1483#define HCR_ENSCXT (1ULL << 53)
1484#define HCR_TTLBIS (1ULL << 54)
1485#define HCR_TTLBOS (1ULL << 55)
1486#define HCR_ATA (1ULL << 56)
1487#define HCR_DCT (1ULL << 57)
1488#define HCR_TID5 (1ULL << 58)
1489#define HCR_TWEDEN (1ULL << 59)
1490#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
1491
1492#define SCR_NS (1U << 0)
1493#define SCR_IRQ (1U << 1)
1494#define SCR_FIQ (1U << 2)
1495#define SCR_EA (1U << 3)
1496#define SCR_FW (1U << 4)
1497#define SCR_AW (1U << 5)
1498#define SCR_NET (1U << 6)
1499#define SCR_SMD (1U << 7)
1500#define SCR_HCE (1U << 8)
1501#define SCR_SIF (1U << 9)
1502#define SCR_RW (1U << 10)
1503#define SCR_ST (1U << 11)
1504#define SCR_TWI (1U << 12)
1505#define SCR_TWE (1U << 13)
1506#define SCR_TLOR (1U << 14)
1507#define SCR_TERR (1U << 15)
1508#define SCR_APK (1U << 16)
1509#define SCR_API (1U << 17)
1510#define SCR_EEL2 (1U << 18)
1511#define SCR_EASE (1U << 19)
1512#define SCR_NMEA (1U << 20)
1513#define SCR_FIEN (1U << 21)
1514#define SCR_ENSCXT (1U << 25)
1515#define SCR_ATA (1U << 26)
1516
1517
1518uint32_t vfp_get_fpscr(CPUARMState *env);
1519void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1520
1521
1522
1523
1524
1525
1526
1527
1528#define FPSR_MASK 0xf800009f
1529#define FPCR_MASK 0x07ff9f00
1530
1531#define FPCR_IOE (1 << 8)
1532#define FPCR_DZE (1 << 9)
1533#define FPCR_OFE (1 << 10)
1534#define FPCR_UFE (1 << 11)
1535#define FPCR_IXE (1 << 12)
1536#define FPCR_IDE (1 << 15)
1537#define FPCR_FZ16 (1 << 19)
1538#define FPCR_FZ (1 << 24)
1539#define FPCR_DN (1 << 25)
1540#define FPCR_QC (1 << 27)
1541
1542static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1543{
1544 return vfp_get_fpscr(env) & FPSR_MASK;
1545}
1546
1547static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1548{
1549 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1550 vfp_set_fpscr(env, new_fpscr);
1551}
1552
1553static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1554{
1555 return vfp_get_fpscr(env) & FPCR_MASK;
1556}
1557
1558static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1559{
1560 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1561 vfp_set_fpscr(env, new_fpscr);
1562}
1563
1564enum arm_cpu_mode {
1565 ARM_CPU_MODE_USR = 0x10,
1566 ARM_CPU_MODE_FIQ = 0x11,
1567 ARM_CPU_MODE_IRQ = 0x12,
1568 ARM_CPU_MODE_SVC = 0x13,
1569 ARM_CPU_MODE_MON = 0x16,
1570 ARM_CPU_MODE_ABT = 0x17,
1571 ARM_CPU_MODE_HYP = 0x1a,
1572 ARM_CPU_MODE_UND = 0x1b,
1573 ARM_CPU_MODE_SYS = 0x1f
1574};
1575
1576
1577#define ARM_VFP_FPSID 0
1578#define ARM_VFP_FPSCR 1
1579#define ARM_VFP_MVFR2 5
1580#define ARM_VFP_MVFR1 6
1581#define ARM_VFP_MVFR0 7
1582#define ARM_VFP_FPEXC 8
1583#define ARM_VFP_FPINST 9
1584#define ARM_VFP_FPINST2 10
1585
1586
1587#define ARM_IWMMXT_wCID 0
1588#define ARM_IWMMXT_wCon 1
1589#define ARM_IWMMXT_wCSSF 2
1590#define ARM_IWMMXT_wCASF 3
1591#define ARM_IWMMXT_wCGR0 8
1592#define ARM_IWMMXT_wCGR1 9
1593#define ARM_IWMMXT_wCGR2 10
1594#define ARM_IWMMXT_wCGR3 11
1595
1596
1597FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1598FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1599FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1600FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1601FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1602FIELD(V7M_CCR, STKALIGN, 9, 1)
1603FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1604FIELD(V7M_CCR, DC, 16, 1)
1605FIELD(V7M_CCR, IC, 17, 1)
1606FIELD(V7M_CCR, BP, 18, 1)
1607
1608
1609FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1610FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1611FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1612FIELD(V7M_SCR, SEVONPEND, 4, 1)
1613
1614
1615FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1616FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1617FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1618FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1619FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1620FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1621FIELD(V7M_AIRCR, PRIS, 14, 1)
1622FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1623FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1624
1625
1626FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1627FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1628FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1629FIELD(V7M_CFSR, MSTKERR, 4, 1)
1630FIELD(V7M_CFSR, MLSPERR, 5, 1)
1631FIELD(V7M_CFSR, MMARVALID, 7, 1)
1632
1633
1634FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1635FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1636FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1637FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1638FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1639FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1640FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1641
1642
1643FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1644FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1645FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1646FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1647FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1648FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1649FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1650
1651
1652FIELD(V7M_CFSR, MMFSR, 0, 8)
1653FIELD(V7M_CFSR, BFSR, 8, 8)
1654FIELD(V7M_CFSR, UFSR, 16, 16)
1655
1656
1657FIELD(V7M_HFSR, VECTTBL, 1, 1)
1658FIELD(V7M_HFSR, FORCED, 30, 1)
1659FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1660
1661
1662FIELD(V7M_DFSR, HALTED, 0, 1)
1663FIELD(V7M_DFSR, BKPT, 1, 1)
1664FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1665FIELD(V7M_DFSR, VCATCH, 3, 1)
1666FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1667
1668
1669FIELD(V7M_SFSR, INVEP, 0, 1)
1670FIELD(V7M_SFSR, INVIS, 1, 1)
1671FIELD(V7M_SFSR, INVER, 2, 1)
1672FIELD(V7M_SFSR, AUVIOL, 3, 1)
1673FIELD(V7M_SFSR, INVTRAN, 4, 1)
1674FIELD(V7M_SFSR, LSPERR, 5, 1)
1675FIELD(V7M_SFSR, SFARVALID, 6, 1)
1676FIELD(V7M_SFSR, LSERR, 7, 1)
1677
1678
1679FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1680FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1681FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1682
1683
1684FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1685FIELD(V7M_CLIDR, LOUIS, 21, 3)
1686FIELD(V7M_CLIDR, LOC, 24, 3)
1687FIELD(V7M_CLIDR, LOUU, 27, 3)
1688FIELD(V7M_CLIDR, ICB, 30, 2)
1689
1690FIELD(V7M_CSSELR, IND, 0, 1)
1691FIELD(V7M_CSSELR, LEVEL, 1, 3)
1692
1693
1694
1695
1696FIELD(V7M_CSSELR, INDEX, 0, 4)
1697
1698
1699FIELD(V7M_FPCCR, LSPACT, 0, 1)
1700FIELD(V7M_FPCCR, USER, 1, 1)
1701FIELD(V7M_FPCCR, S, 2, 1)
1702FIELD(V7M_FPCCR, THREAD, 3, 1)
1703FIELD(V7M_FPCCR, HFRDY, 4, 1)
1704FIELD(V7M_FPCCR, MMRDY, 5, 1)
1705FIELD(V7M_FPCCR, BFRDY, 6, 1)
1706FIELD(V7M_FPCCR, SFRDY, 7, 1)
1707FIELD(V7M_FPCCR, MONRDY, 8, 1)
1708FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1709FIELD(V7M_FPCCR, UFRDY, 10, 1)
1710FIELD(V7M_FPCCR, RES0, 11, 15)
1711FIELD(V7M_FPCCR, TS, 26, 1)
1712FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1713FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1714FIELD(V7M_FPCCR, LSPENS, 29, 1)
1715FIELD(V7M_FPCCR, LSPEN, 30, 1)
1716FIELD(V7M_FPCCR, ASPEN, 31, 1)
1717
1718#define R_V7M_FPCCR_BANKED_MASK \
1719 (R_V7M_FPCCR_LSPACT_MASK | \
1720 R_V7M_FPCCR_USER_MASK | \
1721 R_V7M_FPCCR_THREAD_MASK | \
1722 R_V7M_FPCCR_MMRDY_MASK | \
1723 R_V7M_FPCCR_SPLIMVIOL_MASK | \
1724 R_V7M_FPCCR_UFRDY_MASK | \
1725 R_V7M_FPCCR_ASPEN_MASK)
1726
1727
1728
1729
1730FIELD(MIDR_EL1, REVISION, 0, 4)
1731FIELD(MIDR_EL1, PARTNUM, 4, 12)
1732FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
1733FIELD(MIDR_EL1, VARIANT, 20, 4)
1734FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
1735
1736FIELD(ID_ISAR0, SWAP, 0, 4)
1737FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1738FIELD(ID_ISAR0, BITFIELD, 8, 4)
1739FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1740FIELD(ID_ISAR0, COPROC, 16, 4)
1741FIELD(ID_ISAR0, DEBUG, 20, 4)
1742FIELD(ID_ISAR0, DIVIDE, 24, 4)
1743
1744FIELD(ID_ISAR1, ENDIAN, 0, 4)
1745FIELD(ID_ISAR1, EXCEPT, 4, 4)
1746FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
1747FIELD(ID_ISAR1, EXTEND, 12, 4)
1748FIELD(ID_ISAR1, IFTHEN, 16, 4)
1749FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
1750FIELD(ID_ISAR1, INTERWORK, 24, 4)
1751FIELD(ID_ISAR1, JAZELLE, 28, 4)
1752
1753FIELD(ID_ISAR2, LOADSTORE, 0, 4)
1754FIELD(ID_ISAR2, MEMHINT, 4, 4)
1755FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
1756FIELD(ID_ISAR2, MULT, 12, 4)
1757FIELD(ID_ISAR2, MULTS, 16, 4)
1758FIELD(ID_ISAR2, MULTU, 20, 4)
1759FIELD(ID_ISAR2, PSR_AR, 24, 4)
1760FIELD(ID_ISAR2, REVERSAL, 28, 4)
1761
1762FIELD(ID_ISAR3, SATURATE, 0, 4)
1763FIELD(ID_ISAR3, SIMD, 4, 4)
1764FIELD(ID_ISAR3, SVC, 8, 4)
1765FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
1766FIELD(ID_ISAR3, TABBRANCH, 16, 4)
1767FIELD(ID_ISAR3, T32COPY, 20, 4)
1768FIELD(ID_ISAR3, TRUENOP, 24, 4)
1769FIELD(ID_ISAR3, T32EE, 28, 4)
1770
1771FIELD(ID_ISAR4, UNPRIV, 0, 4)
1772FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
1773FIELD(ID_ISAR4, WRITEBACK, 8, 4)
1774FIELD(ID_ISAR4, SMC, 12, 4)
1775FIELD(ID_ISAR4, BARRIER, 16, 4)
1776FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
1777FIELD(ID_ISAR4, PSR_M, 24, 4)
1778FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
1779
1780FIELD(ID_ISAR5, SEVL, 0, 4)
1781FIELD(ID_ISAR5, AES, 4, 4)
1782FIELD(ID_ISAR5, SHA1, 8, 4)
1783FIELD(ID_ISAR5, SHA2, 12, 4)
1784FIELD(ID_ISAR5, CRC32, 16, 4)
1785FIELD(ID_ISAR5, RDM, 24, 4)
1786FIELD(ID_ISAR5, VCMA, 28, 4)
1787
1788FIELD(ID_ISAR6, JSCVT, 0, 4)
1789FIELD(ID_ISAR6, DP, 4, 4)
1790FIELD(ID_ISAR6, FHM, 8, 4)
1791FIELD(ID_ISAR6, SB, 12, 4)
1792FIELD(ID_ISAR6, SPECRES, 16, 4)
1793
1794FIELD(ID_MMFR3, CMAINTVA, 0, 4)
1795FIELD(ID_MMFR3, CMAINTSW, 4, 4)
1796FIELD(ID_MMFR3, BPMAINT, 8, 4)
1797FIELD(ID_MMFR3, MAINTBCST, 12, 4)
1798FIELD(ID_MMFR3, PAN, 16, 4)
1799FIELD(ID_MMFR3, COHWALK, 20, 4)
1800FIELD(ID_MMFR3, CMEMSZ, 24, 4)
1801FIELD(ID_MMFR3, SUPERSEC, 28, 4)
1802
1803FIELD(ID_MMFR4, SPECSEI, 0, 4)
1804FIELD(ID_MMFR4, AC2, 4, 4)
1805FIELD(ID_MMFR4, XNX, 8, 4)
1806FIELD(ID_MMFR4, CNP, 12, 4)
1807FIELD(ID_MMFR4, HPDS, 16, 4)
1808FIELD(ID_MMFR4, LSM, 20, 4)
1809FIELD(ID_MMFR4, CCIDX, 24, 4)
1810FIELD(ID_MMFR4, EVT, 28, 4)
1811
1812FIELD(ID_AA64ISAR0, AES, 4, 4)
1813FIELD(ID_AA64ISAR0, SHA1, 8, 4)
1814FIELD(ID_AA64ISAR0, SHA2, 12, 4)
1815FIELD(ID_AA64ISAR0, CRC32, 16, 4)
1816FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
1817FIELD(ID_AA64ISAR0, RDM, 28, 4)
1818FIELD(ID_AA64ISAR0, SHA3, 32, 4)
1819FIELD(ID_AA64ISAR0, SM3, 36, 4)
1820FIELD(ID_AA64ISAR0, SM4, 40, 4)
1821FIELD(ID_AA64ISAR0, DP, 44, 4)
1822FIELD(ID_AA64ISAR0, FHM, 48, 4)
1823FIELD(ID_AA64ISAR0, TS, 52, 4)
1824FIELD(ID_AA64ISAR0, TLB, 56, 4)
1825FIELD(ID_AA64ISAR0, RNDR, 60, 4)
1826
1827FIELD(ID_AA64ISAR1, DPB, 0, 4)
1828FIELD(ID_AA64ISAR1, APA, 4, 4)
1829FIELD(ID_AA64ISAR1, API, 8, 4)
1830FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
1831FIELD(ID_AA64ISAR1, FCMA, 16, 4)
1832FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
1833FIELD(ID_AA64ISAR1, GPA, 24, 4)
1834FIELD(ID_AA64ISAR1, GPI, 28, 4)
1835FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
1836FIELD(ID_AA64ISAR1, SB, 36, 4)
1837FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
1838
1839FIELD(ID_AA64PFR0, EL0, 0, 4)
1840FIELD(ID_AA64PFR0, EL1, 4, 4)
1841FIELD(ID_AA64PFR0, EL2, 8, 4)
1842FIELD(ID_AA64PFR0, EL3, 12, 4)
1843FIELD(ID_AA64PFR0, FP, 16, 4)
1844FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
1845FIELD(ID_AA64PFR0, GIC, 24, 4)
1846FIELD(ID_AA64PFR0, RAS, 28, 4)
1847FIELD(ID_AA64PFR0, SVE, 32, 4)
1848
1849FIELD(ID_AA64PFR1, BT, 0, 4)
1850FIELD(ID_AA64PFR1, SBSS, 4, 4)
1851FIELD(ID_AA64PFR1, MTE, 8, 4)
1852FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
1853
1854FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
1855FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
1856FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
1857FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
1858FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
1859FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
1860FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
1861FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
1862FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
1863FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
1864FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
1865FIELD(ID_AA64MMFR0, EXS, 44, 4)
1866
1867FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
1868FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
1869FIELD(ID_AA64MMFR1, VH, 8, 4)
1870FIELD(ID_AA64MMFR1, HPDS, 12, 4)
1871FIELD(ID_AA64MMFR1, LO, 16, 4)
1872FIELD(ID_AA64MMFR1, PAN, 20, 4)
1873FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
1874FIELD(ID_AA64MMFR1, XNX, 28, 4)
1875
1876FIELD(ID_AA64MMFR2, CNP, 0, 4)
1877FIELD(ID_AA64MMFR2, UAO, 4, 4)
1878FIELD(ID_AA64MMFR2, LSM, 8, 4)
1879FIELD(ID_AA64MMFR2, IESB, 12, 4)
1880FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
1881FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
1882FIELD(ID_AA64MMFR2, NV, 24, 4)
1883FIELD(ID_AA64MMFR2, ST, 28, 4)
1884FIELD(ID_AA64MMFR2, AT, 32, 4)
1885FIELD(ID_AA64MMFR2, IDS, 36, 4)
1886FIELD(ID_AA64MMFR2, FWB, 40, 4)
1887FIELD(ID_AA64MMFR2, TTL, 48, 4)
1888FIELD(ID_AA64MMFR2, BBM, 52, 4)
1889FIELD(ID_AA64MMFR2, EVT, 56, 4)
1890FIELD(ID_AA64MMFR2, E0PD, 60, 4)
1891
1892FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
1893FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
1894FIELD(ID_AA64DFR0, PMUVER, 8, 4)
1895FIELD(ID_AA64DFR0, BRPS, 12, 4)
1896FIELD(ID_AA64DFR0, WRPS, 20, 4)
1897FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
1898FIELD(ID_AA64DFR0, PMSVER, 32, 4)
1899FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
1900FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
1901
1902FIELD(ID_DFR0, COPDBG, 0, 4)
1903FIELD(ID_DFR0, COPSDBG, 4, 4)
1904FIELD(ID_DFR0, MMAPDBG, 8, 4)
1905FIELD(ID_DFR0, COPTRC, 12, 4)
1906FIELD(ID_DFR0, MMAPTRC, 16, 4)
1907FIELD(ID_DFR0, MPROFDBG, 20, 4)
1908FIELD(ID_DFR0, PERFMON, 24, 4)
1909FIELD(ID_DFR0, TRACEFILT, 28, 4)
1910
1911FIELD(DBGDIDR, SE_IMP, 12, 1)
1912FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
1913FIELD(DBGDIDR, VERSION, 16, 4)
1914FIELD(DBGDIDR, CTX_CMPS, 20, 4)
1915FIELD(DBGDIDR, BRPS, 24, 4)
1916FIELD(DBGDIDR, WRPS, 28, 4)
1917
1918FIELD(MVFR0, SIMDREG, 0, 4)
1919FIELD(MVFR0, FPSP, 4, 4)
1920FIELD(MVFR0, FPDP, 8, 4)
1921FIELD(MVFR0, FPTRAP, 12, 4)
1922FIELD(MVFR0, FPDIVIDE, 16, 4)
1923FIELD(MVFR0, FPSQRT, 20, 4)
1924FIELD(MVFR0, FPSHVEC, 24, 4)
1925FIELD(MVFR0, FPROUND, 28, 4)
1926
1927FIELD(MVFR1, FPFTZ, 0, 4)
1928FIELD(MVFR1, FPDNAN, 4, 4)
1929FIELD(MVFR1, SIMDLS, 8, 4)
1930FIELD(MVFR1, SIMDINT, 12, 4)
1931FIELD(MVFR1, SIMDSP, 16, 4)
1932FIELD(MVFR1, SIMDHP, 20, 4)
1933FIELD(MVFR1, FPHP, 24, 4)
1934FIELD(MVFR1, SIMDFMAC, 28, 4)
1935
1936FIELD(MVFR2, SIMDMISC, 0, 4)
1937FIELD(MVFR2, FPMISC, 4, 4)
1938
1939QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
1940
1941
1942
1943
1944
1945enum arm_features {
1946 ARM_FEATURE_AUXCR,
1947 ARM_FEATURE_XSCALE,
1948 ARM_FEATURE_IWMMXT,
1949 ARM_FEATURE_V6,
1950 ARM_FEATURE_V6K,
1951 ARM_FEATURE_V7,
1952 ARM_FEATURE_THUMB2,
1953 ARM_FEATURE_PMSA,
1954 ARM_FEATURE_NEON,
1955 ARM_FEATURE_M,
1956 ARM_FEATURE_OMAPCP,
1957 ARM_FEATURE_THUMB2EE,
1958 ARM_FEATURE_V7MP,
1959 ARM_FEATURE_V7VE,
1960 ARM_FEATURE_V4T,
1961 ARM_FEATURE_V5,
1962 ARM_FEATURE_STRONGARM,
1963 ARM_FEATURE_VAPA,
1964 ARM_FEATURE_GENERIC_TIMER,
1965 ARM_FEATURE_MVFR,
1966 ARM_FEATURE_DUMMY_C15_REGS,
1967 ARM_FEATURE_CACHE_TEST_CLEAN,
1968 ARM_FEATURE_CACHE_DIRTY_REG,
1969 ARM_FEATURE_CACHE_BLOCK_OPS,
1970 ARM_FEATURE_MPIDR,
1971 ARM_FEATURE_PXN,
1972 ARM_FEATURE_LPAE,
1973 ARM_FEATURE_V8,
1974 ARM_FEATURE_AARCH64,
1975 ARM_FEATURE_CBAR,
1976 ARM_FEATURE_CRC,
1977 ARM_FEATURE_CBAR_RO,
1978 ARM_FEATURE_EL2,
1979 ARM_FEATURE_EL3,
1980 ARM_FEATURE_THUMB_DSP,
1981 ARM_FEATURE_PMU,
1982 ARM_FEATURE_VBAR,
1983 ARM_FEATURE_M_SECURITY,
1984 ARM_FEATURE_M_MAIN,
1985};
1986
1987static inline int arm_feature(CPUARMState *env, int feature)
1988{
1989 return (env->features & (1ULL << feature)) != 0;
1990}
1991
1992void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
1993
1994#if !defined(CONFIG_USER_ONLY)
1995
1996
1997
1998
1999
2000
2001static inline bool arm_is_secure_below_el3(CPUARMState *env)
2002{
2003 if (arm_feature(env, ARM_FEATURE_EL3)) {
2004 return !(env->cp15.scr_el3 & SCR_NS);
2005 } else {
2006
2007
2008
2009 return false;
2010 }
2011}
2012
2013
2014static inline bool arm_is_el3_or_mon(CPUARMState *env)
2015{
2016 if (arm_feature(env, ARM_FEATURE_EL3)) {
2017 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2018
2019 return true;
2020 } else if (!is_a64(env) &&
2021 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2022
2023 return true;
2024 }
2025 }
2026 return false;
2027}
2028
2029
2030static inline bool arm_is_secure(CPUARMState *env)
2031{
2032 if (arm_is_el3_or_mon(env)) {
2033 return true;
2034 }
2035 return arm_is_secure_below_el3(env);
2036}
2037
2038#else
2039static inline bool arm_is_secure_below_el3(CPUARMState *env)
2040{
2041 return false;
2042}
2043
2044static inline bool arm_is_secure(CPUARMState *env)
2045{
2046 return false;
2047}
2048#endif
2049
2050
2051
2052
2053
2054
2055
2056uint64_t arm_hcr_el2_eff(CPUARMState *env);
2057
2058
2059static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2060{
2061
2062
2063
2064 assert(el >= 1 && el <= 3);
2065 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
2066
2067
2068
2069
2070
2071 if (el == 3) {
2072 return aa64;
2073 }
2074
2075 if (arm_feature(env, ARM_FEATURE_EL3)) {
2076 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2077 }
2078
2079 if (el == 2) {
2080 return aa64;
2081 }
2082
2083 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
2084 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2085 }
2086
2087 return aa64;
2088}
2089
2090
2091
2092
2093
2094
2095
2096
2097static inline bool access_secure_reg(CPUARMState *env)
2098{
2099 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2100 !arm_el_is_aa64(env, 3) &&
2101 !(env->cp15.scr_el3 & SCR_NS));
2102
2103 return ret;
2104}
2105
2106
2107#define A32_BANKED_REG_GET(_env, _regname, _secure) \
2108 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2109
2110#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
2111 do { \
2112 if (_secure) { \
2113 (_env)->cp15._regname##_s = (_val); \
2114 } else { \
2115 (_env)->cp15._regname##_ns = (_val); \
2116 } \
2117 } while (0)
2118
2119
2120
2121
2122
2123
2124#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
2125 A32_BANKED_REG_GET((_env), _regname, \
2126 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
2127
2128#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
2129 A32_BANKED_REG_SET((_env), _regname, \
2130 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
2131 (_val))
2132
2133void arm_cpu_list(void);
2134uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2135 uint32_t cur_el, bool secure);
2136
2137
2138#ifndef CONFIG_USER_ONLY
2139bool armv7m_nvic_can_take_pending_exception(void *opaque);
2140#else
2141static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
2142{
2143 return true;
2144}
2145#endif
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
2198 bool *ptargets_secure);
2199
2200
2201
2202
2203
2204
2205
2206
2207void armv7m_nvic_acknowledge_irq(void *opaque);
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243int armv7m_nvic_raw_execution_priority(void *opaque);
2244
2245
2246
2247
2248
2249
2250
2251#ifndef CONFIG_USER_ONLY
2252bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
2253#else
2254static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
2255{
2256 return false;
2257}
2258#endif
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286#define CP_REG_AA64_SHIFT 28
2287#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
2288
2289
2290
2291
2292
2293#define CP_REG_NS_SHIFT 29
2294#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
2295
2296#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
2297 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
2298 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
2299
2300#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
2301 (CP_REG_AA64_MASK | \
2302 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
2303 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
2304 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
2305 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
2306 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
2307 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
2308
2309
2310
2311
2312static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
2313{
2314 uint32_t cpregid = kvmid;
2315 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
2316 cpregid |= CP_REG_AA64_MASK;
2317 } else {
2318 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
2319 cpregid |= (1 << 15);
2320 }
2321
2322
2323
2324
2325 cpregid |= 1 << CP_REG_NS_SHIFT;
2326 }
2327 return cpregid;
2328}
2329
2330
2331
2332
2333static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
2334{
2335 uint64_t kvmid;
2336
2337 if (cpregid & CP_REG_AA64_MASK) {
2338 kvmid = cpregid & ~CP_REG_AA64_MASK;
2339 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
2340 } else {
2341 kvmid = cpregid & ~(1 << 15);
2342 if (cpregid & (1 << 15)) {
2343 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
2344 } else {
2345 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
2346 }
2347 }
2348 return kvmid;
2349}
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379#define ARM_CP_SPECIAL 0x0001
2380#define ARM_CP_CONST 0x0002
2381#define ARM_CP_64BIT 0x0004
2382#define ARM_CP_SUPPRESS_TB_END 0x0008
2383#define ARM_CP_OVERRIDE 0x0010
2384#define ARM_CP_ALIAS 0x0020
2385#define ARM_CP_IO 0x0040
2386#define ARM_CP_NO_RAW 0x0080
2387#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
2388#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
2389#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
2390#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
2391#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
2392#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
2393#define ARM_CP_FPU 0x1000
2394#define ARM_CP_SVE 0x2000
2395#define ARM_CP_NO_GDB 0x4000
2396#define ARM_CP_RAISES_EXC 0x8000
2397#define ARM_CP_NEWEL 0x10000
2398
2399#define ARM_CP_SENTINEL 0xfffff
2400
2401#define ARM_CP_FLAG_MASK 0x1f0ff
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412enum {
2413 ARM_CP_STATE_AA32 = 0,
2414 ARM_CP_STATE_AA64 = 1,
2415 ARM_CP_STATE_BOTH = 2,
2416};
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428enum {
2429 ARM_CP_SECSTATE_S = (1 << 0),
2430 ARM_CP_SECSTATE_NS = (1 << 1),
2431};
2432
2433
2434
2435
2436
2437static inline bool cptype_valid(int cptype)
2438{
2439 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
2440 || ((cptype & ARM_CP_SPECIAL) &&
2441 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
2442}
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461#define PL3_R 0x80
2462#define PL3_W 0x40
2463#define PL2_R (0x20 | PL3_R)
2464#define PL2_W (0x10 | PL3_W)
2465#define PL1_R (0x08 | PL2_R)
2466#define PL1_W (0x04 | PL2_W)
2467#define PL0_R (0x02 | PL1_R)
2468#define PL0_W (0x01 | PL1_W)
2469
2470
2471
2472
2473
2474
2475
2476#ifdef CONFIG_USER_ONLY
2477#define PL0U_R PL0_R
2478#else
2479#define PL0U_R PL1_R
2480#endif
2481
2482#define PL3_RW (PL3_R | PL3_W)
2483#define PL2_RW (PL2_R | PL2_W)
2484#define PL1_RW (PL1_R | PL1_W)
2485#define PL0_RW (PL0_R | PL0_W)
2486
2487
2488static inline int arm_highest_el(CPUARMState *env)
2489{
2490 if (arm_feature(env, ARM_FEATURE_EL3)) {
2491 return 3;
2492 }
2493 if (arm_feature(env, ARM_FEATURE_EL2)) {
2494 return 2;
2495 }
2496 return 1;
2497}
2498
2499
2500static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2501{
2502 return env->v7m.exception != 0;
2503}
2504
2505
2506
2507
2508static inline int arm_current_el(CPUARMState *env)
2509{
2510 if (arm_feature(env, ARM_FEATURE_M)) {
2511 return arm_v7m_is_handler_mode(env) ||
2512 !(env->v7m.control[env->v7m.secure] & 1);
2513 }
2514
2515 if (is_a64(env)) {
2516 return extract32(env->pstate, 2, 2);
2517 }
2518
2519 switch (env->uncached_cpsr & 0x1f) {
2520 case ARM_CPU_MODE_USR:
2521 return 0;
2522 case ARM_CPU_MODE_HYP:
2523 return 2;
2524 case ARM_CPU_MODE_MON:
2525 return 3;
2526 default:
2527 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2528
2529
2530
2531 return 3;
2532 }
2533
2534 return 1;
2535 }
2536}
2537
2538typedef struct ARMCPRegInfo ARMCPRegInfo;
2539
2540typedef enum CPAccessResult {
2541
2542 CP_ACCESS_OK = 0,
2543
2544
2545
2546
2547
2548
2549 CP_ACCESS_TRAP = 1,
2550
2551
2552
2553
2554 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
2555
2556 CP_ACCESS_TRAP_EL2 = 3,
2557 CP_ACCESS_TRAP_EL3 = 4,
2558
2559 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
2560 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
2561
2562
2563
2564 CP_ACCESS_TRAP_FP_EL2 = 7,
2565 CP_ACCESS_TRAP_FP_EL3 = 8,
2566} CPAccessResult;
2567
2568
2569
2570
2571typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2572typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
2573 uint64_t value);
2574
2575typedef CPAccessResult CPAccessFn(CPUARMState *env,
2576 const ARMCPRegInfo *opaque,
2577 bool isread);
2578
2579typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2580
2581#define CP_ANY 0xff
2582
2583
2584struct ARMCPRegInfo {
2585
2586 const char *name;
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604 uint8_t cp;
2605 uint8_t crn;
2606 uint8_t crm;
2607 uint8_t opc0;
2608 uint8_t opc1;
2609 uint8_t opc2;
2610
2611 int state;
2612
2613 int type;
2614
2615 int access;
2616
2617 int secure;
2618
2619
2620
2621
2622 void *opaque;
2623
2624
2625
2626 uint64_t resetvalue;
2627
2628
2629
2630
2631
2632
2633 ptrdiff_t fieldoffset;
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646 ptrdiff_t bank_fieldoffsets[2];
2647
2648
2649
2650
2651
2652
2653 CPAccessFn *accessfn;
2654
2655
2656
2657
2658 CPReadFn *readfn;
2659
2660
2661
2662
2663 CPWriteFn *writefn;
2664
2665
2666
2667
2668
2669 CPReadFn *raw_readfn;
2670
2671
2672
2673
2674
2675
2676 CPWriteFn *raw_writefn;
2677
2678
2679
2680
2681 CPResetFn *resetfn;
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693 CPReadFn *orig_readfn;
2694 CPWriteFn *orig_writefn;
2695};
2696
2697
2698
2699
2700#define CPREG_FIELD32(env, ri) \
2701 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2702#define CPREG_FIELD64(env, ri) \
2703 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2704
2705#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2706
2707void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2708 const ARMCPRegInfo *regs, void *opaque);
2709void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2710 const ARMCPRegInfo *regs, void *opaque);
2711static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2712{
2713 define_arm_cp_regs_with_opaque(cpu, regs, 0);
2714}
2715static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2716{
2717 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2718}
2719const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2720
2721
2722
2723
2724
2725
2726
2727typedef struct ARMCPRegUserSpaceInfo {
2728
2729 const char *name;
2730
2731
2732 bool is_glob;
2733
2734
2735 uint64_t exported_bits;
2736
2737
2738 uint64_t fixed_bits;
2739} ARMCPRegUserSpaceInfo;
2740
2741#define REGUSERINFO_SENTINEL { .name = NULL }
2742
2743void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
2744
2745
2746void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2747 uint64_t value);
2748
2749uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2750
2751
2752
2753
2754void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2755
2756
2757
2758
2759static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2760{
2761 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2762}
2763
2764static inline bool cp_access_ok(int current_el,
2765 const ARMCPRegInfo *ri, int isread)
2766{
2767 return (ri->access >> ((current_el * 2) + isread)) & 1;
2768}
2769
2770
2771uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787bool write_list_to_cpustate(ARMCPU *cpu);
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2811
2812#define ARM_CPUID_TI915T 0x54029152
2813#define ARM_CPUID_TI925T 0x54029252
2814
2815#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2816#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2817#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2818
2819#define cpu_signal_handler cpu_arm_signal_handler
2820#define cpu_list arm_cpu_list
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916#define ARM_MMU_IDX_A 0x10
2917#define ARM_MMU_IDX_NOTLB 0x20
2918#define ARM_MMU_IDX_M 0x40
2919
2920
2921#define ARM_MMU_IDX_M_PRIV 0x1
2922#define ARM_MMU_IDX_M_NEGPRI 0x2
2923#define ARM_MMU_IDX_M_S 0x4
2924
2925#define ARM_MMU_IDX_TYPE_MASK \
2926 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
2927#define ARM_MMU_IDX_COREIDX_MASK 0xf
2928
2929typedef enum ARMMMUIdx {
2930
2931
2932
2933 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
2934 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A,
2935
2936 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A,
2937 ARMMMUIdx_E10_1_PAN = 3 | ARM_MMU_IDX_A,
2938
2939 ARMMMUIdx_E2 = 4 | ARM_MMU_IDX_A,
2940 ARMMMUIdx_E20_2 = 5 | ARM_MMU_IDX_A,
2941 ARMMMUIdx_E20_2_PAN = 6 | ARM_MMU_IDX_A,
2942
2943 ARMMMUIdx_SE10_0 = 7 | ARM_MMU_IDX_A,
2944 ARMMMUIdx_SE10_1 = 8 | ARM_MMU_IDX_A,
2945 ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A,
2946 ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A,
2947
2948
2949
2950
2951
2952 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
2953 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
2954 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
2955
2956
2957
2958
2959
2960
2961
2962 ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB,
2963
2964
2965
2966
2967 ARMMMUIdx_MUser = ARM_MMU_IDX_M,
2968 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
2969 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
2970 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
2971 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
2972 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
2973 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
2974 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
2975} ARMMMUIdx;
2976
2977
2978
2979
2980
2981#define TO_CORE_BIT(NAME) \
2982 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
2983
2984typedef enum ARMMMUIdxBit {
2985 TO_CORE_BIT(E10_0),
2986 TO_CORE_BIT(E20_0),
2987 TO_CORE_BIT(E10_1),
2988 TO_CORE_BIT(E10_1_PAN),
2989 TO_CORE_BIT(E2),
2990 TO_CORE_BIT(E20_2),
2991 TO_CORE_BIT(E20_2_PAN),
2992 TO_CORE_BIT(SE10_0),
2993 TO_CORE_BIT(SE10_1),
2994 TO_CORE_BIT(SE10_1_PAN),
2995 TO_CORE_BIT(SE3),
2996
2997 TO_CORE_BIT(MUser),
2998 TO_CORE_BIT(MPriv),
2999 TO_CORE_BIT(MUserNegPri),
3000 TO_CORE_BIT(MPrivNegPri),
3001 TO_CORE_BIT(MSUser),
3002 TO_CORE_BIT(MSPriv),
3003 TO_CORE_BIT(MSUserNegPri),
3004 TO_CORE_BIT(MSPrivNegPri),
3005} ARMMMUIdxBit;
3006
3007#undef TO_CORE_BIT
3008
3009#define MMU_USER_IDX 0
3010
3011
3012typedef enum ARMASIdx {
3013 ARMASIdx_NS = 0,
3014 ARMASIdx_S = 1,
3015} ARMASIdx;
3016
3017
3018static inline int arm_debug_target_el(CPUARMState *env)
3019{
3020 bool secure = arm_is_secure(env);
3021 bool route_to_el2 = false;
3022
3023 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
3024 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
3025 env->cp15.mdcr_el2 & MDCR_TDE;
3026 }
3027
3028 if (route_to_el2) {
3029 return 2;
3030 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
3031 !arm_el_is_aa64(env, 3) && secure) {
3032 return 3;
3033 } else {
3034 return 1;
3035 }
3036}
3037
3038static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
3039{
3040
3041
3042
3043 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
3044}
3045
3046
3047static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
3048{
3049 int cur_el = arm_current_el(env);
3050 int debug_el;
3051
3052 if (cur_el == 3) {
3053 return false;
3054 }
3055
3056
3057 if (arm_is_secure_below_el3(env)
3058 && extract32(env->cp15.mdcr_el3, 16, 1)) {
3059 return false;
3060 }
3061
3062
3063
3064
3065
3066 debug_el = arm_debug_target_el(env);
3067
3068 if (cur_el == debug_el) {
3069 return extract32(env->cp15.mdscr_el1, 13, 1)
3070 && !(env->daif & PSTATE_D);
3071 }
3072
3073
3074 return debug_el > cur_el;
3075}
3076
3077static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
3078{
3079 int el = arm_current_el(env);
3080
3081 if (el == 0 && arm_el_is_aa64(env, 1)) {
3082 return aa64_generate_debug_exceptions(env);
3083 }
3084
3085 if (arm_is_secure(env)) {
3086 int spd;
3087
3088 if (el == 0 && (env->cp15.sder & 1)) {
3089
3090
3091
3092
3093 return true;
3094 }
3095
3096 spd = extract32(env->cp15.mdcr_el3, 14, 2);
3097 switch (spd) {
3098 case 1:
3099
3100 case 0:
3101
3102
3103
3104
3105
3106 return true;
3107 case 2:
3108 return false;
3109 case 3:
3110 return true;
3111 }
3112 }
3113
3114 return el != 2;
3115}
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128static inline bool arm_generate_debug_exceptions(CPUARMState *env)
3129{
3130 if (env->aarch64) {
3131 return aa64_generate_debug_exceptions(env);
3132 } else {
3133 return aa32_generate_debug_exceptions(env);
3134 }
3135}
3136
3137
3138
3139
3140static inline bool arm_singlestep_active(CPUARMState *env)
3141{
3142 return extract32(env->cp15.mdscr_el1, 0, 1)
3143 && arm_el_is_aa64(env, arm_debug_target_el(env))
3144 && arm_generate_debug_exceptions(env);
3145}
3146
3147static inline bool arm_sctlr_b(CPUARMState *env)
3148{
3149 return
3150
3151
3152
3153
3154#ifndef CONFIG_USER_ONLY
3155 !arm_feature(env, ARM_FEATURE_V7) &&
3156#endif
3157 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3158}
3159
3160uint64_t arm_sctlr(CPUARMState *env, int el);
3161
3162static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
3163 bool sctlr_b)
3164{
3165#ifdef CONFIG_USER_ONLY
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178 if (sctlr_b) {
3179 return true;
3180 }
3181#endif
3182
3183 return env->uncached_cpsr & CPSR_E;
3184}
3185
3186static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3187{
3188 return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3189}
3190
3191
3192static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3193{
3194 if (!is_a64(env)) {
3195 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
3196 } else {
3197 int cur_el = arm_current_el(env);
3198 uint64_t sctlr = arm_sctlr(env, cur_el);
3199 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
3200 }
3201}
3202
3203typedef CPUARMState CPUArchState;
3204typedef ARMCPU ArchCPU;
3205
3206#include "exec/cpu-all.h"
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
3227FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)
3228FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1)
3229FIELD(TBFLAG_ANY, BE_DATA, 28, 1)
3230FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
3231
3232FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)
3233
3234FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
3235
3236
3237
3238
3239FIELD(TBFLAG_AM32, CONDEXEC, 0, 8)
3240FIELD(TBFLAG_AM32, THUMB, 8, 1)
3241
3242
3243
3244
3245FIELD(TBFLAG_A32, VECLEN, 9, 3)
3246FIELD(TBFLAG_A32, VECSTRIDE, 12, 2)
3247
3248
3249
3250
3251
3252
3253FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2)
3254FIELD(TBFLAG_A32, VFPEN, 14, 1)
3255FIELD(TBFLAG_A32, SCTLR_B, 15, 1)
3256FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1)
3257
3258
3259
3260
3261
3262FIELD(TBFLAG_A32, NS, 17, 1)
3263
3264
3265
3266
3267
3268FIELD(TBFLAG_M32, HANDLER, 9, 1)
3269
3270FIELD(TBFLAG_M32, STACKCHECK, 10, 1)
3271
3272FIELD(TBFLAG_M32, LSPACT, 11, 1)
3273
3274FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1)
3275
3276FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1)
3277
3278
3279
3280
3281FIELD(TBFLAG_A64, TBII, 0, 2)
3282FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3283FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
3284FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3285FIELD(TBFLAG_A64, BT, 9, 1)
3286FIELD(TBFLAG_A64, BTYPE, 10, 2)
3287FIELD(TBFLAG_A64, TBID, 12, 2)
3288FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
3299{
3300 return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX);
3301}
3302
3303static inline bool bswap_code(bool sctlr_b)
3304{
3305#ifdef CONFIG_USER_ONLY
3306
3307
3308
3309
3310 return
3311#ifdef TARGET_WORDS_BIGENDIAN
3312 1 ^
3313#endif
3314 sctlr_b;
3315#else
3316
3317
3318
3319 return 0;
3320#endif
3321}
3322
3323#ifdef CONFIG_USER_ONLY
3324static inline bool arm_cpu_bswap_data(CPUARMState *env)
3325{
3326 return
3327#ifdef TARGET_WORDS_BIGENDIAN
3328 1 ^
3329#endif
3330 arm_cpu_data_is_big_endian(env);
3331}
3332#endif
3333
3334void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3335 target_ulong *cs_base, uint32_t *flags);
3336
3337enum {
3338 QEMU_PSCI_CONDUIT_DISABLED = 0,
3339 QEMU_PSCI_CONDUIT_SMC = 1,
3340 QEMU_PSCI_CONDUIT_HVC = 2,
3341};
3342
3343#ifndef CONFIG_USER_ONLY
3344
3345static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3346{
3347 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3348}
3349
3350
3351
3352
3353
3354static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3355{
3356 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3357}
3358#endif
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3371 void *opaque);
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3383 *opaque);
3384
3385
3386
3387
3388
3389void arm_rebuild_hflags(CPUARMState *env);
3390
3391
3392
3393
3394
3395static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3396{
3397 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3398}
3399
3400
3401
3402
3403
3404static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3405{
3406 return &env->vfp.zregs[regno].d[0];
3407}
3408
3409
3410
3411
3412
3413static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3414{
3415 return &env->vfp.zregs[regno].d[0];
3416}
3417
3418
3419extern const uint64_t pred_esz_masks[4];
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
3441{
3442 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3443}
3444
3445static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
3446{
3447 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3448}
3449
3450static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
3451{
3452 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
3453}
3454
3455static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
3456{
3457 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
3458}
3459
3460static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
3461{
3462 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
3463}
3464
3465static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
3466{
3467 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
3468}
3469
3470static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
3471{
3472 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
3473}
3474
3475static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
3476{
3477 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
3478}
3479
3480static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
3481{
3482 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
3483}
3484
3485static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
3486{
3487 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
3488}
3489
3490static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
3491{
3492 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
3493}
3494
3495static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
3496{
3497 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
3498}
3499
3500static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
3501{
3502 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
3503}
3504
3505static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
3506{
3507 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
3508}
3509
3510static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
3511{
3512 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
3513}
3514
3515static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
3516{
3517
3518
3519
3520
3521
3522 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3523}
3524
3525static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
3526{
3527
3528
3529
3530
3531 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
3532}
3533
3534static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
3535{
3536
3537 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
3538}
3539
3540static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
3541{
3542 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
3543}
3544
3545static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
3546{
3547
3548 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
3549}
3550
3551static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
3552{
3553
3554 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
3555}
3556
3557static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
3558{
3559
3560 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
3561}
3562
3563static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
3564{
3565
3566 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
3567}
3568
3569static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
3570{
3571 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
3572}
3573
3574
3575
3576
3577
3578
3579static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
3580{
3581 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
3582}
3583
3584static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
3585{
3586 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
3587}
3588
3589
3590
3591
3592
3593
3594
3595
3596static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
3597{
3598 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
3599}
3600
3601static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
3602{
3603 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
3604}
3605
3606static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
3607{
3608 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
3609}
3610
3611static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
3612{
3613 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
3614}
3615
3616static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
3617{
3618 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
3619}
3620
3621static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
3622{
3623 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
3624}
3625
3626static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
3627{
3628 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
3629}
3630
3631static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
3632{
3633
3634 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
3635 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3636}
3637
3638static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id)
3639{
3640
3641 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
3642 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3643}
3644
3645static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
3646{
3647 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
3648}
3649
3650static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
3651{
3652 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
3653}
3654
3655static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
3656{
3657 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
3658}
3659
3660static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
3661{
3662 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
3663}
3664
3665
3666
3667
3668static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
3669{
3670 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
3671}
3672
3673static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
3674{
3675 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
3676}
3677
3678static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
3679{
3680 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
3681}
3682
3683static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
3684{
3685 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
3686}
3687
3688static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
3689{
3690 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
3691}
3692
3693static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
3694{
3695 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
3696}
3697
3698static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
3699{
3700 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
3701}
3702
3703static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
3704{
3705 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
3706}
3707
3708static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
3709{
3710 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
3711}
3712
3713static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
3714{
3715 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
3716}
3717
3718static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
3719{
3720 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
3721}
3722
3723static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
3724{
3725 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
3726}
3727
3728static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
3729{
3730 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
3731}
3732
3733static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
3734{
3735 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
3736}
3737
3738static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
3739{
3740 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
3741}
3742
3743static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
3744{
3745 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
3746}
3747
3748static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
3749{
3750 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
3751}
3752
3753static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
3754{
3755 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
3756}
3757
3758static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
3759{
3760
3761
3762
3763
3764
3765
3766 return (id->id_aa64isar1 &
3767 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
3768 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
3769 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
3770 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
3771}
3772
3773static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
3774{
3775 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
3776}
3777
3778static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
3779{
3780 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
3781}
3782
3783static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
3784{
3785 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
3786}
3787
3788static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
3789{
3790 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
3791}
3792
3793static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
3794{
3795 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
3796}
3797
3798static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
3799{
3800
3801 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
3802}
3803
3804static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
3805{
3806
3807 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3808}
3809
3810static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
3811{
3812 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
3813}
3814
3815static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
3816{
3817 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
3818}
3819
3820static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
3821{
3822 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
3823}
3824
3825static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
3826{
3827 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
3828}
3829
3830static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
3831{
3832 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
3833}
3834
3835static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
3836{
3837 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
3838}
3839
3840static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
3841{
3842 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
3843}
3844
3845static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
3846{
3847 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
3848}
3849
3850static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
3851{
3852 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
3853 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
3854}
3855
3856static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
3857{
3858 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
3859 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
3860}
3861
3862static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
3863{
3864 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
3865}
3866
3867static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
3868{
3869 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
3870}
3871
3872static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
3873{
3874 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
3875}
3876
3877static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
3878{
3879 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
3880}
3881
3882
3883
3884
3885static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
3886{
3887 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
3888}
3889
3890static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
3891{
3892 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
3893}
3894
3895static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id)
3896{
3897 return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id);
3898}
3899
3900static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id)
3901{
3902 return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id);
3903}
3904
3905static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
3906{
3907 return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
3908}
3909
3910static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
3911{
3912 return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
3913}
3914
3915
3916
3917
3918#define cpu_isar_feature(name, cpu) \
3919 ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
3920
3921#endif
3922