1#ifndef TARGET_ARM_TRANSLATE_H
2#define TARGET_ARM_TRANSLATE_H
3
4#include "exec/translator.h"
5#include "internals.h"
6
7
8
9typedef struct DisasContext {
10 DisasContextBase base;
11 const ARMISARegisters *isar;
12
13
14 target_ulong pc_curr;
15 target_ulong page_start;
16 uint32_t insn;
17
18 int condjmp;
19
20 TCGLabel *condlabel;
21
22 int condexec_mask;
23 int condexec_cond;
24 int thumb;
25 int sctlr_b;
26 MemOp be_data;
27#if !defined(CONFIG_USER_ONLY)
28 int user;
29#endif
30 ARMMMUIdx mmu_idx;
31 uint8_t tbii;
32 uint8_t tbid;
33 bool ns;
34 int fp_excp_el;
35 int sve_excp_el;
36 int sve_len;
37
38 bool secure_routed_to_el3;
39 bool vfp_enabled;
40 int vec_len;
41 int vec_stride;
42 bool v7m_handler_mode;
43 bool v8m_secure;
44 bool v8m_stackcheck;
45 bool v8m_fpccr_s_wrong;
46 bool v7m_new_fp_ctxt_needed;
47 bool v7m_lspact;
48
49
50
51 uint32_t svc_imm;
52 int aarch64;
53 int current_el;
54
55 int debug_target_el;
56 GHashTable *cp_regs;
57 uint64_t features;
58
59
60
61
62
63
64
65 bool fp_access_checked;
66
67
68
69 bool ss_active;
70 bool pstate_ss;
71
72
73
74
75 bool is_ldex;
76
77 bool unpriv;
78
79 bool pauth_active;
80
81 bool bt;
82
83 bool hstr_active;
84
85
86
87
88 int8_t btype;
89
90 bool guarded_page;
91
92 int c15_cpar;
93
94 TCGOp *insn_start;
95#define TMP_A64_MAX 16
96 int tmp_a64_count;
97 TCGv_i64 tmp_a64[TMP_A64_MAX];
98} DisasContext;
99
100typedef struct DisasCompare {
101 TCGCond cond;
102 TCGv_i32 value;
103 bool value_global;
104} DisasCompare;
105
106
107extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
108extern TCGv_i64 cpu_exclusive_addr;
109extern TCGv_i64 cpu_exclusive_val;
110
111static inline int arm_dc_feature(DisasContext *dc, int feature)
112{
113 return (dc->features & (1ULL << feature)) != 0;
114}
115
116static inline int get_mem_index(DisasContext *s)
117{
118 return arm_to_core_mmu_idx(s->mmu_idx);
119}
120
121
122
123
124static inline int default_exception_el(DisasContext *s)
125{
126
127
128
129
130
131 return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3)
132 ? 3 : MAX(1, s->current_el);
133}
134
135static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
136{
137
138
139
140 syn &= ARM_INSN_START_WORD2_MASK;
141 syn >>= ARM_INSN_START_WORD2_SHIFT;
142
143
144 assert(s->insn_start != NULL);
145 tcg_set_insn_start_param(s->insn_start, 2, syn);
146 s->insn_start = NULL;
147}
148
149
150#define DISAS_JUMP DISAS_TARGET_0
151#define DISAS_UPDATE DISAS_TARGET_1
152
153
154
155
156#define DISAS_WFI DISAS_TARGET_2
157#define DISAS_SWI DISAS_TARGET_3
158
159#define DISAS_WFE DISAS_TARGET_4
160#define DISAS_HVC DISAS_TARGET_5
161#define DISAS_SMC DISAS_TARGET_6
162#define DISAS_YIELD DISAS_TARGET_7
163
164
165
166#define DISAS_BX_EXCRET DISAS_TARGET_8
167
168
169
170
171
172
173#define DISAS_EXIT DISAS_TARGET_9
174
175#ifdef TARGET_AARCH64
176void a64_translate_init(void);
177void gen_a64_set_pc_im(uint64_t val);
178extern const TranslatorOps aarch64_translator_ops;
179#else
180static inline void a64_translate_init(void)
181{
182}
183
184static inline void gen_a64_set_pc_im(uint64_t val)
185{
186}
187#endif
188
189void arm_test_cc(DisasCompare *cmp, int cc);
190void arm_free_cc(DisasCompare *cmp);
191void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
192void arm_gen_test_cc(int cc, TCGLabel *label);
193
194
195static inline TCGv_i32 get_ahp_flag(void)
196{
197 TCGv_i32 ret = tcg_temp_new_i32();
198
199 tcg_gen_ld_i32(ret, cpu_env,
200 offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
201 tcg_gen_extract_i32(ret, ret, 26, 1);
202
203 return ret;
204}
205
206
207static inline void set_pstate_bits(uint32_t bits)
208{
209 TCGv_i32 p = tcg_temp_new_i32();
210
211 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
212
213 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
214 tcg_gen_ori_i32(p, p, bits);
215 tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
216 tcg_temp_free_i32(p);
217}
218
219
220static inline void clear_pstate_bits(uint32_t bits)
221{
222 TCGv_i32 p = tcg_temp_new_i32();
223
224 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
225
226 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
227 tcg_gen_andi_i32(p, p, ~bits);
228 tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
229 tcg_temp_free_i32(p);
230}
231
232
233static inline void gen_ss_advance(DisasContext *s)
234{
235 if (s->ss_active) {
236 s->pstate_ss = 0;
237 clear_pstate_bits(PSTATE_SS);
238 }
239}
240
241static inline void gen_exception(int excp, uint32_t syndrome,
242 uint32_t target_el)
243{
244 TCGv_i32 tcg_excp = tcg_const_i32(excp);
245 TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
246 TCGv_i32 tcg_el = tcg_const_i32(target_el);
247
248 gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
249 tcg_syn, tcg_el);
250
251 tcg_temp_free_i32(tcg_el);
252 tcg_temp_free_i32(tcg_syn);
253 tcg_temp_free_i32(tcg_excp);
254}
255
256
257static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
258{
259 bool same_el = (s->debug_target_el == s->current_el);
260
261
262
263
264
265 assert(s->debug_target_el >= s->current_el);
266
267 gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el);
268}
269
270
271
272
273
274
275uint64_t vfp_expand_imm(int size, uint8_t imm8);
276
277
278void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
279 uint32_t opr_sz, uint32_t max_sz);
280void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
281 uint32_t opr_sz, uint32_t max_sz);
282void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
283 uint32_t opr_sz, uint32_t max_sz);
284void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
285 uint32_t opr_sz, uint32_t max_sz);
286void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
287 uint32_t opr_sz, uint32_t max_sz);
288
289void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
290 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
291void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
292 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
293
294void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
295 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
296void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
297 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
298void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
299 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
300
301void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
302void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
303void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
304void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
305void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
306
307void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
308 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
309void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
310 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
311void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
312 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
313void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
314 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
315
316void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
317 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
318void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
319 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
320
321void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
322 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
323void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
324 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
325void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
326 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
327void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
328 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
329
330void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
331 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
332void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
333 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
334
335void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
336 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
337void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
338 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
339
340void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
341 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
342void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
343 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
344
345void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
346 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
347void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
348 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
349
350
351
352
353#define dc_isar_feature(name, ctx) \
354 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
355
356
357typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
358typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
359 uint32_t, uint32_t);
360typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
361 uint32_t, uint32_t, uint32_t);
362typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
363 uint32_t, uint32_t, uint32_t);
364
365
366typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
367typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
368typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
369typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
370typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
371typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
372typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
373typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
374typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
375typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
376typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
377typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
378typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
379typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
380typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
381
382#endif
383