LXR qemu/target/mips/internal.h

   1/*
   2 * MIPS internal definitions and helpers
   3 *
   4 * This work is licensed under the terms of the GNU GPL, version 2 or later.
   5 * See the COPYING file in the top-level directory.
   6 */
   7
   8#ifndef MIPS_INTERNAL_H
   9#define MIPS_INTERNAL_H
  10
  11#include "fpu/softfloat-helpers.h"
  12
  13/*
  14 * MMU types, the first four entries have the same layout as the
  15 * CP0C0_MT field.
  16 */
  17enum mips_mmu_types {
  18    MMU_TYPE_NONE,
  19    MMU_TYPE_R4000,
  20    MMU_TYPE_RESERVED,
  21    MMU_TYPE_FMT,
  22    MMU_TYPE_R3000,
  23    MMU_TYPE_R6000,
  24    MMU_TYPE_R8000
  25};
  26
  27struct mips_def_t {
  28    const char *name;
  29    int32_t CP0_PRid;
  30    int32_t CP0_Config0;
  31    int32_t CP0_Config1;
  32    int32_t CP0_Config2;
  33    int32_t CP0_Config3;
  34    int32_t CP0_Config4;
  35    int32_t CP0_Config4_rw_bitmask;
  36    int32_t CP0_Config5;
  37    int32_t CP0_Config5_rw_bitmask;
  38    int32_t CP0_Config6;
  39    int32_t CP0_Config7;
  40    target_ulong CP0_LLAddr_rw_bitmask;
  41    int CP0_LLAddr_shift;
  42    int32_t SYNCI_Step;
  43    int32_t CCRes;
  44    int32_t CP0_Status_rw_bitmask;
  45    int32_t CP0_TCStatus_rw_bitmask;
  46    int32_t CP0_SRSCtl;
  47    int32_t CP1_fcr0;
  48    int32_t CP1_fcr31_rw_bitmask;
  49    int32_t CP1_fcr31;
  50    int32_t MSAIR;
  51    int32_t SEGBITS;
  52    int32_t PABITS;
  53    int32_t CP0_SRSConf0_rw_bitmask;
  54    int32_t CP0_SRSConf0;
  55    int32_t CP0_SRSConf1_rw_bitmask;
  56    int32_t CP0_SRSConf1;
  57    int32_t CP0_SRSConf2_rw_bitmask;
  58    int32_t CP0_SRSConf2;
  59    int32_t CP0_SRSConf3_rw_bitmask;
  60    int32_t CP0_SRSConf3;
  61    int32_t CP0_SRSConf4_rw_bitmask;
  62    int32_t CP0_SRSConf4;
  63    int32_t CP0_PageGrain_rw_bitmask;
  64    int32_t CP0_PageGrain;
  65    target_ulong CP0_EBaseWG_rw_bitmask;
  66    uint64_t insn_flags;
  67    enum mips_mmu_types mmu_type;
  68    int32_t SAARP;
  69};
  70
  71extern const struct mips_def_t mips_defs[];
  72extern const int mips_defs_number;
  73
  74enum CPUMIPSMSADataFormat {
  75    DF_BYTE = 0,
  76    DF_HALF,
  77    DF_WORD,
  78    DF_DOUBLE
  79};
  80
  81void mips_cpu_do_interrupt(CPUState *cpu);
  82bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
  83void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
  84hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
  85int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
  86int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  87void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
  88                                  MMUAccessType access_type,
  89                                  int mmu_idx, uintptr_t retaddr);
  90
  91#if !defined(CONFIG_USER_ONLY)
  92
  93typedef struct r4k_tlb_t r4k_tlb_t;
  94struct r4k_tlb_t {
  95    target_ulong VPN;
  96    uint32_t PageMask;
  97    uint16_t ASID;
  98    uint32_t MMID;
  99    unsigned int G:1;
 100    unsigned int C0:3;
 101    unsigned int C1:3;
 102    unsigned int V0:1;
 103    unsigned int V1:1;
 104    unsigned int D0:1;
 105    unsigned int D1:1;
 106    unsigned int XI0:1;
 107    unsigned int XI1:1;
 108    unsigned int RI0:1;
 109    unsigned int RI1:1;
 110    unsigned int EHINV:1;
 111    uint64_t PFN[2];
 112};
 113
 114struct CPUMIPSTLBContext {
 115    uint32_t nb_tlb;
 116    uint32_t tlb_in_use;
 117    int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
 118                       target_ulong address, int rw, int access_type);
 119    void (*helper_tlbwi)(struct CPUMIPSState *env);
 120    void (*helper_tlbwr)(struct CPUMIPSState *env);
 121    void (*helper_tlbp)(struct CPUMIPSState *env);
 122    void (*helper_tlbr)(struct CPUMIPSState *env);
 123    void (*helper_tlbinv)(struct CPUMIPSState *env);
 124    void (*helper_tlbinvf)(struct CPUMIPSState *env);
 125    union {
 126        struct {
 127            r4k_tlb_t tlb[MIPS_TLB_MAX];
 128        } r4k;
 129    } mmu;
 130};
 131
 132int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
 133                       target_ulong address, int rw, int access_type);
 134int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
 135                          target_ulong address, int rw, int access_type);
 136int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
 137                    target_ulong address, int rw, int access_type);
 138void r4k_helper_tlbwi(CPUMIPSState *env);
 139void r4k_helper_tlbwr(CPUMIPSState *env);
 140void r4k_helper_tlbp(CPUMIPSState *env);
 141void r4k_helper_tlbr(CPUMIPSState *env);
 142void r4k_helper_tlbinv(CPUMIPSState *env);
 143void r4k_helper_tlbinvf(CPUMIPSState *env);
 144void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
 145
 146void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
 147                                    vaddr addr, unsigned size,
 148                                    MMUAccessType access_type,
 149                                    int mmu_idx, MemTxAttrs attrs,
 150                                    MemTxResult response, uintptr_t retaddr);
 151hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
 152                                  int rw);
 153#endif
 154
 155#define cpu_signal_handler cpu_mips_signal_handler
 156
 157#ifndef CONFIG_USER_ONLY
 158extern const VMStateDescription vmstate_mips_cpu;
 159#endif
 160
 161static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 162{
 163    return (env->CP0_Status & (1 << CP0St_IE)) &&
 164        !(env->CP0_Status & (1 << CP0St_EXL)) &&
 165        !(env->CP0_Status & (1 << CP0St_ERL)) &&
 166        !(env->hflags & MIPS_HFLAG_DM) &&
 167        /*
 168         * Note that the TCStatus IXMT field is initialized to zero,
 169         * and only MT capable cores can set it to one. So we don't
 170         * need to check for MT capabilities here.
 171         */
 172        !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
 173}
 174
 175/* Check if there is pending and not masked out interrupt */
 176static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 177{
 178    int32_t pending;
 179    int32_t status;
 180    bool r;
 181
 182    pending = env->CP0_Cause & CP0Ca_IP_mask;
 183    status = env->CP0_Status & CP0Ca_IP_mask;
 184
 185    if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 186        /*
 187         * A MIPS configured with a vectorizing external interrupt controller
 188         * will feed a vector into the Cause pending lines. The core treats
 189         * the status lines as a vector level, not as indiviual masks.
 190         */
 191        r = pending > status;
 192    } else {
 193        /*
 194         * A MIPS configured with compatibility or VInt (Vectored Interrupts)
 195         * treats the pending lines as individual interrupt lines, the status
 196         * lines are individual masks.
 197         */
 198        r = (pending & status) != 0;
 199    }
 200    return r;
 201}
 202
 203void mips_tcg_init(void);
 204
 205/* TODO QOM'ify CPU reset and remove */
 206void cpu_state_reset(CPUMIPSState *s);
 207void cpu_mips_realize_env(CPUMIPSState *env);
 208
 209/* cp0_timer.c */
 210uint32_t cpu_mips_get_random(CPUMIPSState *env);
 211uint32_t cpu_mips_get_count(CPUMIPSState *env);
 212void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
 213void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
 214void cpu_mips_start_count(CPUMIPSState *env);
 215void cpu_mips_stop_count(CPUMIPSState *env);
 216
 217/* helper.c */
 218bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 219                       MMUAccessType access_type, int mmu_idx,
 220                       bool probe, uintptr_t retaddr);
 221
 222/* op_helper.c */
 223uint32_t float_class_s(uint32_t arg, float_status *fst);
 224uint64_t float_class_d(uint64_t arg, float_status *fst);
 225
 226extern unsigned int ieee_rm[];
 227int ieee_ex_to_mips(int xcpt);
 228void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
 229
 230static inline void restore_rounding_mode(CPUMIPSState *env)
 231{
 232    set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
 233                            &env->active_fpu.fp_status);
 234}
 235
 236static inline void restore_flush_mode(CPUMIPSState *env)
 237{
 238    set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
 239                      &env->active_fpu.fp_status);
 240}
 241
 242static inline void restore_snan_bit_mode(CPUMIPSState *env)
 243{
 244    set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
 245                        &env->active_fpu.fp_status);
 246}
 247
 248static inline void restore_fp_status(CPUMIPSState *env)
 249{
 250    restore_rounding_mode(env);
 251    restore_flush_mode(env);
 252    restore_snan_bit_mode(env);
 253}
 254
 255static inline void restore_msa_fp_status(CPUMIPSState *env)
 256{
 257    float_status *status = &env->active_tc.msa_fp_status;
 258    int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
 259    bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
 260
 261    set_float_rounding_mode(ieee_rm[rounding_mode], status);
 262    set_flush_to_zero(flush_to_zero, status);
 263    set_flush_inputs_to_zero(flush_to_zero, status);
 264}
 265
 266static inline void restore_pamask(CPUMIPSState *env)
 267{
 268    if (env->hflags & MIPS_HFLAG_ELPA) {
 269        env->PAMask = (1ULL << env->PABITS) - 1;
 270    } else {
 271        env->PAMask = PAMASK_BASE;
 272    }
 273}
 274
 275static inline int mips_vpe_active(CPUMIPSState *env)
 276{
 277    int active = 1;
 278
 279    /* Check that the VPE is enabled.  */
 280    if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 281        active = 0;
 282    }
 283    /* Check that the VPE is activated.  */
 284    if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 285        active = 0;
 286    }
 287
 288    /*
 289     * Now verify that there are active thread contexts in the VPE.
 290     *
 291     * This assumes the CPU model will internally reschedule threads
 292     * if the active one goes to sleep. If there are no threads available
 293     * the active one will be in a sleeping state, and we can turn off
 294     * the entire VPE.
 295     */
 296    if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 297        /* TC is not activated.  */
 298        active = 0;
 299    }
 300    if (env->active_tc.CP0_TCHalt & 1) {
 301        /* TC is in halt state.  */
 302        active = 0;
 303    }
 304
 305    return active;
 306}
 307
 308static inline int mips_vp_active(CPUMIPSState *env)
 309{
 310    CPUState *other_cs = first_cpu;
 311
 312    /* Check if the VP disabled other VPs (which means the VP is enabled) */
 313    if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
 314        return 1;
 315    }
 316
 317    /* Check if the virtual processor is disabled due to a DVP */
 318    CPU_FOREACH(other_cs) {
 319        MIPSCPU *other_cpu = MIPS_CPU(other_cs);
 320        if ((&other_cpu->env != env) &&
 321            ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
 322            return 0;
 323        }
 324    }
 325    return 1;
 326}
 327
 328static inline void compute_hflags(CPUMIPSState *env)
 329{
 330    env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 331                     MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 332                     MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
 333                     MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
 334                     MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
 335    if (env->CP0_Status & (1 << CP0St_ERL)) {
 336        env->hflags |= MIPS_HFLAG_ERL;
 337    }
 338    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 339        !(env->CP0_Status & (1 << CP0St_ERL)) &&
 340        !(env->hflags & MIPS_HFLAG_DM)) {
 341        env->hflags |= (env->CP0_Status >> CP0St_KSU) &
 342                       MIPS_HFLAG_KSU;
 343    }
 344#if defined(TARGET_MIPS64)
 345    if ((env->insn_flags & ISA_MIPS3) &&
 346        (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 347         (env->CP0_Status & (1 << CP0St_PX)) ||
 348         (env->CP0_Status & (1 << CP0St_UX)))) {
 349        env->hflags |= MIPS_HFLAG_64;
 350    }
 351
 352    if (!(env->insn_flags & ISA_MIPS3)) {
 353        env->hflags |= MIPS_HFLAG_AWRAP;
 354    } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 355               !(env->CP0_Status & (1 << CP0St_UX))) {
 356        env->hflags |= MIPS_HFLAG_AWRAP;
 357    } else if (env->insn_flags & ISA_MIPS64R6) {
 358        /* Address wrapping for Supervisor and Kernel is specified in R6 */
 359        if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
 360             !(env->CP0_Status & (1 << CP0St_SX))) ||
 361            (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
 362             !(env->CP0_Status & (1 << CP0St_KX)))) {
 363            env->hflags |= MIPS_HFLAG_AWRAP;
 364        }
 365    }
 366#endif
 367    if (((env->CP0_Status & (1 << CP0St_CU0)) &&
 368         !(env->insn_flags & ISA_MIPS32R6)) ||
 369        !(env->hflags & MIPS_HFLAG_KSU)) {
 370        env->hflags |= MIPS_HFLAG_CP0;
 371    }
 372    if (env->CP0_Status & (1 << CP0St_CU1)) {
 373        env->hflags |= MIPS_HFLAG_FPU;
 374    }
 375    if (env->CP0_Status & (1 << CP0St_FR)) {
 376        env->hflags |= MIPS_HFLAG_F64;
 377    }
 378    if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
 379        (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
 380        env->hflags |= MIPS_HFLAG_SBRI;
 381    }
 382    if (env->insn_flags & ASE_DSP_R3) {
 383        /*
 384         * Our cpu supports DSP R3 ASE, so enable
 385         * access to DSP R3 resources.
 386         */
 387        if (env->CP0_Status & (1 << CP0St_MX)) {
 388            env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
 389                           MIPS_HFLAG_DSP_R3;
 390        }
 391    } else if (env->insn_flags & ASE_DSP_R2) {
 392        /*
 393         * Our cpu supports DSP R2 ASE, so enable
 394         * access to DSP R2 resources.
 395         */
 396        if (env->CP0_Status & (1 << CP0St_MX)) {
 397            env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2;
 398        }
 399
 400    } else if (env->insn_flags & ASE_DSP) {
 401        /*
 402         * Our cpu supports DSP ASE, so enable
 403         * access to DSP resources.
 404         */
 405        if (env->CP0_Status & (1 << CP0St_MX)) {
 406            env->hflags |= MIPS_HFLAG_DSP;
 407        }
 408
 409    }
 410    if (env->insn_flags & ISA_MIPS32R2) {
 411        if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
 412            env->hflags |= MIPS_HFLAG_COP1X;
 413        }
 414    } else if (env->insn_flags & ISA_MIPS32) {
 415        if (env->hflags & MIPS_HFLAG_64) {
 416            env->hflags |= MIPS_HFLAG_COP1X;
 417        }
 418    } else if (env->insn_flags & ISA_MIPS4) {
 419        /*
 420         * All supported MIPS IV CPUs use the XX (CU3) to enable
 421         * and disable the MIPS IV extensions to the MIPS III ISA.
 422         * Some other MIPS IV CPUs ignore the bit, so the check here
 423         * would be too restrictive for them.
 424         */
 425        if (env->CP0_Status & (1U << CP0St_CU3)) {
 426            env->hflags |= MIPS_HFLAG_COP1X;
 427        }
 428    }
 429    if (env->insn_flags & ASE_MSA) {
 430        if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
 431            env->hflags |= MIPS_HFLAG_MSA;
 432        }
 433    }
 434    if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
 435        if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
 436            env->hflags |= MIPS_HFLAG_FRE;
 437        }
 438    }
 439    if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
 440        if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
 441            env->hflags |= MIPS_HFLAG_ELPA;
 442        }
 443    }
 444}
 445
 446void cpu_mips_tlb_flush(CPUMIPSState *env);
 447void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
 448void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
 449void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
 450
 451void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
 452                                          int error_code, uintptr_t pc);
 453
 454static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
 455                                                    uint32_t exception,
 456                                                    uintptr_t pc)
 457{
 458    do_raise_exception_err(env, exception, 0, pc);
 459}
 460
 461#endif
 462