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19#include "qemu/osdep.h"
20#include "qemu/log.h"
21#include "cpu.h"
22#include "tcg/tcg-op.h"
23#include "disas/disas.h"
24#include "exec/cpu_ldst.h"
25#include "exec/exec-all.h"
26#include "exec/helper-proto.h"
27#include "exec/helper-gen.h"
28
29#include "exec/translator.h"
30#include "exec/log.h"
31
32#include "instmap.h"
33
34
35static TCGv cpu_gpr[32], cpu_pc;
36static TCGv_i64 cpu_fpr[32];
37static TCGv load_res;
38static TCGv load_val;
39
40#include "exec/gen-icount.h"
41
42typedef struct DisasContext {
43 DisasContextBase base;
44
45 target_ulong pc_succ_insn;
46 target_ulong priv_ver;
47 bool virt_enabled;
48 uint32_t opcode;
49 uint32_t mstatus_fs;
50 uint32_t misa;
51 uint32_t mem_idx;
52
53
54
55
56
57 int frm;
58 bool ext_ifencei;
59} DisasContext;
60
61#ifdef TARGET_RISCV64
62
63static const int tcg_memop_lookup[8] = {
64 [0 ... 7] = -1,
65 [0] = MO_SB,
66 [1] = MO_TESW,
67 [2] = MO_TESL,
68 [3] = MO_TEQ,
69 [4] = MO_UB,
70 [5] = MO_TEUW,
71 [6] = MO_TEUL,
72};
73#endif
74
75#ifdef TARGET_RISCV64
76#define CASE_OP_32_64(X) case X: case glue(X, W)
77#else
78#define CASE_OP_32_64(X) case X
79#endif
80
81static inline bool has_ext(DisasContext *ctx, uint32_t ext)
82{
83 return ctx->misa & ext;
84}
85
86static void generate_exception(DisasContext *ctx, int excp)
87{
88 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
89 TCGv_i32 helper_tmp = tcg_const_i32(excp);
90 gen_helper_raise_exception(cpu_env, helper_tmp);
91 tcg_temp_free_i32(helper_tmp);
92 ctx->base.is_jmp = DISAS_NORETURN;
93}
94
95static void generate_exception_mbadaddr(DisasContext *ctx, int excp)
96{
97 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
98 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
99 TCGv_i32 helper_tmp = tcg_const_i32(excp);
100 gen_helper_raise_exception(cpu_env, helper_tmp);
101 tcg_temp_free_i32(helper_tmp);
102 ctx->base.is_jmp = DISAS_NORETURN;
103}
104
105static void gen_exception_debug(void)
106{
107 TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG);
108 gen_helper_raise_exception(cpu_env, helper_tmp);
109 tcg_temp_free_i32(helper_tmp);
110}
111
112
113static void exit_tb(DisasContext *ctx)
114{
115 if (ctx->base.singlestep_enabled) {
116 gen_exception_debug();
117 } else {
118 tcg_gen_exit_tb(NULL, 0);
119 }
120}
121
122
123static void lookup_and_goto_ptr(DisasContext *ctx)
124{
125 if (ctx->base.singlestep_enabled) {
126 gen_exception_debug();
127 } else {
128 tcg_gen_lookup_and_goto_ptr();
129 }
130}
131
132static void gen_exception_illegal(DisasContext *ctx)
133{
134 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
135}
136
137static void gen_exception_inst_addr_mis(DisasContext *ctx)
138{
139 generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS);
140}
141
142static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
143{
144 if (unlikely(ctx->base.singlestep_enabled)) {
145 return false;
146 }
147
148#ifndef CONFIG_USER_ONLY
149 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
150#else
151 return true;
152#endif
153}
154
155static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
156{
157 if (use_goto_tb(ctx, dest)) {
158
159 tcg_gen_goto_tb(n);
160 tcg_gen_movi_tl(cpu_pc, dest);
161
162
163
164
165 tcg_gen_exit_tb(ctx->base.tb, n);
166 } else {
167 tcg_gen_movi_tl(cpu_pc, dest);
168 lookup_and_goto_ptr(ctx);
169 }
170}
171
172
173
174
175static inline void gen_get_gpr(TCGv t, int reg_num)
176{
177 if (reg_num == 0) {
178 tcg_gen_movi_tl(t, 0);
179 } else {
180 tcg_gen_mov_tl(t, cpu_gpr[reg_num]);
181 }
182}
183
184
185
186
187
188
189static inline void gen_set_gpr(int reg_num_dst, TCGv t)
190{
191 if (reg_num_dst != 0) {
192 tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t);
193 }
194}
195
196static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
197{
198 TCGv rl = tcg_temp_new();
199 TCGv rh = tcg_temp_new();
200
201 tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
202
203 tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
204 tcg_gen_and_tl(rl, rl, arg2);
205 tcg_gen_sub_tl(ret, rh, rl);
206
207 tcg_temp_free(rl);
208 tcg_temp_free(rh);
209}
210
211static void gen_div(TCGv ret, TCGv source1, TCGv source2)
212{
213 TCGv cond1, cond2, zeroreg, resultopt1;
214
215
216
217
218
219 cond1 = tcg_temp_new();
220 cond2 = tcg_temp_new();
221 zeroreg = tcg_const_tl(0);
222 resultopt1 = tcg_temp_new();
223
224 tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
225 tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
226 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
227 ((target_ulong)1) << (TARGET_LONG_BITS - 1));
228 tcg_gen_and_tl(cond1, cond1, cond2);
229 tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0);
230
231 tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
232 resultopt1);
233
234 tcg_gen_or_tl(cond1, cond1, cond2);
235 tcg_gen_movi_tl(resultopt1, (target_ulong)1);
236 tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
237 resultopt1);
238 tcg_gen_div_tl(ret, source1, source2);
239
240 tcg_temp_free(cond1);
241 tcg_temp_free(cond2);
242 tcg_temp_free(zeroreg);
243 tcg_temp_free(resultopt1);
244}
245
246static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
247{
248 TCGv cond1, zeroreg, resultopt1;
249 cond1 = tcg_temp_new();
250
251 zeroreg = tcg_const_tl(0);
252 resultopt1 = tcg_temp_new();
253
254 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
255 tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
256 tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
257 resultopt1);
258 tcg_gen_movi_tl(resultopt1, (target_ulong)1);
259 tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
260 resultopt1);
261 tcg_gen_divu_tl(ret, source1, source2);
262
263 tcg_temp_free(cond1);
264 tcg_temp_free(zeroreg);
265 tcg_temp_free(resultopt1);
266}
267
268static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
269{
270 TCGv cond1, cond2, zeroreg, resultopt1;
271
272 cond1 = tcg_temp_new();
273 cond2 = tcg_temp_new();
274 zeroreg = tcg_const_tl(0);
275 resultopt1 = tcg_temp_new();
276
277 tcg_gen_movi_tl(resultopt1, 1L);
278 tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
279 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
280 (target_ulong)1 << (TARGET_LONG_BITS - 1));
281 tcg_gen_and_tl(cond2, cond1, cond2);
282 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
283
284 tcg_gen_or_tl(cond2, cond1, cond2);
285 tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
286 resultopt1);
287 tcg_gen_rem_tl(resultopt1, source1, source2);
288
289 tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
290 source1);
291
292 tcg_temp_free(cond1);
293 tcg_temp_free(cond2);
294 tcg_temp_free(zeroreg);
295 tcg_temp_free(resultopt1);
296}
297
298static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
299{
300 TCGv cond1, zeroreg, resultopt1;
301 cond1 = tcg_temp_new();
302 zeroreg = tcg_const_tl(0);
303 resultopt1 = tcg_temp_new();
304
305 tcg_gen_movi_tl(resultopt1, (target_ulong)1);
306 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
307 tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
308 resultopt1);
309 tcg_gen_remu_tl(resultopt1, source1, source2);
310
311 tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
312 source1);
313
314 tcg_temp_free(cond1);
315 tcg_temp_free(zeroreg);
316 tcg_temp_free(resultopt1);
317}
318
319static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
320{
321 target_ulong next_pc;
322
323
324 next_pc = ctx->base.pc_next + imm;
325 if (!has_ext(ctx, RVC)) {
326 if ((next_pc & 0x3) != 0) {
327 gen_exception_inst_addr_mis(ctx);
328 return;
329 }
330 }
331 if (rd != 0) {
332 tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
333 }
334
335 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm);
336 ctx->base.is_jmp = DISAS_NORETURN;
337}
338
339#ifdef TARGET_RISCV64
340static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1,
341 target_long imm)
342{
343 TCGv t0 = tcg_temp_new();
344 TCGv t1 = tcg_temp_new();
345 gen_get_gpr(t0, rs1);
346 tcg_gen_addi_tl(t0, t0, imm);
347 int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
348
349 if (memop < 0) {
350 gen_exception_illegal(ctx);
351 return;
352 }
353
354 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop);
355 gen_set_gpr(rd, t1);
356 tcg_temp_free(t0);
357 tcg_temp_free(t1);
358}
359
360static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
361 target_long imm)
362{
363 TCGv t0 = tcg_temp_new();
364 TCGv dat = tcg_temp_new();
365 gen_get_gpr(t0, rs1);
366 tcg_gen_addi_tl(t0, t0, imm);
367 gen_get_gpr(dat, rs2);
368 int memop = tcg_memop_lookup[(opc >> 12) & 0x7];
369
370 if (memop < 0) {
371 gen_exception_illegal(ctx);
372 return;
373 }
374
375 tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop);
376 tcg_temp_free(t0);
377 tcg_temp_free(dat);
378}
379#endif
380
381#ifndef CONFIG_USER_ONLY
382
383
384
385
386
387static void mark_fs_dirty(DisasContext *ctx)
388{
389 TCGv tmp;
390 if (ctx->mstatus_fs == MSTATUS_FS) {
391 return;
392 }
393
394 ctx->mstatus_fs = MSTATUS_FS;
395
396 tmp = tcg_temp_new();
397 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
398 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
399 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
400
401 if (ctx->virt_enabled) {
402 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
403 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
404 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
405 }
406 tcg_temp_free(tmp);
407}
408#else
409static inline void mark_fs_dirty(DisasContext *ctx) { }
410#endif
411
412#if !defined(TARGET_RISCV64)
413static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
414 int rs1, target_long imm)
415{
416 TCGv t0;
417
418 if (ctx->mstatus_fs == 0) {
419 gen_exception_illegal(ctx);
420 return;
421 }
422
423 t0 = tcg_temp_new();
424 gen_get_gpr(t0, rs1);
425 tcg_gen_addi_tl(t0, t0, imm);
426
427 switch (opc) {
428 case OPC_RISC_FLW:
429 if (!has_ext(ctx, RVF)) {
430 goto do_illegal;
431 }
432 tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
433
434 tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
435 break;
436 case OPC_RISC_FLD:
437 if (!has_ext(ctx, RVD)) {
438 goto do_illegal;
439 }
440 tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
441 break;
442 do_illegal:
443 default:
444 gen_exception_illegal(ctx);
445 break;
446 }
447 tcg_temp_free(t0);
448
449 mark_fs_dirty(ctx);
450}
451
452static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
453 int rs2, target_long imm)
454{
455 TCGv t0;
456
457 if (ctx->mstatus_fs == 0) {
458 gen_exception_illegal(ctx);
459 return;
460 }
461
462 t0 = tcg_temp_new();
463 gen_get_gpr(t0, rs1);
464 tcg_gen_addi_tl(t0, t0, imm);
465
466 switch (opc) {
467 case OPC_RISC_FSW:
468 if (!has_ext(ctx, RVF)) {
469 goto do_illegal;
470 }
471 tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
472 break;
473 case OPC_RISC_FSD:
474 if (!has_ext(ctx, RVD)) {
475 goto do_illegal;
476 }
477 tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
478 break;
479 do_illegal:
480 default:
481 gen_exception_illegal(ctx);
482 break;
483 }
484
485 tcg_temp_free(t0);
486}
487#endif
488
489static void gen_set_rm(DisasContext *ctx, int rm)
490{
491 TCGv_i32 t0;
492
493 if (ctx->frm == rm) {
494 return;
495 }
496 ctx->frm = rm;
497 t0 = tcg_const_i32(rm);
498 gen_helper_set_rounding_mode(cpu_env, t0);
499 tcg_temp_free_i32(t0);
500}
501
502static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode)
503{
504 uint8_t funct3 = extract16(opcode, 13, 3);
505 uint8_t rd_rs2 = GET_C_RS2S(opcode);
506 uint8_t rs1s = GET_C_RS1S(opcode);
507
508 switch (funct3) {
509 case 3:
510#if defined(TARGET_RISCV64)
511
512 gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s,
513 GET_C_LD_IMM(opcode));
514#else
515
516 gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s,
517 GET_C_LW_IMM(opcode));
518#endif
519 break;
520 case 7:
521#if defined(TARGET_RISCV64)
522
523 gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2,
524 GET_C_LD_IMM(opcode));
525#else
526
527 gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2,
528 GET_C_LW_IMM(opcode));
529#endif
530 break;
531 }
532}
533
534static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode)
535{
536 uint8_t op = extract16(opcode, 0, 2);
537
538 switch (op) {
539 case 0:
540 decode_RV32_64C0(ctx, opcode);
541 break;
542 }
543}
544
545#define EX_SH(amount) \
546 static int ex_shift_##amount(DisasContext *ctx, int imm) \
547 { \
548 return imm << amount; \
549 }
550EX_SH(1)
551EX_SH(2)
552EX_SH(3)
553EX_SH(4)
554EX_SH(12)
555
556#define REQUIRE_EXT(ctx, ext) do { \
557 if (!has_ext(ctx, ext)) { \
558 return false; \
559 } \
560} while (0)
561
562static int ex_rvc_register(DisasContext *ctx, int reg)
563{
564 return 8 + reg;
565}
566
567static int ex_rvc_shifti(DisasContext *ctx, int imm)
568{
569
570 return imm ? imm : 64;
571}
572
573
574#include "decode_insn32.inc.c"
575
576static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
577 void (*func)(TCGv, TCGv, target_long))
578{
579 TCGv source1;
580 source1 = tcg_temp_new();
581
582 gen_get_gpr(source1, a->rs1);
583
584 (*func)(source1, source1, a->imm);
585
586 gen_set_gpr(a->rd, source1);
587 tcg_temp_free(source1);
588 return true;
589}
590
591static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
592 void (*func)(TCGv, TCGv, TCGv))
593{
594 TCGv source1, source2;
595 source1 = tcg_temp_new();
596 source2 = tcg_temp_new();
597
598 gen_get_gpr(source1, a->rs1);
599 tcg_gen_movi_tl(source2, a->imm);
600
601 (*func)(source1, source1, source2);
602
603 gen_set_gpr(a->rd, source1);
604 tcg_temp_free(source1);
605 tcg_temp_free(source2);
606 return true;
607}
608
609#ifdef TARGET_RISCV64
610static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2)
611{
612 tcg_gen_add_tl(ret, arg1, arg2);
613 tcg_gen_ext32s_tl(ret, ret);
614}
615
616static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2)
617{
618 tcg_gen_sub_tl(ret, arg1, arg2);
619 tcg_gen_ext32s_tl(ret, ret);
620}
621
622static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2)
623{
624 tcg_gen_mul_tl(ret, arg1, arg2);
625 tcg_gen_ext32s_tl(ret, ret);
626}
627
628static bool gen_arith_div_w(DisasContext *ctx, arg_r *a,
629 void(*func)(TCGv, TCGv, TCGv))
630{
631 TCGv source1, source2;
632 source1 = tcg_temp_new();
633 source2 = tcg_temp_new();
634
635 gen_get_gpr(source1, a->rs1);
636 gen_get_gpr(source2, a->rs2);
637 tcg_gen_ext32s_tl(source1, source1);
638 tcg_gen_ext32s_tl(source2, source2);
639
640 (*func)(source1, source1, source2);
641
642 tcg_gen_ext32s_tl(source1, source1);
643 gen_set_gpr(a->rd, source1);
644 tcg_temp_free(source1);
645 tcg_temp_free(source2);
646 return true;
647}
648
649static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
650 void(*func)(TCGv, TCGv, TCGv))
651{
652 TCGv source1, source2;
653 source1 = tcg_temp_new();
654 source2 = tcg_temp_new();
655
656 gen_get_gpr(source1, a->rs1);
657 gen_get_gpr(source2, a->rs2);
658 tcg_gen_ext32u_tl(source1, source1);
659 tcg_gen_ext32u_tl(source2, source2);
660
661 (*func)(source1, source1, source2);
662
663 tcg_gen_ext32s_tl(source1, source1);
664 gen_set_gpr(a->rd, source1);
665 tcg_temp_free(source1);
666 tcg_temp_free(source2);
667 return true;
668}
669
670#endif
671
672static bool gen_arith(DisasContext *ctx, arg_r *a,
673 void(*func)(TCGv, TCGv, TCGv))
674{
675 TCGv source1, source2;
676 source1 = tcg_temp_new();
677 source2 = tcg_temp_new();
678
679 gen_get_gpr(source1, a->rs1);
680 gen_get_gpr(source2, a->rs2);
681
682 (*func)(source1, source1, source2);
683
684 gen_set_gpr(a->rd, source1);
685 tcg_temp_free(source1);
686 tcg_temp_free(source2);
687 return true;
688}
689
690static bool gen_shift(DisasContext *ctx, arg_r *a,
691 void(*func)(TCGv, TCGv, TCGv))
692{
693 TCGv source1 = tcg_temp_new();
694 TCGv source2 = tcg_temp_new();
695
696 gen_get_gpr(source1, a->rs1);
697 gen_get_gpr(source2, a->rs2);
698
699 tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
700 (*func)(source1, source1, source2);
701
702 gen_set_gpr(a->rd, source1);
703 tcg_temp_free(source1);
704 tcg_temp_free(source2);
705 return true;
706}
707
708
709#include "insn_trans/trans_rvi.inc.c"
710#include "insn_trans/trans_rvm.inc.c"
711#include "insn_trans/trans_rva.inc.c"
712#include "insn_trans/trans_rvf.inc.c"
713#include "insn_trans/trans_rvd.inc.c"
714#include "insn_trans/trans_privileged.inc.c"
715
716
717#include "decode_insn16.inc.c"
718
719static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
720{
721
722 if (extract16(opcode, 0, 2) != 3) {
723 if (!has_ext(ctx, RVC)) {
724 gen_exception_illegal(ctx);
725 } else {
726 ctx->pc_succ_insn = ctx->base.pc_next + 2;
727 if (!decode_insn16(ctx, opcode)) {
728
729 decode_RV32_64C(ctx, opcode);
730 }
731 }
732 } else {
733 uint32_t opcode32 = opcode;
734 opcode32 = deposit32(opcode32, 16, 16,
735 translator_lduw(env, ctx->base.pc_next + 2));
736 ctx->pc_succ_insn = ctx->base.pc_next + 4;
737 if (!decode_insn32(ctx, opcode32)) {
738 gen_exception_illegal(ctx);
739 }
740 }
741}
742
743static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
744{
745 DisasContext *ctx = container_of(dcbase, DisasContext, base);
746 CPURISCVState *env = cs->env_ptr;
747 RISCVCPU *cpu = RISCV_CPU(cs);
748
749 ctx->pc_succ_insn = ctx->base.pc_first;
750 ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
751 ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
752 ctx->priv_ver = env->priv_ver;
753#if !defined(CONFIG_USER_ONLY)
754 if (riscv_has_ext(env, RVH)) {
755 ctx->virt_enabled = riscv_cpu_virt_enabled(env);
756 if (env->priv_ver == PRV_M &&
757 get_field(env->mstatus, MSTATUS_MPRV) &&
758 MSTATUS_MPV_ISSET(env)) {
759 ctx->virt_enabled = true;
760 } else if (env->priv == PRV_S &&
761 !riscv_cpu_virt_enabled(env) &&
762 get_field(env->hstatus, HSTATUS_SPRV) &&
763 get_field(env->hstatus, HSTATUS_SPV)) {
764 ctx->virt_enabled = true;
765 }
766 } else {
767 ctx->virt_enabled = false;
768 }
769#else
770 ctx->virt_enabled = false;
771#endif
772 ctx->misa = env->misa;
773 ctx->frm = -1;
774 ctx->ext_ifencei = cpu->cfg.ext_ifencei;
775}
776
777static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
778{
779}
780
781static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
782{
783 DisasContext *ctx = container_of(dcbase, DisasContext, base);
784
785 tcg_gen_insn_start(ctx->base.pc_next);
786}
787
788static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
789 const CPUBreakpoint *bp)
790{
791 DisasContext *ctx = container_of(dcbase, DisasContext, base);
792
793 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
794 ctx->base.is_jmp = DISAS_NORETURN;
795 gen_exception_debug();
796
797
798
799
800 ctx->base.pc_next += 4;
801 return true;
802}
803
804static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
805{
806 DisasContext *ctx = container_of(dcbase, DisasContext, base);
807 CPURISCVState *env = cpu->env_ptr;
808 uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next);
809
810 decode_opc(env, ctx, opcode16);
811 ctx->base.pc_next = ctx->pc_succ_insn;
812
813 if (ctx->base.is_jmp == DISAS_NEXT) {
814 target_ulong page_start;
815
816 page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
817 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
818 ctx->base.is_jmp = DISAS_TOO_MANY;
819 }
820 }
821}
822
823static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
824{
825 DisasContext *ctx = container_of(dcbase, DisasContext, base);
826
827 switch (ctx->base.is_jmp) {
828 case DISAS_TOO_MANY:
829 gen_goto_tb(ctx, 0, ctx->base.pc_next);
830 break;
831 case DISAS_NORETURN:
832 break;
833 default:
834 g_assert_not_reached();
835 }
836}
837
838static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
839{
840#ifndef CONFIG_USER_ONLY
841 RISCVCPU *rvcpu = RISCV_CPU(cpu);
842 CPURISCVState *env = &rvcpu->env;
843#endif
844
845 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
846#ifndef CONFIG_USER_ONLY
847 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt);
848#endif
849 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
850}
851
852static const TranslatorOps riscv_tr_ops = {
853 .init_disas_context = riscv_tr_init_disas_context,
854 .tb_start = riscv_tr_tb_start,
855 .insn_start = riscv_tr_insn_start,
856 .breakpoint_check = riscv_tr_breakpoint_check,
857 .translate_insn = riscv_tr_translate_insn,
858 .tb_stop = riscv_tr_tb_stop,
859 .disas_log = riscv_tr_disas_log,
860};
861
862void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
863{
864 DisasContext ctx;
865
866 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
867}
868
869void riscv_translate_init(void)
870{
871 int i;
872
873
874
875
876 cpu_gpr[0] = NULL;
877
878 for (i = 1; i < 32; i++) {
879 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
880 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
881 }
882
883 for (i = 0; i < 32; i++) {
884 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
885 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
886 }
887
888 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
889 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
890 "load_res");
891 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
892 "load_val");
893}
894