LXR qemu/hw/intc/grlib

   1/*
   2 * QEMU GRLIB IRQMP Emulator
   3 *
   4 * (Multiprocessor and extended interrupt not supported)
   5 *
   6 * Copyright (c) 2010-2019 AdaCore
   7 *
   8 * Permission is hereby granted, free of charge, to any person obtaining a copy
   9 * of this software and associated documentation files (the "Software"), to deal
  10 * in the Software without restriction, including without limitation the rights
  11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12 * copies of the Software, and to permit persons to whom the Software is
  13 * furnished to do so, subject to the following conditions:
  14 *
  15 * The above copyright notice and this permission notice shall be included in
  16 * all copies or substantial portions of the Software.
  17 *
  18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24 * THE SOFTWARE.
  25 */
  26
  27#include "qemu/osdep.h"
  28#include "hw/irq.h"
  29#include "hw/sysbus.h"
  30#include "cpu.h"
  31
  32#include "hw/qdev-properties.h"
  33#include "hw/sparc/grlib.h"
  34
  35#include "trace.h"
  36#include "qapi/error.h"
  37#include "qemu/module.h"
  38
  39#define IRQMP_MAX_CPU 16
  40#define IRQMP_REG_SIZE 256      /* Size of memory mapped registers */
  41
  42/* Memory mapped register offsets */
  43#define LEVEL_OFFSET     0x00
  44#define PENDING_OFFSET   0x04
  45#define FORCE0_OFFSET    0x08
  46#define CLEAR_OFFSET     0x0C
  47#define MP_STATUS_OFFSET 0x10
  48#define BROADCAST_OFFSET 0x14
  49#define MASK_OFFSET      0x40
  50#define FORCE_OFFSET     0x80
  51#define EXTENDED_OFFSET  0xC0
  52
  53#define GRLIB_IRQMP(obj) OBJECT_CHECK(IRQMP, (obj), TYPE_GRLIB_IRQMP)
  54
  55typedef struct IRQMPState IRQMPState;
  56
  57typedef struct IRQMP {
  58    SysBusDevice parent_obj;
  59
  60    MemoryRegion iomem;
  61
  62    IRQMPState *state;
  63    qemu_irq irq;
  64} IRQMP;
  65
  66struct IRQMPState {
  67    uint32_t level;
  68    uint32_t pending;
  69    uint32_t clear;
  70    uint32_t broadcast;
  71
  72    uint32_t mask[IRQMP_MAX_CPU];
  73    uint32_t force[IRQMP_MAX_CPU];
  74    uint32_t extended[IRQMP_MAX_CPU];
  75
  76    IRQMP    *parent;
  77};
  78
  79static void grlib_irqmp_check_irqs(IRQMPState *state)
  80{
  81    uint32_t      pend   = 0;
  82    uint32_t      level0 = 0;
  83    uint32_t      level1 = 0;
  84
  85    assert(state != NULL);
  86    assert(state->parent != NULL);
  87
  88    /* IRQ for CPU 0 (no SMP support) */
  89    pend = (state->pending | state->force[0])
  90        & state->mask[0];
  91
  92    level0 = pend & ~state->level;
  93    level1 = pend &  state->level;
  94
  95    trace_grlib_irqmp_check_irqs(state->pending, state->force[0],
  96                                 state->mask[0], level1, level0);
  97
  98    /* Trigger level1 interrupt first and level0 if there is no level1 */
  99    qemu_set_irq(state->parent->irq, level1 ?: level0);
 100}
 101
 102static void grlib_irqmp_ack_mask(IRQMPState *state, uint32_t mask)
 103{
 104    /* Clear registers */
 105    state->pending  &= ~mask;
 106    state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */
 107
 108    grlib_irqmp_check_irqs(state);
 109}
 110
 111void grlib_irqmp_ack(DeviceState *dev, int intno)
 112{
 113    IRQMP        *irqmp = GRLIB_IRQMP(dev);
 114    IRQMPState   *state;
 115    uint32_t      mask;
 116
 117    state = irqmp->state;
 118    assert(state != NULL);
 119
 120    intno &= 15;
 121    mask = 1 << intno;
 122
 123    trace_grlib_irqmp_ack(intno);
 124
 125    grlib_irqmp_ack_mask(state, mask);
 126}
 127
 128void grlib_irqmp_set_irq(void *opaque, int irq, int level)
 129{
 130    IRQMP      *irqmp = GRLIB_IRQMP(opaque);
 131    IRQMPState *s;
 132    int         i = 0;
 133
 134    s = irqmp->state;
 135    assert(s         != NULL);
 136    assert(s->parent != NULL);
 137
 138
 139    if (level) {
 140        trace_grlib_irqmp_set_irq(irq);
 141
 142        if (s->broadcast & 1 << irq) {
 143            /* Broadcasted IRQ */
 144            for (i = 0; i < IRQMP_MAX_CPU; i++) {
 145                s->force[i] |= 1 << irq;
 146            }
 147        } else {
 148            s->pending |= 1 << irq;
 149        }
 150        grlib_irqmp_check_irqs(s);
 151
 152    }
 153}
 154
 155static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr,
 156                                 unsigned size)
 157{
 158    IRQMP      *irqmp = opaque;
 159    IRQMPState *state;
 160
 161    assert(irqmp != NULL);
 162    state = irqmp->state;
 163    assert(state != NULL);
 164
 165    addr &= 0xff;
 166
 167    /* global registers */
 168    switch (addr) {
 169    case LEVEL_OFFSET:
 170        return state->level;
 171
 172    case PENDING_OFFSET:
 173        return state->pending;
 174
 175    case FORCE0_OFFSET:
 176        /* This register is an "alias" for the force register of CPU 0 */
 177        return state->force[0];
 178
 179    case CLEAR_OFFSET:
 180    case MP_STATUS_OFFSET:
 181        /* Always read as 0 */
 182        return 0;
 183
 184    case BROADCAST_OFFSET:
 185        return state->broadcast;
 186
 187    default:
 188        break;
 189    }
 190
 191    /* mask registers */
 192    if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
 193        int cpu = (addr - MASK_OFFSET) / 4;
 194        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
 195
 196        return state->mask[cpu];
 197    }
 198
 199    /* force registers */
 200    if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
 201        int cpu = (addr - FORCE_OFFSET) / 4;
 202        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
 203
 204        return state->force[cpu];
 205    }
 206
 207    /* extended (not supported) */
 208    if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
 209        int cpu = (addr - EXTENDED_OFFSET) / 4;
 210        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
 211
 212        return state->extended[cpu];
 213    }
 214
 215    trace_grlib_irqmp_readl_unknown(addr);
 216    return 0;
 217}
 218
 219static void grlib_irqmp_write(void *opaque, hwaddr addr,
 220                              uint64_t value, unsigned size)
 221{
 222    IRQMP      *irqmp = opaque;
 223    IRQMPState *state;
 224
 225    assert(irqmp != NULL);
 226    state = irqmp->state;
 227    assert(state != NULL);
 228
 229    addr &= 0xff;
 230
 231    /* global registers */
 232    switch (addr) {
 233    case LEVEL_OFFSET:
 234        value &= 0xFFFF << 1; /* clean up the value */
 235        state->level = value;
 236        return;
 237
 238    case PENDING_OFFSET:
 239        /* Read Only */
 240        return;
 241
 242    case FORCE0_OFFSET:
 243        /* This register is an "alias" for the force register of CPU 0 */
 244
 245        value &= 0xFFFE; /* clean up the value */
 246        state->force[0] = value;
 247        grlib_irqmp_check_irqs(irqmp->state);
 248        return;
 249
 250    case CLEAR_OFFSET:
 251        value &= ~1; /* clean up the value */
 252        grlib_irqmp_ack_mask(state, value);
 253        return;
 254
 255    case MP_STATUS_OFFSET:
 256        /* Read Only (no SMP support) */
 257        return;
 258
 259    case BROADCAST_OFFSET:
 260        value &= 0xFFFE; /* clean up the value */
 261        state->broadcast = value;
 262        return;
 263
 264    default:
 265        break;
 266    }
 267
 268    /* mask registers */
 269    if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
 270        int cpu = (addr - MASK_OFFSET) / 4;
 271        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
 272
 273        value &= ~1; /* clean up the value */
 274        state->mask[cpu] = value;
 275        grlib_irqmp_check_irqs(irqmp->state);
 276        return;
 277    }
 278
 279    /* force registers */
 280    if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
 281        int cpu = (addr - FORCE_OFFSET) / 4;
 282        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
 283
 284        uint32_t force = value & 0xFFFE;
 285        uint32_t clear = (value >> 16) & 0xFFFE;
 286        uint32_t old   = state->force[cpu];
 287
 288        state->force[cpu] = (old | force) & ~clear;
 289        grlib_irqmp_check_irqs(irqmp->state);
 290        return;
 291    }
 292
 293    /* extended (not supported) */
 294    if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
 295        int cpu = (addr - EXTENDED_OFFSET) / 4;
 296        assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
 297
 298        value &= 0xF; /* clean up the value */
 299        state->extended[cpu] = value;
 300        return;
 301    }
 302
 303    trace_grlib_irqmp_writel_unknown(addr, value);
 304}
 305
 306static const MemoryRegionOps grlib_irqmp_ops = {
 307    .read = grlib_irqmp_read,
 308    .write = grlib_irqmp_write,
 309    .endianness = DEVICE_NATIVE_ENDIAN,
 310    .valid = {
 311        .min_access_size = 4,
 312        .max_access_size = 4,
 313    },
 314};
 315
 316static void grlib_irqmp_reset(DeviceState *d)
 317{
 318    IRQMP *irqmp = GRLIB_IRQMP(d);
 319    assert(irqmp->state != NULL);
 320
 321    memset(irqmp->state, 0, sizeof *irqmp->state);
 322    irqmp->state->parent = irqmp;
 323}
 324
 325static void grlib_irqmp_init(Object *obj)
 326{
 327    IRQMP *irqmp = GRLIB_IRQMP(obj);
 328    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 329
 330    qdev_init_gpio_out_named(DEVICE(obj), &irqmp->irq, "grlib-irq", 1);
 331    memory_region_init_io(&irqmp->iomem, obj, &grlib_irqmp_ops, irqmp,
 332                          "irqmp", IRQMP_REG_SIZE);
 333
 334    irqmp->state = g_malloc0(sizeof *irqmp->state);
 335
 336    sysbus_init_mmio(dev, &irqmp->iomem);
 337}
 338
 339static void grlib_irqmp_class_init(ObjectClass *klass, void *data)
 340{
 341    DeviceClass *dc = DEVICE_CLASS(klass);
 342
 343    dc->reset = grlib_irqmp_reset;
 344}
 345
 346static const TypeInfo grlib_irqmp_info = {
 347    .name          = TYPE_GRLIB_IRQMP,
 348    .parent        = TYPE_SYS_BUS_DEVICE,
 349    .instance_size = sizeof(IRQMP),
 350    .instance_init = grlib_irqmp_init,
 351    .class_init    = grlib_irqmp_class_init,
 352};
 353
 354static void grlib_irqmp_register_types(void)
 355{
 356    type_register_static(&grlib_irqmp_info);
 357}
 358
 359type_init(grlib_irqmp_register_types)
 360