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28#include "qemu/osdep.h"
29#include "hw/sysbus.h"
30#include "hw/register.h"
31#include "qemu/bitops.h"
32#include "migration/vmstate.h"
33#include "hw/irq.h"
34#include "qemu/log.h"
35
36
37
38#ifndef XILINX_FPD_SLCR_ERR_DEBUG
39#define XILINX_FPD_SLCR_ERR_DEBUG 0
40#endif
41
42#define TYPE_XILINX_FPD_SLCR "xlnx,versal-fpd-slcr"
43
44#define XILINX_FPD_SLCR(obj) \
45 OBJECT_CHECK(FPD_SLCR, (obj), TYPE_XILINX_FPD_SLCR)
46
47REG32(WPROT0, 0x0)
48 FIELD(WPROT0, ACTIVE, 0, 1)
49REG32(CTRL, 0x4)
50 FIELD(CTRL, SLVERR_ENABLE, 0, 1)
51REG32(ISR, 0x8)
52 FIELD(ISR, ADDR_DECODE_ERR, 0, 1)
53REG32(IMR, 0xc)
54 FIELD(IMR, ADDR_DECODE_ERR, 0, 1)
55REG32(IER, 0x10)
56 FIELD(IER, ADDR_DECODE_ERR, 0, 1)
57REG32(IDR, 0x14)
58 FIELD(IDR, ADDR_DECODE_ERR, 0, 1)
59REG32(ITR, 0x18)
60 FIELD(ITR, ADDR_DECODE_ERR, 0, 1)
61REG32(WDT_CLK_SEL, 0x100)
62 FIELD(WDT_CLK_SEL, SELECT, 0, 1)
63REG32(APUGIC_CTRL, 0x10c)
64 FIELD(APUGIC_CTRL, AWQOS, 16, 4)
65 FIELD(APUGIC_CTRL, ARQOS, 0, 4)
66REG32(BISR_CACHE_CTRL_0, 0x400)
67 FIELD(BISR_CACHE_CTRL_0, CLR, 4, 1)
68 FIELD(BISR_CACHE_CTRL_0, TRIGGER, 0, 1)
69REG32(BISR_CACHE_CTRL_1, 0x404)
70 FIELD(BISR_CACHE_CTRL_1, PGEN_3, 3, 1)
71 FIELD(BISR_CACHE_CTRL_1, PGEN_2, 2, 1)
72 FIELD(BISR_CACHE_CTRL_1, PGEN_1, 1, 1)
73 FIELD(BISR_CACHE_CTRL_1, PGEN_0, 0, 1)
74REG32(BISR_CACHE_STATUS, 0x408)
75 FIELD(BISR_CACHE_STATUS, PASS_3, 9, 1)
76 FIELD(BISR_CACHE_STATUS, DONE_3, 8, 1)
77 FIELD(BISR_CACHE_STATUS, PASS_2, 7, 1)
78 FIELD(BISR_CACHE_STATUS, DONE_2, 6, 1)
79 FIELD(BISR_CACHE_STATUS, PASS_1, 5, 1)
80 FIELD(BISR_CACHE_STATUS, DONE_1, 4, 1)
81 FIELD(BISR_CACHE_STATUS, PASS_0, 3, 1)
82 FIELD(BISR_CACHE_STATUS, DONE_0, 2, 1)
83 FIELD(BISR_CACHE_STATUS, PASS, 1, 1)
84 FIELD(BISR_CACHE_STATUS, DONE, 0, 1)
85REG32(BISR_CACHE_DATA_0, 0x40c)
86REG32(BISR_CACHE_DATA_1, 0x410)
87REG32(BISR_CACHE_DATA_2, 0x414)
88REG32(BISR_CACHE_DATA_3, 0x418)
89REG32(BISR_CACHE_DATA_4, 0x41c)
90REG32(BISR_CACHE_DATA_5, 0x420)
91REG32(BISR_CACHE_DATA_6, 0x424)
92REG32(BISR_CACHE_DATA_7, 0x428)
93REG32(BISR_CACHE_DATA_8, 0x42c)
94REG32(BISR_CACHE_DATA_9, 0x430)
95REG32(BISR_CACHE_DATA_10, 0x434)
96REG32(BISR_CACHE_DATA_11, 0x438)
97REG32(BISR_CACHE_DATA_12, 0x43c)
98REG32(BISR_CACHE_DATA_13, 0x440)
99REG32(BISR_CACHE_DATA_14, 0x444)
100REG32(BISR_CACHE_DATA_15, 0x448)
101REG32(BISR_CACHE_DATA_16, 0x44c)
102REG32(BISR_CACHE_DATA_17, 0x450)
103REG32(BISR_CACHE_DATA_18, 0x454)
104REG32(BISR_CACHE_DATA_19, 0x458)
105REG32(BISR_CACHE_DATA_20, 0x45c)
106REG32(BISR_CACHE_DATA_21, 0x460)
107REG32(BISR_CACHE_DATA_22, 0x464)
108REG32(BISR_CACHE_DATA_23, 0x468)
109REG32(BISR_CACHE_DATA_24, 0x46c)
110REG32(BISR_CACHE_DATA_25, 0x470)
111REG32(BISR_CACHE_DATA_26, 0x474)
112REG32(BISR_CACHE_DATA_27, 0x478)
113REG32(BISR_CACHE_DATA_28, 0x47c)
114REG32(BISR_CACHE_DATA_29, 0x480)
115REG32(BISR_CACHE_DATA_30, 0x484)
116REG32(BISR_CACHE_DATA_31, 0x488)
117REG32(BISR_TEST_DATA_0, 0x48c)
118REG32(BISR_TEST_DATA_1, 0x490)
119REG32(BISR_TEST_DATA_2, 0x494)
120REG32(BISR_TEST_DATA_3, 0x498)
121REG32(BISR_TEST_DATA_4, 0x49c)
122REG32(BISR_TEST_DATA_5, 0x4a0)
123REG32(BISR_TEST_DATA_6, 0x4a4)
124REG32(BISR_TEST_DATA_7, 0x4a8)
125REG32(BISR_TEST_DATA_8, 0x4ac)
126REG32(BISR_TEST_DATA_9, 0x4b0)
127REG32(BISR_TEST_DATA_10, 0x4b4)
128REG32(BISR_TEST_DATA_11, 0x4b8)
129REG32(BISR_TEST_DATA_12, 0x4bc)
130REG32(BISR_TEST_DATA_13, 0x4c0)
131REG32(BISR_TEST_DATA_14, 0x4c4)
132REG32(BISR_TEST_DATA_15, 0x4c8)
133REG32(BISR_TEST_DATA_16, 0x4cc)
134REG32(BISR_TEST_DATA_17, 0x4d0)
135REG32(BISR_TEST_DATA_18, 0x4d4)
136REG32(BISR_TEST_DATA_19, 0x4d8)
137REG32(BISR_TEST_DATA_20, 0x4dc)
138REG32(BISR_TEST_DATA_21, 0x4e0)
139REG32(BISR_TEST_DATA_22, 0x4e4)
140REG32(BISR_TEST_DATA_23, 0x4e8)
141REG32(BISR_TEST_DATA_24, 0x4ec)
142REG32(BISR_TEST_DATA_25, 0x4f0)
143REG32(BISR_TEST_DATA_26, 0x4f4)
144REG32(BISR_TEST_DATA_27, 0x4f8)
145REG32(BISR_TEST_DATA_28, 0x4fc)
146REG32(BISR_TEST_DATA_29, 0x500)
147REG32(BISR_TEST_DATA_30, 0x504)
148REG32(BISR_TEST_DATA_31, 0x508)
149REG32(ECO, 0xffc)
150REG32(AFI_FS, 0x5000)
151 FIELD(AFI_FS, DW_SS0_SEL, 8, 2)
152
153#define FPD_SLCR_R_MAX (R_AFI_FS + 1)
154
155typedef struct FPD_SLCR {
156 SysBusDevice parent_obj;
157 MemoryRegion iomem;
158 qemu_irq irq_imr;
159
160 uint32_t regs[FPD_SLCR_R_MAX];
161 RegisterInfo regs_info[FPD_SLCR_R_MAX];
162} FPD_SLCR;
163
164static void imr_update_irq(FPD_SLCR *s)
165{
166 bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];
167 qemu_set_irq(s->irq_imr, pending);
168}
169
170static void isr_postw(RegisterInfo *reg, uint64_t val64)
171{
172 FPD_SLCR *s = XILINX_FPD_SLCR(reg->opaque);
173 imr_update_irq(s);
174}
175
176static uint64_t ier_prew(RegisterInfo *reg, uint64_t val64)
177{
178 FPD_SLCR *s = XILINX_FPD_SLCR(reg->opaque);
179 uint32_t val = val64;
180
181 s->regs[R_IMR] &= ~val;
182 imr_update_irq(s);
183 return 0;
184}
185
186static uint64_t idr_prew(RegisterInfo *reg, uint64_t val64)
187{
188 FPD_SLCR *s = XILINX_FPD_SLCR(reg->opaque);
189 uint32_t val = val64;
190
191 s->regs[R_IMR] |= val;
192 imr_update_irq(s);
193 return 0;
194}
195
196static uint64_t itr_prew(RegisterInfo *reg, uint64_t val64)
197{
198 FPD_SLCR *s = XILINX_FPD_SLCR(reg->opaque);
199 uint32_t val = val64;
200
201 s->regs[R_ISR] |= val;
202 imr_update_irq(s);
203 return 0;
204}
205
206static const RegisterAccessInfo fpd_slcr_regs_info[] = {
207 { .name = "WPROT0", .addr = A_WPROT0,
208 .reset = 0x1,
209 },{ .name = "CTRL", .addr = A_CTRL,
210 .rsvd = 0xfffffffe,
211 },{ .name = "ISR", .addr = A_ISR,
212 .rsvd = 0xfffffffe,
213 .w1c = 0x1,
214 .post_write = isr_postw,
215 },{ .name = "IMR", .addr = A_IMR,
216 .reset = 0x1,
217 .rsvd = 0xfffffffe,
218 .ro = 0x1,
219 },{ .name = "IER", .addr = A_IER,
220 .rsvd = 0xfffffffe,
221 .pre_write = ier_prew,
222 },{ .name = "IDR", .addr = A_IDR,
223 .rsvd = 0xfffffffe,
224 .pre_write = idr_prew,
225 },{ .name = "ITR", .addr = A_ITR,
226 .rsvd = 0xfffffffe,
227 .pre_write = itr_prew,
228 },{ .name = "WDT_CLK_SEL", .addr = A_WDT_CLK_SEL,
229 .rsvd = 0xfffffffe,
230 },{ .name = "APUGIC_CTRL", .addr = A_APUGIC_CTRL,
231 .reset = 0x40004,
232 .rsvd = 0xfff0fff0,
233 },{ .name = "BISR_CACHE_CTRL_0", .addr = A_BISR_CACHE_CTRL_0,
234 .rsvd = 0xffffffee,
235 },{ .name = "BISR_CACHE_CTRL_1", .addr = A_BISR_CACHE_CTRL_1,
236 .rsvd = 0xfffffff0,
237 },{ .name = "BISR_CACHE_STATUS", .addr = A_BISR_CACHE_STATUS,
238 .rsvd = 0xfffffc00,
239 .ro = 0x3ff,
240 },{ .name = "BISR_CACHE_DATA_0", .addr = A_BISR_CACHE_DATA_0,
241 },{ .name = "BISR_CACHE_DATA_1", .addr = A_BISR_CACHE_DATA_1,
242 },{ .name = "BISR_CACHE_DATA_2", .addr = A_BISR_CACHE_DATA_2,
243 },{ .name = "BISR_CACHE_DATA_3", .addr = A_BISR_CACHE_DATA_3,
244 },{ .name = "BISR_CACHE_DATA_4", .addr = A_BISR_CACHE_DATA_4,
245 },{ .name = "BISR_CACHE_DATA_5", .addr = A_BISR_CACHE_DATA_5,
246 },{ .name = "BISR_CACHE_DATA_6", .addr = A_BISR_CACHE_DATA_6,
247 },{ .name = "BISR_CACHE_DATA_7", .addr = A_BISR_CACHE_DATA_7,
248 },{ .name = "BISR_CACHE_DATA_8", .addr = A_BISR_CACHE_DATA_8,
249 },{ .name = "BISR_CACHE_DATA_9", .addr = A_BISR_CACHE_DATA_9,
250 },{ .name = "BISR_CACHE_DATA_10", .addr = A_BISR_CACHE_DATA_10,
251 },{ .name = "BISR_CACHE_DATA_11", .addr = A_BISR_CACHE_DATA_11,
252 },{ .name = "BISR_CACHE_DATA_12", .addr = A_BISR_CACHE_DATA_12,
253 },{ .name = "BISR_CACHE_DATA_13", .addr = A_BISR_CACHE_DATA_13,
254 },{ .name = "BISR_CACHE_DATA_14", .addr = A_BISR_CACHE_DATA_14,
255 },{ .name = "BISR_CACHE_DATA_15", .addr = A_BISR_CACHE_DATA_15,
256 },{ .name = "BISR_CACHE_DATA_16", .addr = A_BISR_CACHE_DATA_16,
257 },{ .name = "BISR_CACHE_DATA_17", .addr = A_BISR_CACHE_DATA_17,
258 },{ .name = "BISR_CACHE_DATA_18", .addr = A_BISR_CACHE_DATA_18,
259 },{ .name = "BISR_CACHE_DATA_19", .addr = A_BISR_CACHE_DATA_19,
260 },{ .name = "BISR_CACHE_DATA_20", .addr = A_BISR_CACHE_DATA_20,
261 },{ .name = "BISR_CACHE_DATA_21", .addr = A_BISR_CACHE_DATA_21,
262 },{ .name = "BISR_CACHE_DATA_22", .addr = A_BISR_CACHE_DATA_22,
263 },{ .name = "BISR_CACHE_DATA_23", .addr = A_BISR_CACHE_DATA_23,
264 },{ .name = "BISR_CACHE_DATA_24", .addr = A_BISR_CACHE_DATA_24,
265 },{ .name = "BISR_CACHE_DATA_25", .addr = A_BISR_CACHE_DATA_25,
266 },{ .name = "BISR_CACHE_DATA_26", .addr = A_BISR_CACHE_DATA_26,
267 },{ .name = "BISR_CACHE_DATA_27", .addr = A_BISR_CACHE_DATA_27,
268 },{ .name = "BISR_CACHE_DATA_28", .addr = A_BISR_CACHE_DATA_28,
269 },{ .name = "BISR_CACHE_DATA_29", .addr = A_BISR_CACHE_DATA_29,
270 },{ .name = "BISR_CACHE_DATA_30", .addr = A_BISR_CACHE_DATA_30,
271 },{ .name = "BISR_CACHE_DATA_31", .addr = A_BISR_CACHE_DATA_31,
272 },{ .name = "BISR_TEST_DATA_0", .addr = A_BISR_TEST_DATA_0,
273 .ro = 0xffffffff,
274 },{ .name = "BISR_TEST_DATA_1", .addr = A_BISR_TEST_DATA_1,
275 .ro = 0xffffffff,
276 },{ .name = "BISR_TEST_DATA_2", .addr = A_BISR_TEST_DATA_2,
277 .ro = 0xffffffff,
278 },{ .name = "BISR_TEST_DATA_3", .addr = A_BISR_TEST_DATA_3,
279 .ro = 0xffffffff,
280 },{ .name = "BISR_TEST_DATA_4", .addr = A_BISR_TEST_DATA_4,
281 .ro = 0xffffffff,
282 },{ .name = "BISR_TEST_DATA_5", .addr = A_BISR_TEST_DATA_5,
283 .ro = 0xffffffff,
284 },{ .name = "BISR_TEST_DATA_6", .addr = A_BISR_TEST_DATA_6,
285 .ro = 0xffffffff,
286 },{ .name = "BISR_TEST_DATA_7", .addr = A_BISR_TEST_DATA_7,
287 .ro = 0xffffffff,
288 },{ .name = "BISR_TEST_DATA_8", .addr = A_BISR_TEST_DATA_8,
289 .ro = 0xffffffff,
290 },{ .name = "BISR_TEST_DATA_9", .addr = A_BISR_TEST_DATA_9,
291 .ro = 0xffffffff,
292 },{ .name = "BISR_TEST_DATA_10", .addr = A_BISR_TEST_DATA_10,
293 .ro = 0xffffffff,
294 },{ .name = "BISR_TEST_DATA_11", .addr = A_BISR_TEST_DATA_11,
295 .ro = 0xffffffff,
296 },{ .name = "BISR_TEST_DATA_12", .addr = A_BISR_TEST_DATA_12,
297 .ro = 0xffffffff,
298 },{ .name = "BISR_TEST_DATA_13", .addr = A_BISR_TEST_DATA_13,
299 .ro = 0xffffffff,
300 },{ .name = "BISR_TEST_DATA_14", .addr = A_BISR_TEST_DATA_14,
301 .ro = 0xffffffff,
302 },{ .name = "BISR_TEST_DATA_15", .addr = A_BISR_TEST_DATA_15,
303 .ro = 0xffffffff,
304 },{ .name = "BISR_TEST_DATA_16", .addr = A_BISR_TEST_DATA_16,
305 .ro = 0xffffffff,
306 },{ .name = "BISR_TEST_DATA_17", .addr = A_BISR_TEST_DATA_17,
307 .ro = 0xffffffff,
308 },{ .name = "BISR_TEST_DATA_18", .addr = A_BISR_TEST_DATA_18,
309 .ro = 0xffffffff,
310 },{ .name = "BISR_TEST_DATA_19", .addr = A_BISR_TEST_DATA_19,
311 .ro = 0xffffffff,
312 },{ .name = "BISR_TEST_DATA_20", .addr = A_BISR_TEST_DATA_20,
313 .ro = 0xffffffff,
314 },{ .name = "BISR_TEST_DATA_21", .addr = A_BISR_TEST_DATA_21,
315 .ro = 0xffffffff,
316 },{ .name = "BISR_TEST_DATA_22", .addr = A_BISR_TEST_DATA_22,
317 .ro = 0xffffffff,
318 },{ .name = "BISR_TEST_DATA_23", .addr = A_BISR_TEST_DATA_23,
319 .ro = 0xffffffff,
320 },{ .name = "BISR_TEST_DATA_24", .addr = A_BISR_TEST_DATA_24,
321 .ro = 0xffffffff,
322 },{ .name = "BISR_TEST_DATA_25", .addr = A_BISR_TEST_DATA_25,
323 .ro = 0xffffffff,
324 },{ .name = "BISR_TEST_DATA_26", .addr = A_BISR_TEST_DATA_26,
325 .ro = 0xffffffff,
326 },{ .name = "BISR_TEST_DATA_27", .addr = A_BISR_TEST_DATA_27,
327 .ro = 0xffffffff,
328 },{ .name = "BISR_TEST_DATA_28", .addr = A_BISR_TEST_DATA_28,
329 .ro = 0xffffffff,
330 },{ .name = "BISR_TEST_DATA_29", .addr = A_BISR_TEST_DATA_29,
331 .ro = 0xffffffff,
332 },{ .name = "BISR_TEST_DATA_30", .addr = A_BISR_TEST_DATA_30,
333 .ro = 0xffffffff,
334 },{ .name = "BISR_TEST_DATA_31", .addr = A_BISR_TEST_DATA_31,
335 .ro = 0xffffffff,
336 },{ .name = "ECO", .addr = A_ECO,
337 },{ .name = "AFI_FS", .addr = A_AFI_FS,
338 .reset = 0x200,
339 .rsvd = 0xfffff0ff,
340 }
341};
342
343static void fpd_slcr_reset(DeviceState *dev)
344{
345 FPD_SLCR *s = XILINX_FPD_SLCR(dev);
346 unsigned int i;
347
348 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
349 register_reset(&s->regs_info[i]);
350 }
351
352 imr_update_irq(s);
353}
354
355static const MemoryRegionOps fpd_slcr_ops = {
356 .read = register_read_memory,
357 .write = register_write_memory,
358 .endianness = DEVICE_LITTLE_ENDIAN,
359 .valid = {
360 .min_access_size = 4,
361 .max_access_size = 4,
362 },
363};
364
365static void fpd_slcr_init(Object *obj)
366{
367 FPD_SLCR *s = XILINX_FPD_SLCR(obj);
368 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
369 RegisterInfoArray *reg_array;
370
371 memory_region_init(&s->iomem, obj, TYPE_XILINX_FPD_SLCR,
372 FPD_SLCR_R_MAX * 4);
373 reg_array =
374 register_init_block32(DEVICE(obj), fpd_slcr_regs_info,
375 ARRAY_SIZE(fpd_slcr_regs_info),
376 s->regs_info, s->regs,
377 &fpd_slcr_ops,
378 XILINX_FPD_SLCR_ERR_DEBUG,
379 FPD_SLCR_R_MAX * 4);
380 memory_region_add_subregion(&s->iomem,
381 0x0,
382 ®_array->mem);
383 sysbus_init_mmio(sbd, &s->iomem);
384 sysbus_init_irq(sbd, &s->irq_imr);
385}
386
387static const VMStateDescription vmstate_fpd_slcr = {
388 .name = TYPE_XILINX_FPD_SLCR,
389 .version_id = 1,
390 .minimum_version_id = 1,
391 .fields = (VMStateField[]) {
392 VMSTATE_UINT32_ARRAY(regs, FPD_SLCR, FPD_SLCR_R_MAX),
393 VMSTATE_END_OF_LIST(),
394 }
395};
396
397static void fpd_slcr_class_init(ObjectClass *klass, void *data)
398{
399 DeviceClass *dc = DEVICE_CLASS(klass);
400
401 dc->reset = fpd_slcr_reset;
402 dc->vmsd = &vmstate_fpd_slcr;
403}
404
405static const TypeInfo fpd_slcr_info = {
406 .name = TYPE_XILINX_FPD_SLCR,
407 .parent = TYPE_SYS_BUS_DEVICE,
408 .instance_size = sizeof(FPD_SLCR),
409 .class_init = fpd_slcr_class_init,
410 .instance_init = fpd_slcr_init,
411};
412
413static void fpd_slcr_register_types(void)
414{
415 type_register_static(&fpd_slcr_info);
416}
417
418type_init(fpd_slcr_register_types)
419
