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27#include "qemu/osdep.h"
28#include "hw/sysbus.h"
29#include "hw/register.h"
30#include "qemu/bitops.h"
31#include "qemu/log.h"
32#include "migration/vmstate.h"
33#include "hw/qdev-properties.h"
34
35#ifndef XILINX_NOC_NPI_DEV_ERR_DEBUG
36#define XILINX_NOC_NPI_DEV_ERR_DEBUG 0
37#endif
38
39#define TYPE_XILINX_NOC_NPI_DEV "xlnx.noc-npi-dev"
40
41#define XILINX_NOC_NPI_DEV(obj) \
42 OBJECT_CHECK(NOC_NPI_DEV, (obj), TYPE_XILINX_NOC_NPI_DEV)
43
44REG32(REG_PCSR_MASK, 0x0)
45 FIELD(REG_PCSR_MASK, NIDB_DCC_EN, 25, 1)
46 FIELD(REG_PCSR_MASK, NOC_RST_MASK, 24, 1)
47 FIELD(REG_PCSR_MASK, TEST_SAFE, 20, 1)
48 FIELD(REG_PCSR_MASK, SLVERREN, 19, 1)
49 FIELD(REG_PCSR_MASK, SYS_RST_MASK, 15, 3)
50 FIELD(REG_PCSR_MASK, HOLDSTATE, 7, 1)
51 FIELD(REG_PCSR_MASK, INITSTATE, 6, 1)
52 FIELD(REG_PCSR_MASK, ODISABLE, 2, 4)
53 FIELD(REG_PCSR_MASK, GATEREG, 1, 1)
54 FIELD(REG_PCSR_MASK, PCOMPLETE, 0, 1)
55REG32(REG_PCSR_CONTROL, 0x4)
56 FIELD(REG_PCSR_CONTROL, NIDB_DCC_EN, 25, 1)
57 FIELD(REG_PCSR_CONTROL, NOC_RST_MASK, 24, 1)
58 FIELD(REG_PCSR_CONTROL, TEST_SAFE, 20, 1)
59 FIELD(REG_PCSR_CONTROL, SLVERREN, 19, 1)
60 FIELD(REG_PCSR_CONTROL, SYS_RST_MASK, 15, 3)
61 FIELD(REG_PCSR_CONTROL, HOLDSTATE, 7, 1)
62 FIELD(REG_PCSR_CONTROL, INITSTATE, 6, 1)
63 FIELD(REG_PCSR_CONTROL, ODISABLE, 2, 4)
64 FIELD(REG_PCSR_CONTROL, GATEREG, 1, 1)
65 FIELD(REG_PCSR_CONTROL, PCOMPLETE, 0, 1)
66REG32(REG_PCSR_STATUS, 0x8)
67 FIELD(REG_PCSR_STATUS, REMOTE_LINK_READY, 18, 1)
68 FIELD(REG_PCSR_STATUS, LOCAL_LINK_READY, 17, 1)
69 FIELD(REG_PCSR_STATUS, DCC_READY, 16, 1)
70 FIELD(REG_PCSR_STATUS, HARD_FAIL_OR, 11, 3)
71 FIELD(REG_PCSR_STATUS, HARD_FAIL_AND, 8, 3)
72 FIELD(REG_PCSR_STATUS, MEM_CLEAR_PASS, 7, 1)
73 FIELD(REG_PCSR_STATUS, MEM_CLEAR_DONE, 6, 1)
74 FIELD(REG_PCSR_STATUS, CALERROR, 5, 1)
75 FIELD(REG_PCSR_STATUS, CALDONE, 4, 1)
76 FIELD(REG_PCSR_STATUS, INCAL, 3, 1)
77 FIELD(REG_PCSR_STATUS, SCAN_CLEAR_PASS, 2, 1)
78 FIELD(REG_PCSR_STATUS, SCAN_CLEAR_DONE, 1, 1)
79 FIELD(REG_PCSR_STATUS, PCSRLOCK, 0, 1)
80REG32(REG_PCSR_LOCK, 0xc)
81 FIELD(REG_PCSR_LOCK, STATE, 0, 1)
82REG32(REG_CLOCK_MUX, 0x10)
83
84#define NOC_NPI_DEV_R_MAX (8)
85#define NOC_BLOCK_MASK (0x200 - 1)
86#define LOCK_VAL 0xF9E8D7C6
87
88typedef struct NOC_NPI_DEV {
89 SysBusDevice parent_obj;
90 RegisterInfoArray *reg_array;
91 uint64_t map_size;
92
93 uint32_t regs[NOC_NPI_DEV_R_MAX];
94 RegisterInfo regs_info[NOC_NPI_DEV_R_MAX];
95} NOC_NPI_DEV;
96
97static void noc_npi_dev_lock_postw(RegisterInfo *reg, uint64_t val64)
98{
99 NOC_NPI_DEV *s = XILINX_NOC_NPI_DEV(reg->opaque);
100 bool locked = val64 != LOCK_VAL;
101
102 ARRAY_FIELD_DP32(s->regs, REG_PCSR_STATUS, PCSRLOCK, locked);
103}
104
105static const RegisterAccessInfo noc_npi_dev_regs_info[] = {
106 { .name = "REG_PCSR_MASK", .addr = A_REG_PCSR_MASK,
107 .rsvd = 0xfee47f00,
108 .ro = 0xe47f00,
109 },{ .name = "REG_PCSR_CONTROL", .addr = A_REG_PCSR_CONTROL,
110 .reset = 0x1000000,
111 .rsvd = 0xfee47f00,
112 .ro = 0xe47f00,
113 },{ .name = "REG_PCSR_STATUS", .addr = A_REG_PCSR_STATUS,
114 .reset = R_REG_PCSR_STATUS_PCSRLOCK_MASK \
115 | R_REG_PCSR_STATUS_MEM_CLEAR_PASS_MASK \
116 | R_REG_PCSR_STATUS_MEM_CLEAR_DONE_MASK \
117 | R_REG_PCSR_STATUS_CALDONE_MASK \
118 | R_REG_PCSR_STATUS_SCAN_CLEAR_PASS_MASK \
119 | R_REG_PCSR_STATUS_SCAN_CLEAR_DONE_MASK \
120 | R_REG_PCSR_STATUS_DCC_READY_MASK \
121 | R_REG_PCSR_STATUS_LOCAL_LINK_READY_MASK \
122 | R_REG_PCSR_STATUS_REMOTE_LINK_READY_MASK,
123 .rsvd = 0xffffc000,
124 .ro = 0x3fff,
125 },{ .name = "REG_PCSR_LOCK", .addr = A_REG_PCSR_LOCK,
126 .reset = 0x1,
127 .post_write = noc_npi_dev_lock_postw
128 }
129};
130
131static void noc_npi_dev_reset(DeviceState *dev)
132{
133 NOC_NPI_DEV *s = XILINX_NOC_NPI_DEV(dev);
134 unsigned int i;
135
136 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
137 register_reset(&s->regs_info[i]);
138 }
139}
140
141static uint64_t noc_npi_dev_read(void *opaque, hwaddr addr,
142 unsigned size)
143{
144 uint32_t offset;
145
146 offset = addr & NOC_BLOCK_MASK;
147 return register_read_memory(opaque, offset, size);
148}
149
150static void noc_npi_dev_write(void *opaque, hwaddr addr,
151 uint64_t value, unsigned size)
152{
153 uint32_t offset;
154
155 offset = addr & NOC_BLOCK_MASK;
156 register_write_memory(opaque, offset, value, size);
157}
158
159static const MemoryRegionOps noc_npi_dev_ops = {
160 .read = noc_npi_dev_read,
161 .write = noc_npi_dev_write,
162 .endianness = DEVICE_LITTLE_ENDIAN,
163 .valid = {
164 .min_access_size = 1,
165 .max_access_size = 4,
166 },
167};
168
169static void noc_npi_dev_realize(DeviceState *dev, Error **errp)
170{
171 NOC_NPI_DEV *s = XILINX_NOC_NPI_DEV(dev);
172 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
173
174 s->reg_array =
175 register_init_block32(dev, noc_npi_dev_regs_info,
176 ARRAY_SIZE(noc_npi_dev_regs_info),
177 s->regs_info, s->regs,
178 &noc_npi_dev_ops,
179 XILINX_NOC_NPI_DEV_ERR_DEBUG,
180 s->map_size);
181 sysbus_init_mmio(sbd, &s->reg_array->mem);
182}
183
184static const VMStateDescription vmstate_noc_npi_dev = {
185 .name = TYPE_XILINX_NOC_NPI_DEV,
186 .version_id = 1,
187 .minimum_version_id = 1,
188 .fields = (VMStateField[]) {
189 VMSTATE_UINT32_ARRAY(regs, NOC_NPI_DEV, NOC_NPI_DEV_R_MAX),
190 VMSTATE_END_OF_LIST(),
191 }
192};
193
194static Property noc_npi_dev_prop[] = {
195 DEFINE_PROP_UINT64("map-size", NOC_NPI_DEV, map_size, 0x2000000),
196 DEFINE_PROP_END_OF_LIST(),
197};
198
199static void noc_npi_dev_class_init(ObjectClass *klass, void *data)
200{
201 DeviceClass *dc = DEVICE_CLASS(klass);
202
203 dc->reset = noc_npi_dev_reset;
204 dc->vmsd = &vmstate_noc_npi_dev;
205 dc->realize = noc_npi_dev_realize;
206 device_class_set_props(dc, noc_npi_dev_prop);
207}
208
209static const TypeInfo noc_npi_dev_info = {
210 .name = TYPE_XILINX_NOC_NPI_DEV,
211 .parent = TYPE_SYS_BUS_DEVICE,
212 .instance_size = sizeof(NOC_NPI_DEV),
213 .class_init = noc_npi_dev_class_init,
214};
215
216static void noc_npi_dev_register_types(void)
217{
218 type_register_static(&noc_npi_dev_info);
219}
220
221type_init(noc_npi_dev_register_types)
222
