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28#include "qemu/osdep.h"
29#include "hw/sysbus.h"
30#include "hw/register.h"
31#include "qemu/bitops.h"
32#include "qemu/log.h"
33#include "migration/vmstate.h"
34#include "hw/irq.h"
35
36#ifndef XILINX_PCIE_ATTRIB_ERR_DEBUG
37#define XILINX_PCIE_ATTRIB_ERR_DEBUG 0
38#endif
39
40#define TYPE_XILINX_PCIE_ATTRIB "xlnx.nwl-pcie-attrib"
41
42#define XILINX_PCIE_ATTRIB(obj) \
43 OBJECT_CHECK(PCIE_ATTRIB, (obj), TYPE_XILINX_PCIE_ATTRIB)
44
45REG32(ATTR_0, 0x0)
46 FIELD(ATTR_0, ATTR_AER_CAP_ECRC_GEN_CAPABLE, 1, 1)
47 FIELD(ATTR_0, ATTR_AER_CAP_ECRC_CHECK_CAPABLE, 0, 1)
48REG32(ATTR_1, 0x4)
49 FIELD(ATTR_1, ATTR_AER_CAP_ID, 0, 16)
50REG32(ATTR_2, 0x8)
51 FIELD(ATTR_2, ATTR_AER_CAP_VERSION, 1, 4)
52 FIELD(ATTR_2, ATTR_AER_CAP_PERMIT_ROOTERR_UPDATE, 0, 1)
53REG32(ATTR_3, 0xc)
54 FIELD(ATTR_3, ATTR_AER_BASE_PTR, 0, 12)
55REG32(ATTR_4, 0x10)
56 FIELD(ATTR_4, ATTR_AER_CAP_ON, 12, 1)
57 FIELD(ATTR_4, ATTR_AER_CAP_NEXTPTR, 0, 12)
58REG32(ATTR_5, 0x14)
59 FIELD(ATTR_5, ATTR_AER_CAP_OPTIONAL_ERR_SUPPORT, 0, 16)
60REG32(ATTR_6, 0x18)
61 FIELD(ATTR_6, ATTR_AER_CAP_MULTIHEADER, 8, 1)
62 FIELD(ATTR_6, ATTR_AER_CAP_OPTIONAL_ERR_SUPPORT, 0, 8)
63REG32(ATTR_7, 0x1c)
64 FIELD(ATTR_7, ATTR_BAR0, 0, 16)
65REG32(ATTR_8, 0x20)
66 FIELD(ATTR_8, ATTR_BAR0, 0, 16)
67REG32(ATTR_9, 0x24)
68 FIELD(ATTR_9, ATTR_BAR1, 0, 16)
69REG32(ATTR_10, 0x28)
70 FIELD(ATTR_10, ATTR_BAR1, 0, 16)
71REG32(ATTR_11, 0x2c)
72 FIELD(ATTR_11, ATTR_BAR2, 0, 16)
73REG32(ATTR_12, 0x30)
74 FIELD(ATTR_12, ATTR_BAR2, 0, 16)
75REG32(ATTR_13, 0x34)
76 FIELD(ATTR_13, ATTR_BAR3, 0, 16)
77REG32(ATTR_14, 0x38)
78 FIELD(ATTR_14, ATTR_BAR3, 0, 16)
79REG32(ATTR_15, 0x3c)
80 FIELD(ATTR_15, ATTR_BAR4, 0, 16)
81REG32(ATTR_16, 0x40)
82 FIELD(ATTR_16, ATTR_BAR4, 0, 16)
83REG32(ATTR_17, 0x44)
84 FIELD(ATTR_17, ATTR_BAR5, 0, 16)
85REG32(ATTR_18, 0x48)
86 FIELD(ATTR_18, ATTR_BAR5, 0, 16)
87REG32(ATTR_19, 0x4c)
88 FIELD(ATTR_19, ATTR_EXPANSION_ROM, 0, 16)
89REG32(ATTR_20, 0x50)
90 FIELD(ATTR_20, ATTR_EXPANSION_ROM, 0, 16)
91REG32(ATTR_21, 0x54)
92 FIELD(ATTR_21, ATTR_CAPABILITIES_PTR, 0, 8)
93REG32(ATTR_22, 0x58)
94 FIELD(ATTR_22, ATTR_CARDBUS_CIS_POINTER, 0, 16)
95REG32(ATTR_23, 0x5c)
96 FIELD(ATTR_23, ATTR_CARDBUS_CIS_POINTER, 0, 16)
97REG32(ATTR_24, 0x60)
98 FIELD(ATTR_24, ATTR_CLASS_CODE, 0, 16)
99REG32(ATTR_25, 0x64)
100 FIELD(ATTR_25, ATTR_DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED, 15, 1)
101 FIELD(ATTR_25, ATTR_DEV_CAP2_ARI_FORWARDING_SUPPORTED, 14, 1)
102 FIELD(ATTR_25, ATTR_CPL_TIMEOUT_RANGES_SUPPORTED, 10, 4)
103 FIELD(ATTR_25, ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED, 9, 1)
104 FIELD(ATTR_25, ATTR_CMD_INTX_IMPLEMENTED, 8, 1)
105 FIELD(ATTR_25, ATTR_CLASS_CODE, 0, 8)
106REG32(ATTR_26, 0x68)
107 FIELD(ATTR_26, ATTR_DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE, 13, 1)
108 FIELD(ATTR_26, ATTR_DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE, 12, 1)
109 FIELD(ATTR_26, ATTR_ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED, 11, 1)
110 FIELD(ATTR_26, ATTR_DEV_CAP2_MAX_ENDEND_TLP_PREFIXES, 9, 2)
111 FIELD(ATTR_26, ATTR_DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED, 8, 1)
112 FIELD(ATTR_26, ATTR_DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED, 7, 1)
113 FIELD(ATTR_26, ATTR_DEV_CAP2_TPH_COMPLETER_SUPPORTED, 5, 2)
114 FIELD(ATTR_26, ATTR_DEV_CAP2_LTR_MECHANISM_SUPPORTED, 4, 1)
115 FIELD(ATTR_26, ATTR_DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING, 3, 1)
116 FIELD(ATTR_26, ATTR_DEV_CAP2_CAS128_COMPLETER_SUPPORTED, 2, 1)
117 FIELD(ATTR_26, ATTR_DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED, 1, 1)
118 FIELD(ATTR_26, ATTR_DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED, 0, 1)
119REG32(ATTR_27, 0x6c)
120 FIELD(ATTR_27, ATTR_DEV_CAP_ROLE_BASED_ERROR, 13, 1)
121 FIELD(ATTR_27, ATTR_DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT, 11, 2)
122 FIELD(ATTR_27, ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED, 8, 3)
123 FIELD(ATTR_27, ATTR_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE, 7, 1)
124 FIELD(ATTR_27, ATTR_DEV_CAP_EXT_TAG_SUPPORTED, 6, 1)
125 FIELD(ATTR_27, ATTR_DEV_CAP_ENDPOINT_L1_LATENCY, 3, 3)
126 FIELD(ATTR_27, ATTR_DEV_CAP_ENDPOINT_L0S_LATENCY, 0, 3)
127REG32(ATTR_28, 0x70)
128 FIELD(ATTR_28, ATTR_DEV_CONTROL_EXT_TAG_DEFAULT, 9, 1)
129 FIELD(ATTR_28, ATTR_DEV_CONTROL_AUX_POWER_SUPPORTED, 8, 1)
130 FIELD(ATTR_28, ATTR_DEV_CAP_RSVD_31_29, 5, 3)
131 FIELD(ATTR_28, ATTR_DEV_CAP_RSVD_17_16, 3, 2)
132 FIELD(ATTR_28, ATTR_DEV_CAP_RSVD_14_12, 0, 3)
133REG32(ATTR_29, 0x74)
134 FIELD(ATTR_29, ATTR_DSN_BASE_PTR, 0, 12)
135REG32(ATTR_30, 0x78)
136 FIELD(ATTR_30, ATTR_DSN_CAP_ID, 0, 16)
137REG32(ATTR_31, 0x7c)
138 FIELD(ATTR_31, ATTR_DSN_CAP_ON, 12, 1)
139 FIELD(ATTR_31, ATTR_DSN_CAP_NEXTPTR, 0, 12)
140REG32(ATTR_32, 0x80)
141 FIELD(ATTR_32, ATTR_EXT_CFG_CAP_PTR, 4, 6)
142 FIELD(ATTR_32, ATTR_DSN_CAP_VERSION, 0, 4)
143REG32(ATTR_33, 0x84)
144 FIELD(ATTR_33, ATTR_EXT_CFG_XP_CAP_PTR, 0, 10)
145REG32(ATTR_34, 0x88)
146 FIELD(ATTR_34, ATTR_INTERRUPT_PIN, 8, 8)
147 FIELD(ATTR_34, ATTR_HEADER_TYPE, 0, 8)
148REG32(ATTR_35, 0x8c)
149 FIELD(ATTR_35, ATTR_LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP, 15, 1)
150 FIELD(ATTR_35, ATTR_LINK_CAP_CLOCK_POWER_MANAGEMENT, 14, 1)
151 FIELD(ATTR_35, ATTR_LINK_CAP_ASPM_SUPPORT, 12, 2)
152 FIELD(ATTR_35, ATTR_LAST_CONFIG_DWORD, 2, 10)
153 FIELD(ATTR_35, ATTR_IS_SWITCH, 1, 1)
154 FIELD(ATTR_35, ATTR_INTERRUPT_STAT_AUTO, 0, 1)
155REG32(ATTR_36, 0x90)
156 FIELD(ATTR_36, ATTR_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1, 12, 3)
157 FIELD(ATTR_36, ATTR_LINK_CAP_L0S_EXIT_LATENCY_GEN2, 9, 3)
158 FIELD(ATTR_36, ATTR_LINK_CAP_L0S_EXIT_LATENCY_GEN1, 6, 3)
159 FIELD(ATTR_36, ATTR_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2, 3, 3)
160 FIELD(ATTR_36, ATTR_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1, 0, 3)
161REG32(ATTR_37, 0x94)
162 FIELD(ATTR_37, ATTR_LINK_CAP_RSVD_23, 15, 1)
163 FIELD(ATTR_37, ATTR_LINK_CAP_ASPM_OPTIONALITY, 14, 1)
164 FIELD(ATTR_37, ATTR_LINK_CAP_MAX_LINK_SPEED, 10, 4)
165 FIELD(ATTR_37, ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP, 9, 1)
166 FIELD(ATTR_37, ATTR_LINK_CAP_L1_EXIT_LATENCY_GEN2, 6, 3)
167 FIELD(ATTR_37, ATTR_LINK_CAP_L1_EXIT_LATENCY_GEN1, 3, 3)
168 FIELD(ATTR_37, ATTR_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2, 0, 3)
169REG32(ATTR_38, 0x98)
170 FIELD(ATTR_38, ATTR_MPS_FORCE, 9, 1)
171 FIELD(ATTR_38, ATTR_LINK_STATUS_SLOT_CLOCK_CONFIG, 8, 1)
172 FIELD(ATTR_38, ATTR_LINK_CTRL2_TARGET_LINK_SPEED, 4, 4)
173 FIELD(ATTR_38, ATTR_LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE, 3, 1)
174 FIELD(ATTR_38, ATTR_LINK_CTRL2_DEEMPHASIS, 2, 1)
175 FIELD(ATTR_38, ATTR_LINK_CONTROL_RCB, 1, 1)
176 FIELD(ATTR_38, ATTR_LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE, 0, 1)
177REG32(ATTR_39, 0x9c)
178 FIELD(ATTR_39, ATTR_MSI_CAP_64_BIT_ADDR_CAPABLE, 8, 1)
179 FIELD(ATTR_39, ATTR_MSI_BASE_PTR, 0, 8)
180REG32(ATTR_40, 0xa0)
181 FIELD(ATTR_40, ATTR_MSI_CAP_MULTIMSGCAP, 9, 3)
182 FIELD(ATTR_40, ATTR_MSI_CAP_MULTIMSG_EXTENSION, 8, 1)
183 FIELD(ATTR_40, ATTR_MSI_CAP_ID, 0, 8)
184REG32(ATTR_41, 0xa4)
185 FIELD(ATTR_41, ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE, 9, 1)
186 FIELD(ATTR_41, ATTR_MSI_CAP_ON, 8, 1)
187 FIELD(ATTR_41, ATTR_MSI_CAP_NEXTPTR, 0, 8)
188REG32(ATTR_42, 0xa8)
189 FIELD(ATTR_42, ATTR_MSIX_CAP_ID, 8, 8)
190 FIELD(ATTR_42, ATTR_MSIX_BASE_PTR, 0, 8)
191REG32(ATTR_43, 0xac)
192 FIELD(ATTR_43, ATTR_MSIX_CAP_PBA_BIR, 9, 3)
193 FIELD(ATTR_43, ATTR_MSIX_CAP_ON, 8, 1)
194 FIELD(ATTR_43, ATTR_MSIX_CAP_NEXTPTR, 0, 8)
195REG32(ATTR_44, 0xb0)
196 FIELD(ATTR_44, ATTR_MSIX_CAP_PBA_OFFSET, 0, 16)
197REG32(ATTR_45, 0xb4)
198 FIELD(ATTR_45, ATTR_MSIX_CAP_PBA_OFFSET, 3, 13)
199 FIELD(ATTR_45, ATTR_MSIX_CAP_TABLE_BIR, 0, 3)
200REG32(ATTR_46, 0xb8)
201 FIELD(ATTR_46, ATTR_MSIX_CAP_TABLE_OFFSET, 0, 16)
202REG32(ATTR_47, 0xbc)
203 FIELD(ATTR_47, ATTR_MSIX_CAP_TABLE_OFFSET, 0, 13)
204REG32(ATTR_48, 0xc0)
205 FIELD(ATTR_48, ATTR_MSIX_CAP_TABLE_SIZE, 0, 11)
206REG32(ATTR_49, 0xc4)
207 FIELD(ATTR_49, ATTR_PCIE_CAP_CAPABILITY_ID, 8, 8)
208 FIELD(ATTR_49, ATTR_PCIE_BASE_PTR, 0, 8)
209REG32(ATTR_50, 0xc8)
210 FIELD(ATTR_50, ATTR_PCIE_CAP_NEXTPTR, 8, 8)
211 FIELD(ATTR_50, ATTR_PCIE_CAP_DEVICE_PORT_TYPE, 4, 4)
212 FIELD(ATTR_50, ATTR_PCIE_CAP_CAPABILITY_VERSION, 0, 4)
213REG32(ATTR_51, 0xcc)
214 FIELD(ATTR_51, ATTR_PM_BASE_PTR, 8, 8)
215 FIELD(ATTR_51, ATTR_PCIE_REVISION, 4, 4)
216 FIELD(ATTR_51, ATTR_PCIE_CAP_SLOT_IMPLEMENTED, 3, 1)
217 FIELD(ATTR_51, ATTR_PCIE_CAP_RSVD_15_14, 1, 2)
218 FIELD(ATTR_51, ATTR_PCIE_CAP_ON, 0, 1)
219REG32(ATTR_52, 0xd0)
220 FIELD(ATTR_52, ATTR_PM_CAP_ID, 6, 8)
221 FIELD(ATTR_52, ATTR_PM_CAP_DSI, 5, 1)
222 FIELD(ATTR_52, ATTR_PM_CAP_D2SUPPORT, 4, 1)
223 FIELD(ATTR_52, ATTR_PM_CAP_D1SUPPORT, 3, 1)
224 FIELD(ATTR_52, ATTR_PM_CAP_AUXCURRENT, 0, 3)
225REG32(ATTR_53, 0xd4)
226 FIELD(ATTR_53, ATTR_PM_CAP_RSVD_04, 15, 1)
227 FIELD(ATTR_53, ATTR_PM_CAP_PMESUPPORT, 10, 5)
228 FIELD(ATTR_53, ATTR_PM_CAP_PME_CLOCK, 9, 1)
229 FIELD(ATTR_53, ATTR_PM_CAP_ON, 8, 1)
230 FIELD(ATTR_53, ATTR_PM_CAP_NEXTPTR, 0, 8)
231REG32(ATTR_54, 0xd8)
232 FIELD(ATTR_54, ATTR_PM_DATA_SCALE4, 14, 2)
233 FIELD(ATTR_54, ATTR_PM_DATA_SCALE3, 12, 2)
234 FIELD(ATTR_54, ATTR_PM_DATA_SCALE2, 10, 2)
235 FIELD(ATTR_54, ATTR_PM_DATA_SCALE1, 8, 2)
236 FIELD(ATTR_54, ATTR_PM_DATA_SCALE0, 6, 2)
237 FIELD(ATTR_54, ATTR_PM_CSR_NOSOFTRST, 5, 1)
238 FIELD(ATTR_54, ATTR_PM_CSR_BPCCEN, 4, 1)
239 FIELD(ATTR_54, ATTR_PM_CSR_B2B3, 3, 1)
240 FIELD(ATTR_54, ATTR_PM_CAP_VERSION, 0, 3)
241REG32(ATTR_55, 0xdc)
242 FIELD(ATTR_55, ATTR_PM_DATA0, 6, 8)
243 FIELD(ATTR_55, ATTR_PM_DATA_SCALE7, 4, 2)
244 FIELD(ATTR_55, ATTR_PM_DATA_SCALE6, 2, 2)
245 FIELD(ATTR_55, ATTR_PM_DATA_SCALE5, 0, 2)
246REG32(ATTR_56, 0xe0)
247 FIELD(ATTR_56, ATTR_PM_DATA2, 8, 8)
248 FIELD(ATTR_56, ATTR_PM_DATA1, 0, 8)
249REG32(ATTR_57, 0xe4)
250 FIELD(ATTR_57, ATTR_PM_DATA4, 8, 8)
251 FIELD(ATTR_57, ATTR_PM_DATA3, 0, 8)
252REG32(ATTR_58, 0xe8)
253 FIELD(ATTR_58, ATTR_PM_DATA6, 8, 8)
254 FIELD(ATTR_58, ATTR_PM_DATA5, 0, 8)
255REG32(ATTR_59, 0xec)
256 FIELD(ATTR_59, ATTR_PM_DATA7, 0, 8)
257REG32(ATTR_60, 0xf0)
258 FIELD(ATTR_60, ATTR_RBAR_BASE_PTR, 0, 12)
259REG32(ATTR_61, 0xf4)
260 FIELD(ATTR_61, ATTR_RBAR_CAP_ON, 12, 1)
261 FIELD(ATTR_61, ATTR_RBAR_CAP_NEXTPTR, 0, 12)
262REG32(ATTR_62, 0xf8)
263 FIELD(ATTR_62, ATTR_RBAR_CAP_ID, 0, 16)
264REG32(ATTR_63, 0xfc)
265 FIELD(ATTR_63, ATTR_RBAR_NUM, 4, 3)
266 FIELD(ATTR_63, ATTR_RBAR_CAP_VERSION, 0, 4)
267REG32(ATTR_64, 0x100)
268 FIELD(ATTR_64, ATTR_RBAR_CAP_SUP0, 0, 16)
269REG32(ATTR_65, 0x104)
270 FIELD(ATTR_65, ATTR_RBAR_CAP_SUP0, 0, 16)
271REG32(ATTR_66, 0x108)
272 FIELD(ATTR_66, ATTR_RBAR_CAP_SUP1, 0, 16)
273REG32(ATTR_67, 0x10c)
274 FIELD(ATTR_67, ATTR_RBAR_CAP_SUP1, 0, 16)
275REG32(ATTR_68, 0x110)
276 FIELD(ATTR_68, ATTR_RBAR_CAP_SUP2, 0, 16)
277REG32(ATTR_69, 0x114)
278 FIELD(ATTR_69, ATTR_RBAR_CAP_SUP2, 0, 16)
279REG32(ATTR_70, 0x118)
280 FIELD(ATTR_70, ATTR_RBAR_CAP_SUP3, 0, 16)
281REG32(ATTR_71, 0x11c)
282 FIELD(ATTR_71, ATTR_RBAR_CAP_SUP3, 0, 16)
283REG32(ATTR_72, 0x120)
284 FIELD(ATTR_72, ATTR_RBAR_CAP_SUP4, 0, 16)
285REG32(ATTR_73, 0x124)
286 FIELD(ATTR_73, ATTR_RBAR_CAP_SUP4, 0, 16)
287REG32(ATTR_74, 0x128)
288 FIELD(ATTR_74, ATTR_RBAR_CAP_SUP5, 0, 16)
289REG32(ATTR_75, 0x12c)
290 FIELD(ATTR_75, ATTR_RBAR_CAP_SUP5, 0, 16)
291REG32(ATTR_76, 0x130)
292 FIELD(ATTR_76, ATTR_RBAR_CAP_INDEX4, 12, 3)
293 FIELD(ATTR_76, ATTR_RBAR_CAP_INDEX3, 9, 3)
294 FIELD(ATTR_76, ATTR_RBAR_CAP_INDEX2, 6, 3)
295 FIELD(ATTR_76, ATTR_RBAR_CAP_INDEX1, 3, 3)
296 FIELD(ATTR_76, ATTR_RBAR_CAP_INDEX0, 0, 3)
297REG32(ATTR_77, 0x134)
298 FIELD(ATTR_77, ATTR_RBAR_CAP_CONTROL_ENCODEDBAR1, 8, 5)
299 FIELD(ATTR_77, ATTR_RBAR_CAP_CONTROL_ENCODEDBAR0, 3, 5)
300 FIELD(ATTR_77, ATTR_RBAR_CAP_INDEX5, 0, 3)
301REG32(ATTR_78, 0x138)
302 FIELD(ATTR_78, ATTR_RBAR_CAP_CONTROL_ENCODEDBAR4, 10, 5)
303 FIELD(ATTR_78, ATTR_RBAR_CAP_CONTROL_ENCODEDBAR3, 5, 5)
304 FIELD(ATTR_78, ATTR_RBAR_CAP_CONTROL_ENCODEDBAR2, 0, 5)
305REG32(ATTR_79, 0x13c)
306 FIELD(ATTR_79, ATTR_SLOT_CAP_NO_CMD_COMPLETED_SUPPORT, 13, 1)
307 FIELD(ATTR_79, ATTR_SLOT_CAP_MRL_SENSOR_PRESENT, 12, 1)
308 FIELD(ATTR_79, ATTR_SLOT_CAP_HOTPLUG_SURPRISE, 11, 1)
309 FIELD(ATTR_79, ATTR_SLOT_CAP_HOTPLUG_CAPABLE, 10, 1)
310 FIELD(ATTR_79, ATTR_SLOT_CAP_ELEC_INTERLOCK_PRESENT, 9, 1)
311 FIELD(ATTR_79, ATTR_SLOT_CAP_ATT_INDICATOR_PRESENT, 8, 1)
312 FIELD(ATTR_79, ATTR_SLOT_CAP_ATT_BUTTON_PRESENT, 7, 1)
313 FIELD(ATTR_79, ATTR_SELECT_DLL_IF, 6, 1)
314 FIELD(ATTR_79, ATTR_ROOT_CAP_CRS_SW_VISIBILITY, 5, 1)
315 FIELD(ATTR_79, ATTR_RBAR_CAP_CONTROL_ENCODEDBAR5, 0, 5)
316REG32(ATTR_80, 0x140)
317 FIELD(ATTR_80, ATTR_SLOT_CAP_POWER_INDICATOR_PRESENT, 14, 1)
318 FIELD(ATTR_80, ATTR_SLOT_CAP_POWER_CONTROLLER_PRESENT, 13, 1)
319 FIELD(ATTR_80, ATTR_SLOT_CAP_PHYSICAL_SLOT_NUM, 0, 13)
320REG32(ATTR_81, 0x144)
321 FIELD(ATTR_81, ATTR_SSL_MESSAGE_AUTO, 10, 1)
322 FIELD(ATTR_81, ATTR_SLOT_CAP_SLOT_POWER_LIMIT_VALUE, 2, 8)
323 FIELD(ATTR_81, ATTR_SLOT_CAP_SLOT_POWER_LIMIT_SCALE, 0, 2)
324REG32(ATTR_82, 0x148)
325 FIELD(ATTR_82, ATTR_VC_BASE_PTR, 0, 12)
326REG32(ATTR_83, 0x14c)
327 FIELD(ATTR_83, ATTR_VC_CAP_ON, 12, 1)
328 FIELD(ATTR_83, ATTR_VC_CAP_NEXTPTR, 0, 12)
329REG32(ATTR_84, 0x150)
330 FIELD(ATTR_84, ATTR_VC_CAP_ID, 0, 16)
331REG32(ATTR_85, 0x154)
332 FIELD(ATTR_85, ATTR_VSEC_BASE_PTR, 1, 12)
333 FIELD(ATTR_85, ATTR_VC_CAP_REJECT_SNOOP_TRANSACTIONS, 0, 1)
334REG32(ATTR_86, 0x158)
335 FIELD(ATTR_86, ATTR_VSEC_CAP_HDR_ID, 0, 16)
336REG32(ATTR_87, 0x15c)
337 FIELD(ATTR_87, ATTR_VSEC_CAP_HDR_REVISION, 12, 4)
338 FIELD(ATTR_87, ATTR_VSEC_CAP_HDR_LENGTH, 0, 12)
339REG32(ATTR_88, 0x160)
340 FIELD(ATTR_88, ATTR_VSEC_CAP_ID, 0, 16)
341REG32(ATTR_89, 0x164)
342 FIELD(ATTR_89, ATTR_VSEC_CAP_ON, 13, 1)
343 FIELD(ATTR_89, ATTR_VSEC_CAP_NEXTPTR, 1, 12)
344 FIELD(ATTR_89, ATTR_VSEC_CAP_IS_LINK_VISIBLE, 0, 1)
345REG32(ATTR_90, 0x168)
346 FIELD(ATTR_90, ATTR_CRM_MODULE_RSTS, 7, 7)
347 FIELD(ATTR_90, ATTR_USER_CLK_FREQ, 4, 3)
348 FIELD(ATTR_90, ATTR_VSEC_CAP_VERSION, 0, 4)
349REG32(ATTR_91, 0x16c)
350 FIELD(ATTR_91, ATTR_LL_ACK_TIMEOUT_EN, 15, 1)
351 FIELD(ATTR_91, ATTR_LL_ACK_TIMEOUT, 0, 15)
352REG32(ATTR_92, 0x170)
353 FIELD(ATTR_92, ATTR_LL_ACK_TIMEOUT_FUNC, 0, 2)
354REG32(ATTR_93, 0x174)
355 FIELD(ATTR_93, ATTR_LL_REPLAY_TIMEOUT_EN, 15, 1)
356 FIELD(ATTR_93, ATTR_LL_REPLAY_TIMEOUT, 0, 15)
357REG32(ATTR_94, 0x178)
358 FIELD(ATTR_94, ATTR_LL_REPLAY_TIMEOUT_FUNC, 0, 2)
359REG32(ATTR_95, 0x17c)
360 FIELD(ATTR_95, ATTR_PM_ASPML0S_TIMEOUT_EN, 15, 1)
361 FIELD(ATTR_95, ATTR_PM_ASPML0S_TIMEOUT, 0, 15)
362REG32(ATTR_96, 0x180)
363 FIELD(ATTR_96, ATTR_INFER_EI, 6, 5)
364 FIELD(ATTR_96, ATTR_ENTER_RVRY_EI_L0, 5, 1)
365 FIELD(ATTR_96, ATTR_DISABLE_SCRAMBLING, 4, 1)
366 FIELD(ATTR_96, ATTR_DISABLE_LANE_REVERSAL, 3, 1)
367 FIELD(ATTR_96, ATTR_PM_ASPM_FASTEXIT, 2, 1)
368 FIELD(ATTR_96, ATTR_PM_ASPML0S_TIMEOUT_FUNC, 0, 2)
369REG32(ATTR_97, 0x184)
370 FIELD(ATTR_97, ATTR_LTSSM_MAX_LINK_WIDTH, 6, 6)
371 FIELD(ATTR_97, ATTR_LINK_CAP_MAX_LINK_WIDTH, 0, 6)
372REG32(ATTR_98, 0x188)
373 FIELD(ATTR_98, ATTR_N_FTS_COMCLK_GEN2, 8, 8)
374 FIELD(ATTR_98, ATTR_N_FTS_COMCLK_GEN1, 0, 8)
375REG32(ATTR_99, 0x18c)
376 FIELD(ATTR_99, ATTR_N_FTS_GEN2, 8, 8)
377 FIELD(ATTR_99, ATTR_N_FTS_GEN1, 0, 8)
378REG32(ATTR_100, 0x190)
379 FIELD(ATTR_100, ATTR_DNSTREAM_LINK_NUM, 8, 8)
380 FIELD(ATTR_100, ATTR_EXIT_LOOPBACK_ON_EI, 7, 1)
381 FIELD(ATTR_100, ATTR_UPSTREAM_FACING, 6, 1)
382 FIELD(ATTR_100, ATTR_UPCONFIG_CAPABLE, 5, 1)
383 FIELD(ATTR_100, ATTR_PL_FAST_TRAIN, 4, 1)
384 FIELD(ATTR_100, ATTR_PL_AUTO_CONFIG, 1, 3)
385 FIELD(ATTR_100, ATTR_ALLOW_X8_GEN2, 0, 1)
386REG32(ATTR_101, 0x194)
387 FIELD(ATTR_101, ATTR_ENABLE_MSG_ROUTE, 5, 11)
388 FIELD(ATTR_101, ATTR_DISABLE_RX_POISONED_RESP, 4, 1)
389 FIELD(ATTR_101, ATTR_DISABLE_RX_TC_FILTER, 3, 1)
390 FIELD(ATTR_101, ATTR_DISABLE_ID_CHECK, 2, 1)
391 FIELD(ATTR_101, ATTR_DISABLE_BAR_FILTERING, 1, 1)
392 FIELD(ATTR_101, ATTR_DISABLE_ASPM_L1_TIMER, 0, 1)
393REG32(ATTR_102, 0x198)
394 FIELD(ATTR_102, ATTR_TL_TX_RAM_RDATA_LATENCY, 14, 2)
395 FIELD(ATTR_102, ATTR_TL_TX_RAM_RADDR_LATENCY, 13, 1)
396 FIELD(ATTR_102, ATTR_PM_MF, 12, 1)
397 FIELD(ATTR_102, ATTR_DISABLE_ERR_MSG, 11, 1)
398 FIELD(ATTR_102, ATTR_USE_RID_PINS, 10, 1)
399 FIELD(ATTR_102, ATTR_DISABLE_LOCKED_FILTER, 9, 1)
400 FIELD(ATTR_102, ATTR_DISABLE_PPM_FILTER, 8, 1)
401 FIELD(ATTR_102, ATTR_TL_RBYPASS, 7, 1)
402 FIELD(ATTR_102, ATTR_TL_TX_CHECKS_DISABLE, 6, 1)
403 FIELD(ATTR_102, ATTR_TL_TFC_DISABLE, 5, 1)
404 FIELD(ATTR_102, ATTR_TL_RX_RAM_WRITE_LATENCY, 4, 1)
405 FIELD(ATTR_102, ATTR_TL_RX_RAM_RDATA_LATENCY, 2, 2)
406 FIELD(ATTR_102, ATTR_TL_RX_RAM_RADDR_LATENCY, 1, 1)
407 FIELD(ATTR_102, ATTR_ENABLE_RX_TD_ECRC_TRIM, 0, 1)
408REG32(ATTR_103, 0x19c)
409 FIELD(ATTR_103, ATTR_VC0_CPL_INFINITE, 5, 1)
410 FIELD(ATTR_103, ATTR_VC_CAP_VERSION, 1, 4)
411 FIELD(ATTR_103, ATTR_TL_TX_RAM_WRITE_LATENCY, 0, 1)
412REG32(ATTR_104, 0x1a0)
413 FIELD(ATTR_104, ATTR_VC0_RX_RAM_LIMIT, 0, 13)
414REG32(ATTR_105, 0x1a4)
415 FIELD(ATTR_105, ATTR_VC0_TOTAL_CREDITS_CD, 0, 11)
416REG32(ATTR_106, 0x1a8)
417 FIELD(ATTR_106, ATTR_VC0_TOTAL_CREDITS_NPH, 7, 7)
418 FIELD(ATTR_106, ATTR_VC0_TOTAL_CREDITS_CH, 0, 7)
419REG32(ATTR_107, 0x1ac)
420 FIELD(ATTR_107, ATTR_VC0_TOTAL_CREDITS_NPD, 0, 11)
421REG32(ATTR_108, 0x1b0)
422 FIELD(ATTR_108, ATTR_VC0_TOTAL_CREDITS_PD, 0, 11)
423REG32(ATTR_109, 0x1b4)
424 FIELD(ATTR_109, ATTR_TECRC_EP_INV, 15, 1)
425 FIELD(ATTR_109, ATTR_RECRC_CHK_TRIM, 14, 1)
426 FIELD(ATTR_109, ATTR_RECRC_CHK, 12, 2)
427 FIELD(ATTR_109, ATTR_VC0_TX_LASTPACKET, 7, 5)
428 FIELD(ATTR_109, ATTR_VC0_TOTAL_CREDITS_PH, 0, 7)
429REG32(ATTR_110, 0x1b8)
430 FIELD(ATTR_110, ATTR_RP_AUTO_SPD_LOOPCNT, 11, 5)
431 FIELD(ATTR_110, ATTR_RP_AUTO_SPD, 9, 2)
432 FIELD(ATTR_110, ATTR_USER_CLK2_DIV2, 8, 1)
433 FIELD(ATTR_110, ATTR_TRN_NP_FC, 7, 1)
434 FIELD(ATTR_110, ATTR_TRN_DW, 6, 1)
435 FIELD(ATTR_110, ATTR_UR_CFG1, 5, 1)
436 FIELD(ATTR_110, ATTR_UR_ATOMIC, 4, 1)
437 FIELD(ATTR_110, ATTR_UR_PRS_RESPONSE, 3, 1)
438 FIELD(ATTR_110, ATTR_UR_INV_REQ, 2, 1)
439 FIELD(ATTR_110, ATTR_CFG_ECRC_ERR_CPLSTAT, 0, 2)
440REG32(ATTR_111, 0x1bc)
441 FIELD(ATTR_111, ATTR_SPARE_BIT8, 9, 1)
442 FIELD(ATTR_111, ATTR_SPARE_BIT7, 8, 1)
443 FIELD(ATTR_111, ATTR_SPARE_BIT6, 7, 1)
444 FIELD(ATTR_111, ATTR_SPARE_BIT5, 6, 1)
445 FIELD(ATTR_111, ATTR_SPARE_BIT4, 5, 1)
446 FIELD(ATTR_111, ATTR_SPARE_BIT3, 4, 1)
447 FIELD(ATTR_111, ATTR_SPARE_BIT2, 3, 1)
448 FIELD(ATTR_111, ATTR_SPARE_BIT1, 2, 1)
449 FIELD(ATTR_111, ATTR_SPARE_BIT0, 1, 1)
450 FIELD(ATTR_111, ATTR_TEST_MODE_PIN_CHAR, 0, 1)
451REG32(ATTR_112, 0x1c0)
452 FIELD(ATTR_112, ATTR_SPARE_BYTE1, 8, 8)
453 FIELD(ATTR_112, ATTR_SPARE_BYTE0, 0, 8)
454REG32(ATTR_113, 0x1c4)
455 FIELD(ATTR_113, ATTR_SPARE_BYTE3, 8, 8)
456 FIELD(ATTR_113, ATTR_SPARE_BYTE2, 0, 8)
457REG32(ATTR_114, 0x1c8)
458 FIELD(ATTR_114, ATTR_SPARE_WORD0, 0, 16)
459REG32(ATTR_115, 0x1cc)
460 FIELD(ATTR_115, ATTR_SPARE_WORD0, 0, 16)
461REG32(ATTR_116, 0x1d0)
462 FIELD(ATTR_116, ATTR_SPARE_WORD1, 0, 16)
463REG32(ATTR_117, 0x1d4)
464 FIELD(ATTR_117, ATTR_SPARE_WORD1, 0, 16)
465REG32(ATTR_118, 0x1d8)
466 FIELD(ATTR_118, ATTR_SPARE_WORD2, 0, 16)
467REG32(ATTR_119, 0x1dc)
468 FIELD(ATTR_119, ATTR_SPARE_WORD2, 0, 16)
469REG32(ATTR_120, 0x1e0)
470 FIELD(ATTR_120, ATTR_SPARE_WORD3, 0, 16)
471REG32(ATTR_121, 0x1e4)
472 FIELD(ATTR_121, ATTR_SPARE_WORD3, 0, 16)
473REG32(ID, 0x200)
474 FIELD(ID, CFG_VEND_ID, 16, 16)
475 FIELD(ID, CFG_DEV_ID, 0, 16)
476REG32(SUBSYS_ID, 0x204)
477 FIELD(SUBSYS_ID, CFG_SUBSYS_VEND_ID, 16, 16)
478 FIELD(SUBSYS_ID, CFG_SUBSYS_ID, 0, 16)
479REG32(REV_ID, 0x208)
480 FIELD(REV_ID, CFG_REV_ID, 0, 8)
481REG32(DSN_0, 0x20c)
482REG32(DSN_1, 0x210)
483REG32(MGMT_CTRL, 0x214)
484 FIELD(MGMT_CTRL, CFG_MGMT_WR_READONLY, 1, 1)
485 FIELD(MGMT_CTRL, CFG_MGMT_WR_RW1C_AS_RW, 0, 1)
486REG32(PM_CTRL, 0x218)
487 FIELD(PM_CTRL, CFG_TRN_PENDING, 3, 1)
488 FIELD(PM_CTRL, CFG_PM_SEND_PME_TO, 2, 1)
489 FIELD(PM_CTRL, CFG_PM_TURNOFF_OK, 1, 1)
490 FIELD(PM_CTRL, CFG_PM_WAKE, 0, 1)
491REG32(RST_CTRL, 0x220)
492 FIELD(RST_CTRL, PL_RST_N, 6, 1)
493 FIELD(RST_CTRL, FUNC_LVL_RST_N, 5, 1)
494 FIELD(RST_CTRL, DL_RST_N, 3, 1)
495 FIELD(RST_CTRL, TL_RST_N, 2, 1)
496 FIELD(RST_CTRL, CM_STICKY_RST_N, 1, 1)
497 FIELD(RST_CTRL, CM_RST_N, 0, 1)
498REG32(DBG_CTRL, 0x224)
499 FIELD(DBG_CTRL, PL_DBG_MODE, 3, 3)
500 FIELD(DBG_CTRL, DBG_SUB_MODE, 2, 1)
501 FIELD(DBG_CTRL, DBG_MODE, 0, 2)
502REG32(PL_LINK_CTRL_STATUS, 0x228)
503 FIELD(PL_LINK_CTRL_STATUS, DIR_LINK_CHANGE_DONE, 22, 1)
504 FIELD(PL_LINK_CTRL_STATUS, DIR_LINK_CHANGE, 20, 2)
505 FIELD(PL_LINK_CTRL_STATUS, DIR_LINK_AUTON, 19, 1)
506 FIELD(PL_LINK_CTRL_STATUS, DIR_LINK_SPEED, 18, 1)
507 FIELD(PL_LINK_CTRL_STATUS, DIR_LINK_WIDTH, 16, 2)
508 FIELD(PL_LINK_CTRL_STATUS, LINK_UP, 11, 1)
509 FIELD(PL_LINK_CTRL_STATUS, LANE_REVERSAL, 9, 2)
510 FIELD(PL_LINK_CTRL_STATUS, LTSSM_STATE, 3, 6)
511 FIELD(PL_LINK_CTRL_STATUS, LINK_WIDTH, 1, 2)
512 FIELD(PL_LINK_CTRL_STATUS, LINK_RATE, 0, 1)
513REG32(DIR_LTSSM, 0x22c)
514 FIELD(DIR_LTSSM, PL_DIR_LTSSM_STALL, 7, 1)
515 FIELD(DIR_LTSSM, PL_DIR_LTSSM_NEW_VLD, 6, 1)
516 FIELD(DIR_LTSSM, PL_DIR_LTSSM_NEW, 0, 6)
517REG32(EP_CTRL, 0x230)
518 FIELD(EP_CTRL, PL_UPSTREAM_DEEMPH_SOURCE, 1, 1)
519 FIELD(EP_CTRL, PL_RECEIVED_HOT_RST, 0, 1)
520REG32(RP_CTRL, 0x234)
521 FIELD(RP_CTRL, PL_DOWNSTREAM_DEEMPH_SOURCE, 1, 1)
522 FIELD(RP_CTRL, PL_TRANSMIT_HOT_RST, 0, 1)
523REG32(PCIE_STATUS, 0x238)
524 FIELD(PCIE_STATUS, PHY_RDY, 1, 1)
525 FIELD(PCIE_STATUS, PCIE_LINK_UP, 0, 1)
526REG32(MISC_CTRL, 0x300)
527 FIELD(MISC_CTRL, SLVERR_ENABLE, 0, 1)
528REG32(ISR, 0x304)
529 FIELD(ISR, PCIE_RESET, 1, 1)
530 FIELD(ISR, ADDR_DECODE_ERR, 0, 1)
531REG32(IMR, 0x308)
532 FIELD(IMR, PCIE_RESET, 1, 1)
533 FIELD(IMR, ADDR_DECODE_ERR, 0, 1)
534REG32(IER, 0x30c)
535 FIELD(IER, PCIE_RESET, 1, 1)
536 FIELD(IER, ADDR_DECODE_ERR, 0, 1)
537REG32(IDR, 0x310)
538 FIELD(IDR, PCIE_RESET, 1, 1)
539 FIELD(IDR, ADDR_DECODE_ERR, 0, 1)
540REG32(ECO_0, 0x314)
541REG32(ECO_1, 0x318)
542REG32(CB, 0x31c)
543 FIELD(CB, CB1, 1, 1)
544 FIELD(CB, CB0, 0, 1)
545
546#define PCIE_ATTRIB_R_MAX (R_CB + 1)
547
548typedef struct PCIE_ATTRIB {
549 SysBusDevice parent_obj;
550 MemoryRegion iomem;
551 qemu_irq irq_imr;
552
553 uint32_t regs[PCIE_ATTRIB_R_MAX];
554 RegisterInfo regs_info[PCIE_ATTRIB_R_MAX];
555} PCIE_ATTRIB;
556
557static void imr_update_irq(PCIE_ATTRIB *s)
558{
559 bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];
560 qemu_set_irq(s->irq_imr, pending);
561}
562
563static void isr_postw(RegisterInfo *reg, uint64_t val64)
564{
565 PCIE_ATTRIB *s = XILINX_PCIE_ATTRIB(reg->opaque);
566 imr_update_irq(s);
567}
568
569static uint64_t ier_prew(RegisterInfo *reg, uint64_t val64)
570{
571 PCIE_ATTRIB *s = XILINX_PCIE_ATTRIB(reg->opaque);
572 uint32_t val = val64;
573
574 s->regs[R_IMR] &= ~val;
575 imr_update_irq(s);
576 return 0;
577}
578
579static uint64_t idr_prew(RegisterInfo *reg, uint64_t val64)
580{
581 PCIE_ATTRIB *s = XILINX_PCIE_ATTRIB(reg->opaque);
582 uint32_t val = val64;
583
584 s->regs[R_IMR] |= val;
585 imr_update_irq(s);
586 return 0;
587}
588
589static const RegisterAccessInfo pcie_attrib_regs_info[] = {
590 { .name = "ATTR_0", .addr = A_ATTR_0,
591 .reset = 0x3,
592 },{ .name = "ATTR_1", .addr = A_ATTR_1,
593 .reset = 0x1,
594 },{ .name = "ATTR_2", .addr = A_ATTR_2,
595 .reset = 0x2,
596 },{ .name = "ATTR_3", .addr = A_ATTR_3,
597 .reset = 0x140,
598 },{ .name = "ATTR_4", .addr = A_ATTR_4,
599 .reset = 0x1000,
600 },{ .name = "ATTR_5", .addr = A_ATTR_5,
601 .reset = 0xff07,
602 },{ .name = "ATTR_6", .addr = A_ATTR_6,
603 .reset = 0x7,
604 },{ .name = "ATTR_7", .addr = A_ATTR_7,
605 .reset = 0x4,
606 },{ .name = "ATTR_8", .addr = A_ATTR_8,
607 .reset = 0xfff0,
608 },{ .name = "ATTR_9", .addr = A_ATTR_9,
609 .reset = 0xffff,
610 },{ .name = "ATTR_10", .addr = A_ATTR_10,
611 .reset = 0xffff,
612 },{ .name = "ATTR_11", .addr = A_ATTR_11,
613 .reset = 0x4,
614 },{ .name = "ATTR_12", .addr = A_ATTR_12,
615 .reset = 0xfff0,
616 },{ .name = "ATTR_13", .addr = A_ATTR_13,
617 .reset = 0xffff,
618 },{ .name = "ATTR_14", .addr = A_ATTR_14,
619 .reset = 0xffff,
620 },{ .name = "ATTR_15", .addr = A_ATTR_15,
621 .reset = 0x4,
622 },{ .name = "ATTR_16", .addr = A_ATTR_16,
623 .reset = 0xfff0,
624 },{ .name = "ATTR_17", .addr = A_ATTR_17,
625 .reset = 0xffff,
626 },{ .name = "ATTR_18", .addr = A_ATTR_18,
627 .reset = 0xffff,
628 },{ .name = "ATTR_19", .addr = A_ATTR_19,
629 },{ .name = "ATTR_20", .addr = A_ATTR_20,
630 },{ .name = "ATTR_21", .addr = A_ATTR_21,
631 .reset = 0x40,
632 },{ .name = "ATTR_22", .addr = A_ATTR_22,
633 },{ .name = "ATTR_23", .addr = A_ATTR_23,
634 },{ .name = "ATTR_24", .addr = A_ATTR_24,
635 .reset = 0x8000,
636 },{ .name = "ATTR_25", .addr = A_ATTR_25,
637 .reset = 0x905,
638 },{ .name = "ATTR_26", .addr = A_ATTR_26,
639 .reset = 0x3000,
640 },{ .name = "ATTR_27", .addr = A_ATTR_27,
641 .reset = 0x2138,
642 },{ .name = "ATTR_28", .addr = A_ATTR_28,
643 },{ .name = "ATTR_29", .addr = A_ATTR_29,
644 .reset = 0x100,
645 },{ .name = "ATTR_30", .addr = A_ATTR_30,
646 .reset = 0x3,
647 },{ .name = "ATTR_31", .addr = A_ATTR_31,
648 .reset = 0x110c,
649 },{ .name = "ATTR_32", .addr = A_ATTR_32,
650 .reset = 0x3f1,
651 },{ .name = "ATTR_33", .addr = A_ATTR_33,
652 .reset = 0x3ff,
653 },{ .name = "ATTR_34", .addr = A_ATTR_34,
654 .reset = 0x100,
655 },{ .name = "ATTR_35", .addr = A_ATTR_35,
656 .reset = 0xffd,
657 },{ .name = "ATTR_36", .addr = A_ATTR_36,
658 .reset = 0x7fff,
659 },{ .name = "ATTR_37", .addr = A_ATTR_37,
660 .reset = 0x49ff,
661 },{ .name = "ATTR_38", .addr = A_ATTR_38,
662 .reset = 0x120,
663 },{ .name = "ATTR_39", .addr = A_ATTR_39,
664 .reset = 0x148,
665 },{ .name = "ATTR_40", .addr = A_ATTR_40,
666 .reset = 0x405,
667 },{ .name = "ATTR_41", .addr = A_ATTR_41,
668 .reset = 0x160,
669 },{ .name = "ATTR_42", .addr = A_ATTR_42,
670 .reset = 0x119c,
671 },{ .name = "ATTR_43", .addr = A_ATTR_43,
672 .reset = 0x100,
673 },{ .name = "ATTR_44", .addr = A_ATTR_44,
674 .reset = 0x1,
675 },{ .name = "ATTR_45", .addr = A_ATTR_45,
676 .reset = 0x8000,
677 },{ .name = "ATTR_46", .addr = A_ATTR_46,
678 .reset = 0x1,
679 },{ .name = "ATTR_47", .addr = A_ATTR_47,
680 },{ .name = "ATTR_48", .addr = A_ATTR_48,
681 .reset = 0x3,
682 },{ .name = "ATTR_49", .addr = A_ATTR_49,
683 .reset = 0x1060,
684 },{ .name = "ATTR_50", .addr = A_ATTR_50,
685 .reset = 0x9c02,
686 },{ .name = "ATTR_51", .addr = A_ATTR_51,
687 .reset = 0x4021,
688 },{ .name = "ATTR_52", .addr = A_ATTR_52,
689 .reset = 0x40,
690 },{ .name = "ATTR_53", .addr = A_ATTR_53,
691 .reset = 0x3d48,
692 },{ .name = "ATTR_54", .addr = A_ATTR_54,
693 .reset = 0x23,
694 },{ .name = "ATTR_55", .addr = A_ATTR_55,
695 },{ .name = "ATTR_56", .addr = A_ATTR_56,
696 },{ .name = "ATTR_57", .addr = A_ATTR_57,
697 },{ .name = "ATTR_58", .addr = A_ATTR_58,
698 },{ .name = "ATTR_59", .addr = A_ATTR_59,
699 },{ .name = "ATTR_60", .addr = A_ATTR_60,
700 .reset = 0x178,
701 },{ .name = "ATTR_61", .addr = A_ATTR_61,
702 },{ .name = "ATTR_62", .addr = A_ATTR_62,
703 .reset = 0x15,
704 },{ .name = "ATTR_63", .addr = A_ATTR_63,
705 .reset = 0x1,
706 },{ .name = "ATTR_64", .addr = A_ATTR_64,
707 .reset = 0x1,
708 },{ .name = "ATTR_65", .addr = A_ATTR_65,
709 },{ .name = "ATTR_66", .addr = A_ATTR_66,
710 .reset = 0x1,
711 },{ .name = "ATTR_67", .addr = A_ATTR_67,
712 },{ .name = "ATTR_68", .addr = A_ATTR_68,
713 .reset = 0x1,
714 },{ .name = "ATTR_69", .addr = A_ATTR_69,
715 },{ .name = "ATTR_70", .addr = A_ATTR_70,
716 .reset = 0x1,
717 },{ .name = "ATTR_71", .addr = A_ATTR_71,
718 },{ .name = "ATTR_72", .addr = A_ATTR_72,
719 .reset = 0x1,
720 },{ .name = "ATTR_73", .addr = A_ATTR_73,
721 },{ .name = "ATTR_74", .addr = A_ATTR_74,
722 .reset = 0x1,
723 },{ .name = "ATTR_75", .addr = A_ATTR_75,
724 },{ .name = "ATTR_76", .addr = A_ATTR_76,
725 },{ .name = "ATTR_77", .addr = A_ATTR_77,
726 },{ .name = "ATTR_78", .addr = A_ATTR_78,
727 },{ .name = "ATTR_79", .addr = A_ATTR_79,
728 },{ .name = "ATTR_80", .addr = A_ATTR_80,
729 },{ .name = "ATTR_81", .addr = A_ATTR_81,
730 },{ .name = "ATTR_82", .addr = A_ATTR_82,
731 .reset = 0x10c,
732 },{ .name = "ATTR_83", .addr = A_ATTR_83,
733 .reset = 0x1128,
734 },{ .name = "ATTR_84", .addr = A_ATTR_84,
735 .reset = 0x2,
736 },{ .name = "ATTR_85", .addr = A_ATTR_85,
737 .reset = 0x250,
738 },{ .name = "ATTR_86", .addr = A_ATTR_86,
739 .reset = 0x1234,
740 },{ .name = "ATTR_87", .addr = A_ATTR_87,
741 .reset = 0x1018,
742 },{ .name = "ATTR_88", .addr = A_ATTR_88,
743 .reset = 0xb,
744 },{ .name = "ATTR_89", .addr = A_ATTR_89,
745 .reset = 0x2281,
746 },{ .name = "ATTR_90", .addr = A_ATTR_90,
747 .reset = 0x31,
748 },{ .name = "ATTR_91", .addr = A_ATTR_91,
749 },{ .name = "ATTR_92", .addr = A_ATTR_92,
750 },{ .name = "ATTR_93", .addr = A_ATTR_93,
751 },{ .name = "ATTR_94", .addr = A_ATTR_94,
752 .reset = 0x1,
753 },{ .name = "ATTR_95", .addr = A_ATTR_95,
754 },{ .name = "ATTR_96", .addr = A_ATTR_96,
755 .reset = 0x28,
756 },{ .name = "ATTR_97", .addr = A_ATTR_97,
757 .reset = 0x104,
758 },{ .name = "ATTR_98", .addr = A_ATTR_98,
759 .reset = 0xffff,
760 },{ .name = "ATTR_99", .addr = A_ATTR_99,
761 .reset = 0xffff,
762 },{ .name = "ATTR_100", .addr = A_ATTR_100,
763 .reset = 0xf0,
764 },{ .name = "ATTR_101", .addr = A_ATTR_101,
765 },{ .name = "ATTR_102", .addr = A_ATTR_102,
766 .reset = 0x8008,
767 },{ .name = "ATTR_103", .addr = A_ATTR_103,
768 .reset = 0x22,
769 },{ .name = "ATTR_104", .addr = A_ATTR_104,
770 .reset = 0x3ff,
771 },{ .name = "ATTR_105", .addr = A_ATTR_105,
772 .reset = 0x172,
773 },{ .name = "ATTR_106", .addr = A_ATTR_106,
774 .reset = 0x248,
775 },{ .name = "ATTR_107", .addr = A_ATTR_107,
776 .reset = 0x8,
777 },{ .name = "ATTR_108", .addr = A_ATTR_108,
778 .reset = 0x20,
779 },{ .name = "ATTR_109", .addr = A_ATTR_109,
780 .reset = 0x7e04,
781 },{ .name = "ATTR_110", .addr = A_ATTR_110,
782 .reset = 0xfabc,
783 },{ .name = "ATTR_111", .addr = A_ATTR_111,
784 },{ .name = "ATTR_112", .addr = A_ATTR_112,
785 },{ .name = "ATTR_113", .addr = A_ATTR_113,
786 },{ .name = "ATTR_114", .addr = A_ATTR_114,
787 },{ .name = "ATTR_115", .addr = A_ATTR_115,
788 },{ .name = "ATTR_116", .addr = A_ATTR_116,
789 },{ .name = "ATTR_117", .addr = A_ATTR_117,
790 },{ .name = "ATTR_118", .addr = A_ATTR_118,
791 },{ .name = "ATTR_119", .addr = A_ATTR_119,
792 },{ .name = "ATTR_120", .addr = A_ATTR_120,
793 },{ .name = "ATTR_121", .addr = A_ATTR_121,
794 },{ .name = "ID", .addr = A_ID,
795 .reset = 0x10ee7024,
796 },{ .name = "SUBSYS_ID", .addr = A_SUBSYS_ID,
797 .reset = 0x10ee0007,
798 },{ .name = "REV_ID", .addr = A_REV_ID,
799 },{ .name = "DSN_0", .addr = A_DSN_0,
800 },{ .name = "DSN_1", .addr = A_DSN_1,
801 },{ .name = "MGMT_CTRL", .addr = A_MGMT_CTRL,
802 },{ .name = "PM_CTRL", .addr = A_PM_CTRL,
803 .reset = 0x7,
804 .ro = 0x8,
805 },{ .name = "RST_CTRL", .addr = A_RST_CTRL,
806 .reset = 0x6f,
807 },{ .name = "DBG_CTRL", .addr = A_DBG_CTRL,
808 },{ .name = "PL_LINK_CTRL_STATUS", .addr = A_PL_LINK_CTRL_STATUS,
809 .rsvd = 0xf000,
810 .ro = 0x40ffff,
811 },{ .name = "DIR_LTSSM", .addr = A_DIR_LTSSM,
812 },{ .name = "EP_CTRL", .addr = A_EP_CTRL,
813 .ro = 0x1,
814 },{ .name = "RP_CTRL", .addr = A_RP_CTRL,
815 },{ .name = "PCIE_STATUS", .addr = A_PCIE_STATUS,
816 .ro = 0x3,
817
818 .reset = R_PCIE_STATUS_PHY_RDY_MASK | R_PCIE_STATUS_PCIE_LINK_UP_MASK,
819 },{ .name = "MISC_CTRL", .addr = A_MISC_CTRL,
820 },{ .name = "ISR", .addr = A_ISR,
821 .w1c = 0x3,
822 .post_write = isr_postw,
823 },{ .name = "IMR", .addr = A_IMR,
824 .reset = 0x3,
825 .ro = 0x3,
826 },{ .name = "IER", .addr = A_IER,
827 .pre_write = ier_prew,
828 },{ .name = "IDR", .addr = A_IDR,
829 .pre_write = idr_prew,
830 },{ .name = "ECO_0", .addr = A_ECO_0,
831 },{ .name = "ECO_1", .addr = A_ECO_1,
832 .reset = 0xffffffff,
833 },{ .name = "CB", .addr = A_CB,
834 .reset = 0x1,
835 }
836};
837
838static void pcie_attrib_reset(DeviceState *dev)
839{
840 PCIE_ATTRIB *s = XILINX_PCIE_ATTRIB(dev);
841 unsigned int i;
842
843 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
844 register_reset(&s->regs_info[i]);
845 }
846
847 imr_update_irq(s);
848}
849
850static const MemoryRegionOps pcie_attrib_ops = {
851 .read = register_read_memory,
852 .write = register_write_memory,
853 .endianness = DEVICE_LITTLE_ENDIAN,
854 .valid = {
855 .min_access_size = 4,
856 .max_access_size = 4,
857 },
858};
859
860static void pcie_attrib_init(Object *obj)
861{
862 PCIE_ATTRIB *s = XILINX_PCIE_ATTRIB(obj);
863 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
864 RegisterInfoArray *reg_array;
865
866 memory_region_init(&s->iomem, obj, TYPE_XILINX_PCIE_ATTRIB,
867 PCIE_ATTRIB_R_MAX * 4);
868 reg_array =
869 register_init_block32(DEVICE(obj), pcie_attrib_regs_info,
870 ARRAY_SIZE(pcie_attrib_regs_info),
871 s->regs_info, s->regs,
872 &pcie_attrib_ops,
873 XILINX_PCIE_ATTRIB_ERR_DEBUG,
874 PCIE_ATTRIB_R_MAX * 4);
875 memory_region_add_subregion(&s->iomem,
876 0x0,
877 ®_array->mem);
878 sysbus_init_mmio(sbd, &s->iomem);
879 sysbus_init_irq(sbd, &s->irq_imr);
880}
881
882static const VMStateDescription vmstate_pcie_attrib = {
883 .name = TYPE_XILINX_PCIE_ATTRIB,
884 .version_id = 1,
885 .minimum_version_id = 1,
886 .fields = (VMStateField[]) {
887 VMSTATE_UINT32_ARRAY(regs, PCIE_ATTRIB, PCIE_ATTRIB_R_MAX),
888 VMSTATE_END_OF_LIST(),
889 }
890};
891
892static void pcie_attrib_class_init(ObjectClass *klass, void *data)
893{
894 DeviceClass *dc = DEVICE_CLASS(klass);
895
896 dc->reset = pcie_attrib_reset;
897 dc->vmsd = &vmstate_pcie_attrib;
898}
899
900static const TypeInfo pcie_attrib_info = {
901 .name = TYPE_XILINX_PCIE_ATTRIB,
902 .parent = TYPE_SYS_BUS_DEVICE,
903 .instance_size = sizeof(PCIE_ATTRIB),
904 .class_init = pcie_attrib_class_init,
905 .instance_init = pcie_attrib_init,
906};
907
908static void pcie_attrib_register_types(void)
909{
910 type_register_static(&pcie_attrib_info);
911}
912
913type_init(pcie_attrib_register_types)
914
