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27#include "qemu/osdep.h"
28#include "hw/sysbus.h"
29#include "hw/register.h"
30#include "qemu/bitops.h"
31#include "qemu/log.h"
32#include "qom/object.h"
33#include "migration/vmstate.h"
34#include "hw/qdev-properties.h"
35#include "hw/usb/hcd-dwc3.h"
36
37#ifndef USB_DWC3_ERR_DEBUG
38#define USB_DWC3_ERR_DEBUG 0
39#endif
40
41#define HOST_MODE 1
42#define FIFO_LEN 0x1000
43
44REG32(GSBUSCFG0, 0x00)
45 FIELD(GSBUSCFG0, DATRDREQINFO, 28, 4)
46 FIELD(GSBUSCFG0, DESRDREQINFO, 24, 4)
47 FIELD(GSBUSCFG0, DATWRREQINFO, 20, 4)
48 FIELD(GSBUSCFG0, DESWRREQINFO, 16, 4)
49 FIELD(GSBUSCFG0, RESERVED_15_12, 12, 4)
50 FIELD(GSBUSCFG0, DATBIGEND, 11, 1)
51 FIELD(GSBUSCFG0, DESBIGEND, 10, 1)
52 FIELD(GSBUSCFG0, RESERVED_9_8, 8, 2)
53 FIELD(GSBUSCFG0, INCR256BRSTENA, 7, 1)
54 FIELD(GSBUSCFG0, INCR128BRSTENA, 6, 1)
55 FIELD(GSBUSCFG0, INCR64BRSTENA, 5, 1)
56 FIELD(GSBUSCFG0, INCR32BRSTENA, 4, 1)
57 FIELD(GSBUSCFG0, INCR16BRSTENA, 3, 1)
58 FIELD(GSBUSCFG0, INCR8BRSTENA, 2, 1)
59 FIELD(GSBUSCFG0, INCR4BRSTENA, 1, 1)
60 FIELD(GSBUSCFG0, INCRBRSTENA, 0, 1)
61REG32(GSBUSCFG1, 0x04)
62 FIELD(GSBUSCFG1, RESERVED_31_13, 13, 19)
63 FIELD(GSBUSCFG1, EN1KPAGE, 12, 1)
64 FIELD(GSBUSCFG1, PIPETRANSLIMIT, 8, 4)
65 FIELD(GSBUSCFG1, RESERVED_7_0, 0, 8)
66REG32(GTXTHRCFG, 0x08)
67 FIELD(GTXTHRCFG, RESERVED_31, 31, 1)
68 FIELD(GTXTHRCFG, RESERVED_30, 30, 1)
69 FIELD(GTXTHRCFG, USBTXPKTCNTSEL, 29, 1)
70 FIELD(GTXTHRCFG, RESERVED_28, 28, 1)
71 FIELD(GTXTHRCFG, USBTXPKTCNT, 24, 4)
72 FIELD(GTXTHRCFG, USBMAXTXBURSTSIZE, 16, 8)
73 FIELD(GTXTHRCFG, RESERVED_15, 15, 1)
74 FIELD(GTXTHRCFG, RESERVED_14, 14, 1)
75 FIELD(GTXTHRCFG, RESERVED_13_11, 11, 3)
76 FIELD(GTXTHRCFG, RESERVED_10_0, 0, 11)
77REG32(GRXTHRCFG, 0x0c)
78 FIELD(GRXTHRCFG, RESERVED_31_30, 30, 2)
79 FIELD(GRXTHRCFG, USBRXPKTCNTSEL, 29, 1)
80 FIELD(GRXTHRCFG, RESERVED_28, 28, 1)
81 FIELD(GRXTHRCFG, USBRXPKTCNT, 24, 4)
82 FIELD(GRXTHRCFG, USBMAXRXBURSTSIZE, 19, 5)
83 FIELD(GRXTHRCFG, RESERVED_18_16, 16, 3)
84 FIELD(GRXTHRCFG, RESERVED_15, 15, 1)
85 FIELD(GRXTHRCFG, RESERVED_14_13, 13, 2)
86 FIELD(GRXTHRCFG, RESVISOCOUTSPC, 0, 13)
87REG32(GCTL, 0x10)
88 FIELD(GCTL, PWRDNSCALE, 19, 13)
89 FIELD(GCTL, MASTERFILTBYPASS, 18, 1)
90 FIELD(GCTL, BYPSSETADDR, 17, 1)
91 FIELD(GCTL, U2RSTECN, 16, 1)
92 FIELD(GCTL, FRMSCLDWN, 14, 2)
93 FIELD(GCTL, PRTCAPDIR, 12, 2)
94 FIELD(GCTL, CORESOFTRESET, 11, 1)
95 FIELD(GCTL, U1U2TIMERSCALE, 9, 1)
96 FIELD(GCTL, DEBUGATTACH, 8, 1)
97 FIELD(GCTL, RAMCLKSEL, 6, 2)
98 FIELD(GCTL, SCALEDOWN, 4, 2)
99 FIELD(GCTL, DISSCRAMBLE, 3, 1)
100 FIELD(GCTL, U2EXIT_LFPS, 2, 1)
101 FIELD(GCTL, GBLHIBERNATIONEN, 1, 1)
102 FIELD(GCTL, DSBLCLKGTNG, 0, 1)
103REG32(GPMSTS, 0x14)
104REG32(GSTS, 0x18)
105 FIELD(GSTS, CBELT, 20, 12)
106 FIELD(GSTS, RESERVED_19_12, 12, 8)
107 FIELD(GSTS, SSIC_IP, 11, 1)
108 FIELD(GSTS, OTG_IP, 10, 1)
109 FIELD(GSTS, BC_IP, 9, 1)
110 FIELD(GSTS, ADP_IP, 8, 1)
111 FIELD(GSTS, HOST_IP, 7, 1)
112 FIELD(GSTS, DEVICE_IP, 6, 1)
113 FIELD(GSTS, CSRTIMEOUT, 5, 1)
114 FIELD(GSTS, BUSERRADDRVLD, 4, 1)
115 FIELD(GSTS, RESERVED_3_2, 2, 2)
116 FIELD(GSTS, CURMOD, 0, 2)
117REG32(GUCTL1, 0x1c)
118 FIELD(GUCTL1, RESUME_OPMODE_HS_HOST, 10, 1)
119REG32(GSNPSID, 0x20)
120REG32(GGPIO, 0x24)
121 FIELD(GGPIO, GPO, 16, 16)
122 FIELD(GGPIO, GPI, 0, 16)
123REG32(GUID, 0x28)
124REG32(GUCTL, 0x2c)
125 FIELD(GUCTL, REFCLKPER, 22, 10)
126 FIELD(GUCTL, NOEXTRDL, 21, 1)
127 FIELD(GUCTL, RESERVED_20_18, 18, 3)
128 FIELD(GUCTL, SPRSCTRLTRANSEN, 17, 1)
129 FIELD(GUCTL, RESBWHSEPS, 16, 1)
130 FIELD(GUCTL, RESERVED_15, 15, 1)
131 FIELD(GUCTL, USBHSTINAUTORETRYEN, 14, 1)
132 FIELD(GUCTL, ENOVERLAPCHK, 13, 1)
133 FIELD(GUCTL, EXTCAPSUPPTEN, 12, 1)
134 FIELD(GUCTL, INSRTEXTRFSBODI, 11, 1)
135 FIELD(GUCTL, DTCT, 9, 2)
136 FIELD(GUCTL, DTFT, 0, 9)
137REG32(GBUSERRADDRLO, 0x30)
138REG32(GBUSERRADDRHI, 0x34)
139REG32(GHWPARAMS0, 0x40)
140 FIELD(GHWPARAMS0, GHWPARAMS0_31_24, 24, 8)
141 FIELD(GHWPARAMS0, GHWPARAMS0_23_16, 16, 8)
142 FIELD(GHWPARAMS0, GHWPARAMS0_15_8, 8, 8)
143 FIELD(GHWPARAMS0, GHWPARAMS0_7_6, 6, 2)
144 FIELD(GHWPARAMS0, GHWPARAMS0_5_3, 3, 3)
145 FIELD(GHWPARAMS0, GHWPARAMS0_2_0, 0, 3)
146REG32(GHWPARAMS1, 0x44)
147 FIELD(GHWPARAMS1, GHWPARAMS1_31, 31, 1)
148 FIELD(GHWPARAMS1, GHWPARAMS1_30, 30, 1)
149 FIELD(GHWPARAMS1, GHWPARAMS1_29, 29, 1)
150 FIELD(GHWPARAMS1, GHWPARAMS1_28, 28, 1)
151 FIELD(GHWPARAMS1, GHWPARAMS1_27, 27, 1)
152 FIELD(GHWPARAMS1, GHWPARAMS1_26, 26, 1)
153 FIELD(GHWPARAMS1, GHWPARAMS1_25_24, 24, 2)
154 FIELD(GHWPARAMS1, GHWPARAMS1_23, 23, 1)
155 FIELD(GHWPARAMS1, GHWPARAMS1_22_21, 21, 2)
156 FIELD(GHWPARAMS1, GHWPARAMS1_20_15, 15, 6)
157 FIELD(GHWPARAMS1, GHWPARAMS1_14_12, 12, 3)
158 FIELD(GHWPARAMS1, GHWPARAMS1_11_9, 9, 3)
159 FIELD(GHWPARAMS1, GHWPARAMS1_8_6, 6, 3)
160 FIELD(GHWPARAMS1, GHWPARAMS1_5_3, 3, 3)
161 FIELD(GHWPARAMS1, GHWPARAMS1_2_0, 0, 3)
162REG32(GHWPARAMS2, 0x48)
163REG32(GHWPARAMS3, 0x4c)
164 FIELD(GHWPARAMS3, GHWPARAMS3_31, 31, 1)
165 FIELD(GHWPARAMS3, GHWPARAMS3_30_23, 23, 8)
166 FIELD(GHWPARAMS3, GHWPARAMS3_22_18, 18, 5)
167 FIELD(GHWPARAMS3, GHWPARAMS3_17_12, 12, 6)
168 FIELD(GHWPARAMS3, GHWPARAMS3_11, 11, 1)
169 FIELD(GHWPARAMS3, GHWPARAMS3_10, 10, 1)
170 FIELD(GHWPARAMS3, GHWPARAMS3_9_8, 8, 2)
171 FIELD(GHWPARAMS3, GHWPARAMS3_7_6, 6, 2)
172 FIELD(GHWPARAMS3, GHWPARAMS3_5_4, 4, 2)
173 FIELD(GHWPARAMS3, GHWPARAMS3_3_2, 2, 2)
174 FIELD(GHWPARAMS3, GHWPARAMS3_1_0, 0, 2)
175REG32(GHWPARAMS4, 0x50)
176 FIELD(GHWPARAMS4, GHWPARAMS4_31_28, 28, 4)
177 FIELD(GHWPARAMS4, GHWPARAMS4_27_24, 24, 4)
178 FIELD(GHWPARAMS4, GHWPARAMS4_23, 23, 1)
179 FIELD(GHWPARAMS4, GHWPARAMS4_22, 22, 1)
180 FIELD(GHWPARAMS4, GHWPARAMS4_21, 21, 1)
181 FIELD(GHWPARAMS4, GHWPARAMS4_20_17, 17, 4)
182 FIELD(GHWPARAMS4, GHWPARAMS4_16_13, 13, 4)
183 FIELD(GHWPARAMS4, GHWPARAMS4_12, 12, 1)
184 FIELD(GHWPARAMS4, GHWPARAMS4_11, 11, 1)
185 FIELD(GHWPARAMS4, GHWPARAMS4_10_9, 9, 2)
186 FIELD(GHWPARAMS4, GHWPARAMS4_8_7, 7, 2)
187 FIELD(GHWPARAMS4, GHWPARAMS4_6, 6, 1)
188 FIELD(GHWPARAMS4, GHWPARAMS4_5_0, 0, 6)
189REG32(GHWPARAMS5, 0x54)
190 FIELD(GHWPARAMS5, GHWPARAMS5_31_28, 28, 4)
191 FIELD(GHWPARAMS5, GHWPARAMS5_27_22, 22, 6)
192 FIELD(GHWPARAMS5, GHWPARAMS5_21_16, 16, 6)
193 FIELD(GHWPARAMS5, GHWPARAMS5_15_10, 10, 6)
194 FIELD(GHWPARAMS5, GHWPARAMS5_9_4, 4, 6)
195 FIELD(GHWPARAMS5, GHWPARAMS5_3_0, 0, 4)
196REG32(GHWPARAMS6, 0x58)
197 FIELD(GHWPARAMS6, GHWPARAMS6_31_16, 16, 16)
198 FIELD(GHWPARAMS6, BUSFLTRSSUPPORT, 15, 1)
199 FIELD(GHWPARAMS6, BCSUPPORT, 14, 1)
200 FIELD(GHWPARAMS6, OTG_SS_SUPPORT, 13, 1)
201 FIELD(GHWPARAMS6, ADPSUPPORT, 12, 1)
202 FIELD(GHWPARAMS6, HNPSUPPORT, 11, 1)
203 FIELD(GHWPARAMS6, SRPSUPPORT, 10, 1)
204 FIELD(GHWPARAMS6, GHWPARAMS6_9_8, 8, 2)
205 FIELD(GHWPARAMS6, GHWPARAMS6_7, 7, 1)
206 FIELD(GHWPARAMS6, GHWPARAMS6_6, 6, 1)
207 FIELD(GHWPARAMS6, GHWPARAMS6_5_0, 0, 6)
208REG32(GHWPARAMS7, 0x5c)
209 FIELD(GHWPARAMS7, GHWPARAMS7_31_16, 16, 16)
210 FIELD(GHWPARAMS7, GHWPARAMS7_15_0, 0, 16)
211REG32(GDBGFIFOSPACE, 0x60)
212 FIELD(GDBGFIFOSPACE, SPACE_AVAILABLE, 16, 16)
213 FIELD(GDBGFIFOSPACE, RESERVED_15_9, 9, 7)
214 FIELD(GDBGFIFOSPACE, FIFO_QUEUE_SELECT, 0, 9)
215REG32(GUCTL2, 0x9c)
216 FIELD(GUCTL2, RESERVED_31_26, 26, 6)
217 FIELD(GUCTL2, EN_HP_PM_TIMER, 19, 7)
218 FIELD(GUCTL2, NOLOWPWRDUR, 15, 4)
219 FIELD(GUCTL2, RST_ACTBITLATER, 14, 1)
220 FIELD(GUCTL2, RESERVED_13, 13, 1)
221 FIELD(GUCTL2, DISABLECFC, 11, 1)
222REG32(GUSB2PHYCFG, 0x100)
223 FIELD(GUSB2PHYCFG, U2_FREECLK_EXISTS, 30, 1)
224 FIELD(GUSB2PHYCFG, ULPI_LPM_WITH_OPMODE_CHK, 29, 1)
225 FIELD(GUSB2PHYCFG, RESERVED_25, 25, 1)
226 FIELD(GUSB2PHYCFG, LSTRD, 22, 3)
227 FIELD(GUSB2PHYCFG, LSIPD, 19, 3)
228 FIELD(GUSB2PHYCFG, ULPIEXTVBUSINDIACTOR, 18, 1)
229 FIELD(GUSB2PHYCFG, ULPIEXTVBUSDRV, 17, 1)
230 FIELD(GUSB2PHYCFG, RESERVED_16, 16, 1)
231 FIELD(GUSB2PHYCFG, ULPIAUTORES, 15, 1)
232 FIELD(GUSB2PHYCFG, RESERVED_14, 14, 1)
233 FIELD(GUSB2PHYCFG, USBTRDTIM, 10, 4)
234 FIELD(GUSB2PHYCFG, XCVRDLY, 9, 1)
235 FIELD(GUSB2PHYCFG, ENBLSLPM, 8, 1)
236 FIELD(GUSB2PHYCFG, PHYSEL, 7, 1)
237 FIELD(GUSB2PHYCFG, SUSPENDUSB20, 6, 1)
238 FIELD(GUSB2PHYCFG, FSINTF, 5, 1)
239 FIELD(GUSB2PHYCFG, ULPI_UTMI_SEL, 4, 1)
240 FIELD(GUSB2PHYCFG, PHYIF, 3, 1)
241 FIELD(GUSB2PHYCFG, TOUTCAL, 0, 3)
242REG32(GUSB2I2CCTL, 0x140)
243REG32(GUSB2PHYACC_ULPI, 0x180)
244 FIELD(GUSB2PHYACC_ULPI, RESERVED_31_27, 27, 5)
245 FIELD(GUSB2PHYACC_ULPI, DISUIPIDRVR, 26, 1)
246 FIELD(GUSB2PHYACC_ULPI, NEWREGREQ, 25, 1)
247 FIELD(GUSB2PHYACC_ULPI, VSTSDONE, 24, 1)
248 FIELD(GUSB2PHYACC_ULPI, VSTSBSY, 23, 1)
249 FIELD(GUSB2PHYACC_ULPI, REGWR, 22, 1)
250 FIELD(GUSB2PHYACC_ULPI, REGADDR, 16, 6)
251 FIELD(GUSB2PHYACC_ULPI, EXTREGADDR, 8, 8)
252 FIELD(GUSB2PHYACC_ULPI, REGDATA, 0, 8)
253REG32(GTXFIFOSIZ0, 0x200)
254 FIELD(GTXFIFOSIZ0, TXFSTADDR_N, 16, 16)
255 FIELD(GTXFIFOSIZ0, TXFDEP_N, 0, 16)
256REG32(GTXFIFOSIZ1, 0x204)
257 FIELD(GTXFIFOSIZ1, TXFSTADDR_N, 16, 16)
258 FIELD(GTXFIFOSIZ1, TXFDEP_N, 0, 16)
259REG32(GTXFIFOSIZ2, 0x208)
260 FIELD(GTXFIFOSIZ2, TXFSTADDR_N, 16, 16)
261 FIELD(GTXFIFOSIZ2, TXFDEP_N, 0, 16)
262REG32(GTXFIFOSIZ3, 0x20c)
263 FIELD(GTXFIFOSIZ3, TXFSTADDR_N, 16, 16)
264 FIELD(GTXFIFOSIZ3, TXFDEP_N, 0, 16)
265REG32(GTXFIFOSIZ4, 0x210)
266 FIELD(GTXFIFOSIZ4, TXFSTADDR_N, 16, 16)
267 FIELD(GTXFIFOSIZ4, TXFDEP_N, 0, 16)
268REG32(GTXFIFOSIZ5, 0x214)
269 FIELD(GTXFIFOSIZ5, TXFSTADDR_N, 16, 16)
270 FIELD(GTXFIFOSIZ5, TXFDEP_N, 0, 16)
271REG32(GRXFIFOSIZ0, 0x280)
272 FIELD(GRXFIFOSIZ0, RXFSTADDR_N, 16, 16)
273 FIELD(GRXFIFOSIZ0, RXFDEP_N, 0, 16)
274REG32(GRXFIFOSIZ1, 0x284)
275 FIELD(GRXFIFOSIZ1, RXFSTADDR_N, 16, 16)
276 FIELD(GRXFIFOSIZ1, RXFDEP_N, 0, 16)
277REG32(GRXFIFOSIZ2, 0x288)
278 FIELD(GRXFIFOSIZ2, RXFSTADDR_N, 16, 16)
279 FIELD(GRXFIFOSIZ2, RXFDEP_N, 0, 16)
280REG32(GEVNTADRLO_0, 0x300)
281REG32(GEVNTADRHI_0, 0x304)
282REG32(GEVNTSIZ_0, 0x308)
283 FIELD(GEVNTSIZ_0, EVNTINTRPTMASK, 31, 1)
284 FIELD(GEVNTSIZ_0, RESERVED_30_16, 16, 15)
285 FIELD(GEVNTSIZ_0, EVENTSIZ, 0, 16)
286REG32(GEVNTCOUNT_0, 0x30c)
287 FIELD(GEVNTCOUNT_0, EVNT_HANDLER_BUSY, 31, 1)
288 FIELD(GEVNTCOUNT_0, RESERVED_30_16, 16, 15)
289 FIELD(GEVNTCOUNT_0, EVNTCOUNT, 0, 16)
290REG32(GEVNTADRLO_1, 0x310)
291REG32(GEVNTADRHI_1, 0x314)
292REG32(GEVNTSIZ_1, 0x318)
293 FIELD(GEVNTSIZ_1, EVNTINTRPTMASK, 31, 1)
294 FIELD(GEVNTSIZ_1, RESERVED_30_16, 16, 15)
295 FIELD(GEVNTSIZ_1, EVENTSIZ, 0, 16)
296REG32(GEVNTCOUNT_1, 0x31c)
297 FIELD(GEVNTCOUNT_1, EVNT_HANDLER_BUSY, 31, 1)
298 FIELD(GEVNTCOUNT_1, RESERVED_30_16, 16, 15)
299 FIELD(GEVNTCOUNT_1, EVNTCOUNT, 0, 16)
300REG32(GEVNTADRLO_2, 0x320)
301REG32(GEVNTADRHI_2, 0x324)
302REG32(GEVNTSIZ_2, 0x328)
303 FIELD(GEVNTSIZ_2, EVNTINTRPTMASK, 31, 1)
304 FIELD(GEVNTSIZ_2, RESERVED_30_16, 16, 15)
305 FIELD(GEVNTSIZ_2, EVENTSIZ, 0, 16)
306REG32(GEVNTCOUNT_2, 0x32c)
307 FIELD(GEVNTCOUNT_2, EVNT_HANDLER_BUSY, 31, 1)
308 FIELD(GEVNTCOUNT_2, RESERVED_30_16, 16, 15)
309 FIELD(GEVNTCOUNT_2, EVNTCOUNT, 0, 16)
310REG32(GEVNTADRLO_3, 0x330)
311REG32(GEVNTADRHI_3, 0x334)
312REG32(GEVNTSIZ_3, 0x338)
313 FIELD(GEVNTSIZ_3, EVNTINTRPTMASK, 31, 1)
314 FIELD(GEVNTSIZ_3, RESERVED_30_16, 16, 15)
315 FIELD(GEVNTSIZ_3, EVENTSIZ, 0, 16)
316REG32(GEVNTCOUNT_3, 0x33c)
317 FIELD(GEVNTCOUNT_3, EVNT_HANDLER_BUSY, 31, 1)
318 FIELD(GEVNTCOUNT_3, RESERVED_30_16, 16, 15)
319 FIELD(GEVNTCOUNT_3, EVNTCOUNT, 0, 16)
320REG32(GHWPARAMS8, 0x500)
321REG32(GTXFIFOPRIDEV, 0x510)
322 FIELD(GTXFIFOPRIDEV, RESERVED_31_N, 6, 26)
323 FIELD(GTXFIFOPRIDEV, GTXFIFOPRIDEV, 0, 6)
324REG32(GTXFIFOPRIHST, 0x518)
325 FIELD(GTXFIFOPRIHST, RESERVED_31_16, 3, 29)
326 FIELD(GTXFIFOPRIHST, GTXFIFOPRIHST, 0, 3)
327REG32(GRXFIFOPRIHST, 0x51c)
328 FIELD(GRXFIFOPRIHST, RESERVED_31_16, 3, 29)
329 FIELD(GRXFIFOPRIHST, GRXFIFOPRIHST, 0, 3)
330REG32(GDMAHLRATIO, 0x524)
331 FIELD(GDMAHLRATIO, RESERVED_31_13, 13, 19)
332 FIELD(GDMAHLRATIO, HSTRXFIFO, 8, 5)
333 FIELD(GDMAHLRATIO, RESERVED_7_5, 5, 3)
334 FIELD(GDMAHLRATIO, HSTTXFIFO, 0, 5)
335REG32(GFLADJ, 0x530)
336 FIELD(GFLADJ, GFLADJ_REFCLK_240MHZDECR_PLS1, 31, 1)
337 FIELD(GFLADJ, GFLADJ_REFCLK_240MHZ_DECR, 24, 7)
338 FIELD(GFLADJ, GFLADJ_REFCLK_LPM_SEL, 23, 1)
339 FIELD(GFLADJ, RESERVED_22, 22, 1)
340 FIELD(GFLADJ, GFLADJ_REFCLK_FLADJ, 8, 14)
341 FIELD(GFLADJ, GFLADJ_30MHZ_SDBND_SEL, 7, 1)
342 FIELD(GFLADJ, GFLADJ_30MHZ, 0, 6)
343
344static void reset_csr(USBDWC3 *s)
345{
346 int i = 0;
347
348
349
350
351
352 for (i = 0; i < R_GCTL; i++) {
353 register_reset(&s->regs_info[i]);
354 }
355
356 for (i = R_GCTL; i < R_GBUSERRADDRLO; i++) {
357 if (i == R_GUCTL1 || i == R_GPMSTS) {
358 register_reset(&s->regs_info[i]);
359 } else {
360 continue;
361 }
362 }
363
364 for (i = R_GBUSERRADDRLO; i < USB_DWC3_R_MAX; i++) {
365 register_reset(&s->regs_info[i]);
366 }
367
368 xhci_sysbus_reset(DEVICE(s));
369}
370
371static void usb_dwc3_gctl_postw(RegisterInfo *reg, uint64_t val64)
372{
373 USBDWC3 *s = USB_DWC3(reg->opaque);
374
375 if (ARRAY_FIELD_EX32(s->regs, GCTL, CORESOFTRESET)) {
376 reset_csr(s);
377 }
378}
379
380static void usb_dwc3_guid_postw(RegisterInfo *reg, uint64_t val64)
381{
382 USBDWC3 *s = USB_DWC3(reg->opaque);
383
384 s->regs[R_GUID] = s->cfg.dwc_usb3_user;
385}
386
387static const RegisterAccessInfo usb_dwc3_regs_info[] = {
388 { .name = "GSBUSCFG0", .addr = A_GSBUSCFG0,
389 .ro = 0xf300,
390 },{ .name = "GSBUSCFG1", .addr = A_GSBUSCFG1,
391 .reset = 0x300,
392 .ro = 0xffffe0ff,
393 },{ .name = "GTXTHRCFG", .addr = A_GTXTHRCFG,
394 .ro = 0xd000ffff,
395 },{ .name = "GRXTHRCFG", .addr = A_GRXTHRCFG,
396 .ro = 0xd007e000,
397 },{ .name = "GCTL", .addr = A_GCTL,
398 .reset = 0x30c13004, .post_write = usb_dwc3_gctl_postw,
399 },{ .name = "GPMSTS", .addr = A_GPMSTS,
400 .ro = 0xfffffff,
401 },{ .name = "GSTS", .addr = A_GSTS,
402 .reset = 0x7e800000,
403 .ro = 0xffffffcf,
404 .w1c = 0x30,
405 },{ .name = "GUCTL1", .addr = A_GUCTL1,
406 .reset = 0x198a,
407 .ro = 0x7800,
408 },{ .name = "GSNPSID", .addr = A_GSNPSID,
409 .reset = 0x5533330a,
410 .ro = 0xffffffff,
411 },{ .name = "GGPIO", .addr = A_GGPIO,
412 .ro = 0xffff,
413 },{ .name = "GUID", .addr = A_GUID,
414 .reset = 0x12345678, .post_write = usb_dwc3_guid_postw,
415 },{ .name = "GUCTL", .addr = A_GUCTL,
416 .reset = 0x0c808010,
417 .ro = 0x1c8000,
418 },{ .name = "GBUSERRADDRLO", .addr = A_GBUSERRADDRLO,
419 .ro = 0xffffffff,
420 },{ .name = "GBUSERRADDRHI", .addr = A_GBUSERRADDRHI,
421 .ro = 0xffffffff,
422 },{ .name = "GHWPARAMS0", .addr = A_GHWPARAMS0,
423 .reset = 0x4020404a,
424 .ro = 0xffffffff,
425 },{ .name = "GHWPARAMS1", .addr = A_GHWPARAMS1,
426 .reset = 0x222493b,
427 .ro = 0xffffffff,
428 },{ .name = "GHWPARAMS2", .addr = A_GHWPARAMS2,
429 .reset = 0x12345678,
430 .ro = 0xffffffff,
431 },{ .name = "GHWPARAMS3", .addr = A_GHWPARAMS3,
432 .reset = 0x618c088,
433 .ro = 0xffffffff,
434 },{ .name = "GHWPARAMS4", .addr = A_GHWPARAMS4,
435 .reset = 0x47822004,
436 .ro = 0xffffffff,
437 },{ .name = "GHWPARAMS5", .addr = A_GHWPARAMS5,
438 .reset = 0x4202088,
439 .ro = 0xffffffff,
440 },{ .name = "GHWPARAMS6", .addr = A_GHWPARAMS6,
441 .reset = 0x7850c20,
442 .ro = 0xffffffff,
443 },{ .name = "GHWPARAMS7", .addr = A_GHWPARAMS7,
444 .ro = 0xffffffff,
445 },{ .name = "GDBGFIFOSPACE", .addr = A_GDBGFIFOSPACE,
446 .reset = 0xa0000,
447 .ro = 0xfffffe00,
448 },{ .name = "GUCTL2", .addr = A_GUCTL2,
449 .reset = 0x40d,
450 .ro = 0x2000,
451 },{ .name = "GUSB2PHYCFG", .addr = A_GUSB2PHYCFG,
452 .reset = 0x40102410,
453 .ro = 0x1e014030,
454 },{ .name = "GUSB2I2CCTL", .addr = A_GUSB2I2CCTL,
455 .ro = 0xffffffff,
456 },{ .name = "GUSB2PHYACC_ULPI", .addr = A_GUSB2PHYACC_ULPI,
457 .ro = 0xfd000000,
458 },{ .name = "GTXFIFOSIZ0", .addr = A_GTXFIFOSIZ0,
459 .reset = 0x2c7000a,
460 },{ .name = "GTXFIFOSIZ1", .addr = A_GTXFIFOSIZ1,
461 .reset = 0x2d10103,
462 },{ .name = "GTXFIFOSIZ2", .addr = A_GTXFIFOSIZ2,
463 .reset = 0x3d40103,
464 },{ .name = "GTXFIFOSIZ3", .addr = A_GTXFIFOSIZ3,
465 .reset = 0x4d70083,
466 },{ .name = "GTXFIFOSIZ4", .addr = A_GTXFIFOSIZ4,
467 .reset = 0x55a0083,
468 },{ .name = "GTXFIFOSIZ5", .addr = A_GTXFIFOSIZ5,
469 .reset = 0x5dd0083,
470 },{ .name = "GRXFIFOSIZ0", .addr = A_GRXFIFOSIZ0,
471 .reset = 0x1c20105,
472 },{ .name = "GRXFIFOSIZ1", .addr = A_GRXFIFOSIZ1,
473 .reset = 0x2c70000,
474 },{ .name = "GRXFIFOSIZ2", .addr = A_GRXFIFOSIZ2,
475 .reset = 0x2c70000,
476 },{ .name = "GEVNTADRLO_0", .addr = A_GEVNTADRLO_0,
477 },{ .name = "GEVNTADRHI_0", .addr = A_GEVNTADRHI_0,
478 },{ .name = "GEVNTSIZ_0", .addr = A_GEVNTSIZ_0,
479 .ro = 0x7fff0000,
480 },{ .name = "GEVNTCOUNT_0", .addr = A_GEVNTCOUNT_0,
481 .ro = 0x7fff0000,
482 },{ .name = "GEVNTADRLO_1", .addr = A_GEVNTADRLO_1,
483 },{ .name = "GEVNTADRHI_1", .addr = A_GEVNTADRHI_1,
484 },{ .name = "GEVNTSIZ_1", .addr = A_GEVNTSIZ_1,
485 .ro = 0x7fff0000,
486 },{ .name = "GEVNTCOUNT_1", .addr = A_GEVNTCOUNT_1,
487 .ro = 0x7fff0000,
488 },{ .name = "GEVNTADRLO_2", .addr = A_GEVNTADRLO_2,
489 },{ .name = "GEVNTADRHI_2", .addr = A_GEVNTADRHI_2,
490 },{ .name = "GEVNTSIZ_2", .addr = A_GEVNTSIZ_2,
491 .ro = 0x7fff0000,
492 },{ .name = "GEVNTCOUNT_2", .addr = A_GEVNTCOUNT_2,
493 .ro = 0x7fff0000,
494 },{ .name = "GEVNTADRLO_3", .addr = A_GEVNTADRLO_3,
495 },{ .name = "GEVNTADRHI_3", .addr = A_GEVNTADRHI_3,
496 },{ .name = "GEVNTSIZ_3", .addr = A_GEVNTSIZ_3,
497 .ro = 0x7fff0000,
498 },{ .name = "GEVNTCOUNT_3", .addr = A_GEVNTCOUNT_3,
499 .ro = 0x7fff0000,
500 },{ .name = "GHWPARAMS8", .addr = A_GHWPARAMS8,
501 .reset = 0x478,
502 .ro = 0xffffffff,
503 },{ .name = "GTXFIFOPRIDEV", .addr = A_GTXFIFOPRIDEV,
504 .ro = 0xffffffc0,
505 },{ .name = "GTXFIFOPRIHST", .addr = A_GTXFIFOPRIHST,
506 .ro = 0xfffffff8,
507 },{ .name = "GRXFIFOPRIHST", .addr = A_GRXFIFOPRIHST,
508 .ro = 0xfffffff8,
509 },{ .name = "GDMAHLRATIO", .addr = A_GDMAHLRATIO,
510 .ro = 0xffffe0e0,
511 },{ .name = "GFLADJ", .addr = A_GFLADJ,
512 .reset = 0xc83f020,
513 .rsvd = 0x40,
514 .ro = 0x400040,
515 }
516};
517
518static void usb_dwc3_reset(DeviceState *dev)
519{
520 USBDWC3 *s = USB_DWC3(dev);
521 unsigned int i;
522
523 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
524 register_reset(&s->regs_info[i]);
525 }
526 xhci_sysbus_reset(dev);
527}
528
529static const MemoryRegionOps usb_dwc3_ops = {
530 .read = register_read_memory,
531 .write = register_write_memory,
532 .endianness = DEVICE_LITTLE_ENDIAN,
533 .valid = {
534 .min_access_size = 4,
535 .max_access_size = 4,
536 },
537};
538
539static void usb_dwc3_init(Object *obj)
540{
541 USBDWC3 *s = USB_DWC3(obj);
542 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
543 RegisterInfoArray *reg_array;
544 XHCISysbusState *ss = XHCI_SYSBUS(obj);
545
546 memory_region_init(&s->iomem, obj, TYPE_USB_DWC3, USB_DWC3_R_MAX * 4);
547 reg_array =
548 register_init_block32(DEVICE(obj), usb_dwc3_regs_info,
549 ARRAY_SIZE(usb_dwc3_regs_info),
550 s->regs_info, s->regs,
551 &usb_dwc3_ops,
552 USB_DWC3_ERR_DEBUG,
553 USB_DWC3_R_MAX * 4);
554 memory_region_add_subregion(&s->iomem,
555 0x0,
556 ®_array->mem);
557 sysbus_init_mmio(sbd, &s->iomem);
558 s->cfg.mode = HOST_MODE;
559 ss->xhci.numintrs = 4;
560 ss->xhci.numslots = 2;
561}
562
563static Property usb_dwc3_properties[] = {
564 DEFINE_PROP_BOOL("usb2-mode", USBDWC3, cfg.usb2_mode, false),
565 DEFINE_PROP_UINT32("DWC_USB3_USERID", USBDWC3, cfg.dwc_usb3_user,
566 0x12345678),
567 DEFINE_PROP_END_OF_LIST(),
568};
569
570static void usb_dwc3_class_init(ObjectClass *klass, void *data)
571{
572 DeviceClass *dc = DEVICE_CLASS(klass);
573
574 dc->reset = usb_dwc3_reset;
575 device_class_set_props(dc, usb_dwc3_properties);
576}
577
578static const TypeInfo usb_dwc3_info = {
579 .name = TYPE_USB_DWC3,
580 .parent = TYPE_XHCI_SYSBUS,
581 .instance_size = sizeof(USBDWC3),
582 .class_init = usb_dwc3_class_init,
583 .instance_init = usb_dwc3_init,
584};
585
586static void usb_dwc3_register_types(void)
587{
588 type_register_static(&usb_dwc3_info);
589}
590
591type_init(usb_dwc3_register_types)
592
