1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 7 * Copyright (C) 2016 Imagination Technologies 8 * 9 */ 10 11#ifndef MIPS_GIC_H 12#define MIPS_GIC_H 13 14#include "qemu/units.h" 15#include "hw/timer/mips_gictimer.h" 16#include "hw/sysbus.h" 17#include "cpu.h" 18/* 19 * GIC Specific definitions 20 */ 21 22/* The MIPS default location */ 23#define GIC_BASE_ADDR 0x1bdc0000ULL 24#define GIC_ADDRSPACE_SZ (128 * KiB) 25 26/* Constants */ 27#define GIC_POL_POS 1 28#define GIC_POL_NEG 0 29#define GIC_TRIG_EDGE 1 30#define GIC_TRIG_LEVEL 0 31 32#define MSK(n) ((1ULL << (n)) - 1) 33 34/* GIC Address Space */ 35#define SHARED_SECTION_OFS 0x0000 36#define SHARED_SECTION_SIZE 0x8000 37#define VP_LOCAL_SECTION_OFS 0x8000 38#define VP_LOCAL_SECTION_SIZE 0x4000 39#define VP_OTHER_SECTION_OFS 0xc000 40#define VP_OTHER_SECTION_SIZE 0x4000 41#define USM_VISIBLE_SECTION_OFS 0x10000 42#define USM_VISIBLE_SECTION_SIZE 0x10000 43 44/* Register Map for Shared Section */ 45 46#define GIC_SH_CONFIG_OFS 0x0000 47 48/* Shared Global Counter */ 49#define GIC_SH_COUNTERLO_OFS 0x0010 50#define GIC_SH_COUNTERHI_OFS 0x0014 51#define GIC_SH_REVISIONID_OFS 0x0020 52 53/* Set/Clear corresponding bit in Edge Detect Register */ 54#define GIC_SH_WEDGE_OFS 0x0280 55 56/* Reset Mask - Disables Interrupt */ 57#define GIC_SH_RMASK_OFS 0x0300 58#define GIC_SH_RMASK_LAST_OFS 0x031c 59 60/* Set Mask (WO) - Enables Interrupt */ 61#define GIC_SH_SMASK_OFS 0x0380 62#define GIC_SH_SMASK_LAST_OFS 0x039c 63 64/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ 65#define GIC_SH_MASK_OFS 0x0400 66#define GIC_SH_MASK_LAST_OFS 0x041c 67 68/* Pending Global Interrupts (RO) */ 69#define GIC_SH_PEND_OFS 0x0480 70#define GIC_SH_PEND_LAST_OFS 0x049c 71 72#define GIC_SH_MAP0_PIN_OFS 0x0500 73#define GIC_SH_MAP255_PIN_OFS 0x08fc 74 75#define GIC_SH_MAP0_VP_OFS 0x2000 76#define GIC_SH_MAP255_VP_LAST_OFS 0x3fe4 77 78/* Register Map for Local Section */ 79#define GIC_VP_CTL_OFS 0x0000 80#define GIC_VP_PEND_OFS 0x0004 81#define GIC_VP_MASK_OFS 0x0008 82#define GIC_VP_RMASK_OFS 0x000c 83#define GIC_VP_SMASK_OFS 0x0010 84#define GIC_VP_WD_MAP_OFS 0x0040 85#define GIC_VP_COMPARE_MAP_OFS 0x0044 86#define GIC_VP_TIMER_MAP_OFS 0x0048 87#define GIC_VP_FDC_MAP_OFS 0x004c 88#define GIC_VP_PERFCTR_MAP_OFS 0x0050 89#define GIC_VP_SWINT0_MAP_OFS 0x0054 90#define GIC_VP_SWINT1_MAP_OFS 0x0058 91#define GIC_VP_OTHER_ADDR_OFS 0x0080 92#define GIC_VP_IDENT_OFS 0x0088 93#define GIC_VP_WD_CONFIG0_OFS 0x0090 94#define GIC_VP_WD_COUNT0_OFS 0x0094 95#define GIC_VP_WD_INITIAL0_OFS 0x0098 96#define GIC_VP_COMPARE_LO_OFS 0x00a0 97#define GIC_VP_COMPARE_HI_OFS 0x00a4 98#define GIC_VL_BRK_GROUP 0x3080 99 100/* User-Mode Visible Section Register */ 101/* Read-only alias for GIC Shared CounterLo */ 102#define GIC_USER_MODE_COUNTERLO 0x0000 103/* Read-only alias for GIC Shared CounterHi */ 104#define GIC_USER_MODE_COUNTERHI 0x0004 105 106/* Masks */ 107#define GIC_SH_CONFIG_COUNTSTOP_SHF 28 108#define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) 109#define GIC_SH_CONFIG_COUNTBITS_SHF 24 110#define GIC_SH_CONFIG_COUNTBITS_MSK (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF) 111#define GIC_SH_CONFIG_NUMINTRS_SHF 16 112#define GIC_SH_CONFIG_NUMINTRS_MSK (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF) 113#define GIC_SH_CONFIG_PVPS_SHF 0 114#define GIC_SH_CONFIG_PVPS_MSK (MSK(8) << GIC_SH_CONFIG_NUMVPS_SHF) 115 116#define GIC_SH_WEDGE_RW_SHF 31 117#define GIC_SH_WEDGE_RW_MSK (MSK(1) << GIC_SH_WEDGE_RW_SHF) 118 119#define GIC_MAP_TO_PIN_SHF 31 120#define GIC_MAP_TO_PIN_MSK (MSK(1) << GIC_MAP_TO_PIN_SHF) 121#define GIC_MAP_TO_NMI_SHF 30 122#define GIC_MAP_TO_NMI_MSK (MSK(1) << GIC_MAP_TO_NMI_SHF) 123#define GIC_MAP_TO_YQ_SHF 29 124#define GIC_MAP_TO_YQ_MSK (MSK(1) << GIC_MAP_TO_YQ_SHF) 125#define GIC_MAP_SHF 0 126#define GIC_MAP_MSK (MSK(6) << GIC_MAP_SHF) 127#define GIC_MAP_TO_PIN_REG_MSK \ 128 (GIC_MAP_TO_PIN_MSK | GIC_MAP_TO_NMI_MSK | GIC_MAP_TO_YQ_MSK | GIC_MAP_MSK) 129 130/* GIC_VP_CTL Masks */ 131#define GIC_VP_CTL_FDC_RTBL_SHF 4 132#define GIC_VP_CTL_FDC_RTBL_MSK (MSK(1) << GIC_VP_CTL_FDC_RTBL_SHF) 133#define GIC_VP_CTL_SWINT_RTBL_SHF 3 134#define GIC_VP_CTL_SWINT_RTBL_MSK (MSK(1) << GIC_VP_CTL_SWINT_RTBL_SHF) 135#define GIC_VP_CTL_PERFCNT_RTBL_SHF 2 136#define GIC_VP_CTL_PERFCNT_RTBL_MSK (MSK(1) << GIC_VP_CTL_PERFCNT_RTBL_SHF) 137#define GIC_VP_CTL_TIMER_RTBL_SHF 1 138#define GIC_VP_CTL_TIMER_RTBL_MSK (MSK(1) << GIC_VP_CTL_TIMER_RTBL_SHF) 139#define GIC_VP_CTL_EIC_MODE_SHF 0 140#define GIC_VP_CTL_EIC_MODE_MSK (MSK(1) << GIC_VP_CTL_EIC_MODE_SHF) 141 142/* GIC_VP_MASK Masks */ 143#define GIC_VP_MASK_FDC_SHF 6 144#define GIC_VP_MASK_FDC_MSK (MSK(1) << GIC_VP_MASK_FDC_SHF) 145#define GIC_VP_MASK_SWINT1_SHF 5 146#define GIC_VP_MASK_SWINT1_MSK (MSK(1) << GIC_VP_MASK_SWINT1_SHF) 147#define GIC_VP_MASK_SWINT0_SHF 4 148#define GIC_VP_MASK_SWINT0_MSK (MSK(1) << GIC_VP_MASK_SWINT0_SHF) 149#define GIC_VP_MASK_PERFCNT_SHF 3 150#define GIC_VP_MASK_PERFCNT_MSK (MSK(1) << GIC_VP_MASK_PERFCNT_SHF) 151#define GIC_VP_MASK_TIMER_SHF 2 152#define GIC_VP_MASK_TIMER_MSK (MSK(1) << GIC_VP_MASK_TIMER_SHF) 153#define GIC_VP_MASK_CMP_SHF 1 154#define GIC_VP_MASK_CMP_MSK (MSK(1) << GIC_VP_MASK_CMP_SHF) 155#define GIC_VP_MASK_WD_SHF 0 156#define GIC_VP_MASK_WD_MSK (MSK(1) << GIC_VP_MASK_WD_SHF) 157#define GIC_VP_SET_RESET_MSK (MSK(7) << GIC_VP_MASK_WD_SHF) 158 159#define GIC_CPU_INT_MAX 5 /* Core Interrupt 7 */ 160#define GIC_CPU_PIN_OFFSET 2 161 162/* Local GIC interrupts. */ 163#define GIC_NUM_LOCAL_INTRS 7 164#define GIC_LOCAL_INT_FDC 6 /* CPU fast debug channel */ 165#define GIC_LOCAL_INT_SWINT1 5 /* CPU software interrupt 1 */ 166#define GIC_LOCAL_INT_SWINT0 4 /* CPU software interrupt 0 */ 167#define GIC_LOCAL_INT_PERFCTR 3 /* CPU performance counter */ 168#define GIC_LOCAL_INT_TIMER 2 /* CPU timer interrupt */ 169#define GIC_LOCAL_INT_COMPARE 1 /* GIC count and compare timer */ 170#define GIC_LOCAL_INT_WD 0 /* GIC watchdog */ 171 172#define TYPE_MIPS_GIC "mips-gic" 173#define MIPS_GIC(obj) OBJECT_CHECK(MIPSGICState, (obj), TYPE_MIPS_GIC) 174 175/* Support up to 32 VPs and 256 IRQs */ 176#define GIC_MAX_VPS 32 177#define GIC_MAX_INTRS 256 178 179typedef struct MIPSGICState MIPSGICState; 180typedef struct MIPSGICIRQState MIPSGICIRQState; 181typedef struct MIPSGICVPState MIPSGICVPState; 182 183struct MIPSGICIRQState { 184 uint8_t enabled; 185 uint8_t pending; 186 uint32_t map_pin; 187 int32_t map_vp; 188 qemu_irq irq; 189}; 190 191struct MIPSGICVPState { 192 uint32_t ctl; 193 uint32_t pend; 194 uint32_t mask; 195 uint32_t compare_map; 196 uint32_t other_addr; 197 CPUMIPSState *env; 198}; 199 200struct MIPSGICState { 201 SysBusDevice parent_obj; 202 MemoryRegion mr; 203 204 /* Shared Section Registers */ 205 uint32_t sh_config; 206 MIPSGICIRQState *irq_state; 207 208 /* VP Local/Other Section Registers */ 209 MIPSGICVPState *vps; 210 211 /* GIC VP Timer */ 212 MIPSGICTimerState *gic_timer; 213 214 int32_t num_vps; 215 int32_t num_irq; 216}; 217 218#endif /* MIPS_GIC_H */ 219