LXR qemu/include/hw/misc/iomem-cache.h

   1/*
   2 * Copyright (c) 2020 Xilinx Inc.
   3 *
   4 * Written by Francisco Iglesias <francisco.iglesias@xilinx.com>
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24#ifndef XLNX_IOMEM_CACHE_H
  25#define XLNX_IOMEM_CACHE_H
  26
  27#include "hw/sysbus.h"
  28#include "hw/core/cpu.h"
  29#include "hw/ptimer.h"
  30
  31#define TYPE_IOMEM_CACHE "iomem-cache"
  32#define TYPE_IOMEM_CACHE_IOMMU \
  33        "iomem-cache-iommu-memory-region"
  34
  35#define IOMEM_CACHE(obj) \
  36        OBJECT_CHECK(IOMemCache, (obj), TYPE_IOMEM_CACHE)
  37#define IOMEM_CACHE_PARENT_CLASS \
  38    object_class_get_parent(object_class_by_name(TYPE_IOMEM_CACHE))
  39
  40#define MAX_CPU_INDEX 20
  41
  42typedef struct CacheLine {
  43    bool valid;
  44    IOMMUTLBEntry iotlb;
  45    int line_idx;
  46    uint8_t *data;
  47} CacheLine;
  48
  49typedef struct IOMemCacheWrBuf {
  50    uint8_t data[8 * KiB];
  51    hwaddr start;
  52    hwaddr len;
  53    hwaddr max_len;
  54    ptimer_state *timer;
  55    QemuMutex mutex;
  56} IOMemCacheWrBuf;
  57
  58typedef struct IOMemCache IOMemCache;
  59
  60typedef struct IOMemCacheRegion {
  61    IOMemCache *parent;
  62
  63    IOMMUMemoryRegion iommu;
  64
  65    uint64_t offset;
  66} IOMemCacheRegion;
  67
  68typedef struct IOMemCache {
  69    SysBusDevice parent_obj;
  70
  71    IOMemCacheRegion *region;
  72
  73    /* RAM address space and memory region (for cached acceses) */
  74    AddressSpace as_ram;
  75    MemoryRegion mr_ram;
  76    uint8_t *ram_ptr;
  77
  78    /* Uncached address space and memory region */
  79    AddressSpace down_as_uncached;
  80    MemoryRegion down_mr_uncached;
  81
  82    /* DMA address space and memory region */
  83    AddressSpace down_as;
  84    MemoryRegion *down_mr;
  85
  86    /* Cache */
  87    struct {
  88        CacheLine *line;
  89
  90        /* Track allocated */
  91        GHashTable *table;
  92
  93        uint32_t num_lines;
  94        uint32_t line_size;
  95
  96        uint32_t num_allocated;
  97        uint32_t max_allocated;
  98    } cache;
  99
 100    /* Per CPU cache line tracking */
 101    struct {
 102        GHashTable *table;
 103    } cpu_cache[MAX_CPU_INDEX];
 104
 105    QemuMutex mutex;
 106
 107    /* Write buffer */
 108    IOMemCacheWrBuf wbuf;
 109
 110    struct {
 111        uint32_t cache_size;
 112        uint32_t line_size;
 113
 114        /* If set all memory will be treated as cacheable. */
 115        bool cache_all;
 116    } cfg;
 117
 118} IOMemCache;
 119
 120void cpu_clean_inv_one(CPUState *cpu, run_on_cpu_data d);
 121void tlb_flush(CPUState *cpu);
 122
 123#endif
 124