1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#include "qemu/osdep.h"
21#include "qemu/main-loop.h"
22#include "cpu.h"
23#include "exec/helper-proto.h"
24#include "exec/exec-all.h"
25#include "exec/cpu_ldst.h"
26#include "exec/address-spaces.h"
27
28void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
29{
30#ifdef CONFIG_USER_ONLY
31 fprintf(stderr, "outb: port=0x%04x, data=%02x\n", port, data);
32#else
33 address_space_stb(&address_space_io, port, data,
34 cpu_get_mem_attrs(env), NULL);
35#endif
36}
37
38target_ulong helper_inb(CPUX86State *env, uint32_t port)
39{
40#ifdef CONFIG_USER_ONLY
41 fprintf(stderr, "inb: port=0x%04x\n", port);
42 return 0;
43#else
44 return address_space_ldub(&address_space_io, port,
45 cpu_get_mem_attrs(env), NULL);
46#endif
47}
48
49void helper_outw(CPUX86State *env, uint32_t port, uint32_t data)
50{
51#ifdef CONFIG_USER_ONLY
52 fprintf(stderr, "outw: port=0x%04x, data=%04x\n", port, data);
53#else
54 address_space_stw(&address_space_io, port, data,
55 cpu_get_mem_attrs(env), NULL);
56#endif
57}
58
59target_ulong helper_inw(CPUX86State *env, uint32_t port)
60{
61#ifdef CONFIG_USER_ONLY
62 fprintf(stderr, "inw: port=0x%04x\n", port);
63 return 0;
64#else
65 return address_space_lduw(&address_space_io, port,
66 cpu_get_mem_attrs(env), NULL);
67#endif
68}
69
70void helper_outl(CPUX86State *env, uint32_t port, uint32_t data)
71{
72#ifdef CONFIG_USER_ONLY
73 fprintf(stderr, "outl: port=0x%04x, data=%08x\n", port, data);
74#else
75 address_space_stl(&address_space_io, port, data,
76 cpu_get_mem_attrs(env), NULL);
77#endif
78}
79
80target_ulong helper_inl(CPUX86State *env, uint32_t port)
81{
82#ifdef CONFIG_USER_ONLY
83 fprintf(stderr, "inl: port=0x%04x\n", port);
84 return 0;
85#else
86 return address_space_ldl(&address_space_io, port,
87 cpu_get_mem_attrs(env), NULL);
88#endif
89}
90
91void helper_into(CPUX86State *env, int next_eip_addend)
92{
93 int eflags;
94
95 eflags = cpu_cc_compute_all(env, CC_OP);
96 if (eflags & CC_O) {
97 raise_interrupt(env, EXCP04_INTO, 1, 0, next_eip_addend);
98 }
99}
100
101void helper_cpuid(CPUX86State *env)
102{
103 uint32_t eax, ebx, ecx, edx;
104
105 cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0, GETPC());
106
107 cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX],
108 &eax, &ebx, &ecx, &edx);
109 env->regs[R_EAX] = eax;
110 env->regs[R_EBX] = ebx;
111 env->regs[R_ECX] = ecx;
112 env->regs[R_EDX] = edx;
113}
114
115#if defined(CONFIG_USER_ONLY)
116target_ulong helper_read_crN(CPUX86State *env, int reg)
117{
118 return 0;
119}
120
121void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
122{
123}
124#else
125target_ulong helper_read_crN(CPUX86State *env, int reg)
126{
127 target_ulong val;
128
129 cpu_svm_check_intercept_param(env, SVM_EXIT_READ_CR0 + reg, 0, GETPC());
130 switch (reg) {
131 default:
132 val = env->cr[reg];
133 break;
134 case 8:
135 if (!(env->hflags2 & HF2_VINTR_MASK)) {
136 val = cpu_get_apic_tpr(env_archcpu(env)->apic_state);
137 } else {
138 val = env->v_tpr;
139 }
140 break;
141 }
142 return val;
143}
144
145void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
146{
147 cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0, GETPC());
148 switch (reg) {
149 case 0:
150 cpu_x86_update_cr0(env, t0);
151 break;
152 case 3:
153 cpu_x86_update_cr3(env, t0);
154 break;
155 case 4:
156 cpu_x86_update_cr4(env, t0);
157 break;
158 case 8:
159 if (!(env->hflags2 & HF2_VINTR_MASK)) {
160 qemu_mutex_lock_iothread();
161 cpu_set_apic_tpr(env_archcpu(env)->apic_state, t0);
162 qemu_mutex_unlock_iothread();
163 }
164 env->v_tpr = t0 & 0x0f;
165 break;
166 default:
167 env->cr[reg] = t0;
168 break;
169 }
170}
171#endif
172
173void helper_lmsw(CPUX86State *env, target_ulong t0)
174{
175
176
177 t0 = (env->cr[0] & ~0xe) | (t0 & 0xf);
178 helper_write_crN(env, 0, t0);
179}
180
181void helper_invlpg(CPUX86State *env, target_ulong addr)
182{
183 X86CPU *cpu = env_archcpu(env);
184
185 cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0, GETPC());
186 tlb_flush_page(CPU(cpu), addr);
187}
188
189void helper_rdtsc(CPUX86State *env)
190{
191 uint64_t val;
192
193 if ((env->cr[4] & CR4_TSD_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
194 raise_exception_ra(env, EXCP0D_GPF, GETPC());
195 }
196 cpu_svm_check_intercept_param(env, SVM_EXIT_RDTSC, 0, GETPC());
197
198 val = cpu_get_tsc(env) + env->tsc_offset;
199 env->regs[R_EAX] = (uint32_t)(val);
200 env->regs[R_EDX] = (uint32_t)(val >> 32);
201}
202
203void helper_rdtscp(CPUX86State *env)
204{
205 helper_rdtsc(env);
206 env->regs[R_ECX] = (uint32_t)(env->tsc_aux);
207}
208
209void helper_rdpmc(CPUX86State *env)
210{
211 if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) {
212 raise_exception_ra(env, EXCP0D_GPF, GETPC());
213 }
214 cpu_svm_check_intercept_param(env, SVM_EXIT_RDPMC, 0, GETPC());
215
216
217 qemu_log_mask(LOG_UNIMP, "x86: unimplemented rdpmc\n");
218 raise_exception_err(env, EXCP06_ILLOP, 0);
219}
220
221#if defined(CONFIG_USER_ONLY)
222void helper_wrmsr(CPUX86State *env)
223{
224}
225
226void helper_rdmsr(CPUX86State *env)
227{
228}
229#else
230void helper_wrmsr(CPUX86State *env)
231{
232 uint64_t val;
233
234 cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC());
235
236 val = ((uint32_t)env->regs[R_EAX]) |
237 ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
238
239 switch ((uint32_t)env->regs[R_ECX]) {
240 case MSR_IA32_SYSENTER_CS:
241 env->sysenter_cs = val & 0xffff;
242 break;
243 case MSR_IA32_SYSENTER_ESP:
244 env->sysenter_esp = val;
245 break;
246 case MSR_IA32_SYSENTER_EIP:
247 env->sysenter_eip = val;
248 break;
249 case MSR_IA32_APICBASE:
250 cpu_set_apic_base(env_archcpu(env)->apic_state, val);
251 break;
252 case MSR_EFER:
253 {
254 uint64_t update_mask;
255
256 update_mask = 0;
257 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_SYSCALL) {
258 update_mask |= MSR_EFER_SCE;
259 }
260 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
261 update_mask |= MSR_EFER_LME;
262 }
263 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
264 update_mask |= MSR_EFER_FFXSR;
265 }
266 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_NX) {
267 update_mask |= MSR_EFER_NXE;
268 }
269 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
270 update_mask |= MSR_EFER_SVME;
271 }
272 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_FFXSR) {
273 update_mask |= MSR_EFER_FFXSR;
274 }
275 cpu_load_efer(env, (env->efer & ~update_mask) |
276 (val & update_mask));
277 }
278 break;
279 case MSR_STAR:
280 env->star = val;
281 break;
282 case MSR_PAT:
283 env->pat = val;
284 break;
285 case MSR_VM_HSAVE_PA:
286 env->vm_hsave = val;
287 break;
288#ifdef TARGET_X86_64
289 case MSR_LSTAR:
290 env->lstar = val;
291 break;
292 case MSR_CSTAR:
293 env->cstar = val;
294 break;
295 case MSR_FMASK:
296 env->fmask = val;
297 break;
298 case MSR_FSBASE:
299 env->segs[R_FS].base = val;
300 break;
301 case MSR_GSBASE:
302 env->segs[R_GS].base = val;
303 break;
304 case MSR_KERNELGSBASE:
305 env->kernelgsbase = val;
306 break;
307#endif
308 case MSR_MTRRphysBase(0):
309 case MSR_MTRRphysBase(1):
310 case MSR_MTRRphysBase(2):
311 case MSR_MTRRphysBase(3):
312 case MSR_MTRRphysBase(4):
313 case MSR_MTRRphysBase(5):
314 case MSR_MTRRphysBase(6):
315 case MSR_MTRRphysBase(7):
316 env->mtrr_var[((uint32_t)env->regs[R_ECX] -
317 MSR_MTRRphysBase(0)) / 2].base = val;
318 break;
319 case MSR_MTRRphysMask(0):
320 case MSR_MTRRphysMask(1):
321 case MSR_MTRRphysMask(2):
322 case MSR_MTRRphysMask(3):
323 case MSR_MTRRphysMask(4):
324 case MSR_MTRRphysMask(5):
325 case MSR_MTRRphysMask(6):
326 case MSR_MTRRphysMask(7):
327 env->mtrr_var[((uint32_t)env->regs[R_ECX] -
328 MSR_MTRRphysMask(0)) / 2].mask = val;
329 break;
330 case MSR_MTRRfix64K_00000:
331 env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
332 MSR_MTRRfix64K_00000] = val;
333 break;
334 case MSR_MTRRfix16K_80000:
335 case MSR_MTRRfix16K_A0000:
336 env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
337 MSR_MTRRfix16K_80000 + 1] = val;
338 break;
339 case MSR_MTRRfix4K_C0000:
340 case MSR_MTRRfix4K_C8000:
341 case MSR_MTRRfix4K_D0000:
342 case MSR_MTRRfix4K_D8000:
343 case MSR_MTRRfix4K_E0000:
344 case MSR_MTRRfix4K_E8000:
345 case MSR_MTRRfix4K_F0000:
346 case MSR_MTRRfix4K_F8000:
347 env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
348 MSR_MTRRfix4K_C0000 + 3] = val;
349 break;
350 case MSR_MTRRdefType:
351 env->mtrr_deftype = val;
352 break;
353 case MSR_MCG_STATUS:
354 env->mcg_status = val;
355 break;
356 case MSR_MCG_CTL:
357 if ((env->mcg_cap & MCG_CTL_P)
358 && (val == 0 || val == ~(uint64_t)0)) {
359 env->mcg_ctl = val;
360 }
361 break;
362 case MSR_TSC_AUX:
363 env->tsc_aux = val;
364 break;
365 case MSR_IA32_MISC_ENABLE:
366 env->msr_ia32_misc_enable = val;
367 break;
368 case MSR_IA32_BNDCFGS:
369
370
371 env->msr_bndcfgs = val;
372 cpu_sync_bndcs_hflags(env);
373 break;
374 default:
375 if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
376 && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
377 (4 * env->mcg_cap & 0xff)) {
378 uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
379 if ((offset & 0x3) != 0
380 || (val == 0 || val == ~(uint64_t)0)) {
381 env->mce_banks[offset] = val;
382 }
383 break;
384 }
385
386 break;
387 }
388}
389
390void helper_rdmsr(CPUX86State *env)
391{
392 X86CPU *x86_cpu = env_archcpu(env);
393 uint64_t val;
394
395 cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0, GETPC());
396
397 switch ((uint32_t)env->regs[R_ECX]) {
398 case MSR_IA32_SYSENTER_CS:
399 val = env->sysenter_cs;
400 break;
401 case MSR_IA32_SYSENTER_ESP:
402 val = env->sysenter_esp;
403 break;
404 case MSR_IA32_SYSENTER_EIP:
405 val = env->sysenter_eip;
406 break;
407 case MSR_IA32_APICBASE:
408 val = cpu_get_apic_base(env_archcpu(env)->apic_state);
409 break;
410 case MSR_EFER:
411 val = env->efer;
412 break;
413 case MSR_STAR:
414 val = env->star;
415 break;
416 case MSR_PAT:
417 val = env->pat;
418 break;
419 case MSR_VM_HSAVE_PA:
420 val = env->vm_hsave;
421 break;
422 case MSR_IA32_PERF_STATUS:
423
424 val = 1000ULL;
425
426 val |= (((uint64_t)4ULL) << 40);
427 break;
428#ifdef TARGET_X86_64
429 case MSR_LSTAR:
430 val = env->lstar;
431 break;
432 case MSR_CSTAR:
433 val = env->cstar;
434 break;
435 case MSR_FMASK:
436 val = env->fmask;
437 break;
438 case MSR_FSBASE:
439 val = env->segs[R_FS].base;
440 break;
441 case MSR_GSBASE:
442 val = env->segs[R_GS].base;
443 break;
444 case MSR_KERNELGSBASE:
445 val = env->kernelgsbase;
446 break;
447 case MSR_TSC_AUX:
448 val = env->tsc_aux;
449 break;
450#endif
451 case MSR_SMI_COUNT:
452 val = env->msr_smi_count;
453 break;
454 case MSR_MTRRphysBase(0):
455 case MSR_MTRRphysBase(1):
456 case MSR_MTRRphysBase(2):
457 case MSR_MTRRphysBase(3):
458 case MSR_MTRRphysBase(4):
459 case MSR_MTRRphysBase(5):
460 case MSR_MTRRphysBase(6):
461 case MSR_MTRRphysBase(7):
462 val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
463 MSR_MTRRphysBase(0)) / 2].base;
464 break;
465 case MSR_MTRRphysMask(0):
466 case MSR_MTRRphysMask(1):
467 case MSR_MTRRphysMask(2):
468 case MSR_MTRRphysMask(3):
469 case MSR_MTRRphysMask(4):
470 case MSR_MTRRphysMask(5):
471 case MSR_MTRRphysMask(6):
472 case MSR_MTRRphysMask(7):
473 val = env->mtrr_var[((uint32_t)env->regs[R_ECX] -
474 MSR_MTRRphysMask(0)) / 2].mask;
475 break;
476 case MSR_MTRRfix64K_00000:
477 val = env->mtrr_fixed[0];
478 break;
479 case MSR_MTRRfix16K_80000:
480 case MSR_MTRRfix16K_A0000:
481 val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
482 MSR_MTRRfix16K_80000 + 1];
483 break;
484 case MSR_MTRRfix4K_C0000:
485 case MSR_MTRRfix4K_C8000:
486 case MSR_MTRRfix4K_D0000:
487 case MSR_MTRRfix4K_D8000:
488 case MSR_MTRRfix4K_E0000:
489 case MSR_MTRRfix4K_E8000:
490 case MSR_MTRRfix4K_F0000:
491 case MSR_MTRRfix4K_F8000:
492 val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] -
493 MSR_MTRRfix4K_C0000 + 3];
494 break;
495 case MSR_MTRRdefType:
496 val = env->mtrr_deftype;
497 break;
498 case MSR_MTRRcap:
499 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
500 val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT |
501 MSR_MTRRcap_WC_SUPPORTED;
502 } else {
503
504 val = 0;
505 }
506 break;
507 case MSR_MCG_CAP:
508 val = env->mcg_cap;
509 break;
510 case MSR_MCG_CTL:
511 if (env->mcg_cap & MCG_CTL_P) {
512 val = env->mcg_ctl;
513 } else {
514 val = 0;
515 }
516 break;
517 case MSR_MCG_STATUS:
518 val = env->mcg_status;
519 break;
520 case MSR_IA32_MISC_ENABLE:
521 val = env->msr_ia32_misc_enable;
522 break;
523 case MSR_IA32_BNDCFGS:
524 val = env->msr_bndcfgs;
525 break;
526 case MSR_IA32_UCODE_REV:
527 val = x86_cpu->ucode_rev;
528 break;
529 default:
530 if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
531 && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
532 (4 * env->mcg_cap & 0xff)) {
533 uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL;
534 val = env->mce_banks[offset];
535 break;
536 }
537
538 val = 0;
539 break;
540 }
541 env->regs[R_EAX] = (uint32_t)(val);
542 env->regs[R_EDX] = (uint32_t)(val >> 32);
543}
544#endif
545
546static void do_pause(X86CPU *cpu)
547{
548 CPUState *cs = CPU(cpu);
549
550
551 cs->exception_index = EXCP_INTERRUPT;
552 cpu_loop_exit(cs);
553}
554
555static void do_hlt(X86CPU *cpu)
556{
557 CPUState *cs = CPU(cpu);
558 CPUX86State *env = &cpu->env;
559
560 env->hflags &= ~HF_INHIBIT_IRQ_MASK;
561 cs->halted = 1;
562 cs->exception_index = EXCP_HLT;
563 cpu_loop_exit(cs);
564}
565
566void helper_hlt(CPUX86State *env, int next_eip_addend)
567{
568 X86CPU *cpu = env_archcpu(env);
569
570 cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0, GETPC());
571 env->eip += next_eip_addend;
572
573 do_hlt(cpu);
574}
575
576void helper_monitor(CPUX86State *env, target_ulong ptr)
577{
578 if ((uint32_t)env->regs[R_ECX] != 0) {
579 raise_exception_ra(env, EXCP0D_GPF, GETPC());
580 }
581
582 cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0, GETPC());
583}
584
585void helper_mwait(CPUX86State *env, int next_eip_addend)
586{
587 CPUState *cs = env_cpu(env);
588 X86CPU *cpu = env_archcpu(env);
589
590 if ((uint32_t)env->regs[R_ECX] != 0) {
591 raise_exception_ra(env, EXCP0D_GPF, GETPC());
592 }
593 cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0, GETPC());
594 env->eip += next_eip_addend;
595
596
597 if (cs->cpu_index != 0 || CPU_NEXT(cs) != NULL) {
598 do_pause(cpu);
599 } else {
600 do_hlt(cpu);
601 }
602}
603
604void helper_pause(CPUX86State *env, int next_eip_addend)
605{
606 X86CPU *cpu = env_archcpu(env);
607
608 cpu_svm_check_intercept_param(env, SVM_EXIT_PAUSE, 0, GETPC());
609 env->eip += next_eip_addend;
610
611 do_pause(cpu);
612}
613
614void helper_debug(CPUX86State *env)
615{
616 CPUState *cs = env_cpu(env);
617
618 cs->exception_index = EXCP_DEBUG;
619 cpu_loop_exit(cs);
620}
621
622uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx)
623{
624 if ((env->cr[4] & CR4_PKE_MASK) == 0) {
625 raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
626 }
627 if (ecx != 0) {
628 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
629 }
630
631 return env->pkru;
632}
633
634void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val)
635{
636 CPUState *cs = env_cpu(env);
637
638 if ((env->cr[4] & CR4_PKE_MASK) == 0) {
639 raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
640 }
641 if (ecx != 0 || (val & 0xFFFFFFFF00000000ull)) {
642 raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
643 }
644
645 env->pkru = val;
646 tlb_flush(cs);
647}
648
