LXR qemu/target/arm/gdbstub64.c

   1/*
   2 * ARM gdb server stub: AArch64 specific functions.
   3 *
   4 * Copyright (c) 2013 SUSE LINUX Products GmbH
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19#include "qemu/osdep.h"
  20#include "cpu.h"
  21#include "exec/gdbstub.h"
  22#include "internals.h"
  23
  24#ifndef CONFIG_USER_ONLY
  25
  26/* FIXME: This should be generalized and moved into helper.c */
  27static void map_a32_to_a64_regs(CPUARMState *env)
  28{
  29    unsigned int i;
  30
  31    for (i = 0; i < 13; i++) {
  32        env->xregs[i] = env->regs[i];
  33    }
  34    env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
  35    env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
  36
  37    for (i = 0; i < ARRAY_SIZE(env->fiq_regs); i++) {
  38        env->xregs[i + 24] = env->fiq_regs[i];
  39    }
  40    env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
  41    env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
  42
  43    /* HAX!  */
  44    env->xregs[31] = env->regs[13];
  45
  46    env->pc = env->regs[15];
  47    pstate_write(env, env->spsr | (1 << 4));
  48}
  49
  50static void map_a64_to_a32_regs(CPUARMState *env)
  51{
  52    unsigned int i = 0;
  53
  54    for (i = 0; i < 13; i++) {
  55        env->regs[i] = env->xregs[i];
  56    }
  57    env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
  58    env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
  59
  60    for (i = 0; i < ARRAY_SIZE(env->usr_regs); i++) {
  61        env->fiq_regs[i] = env->xregs[i + 24];
  62    }
  63    env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
  64    env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
  65
  66    env->regs[15] = env->pc;
  67}
  68
  69#endif
  70
  71int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
  72{
  73    ARMCPU *cpu = ARM_CPU(cs);
  74    CPUARMState *env = &cpu->env;
  75
  76#ifndef CONFIG_USER_ONLY
  77    if (!is_a64(env)) {
  78        map_a32_to_a64_regs(env);
  79    }
  80#endif
  81
  82    if (n < 31) {
  83        /* Core integer register.  */
  84        return gdb_get_reg64(mem_buf, env->xregs[n]);
  85    }
  86    switch (n) {
  87    case 31:
  88    {
  89        unsigned int cur_el = arm_current_el(env);
  90        uint64_t sp;
  91
  92        aarch64_save_sp(env, cur_el);
  93        switch (env->debug_ctx) {
  94            case DEBUG_EL0:
  95                sp = env->sp_el[0];
  96                break;
  97            case DEBUG_EL1:
  98                sp = env->sp_el[1];
  99                break;
 100            case DEBUG_EL2:
 101                sp = env->sp_el[2];
 102                break;
 103            case DEBUG_EL3:
 104                sp = env->sp_el[3];
 105                break;
 106            default:
 107                sp = env->xregs[31];
 108                break;
 109        }
 110        return gdb_get_reg64(mem_buf, sp);
 111    }
 112    case 32:
 113        return gdb_get_reg64(mem_buf, env->pc);
 114    case 33:
 115        return gdb_get_reg32(mem_buf, pstate_read(env));
 116    }
 117    /* Unknown register.  */
 118    return 0;
 119}
 120
 121int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 122{
 123    ARMCPU *cpu = ARM_CPU(cs);
 124    CPUARMState *env = &cpu->env;
 125    uint64_t tmp;
 126    int rlen = 0;
 127
 128#ifndef CONFIG_USER_ONLY
 129    if (!is_a64(env)) {
 130        map_a32_to_a64_regs(env);
 131    }
 132#endif
 133
 134    tmp = ldq_p(mem_buf);
 135
 136    if (n < 31) {
 137        /* Core integer register.  */
 138        env->xregs[n] = tmp;
 139        rlen = 8;
 140    }
 141    switch (n) {
 142    case 31: {
 143        unsigned int cur_el = arm_current_el(env);
 144
 145        aarch64_save_sp(env, cur_el);
 146        switch (env->debug_ctx) {
 147            case DEBUG_EL0:
 148                env->sp_el[0] = tmp;
 149                break;
 150            case DEBUG_EL1:
 151                env->sp_el[1] = tmp;
 152                break;
 153            case DEBUG_EL2:
 154                env->sp_el[2] = tmp;
 155                break;
 156            case DEBUG_EL3:
 157                env->sp_el[3] = tmp;
 158                break;
 159            default:
 160                env->xregs[31] = tmp;
 161                break;
 162        }
 163        aarch64_restore_sp(env, cur_el);
 164        rlen = 8;
 165        break;
 166    }
 167    case 32:
 168        env->pc = tmp;
 169        rlen = 8;
 170        break;
 171    case 33:
 172        /* CPSR */
 173        pstate_write(env, tmp);
 174        rlen = 4;
 175        break;
 176    }
 177
 178#ifndef CONFIG_USER_ONLY
 179    if (!is_a64(env)) {
 180        map_a64_to_a32_regs(env);
 181    }
 182#endif
 183
 184    /* Unknown register.  */
 185    return rlen;
 186}
 187