qemu/target/mips/translate_init.inc.c
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   1/*
   2 *  MIPS emulation for qemu: CPU initialisation routines.
   3 *
   4 *  Copyright (c) 2004-2005 Jocelyn Mayer
   5 *  Copyright (c) 2007 Herve Poussineau
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21/* CPU / CPU family specific config register values. */
  22
  23/* Have config1, uncached coherency */
  24#define MIPS_CONFIG0                                              \
  25  ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
  26
  27/* Have config2, no coprocessor2 attached, no MDMX support attached,
  28   no performance counters, watch registers present,
  29   no code compression, EJTAG present, no FPU */
  30#define MIPS_CONFIG1                                              \
  31((1U << CP0C1_M) |                                                \
  32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
  33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) |            \
  34 (0 << CP0C1_FP))
  35
  36/* Have config3, no tertiary/secondary caches implemented */
  37#define MIPS_CONFIG2                                              \
  38((1U << CP0C2_M))
  39
  40/* No config4, no DSP ASE, no large physaddr (PABITS),
  41   no external interrupt controller, no vectored interrupts,
  42   no 1kb pages, no SmartMIPS ASE, no trace logic */
  43#define MIPS_CONFIG3                                              \
  44((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
  45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
  46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
  47
  48#define MIPS_CONFIG4                                              \
  49((0 << CP0C4_M))
  50
  51#define MIPS_CONFIG5                                              \
  52((0 << CP0C5_M))
  53
  54/*****************************************************************************/
  55/* MIPS CPU definitions */
  56const mips_def_t mips_defs[] =
  57{
  58    {
  59        .name = "4Kc",
  60        .CP0_PRid = 0x00018000,
  61        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
  62        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
  63                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  64                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
  65                       (0 << CP0C1_CA),
  66        .CP0_Config2 = MIPS_CONFIG2,
  67        .CP0_Config3 = MIPS_CONFIG3,
  68        .CP0_LLAddr_rw_bitmask = 0,
  69        .CP0_LLAddr_shift = 4,
  70        .SYNCI_Step = 32,
  71        .CCRes = 2,
  72        .CP0_Status_rw_bitmask = 0x1278FF17,
  73        .SEGBITS = 32,
  74        .PABITS = 32,
  75        .insn_flags = CPU_MIPS32,
  76        .mmu_type = MMU_TYPE_R4000,
  77    },
  78    {
  79        .name = "4Km",
  80        .CP0_PRid = 0x00018300,
  81        /* Config1 implemented, fixed mapping MMU,
  82           no virtual icache, uncached coherency. */
  83        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
  84        .CP0_Config1 = MIPS_CONFIG1 |
  85                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
  86                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
  87                       (1 << CP0C1_CA),
  88        .CP0_Config2 = MIPS_CONFIG2,
  89        .CP0_Config3 = MIPS_CONFIG3,
  90        .CP0_LLAddr_rw_bitmask = 0,
  91        .CP0_LLAddr_shift = 4,
  92        .SYNCI_Step = 32,
  93        .CCRes = 2,
  94        .CP0_Status_rw_bitmask = 0x1258FF17,
  95        .SEGBITS = 32,
  96        .PABITS = 32,
  97        .insn_flags = CPU_MIPS32 | ASE_MIPS16,
  98        .mmu_type = MMU_TYPE_FMT,
  99    },
 100    {
 101        .name = "4KEcR1",
 102        .CP0_PRid = 0x00018400,
 103        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
 104        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 105                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 106                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 107                       (0 << CP0C1_CA),
 108        .CP0_Config2 = MIPS_CONFIG2,
 109        .CP0_Config3 = MIPS_CONFIG3,
 110        .CP0_LLAddr_rw_bitmask = 0,
 111        .CP0_LLAddr_shift = 4,
 112        .SYNCI_Step = 32,
 113        .CCRes = 2,
 114        .CP0_Status_rw_bitmask = 0x1278FF17,
 115        .SEGBITS = 32,
 116        .PABITS = 32,
 117        .insn_flags = CPU_MIPS32,
 118        .mmu_type = MMU_TYPE_R4000,
 119    },
 120    {
 121        .name = "4KEmR1",
 122        .CP0_PRid = 0x00018500,
 123        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
 124        .CP0_Config1 = MIPS_CONFIG1 |
 125                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 126                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 127                       (1 << CP0C1_CA),
 128        .CP0_Config2 = MIPS_CONFIG2,
 129        .CP0_Config3 = MIPS_CONFIG3,
 130        .CP0_LLAddr_rw_bitmask = 0,
 131        .CP0_LLAddr_shift = 4,
 132        .SYNCI_Step = 32,
 133        .CCRes = 2,
 134        .CP0_Status_rw_bitmask = 0x1258FF17,
 135        .SEGBITS = 32,
 136        .PABITS = 32,
 137        .insn_flags = CPU_MIPS32 | ASE_MIPS16,
 138        .mmu_type = MMU_TYPE_FMT,
 139    },
 140    {
 141        .name = "4KEc",
 142        .CP0_PRid = 0x00019000,
 143        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 144                    (MMU_TYPE_R4000 << CP0C0_MT),
 145        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 146                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 147                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 148                       (0 << CP0C1_CA),
 149        .CP0_Config2 = MIPS_CONFIG2,
 150        .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 151        .CP0_LLAddr_rw_bitmask = 0,
 152        .CP0_LLAddr_shift = 4,
 153        .SYNCI_Step = 32,
 154        .CCRes = 2,
 155        .CP0_Status_rw_bitmask = 0x1278FF17,
 156        .SEGBITS = 32,
 157        .PABITS = 32,
 158        .insn_flags = CPU_MIPS32R2,
 159        .mmu_type = MMU_TYPE_R4000,
 160    },
 161    {
 162        .name = "4KEm",
 163        .CP0_PRid = 0x00019100,
 164        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 165                       (MMU_TYPE_FMT << CP0C0_MT),
 166        .CP0_Config1 = MIPS_CONFIG1 |
 167                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 168                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 169                       (1 << CP0C1_CA),
 170        .CP0_Config2 = MIPS_CONFIG2,
 171        .CP0_Config3 = MIPS_CONFIG3,
 172        .CP0_LLAddr_rw_bitmask = 0,
 173        .CP0_LLAddr_shift = 4,
 174        .SYNCI_Step = 32,
 175        .CCRes = 2,
 176        .CP0_Status_rw_bitmask = 0x1258FF17,
 177        .SEGBITS = 32,
 178        .PABITS = 32,
 179        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
 180        .mmu_type = MMU_TYPE_FMT,
 181    },
 182    {
 183        .name = "24Kc",
 184        .CP0_PRid = 0x00019300,
 185        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 186                       (MMU_TYPE_R4000 << CP0C0_MT),
 187        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 188                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 189                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 190                       (1 << CP0C1_CA),
 191        .CP0_Config2 = MIPS_CONFIG2,
 192        .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 193        .CP0_LLAddr_rw_bitmask = 0,
 194        .CP0_LLAddr_shift = 4,
 195        .SYNCI_Step = 32,
 196        .CCRes = 2,
 197        /* No DSP implemented. */
 198        .CP0_Status_rw_bitmask = 0x1278FF1F,
 199        .SEGBITS = 32,
 200        .PABITS = 32,
 201        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
 202        .mmu_type = MMU_TYPE_R4000,
 203    },
 204    {
 205        .name = "24KEc",
 206        .CP0_PRid = 0x00019600,
 207        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 208                       (MMU_TYPE_R4000 << CP0C0_MT),
 209        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 210                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 211                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 212                       (1 << CP0C1_CA),
 213        .CP0_Config2 = MIPS_CONFIG2,
 214        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
 215        .CP0_LLAddr_rw_bitmask = 0,
 216        .CP0_LLAddr_shift = 4,
 217        .SYNCI_Step = 32,
 218        .CCRes = 2,
 219        /* we have a DSP, but no FPU */
 220        .CP0_Status_rw_bitmask = 0x1378FF1F,
 221        .SEGBITS = 32,
 222        .PABITS = 32,
 223        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
 224        .mmu_type = MMU_TYPE_R4000,
 225    },
 226    {
 227        .name = "24Kf",
 228        .CP0_PRid = 0x00019300,
 229        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 230                    (MMU_TYPE_R4000 << CP0C0_MT),
 231        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 232                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 233                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 234                       (1 << CP0C1_CA),
 235        .CP0_Config2 = MIPS_CONFIG2,
 236        .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
 237        .CP0_LLAddr_rw_bitmask = 0,
 238        .CP0_LLAddr_shift = 4,
 239        .SYNCI_Step = 32,
 240        .CCRes = 2,
 241        /* No DSP implemented. */
 242        .CP0_Status_rw_bitmask = 0x3678FF1F,
 243        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 244                    (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
 245        .CP1_fcr31 = 0,
 246        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 247        .SEGBITS = 32,
 248        .PABITS = 32,
 249        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
 250        .mmu_type = MMU_TYPE_R4000,
 251    },
 252    {
 253        .name = "34Kf",
 254        .CP0_PRid = 0x00019500,
 255        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 256                       (MMU_TYPE_R4000 << CP0C0_MT),
 257        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 258                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 259                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 260                       (1 << CP0C1_CA),
 261        .CP0_Config2 = MIPS_CONFIG2,
 262        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
 263                       (1 << CP0C3_DSPP),
 264        .CP0_LLAddr_rw_bitmask = 0,
 265        .CP0_LLAddr_shift = 0,
 266        .SYNCI_Step = 32,
 267        .CCRes = 2,
 268        .CP0_Status_rw_bitmask = 0x3778FF1F,
 269        .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
 270                    (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
 271                    (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
 272                    (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
 273                    (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
 274                    (0xff << CP0TCSt_TASID),
 275        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 276                    (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
 277        .CP1_fcr31 = 0,
 278        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 279        .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
 280        .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
 281        .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
 282                    (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
 283        .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
 284        .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
 285                    (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
 286        .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
 287        .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
 288                    (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
 289        .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
 290        .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
 291                    (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
 292        .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
 293        .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
 294                    (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
 295        .SEGBITS = 32,
 296        .PABITS = 32,
 297        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
 298        .mmu_type = MMU_TYPE_R4000,
 299    },
 300    {
 301        .name = "74Kf",
 302        .CP0_PRid = 0x00019700,
 303        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 304                    (MMU_TYPE_R4000 << CP0C0_MT),
 305        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 306                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 307                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
 308                       (1 << CP0C1_CA),
 309        .CP0_Config2 = MIPS_CONFIG2,
 310        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
 311                       (1 << CP0C3_VInt),
 312        .CP0_LLAddr_rw_bitmask = 0,
 313        .CP0_LLAddr_shift = 4,
 314        .SYNCI_Step = 32,
 315        .CCRes = 2,
 316        .CP0_Status_rw_bitmask = 0x3778FF1F,
 317        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 318                    (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
 319        .CP1_fcr31 = 0,
 320        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 321        .SEGBITS = 32,
 322        .PABITS = 32,
 323        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
 324        .mmu_type = MMU_TYPE_R4000,
 325    },
 326    {
 327        .name = "M14K",
 328        .CP0_PRid = 0x00019b00,
 329        /* Config1 implemented, fixed mapping MMU,
 330           no virtual icache, uncached coherency. */
 331        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
 332                       (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
 333        .CP0_Config1 = MIPS_CONFIG1,
 334        .CP0_Config2 = MIPS_CONFIG2,
 335        .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
 336        .CP0_LLAddr_rw_bitmask = 0,
 337        .CP0_LLAddr_shift = 4,
 338        .SYNCI_Step = 32,
 339        .CCRes = 2,
 340        .CP0_Status_rw_bitmask = 0x1258FF17,
 341        .SEGBITS = 32,
 342        .PABITS = 32,
 343        .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
 344        .mmu_type = MMU_TYPE_FMT,
 345    },
 346    {
 347        .name = "M14Kc",
 348        /* This is the TLB-based MMU core.  */
 349        .CP0_PRid = 0x00019c00,
 350        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
 351                       (MMU_TYPE_R4000 << CP0C0_MT),
 352        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
 353                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
 354                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
 355        .CP0_Config2 = MIPS_CONFIG2,
 356        .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
 357        .CP0_LLAddr_rw_bitmask = 0,
 358        .CP0_LLAddr_shift = 4,
 359        .SYNCI_Step = 32,
 360        .CCRes = 2,
 361        .CP0_Status_rw_bitmask = 0x1278FF17,
 362        .SEGBITS = 32,
 363        .PABITS = 32,
 364        .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
 365        .mmu_type = MMU_TYPE_R4000,
 366    },
 367    {
 368        /* FIXME:
 369         * Config3: VZ, CTXTC, CDMM, TL
 370         * Config4: MMUExtDef
 371         * Config5: MRP
 372         * FIR(FCR0): Has2008
 373         * */
 374        .name = "P5600",
 375        .CP0_PRid = 0x0001A800,
 376        .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
 377                    (MMU_TYPE_R4000 << CP0C0_MT),
 378        .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
 379                       (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 380                       (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 381                       (1 << CP0C1_PC) | (1 << CP0C1_FP),
 382        .CP0_Config2 = MIPS_CONFIG2,
 383        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
 384                       (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
 385                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
 386                       (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
 387                       (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
 388        .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
 389                       (0x1c << CP0C4_KScrExist),
 390        .CP0_Config4_rw_bitmask = 0,
 391        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) |
 392                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
 393        .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
 394                                  (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
 395                                  (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
 396        .CP0_LLAddr_rw_bitmask = 0,
 397        .CP0_LLAddr_shift = 0,
 398        .SYNCI_Step = 32,
 399        .CCRes = 2,
 400        .CP0_Status_rw_bitmask = 0x3C68FF1F,
 401        .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
 402                    (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
 403        .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
 404        .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
 405                    (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 406                    (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
 407        .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
 408        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 409        .SEGBITS = 32,
 410        .PABITS = 40,
 411        .insn_flags = CPU_MIPS32R5 | ASE_MSA,
 412        .mmu_type = MMU_TYPE_R4000,
 413    },
 414    {
 415        /* A generic CPU supporting MIPS32 Release 6 ISA.
 416           FIXME: Support IEEE 754-2008 FP.
 417                  Eventually this should be replaced by a real CPU model. */
 418        .name = "mips32r6-generic",
 419        .CP0_PRid = 0x00010000,
 420        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
 421                       (MMU_TYPE_R4000 << CP0C0_MT),
 422        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
 423                       (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 424                       (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 425                       (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 426        .CP0_Config2 = MIPS_CONFIG2,
 427        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
 428                       (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
 429                       (1 << CP0C3_RXI) | (1U << CP0C3_M),
 430        .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
 431                       (3 << CP0C4_IE) | (1U << CP0C4_M),
 432        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
 433        .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
 434                                  (1 << CP0C5_UFE),
 435        .CP0_LLAddr_rw_bitmask = 0,
 436        .CP0_LLAddr_shift = 0,
 437        .SYNCI_Step = 32,
 438        .CCRes = 2,
 439        .CP0_Status_rw_bitmask = 0x3058FF1F,
 440        .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
 441                         (1U << CP0PG_RIE),
 442        .CP0_PageGrain_rw_bitmask = 0,
 443        .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
 444                    (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
 445                    (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
 446        .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
 447        .CP1_fcr31_rw_bitmask = 0x0103FFFF,
 448        .SEGBITS = 32,
 449        .PABITS = 32,
 450        .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
 451        .mmu_type = MMU_TYPE_R4000,
 452    },
 453    {
 454        .name = "I7200",
 455        .CP0_PRid = 0x00010000,
 456        .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
 457                        (MMU_TYPE_R4000 << CP0C0_MT),
 458        .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) |
 459                       (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) |
 460                       (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) |
 461                       (1 << CP0C1_EP),
 462        .CP0_Config2 = MIPS_CONFIG2,
 463        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) |
 464                       (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) |
 465                       (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) |
 466                       (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
 467                       (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
 468                       (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) |
 469                       (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL),
 470        .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
 471                       (2 << CP0C4_IE) | (1U << CP0C4_M),
 472        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
 473        .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
 474                                  (1 << CP0C5_UFE),
 475        .CP0_LLAddr_rw_bitmask = 0,
 476        .CP0_LLAddr_shift = 0,
 477        .SYNCI_Step = 32,
 478        .CCRes = 2,
 479        .CP0_Status_rw_bitmask = 0x3158FF1F,
 480        .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
 481                         (1U << CP0PG_RIE),
 482        .CP0_PageGrain_rw_bitmask = 0,
 483        .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
 484                    (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
 485                    (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV),
 486        .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
 487        .SEGBITS = 32,
 488        .PABITS = 32,
 489        .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 |
 490                      ASE_MT,
 491        .mmu_type = MMU_TYPE_R4000,
 492    },
 493#if defined(TARGET_MIPS64)
 494    {
 495        .name = "R4000",
 496        .CP0_PRid = 0x00000400,
 497        /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
 498        .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
 499        /* Note: Config1 is only used internally, the R4000 has only Config0. */
 500        .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
 501        .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
 502        .CP0_LLAddr_shift = 4,
 503        .SYNCI_Step = 16,
 504        .CCRes = 2,
 505        .CP0_Status_rw_bitmask = 0x3678FFFF,
 506        /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
 507        .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
 508        .CP1_fcr31 = 0,
 509        .CP1_fcr31_rw_bitmask = 0x0183FFFF,
 510        .SEGBITS = 40,
 511        .PABITS = 36,
 512        .insn_flags = CPU_MIPS3,
 513        .mmu_type = MMU_TYPE_R4000,
 514    },
 515    {
 516        .name = "VR5432",
 517        .CP0_PRid = 0x00005400,
 518        /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
 519        .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
 520        .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
 521        .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
 522        .CP0_LLAddr_shift = 4,
 523        .SYNCI_Step = 16,
 524        .CCRes = 2,
 525        .CP0_Status_rw_bitmask = 0x3678FFFF,
 526        /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
 527        .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
 528        .CP1_fcr31 = 0,
 529        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 530        .SEGBITS = 40,
 531        .PABITS = 32,
 532        .insn_flags = CPU_VR54XX,
 533        .mmu_type = MMU_TYPE_R4000,
 534    },
 535    {
 536        .name = "5Kc",
 537        .CP0_PRid = 0x00018100,
 538        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
 539                       (MMU_TYPE_R4000 << CP0C0_MT),
 540        .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
 541                       (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 542                       (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 543                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 544        .CP0_Config2 = MIPS_CONFIG2,
 545        .CP0_Config3 = MIPS_CONFIG3,
 546        .CP0_LLAddr_rw_bitmask = 0,
 547        .CP0_LLAddr_shift = 4,
 548        .SYNCI_Step = 32,
 549        .CCRes = 2,
 550        .CP0_Status_rw_bitmask = 0x12F8FFFF,
 551        .SEGBITS = 42,
 552        .PABITS = 36,
 553        .insn_flags = CPU_MIPS64,
 554        .mmu_type = MMU_TYPE_R4000,
 555    },
 556    {
 557        .name = "5Kf",
 558        .CP0_PRid = 0x00018100,
 559        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
 560                       (MMU_TYPE_R4000 << CP0C0_MT),
 561        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
 562                       (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 563                       (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 564                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 565        .CP0_Config2 = MIPS_CONFIG2,
 566        .CP0_Config3 = MIPS_CONFIG3,
 567        .CP0_LLAddr_rw_bitmask = 0,
 568        .CP0_LLAddr_shift = 4,
 569        .SYNCI_Step = 32,
 570        .CCRes = 2,
 571        .CP0_Status_rw_bitmask = 0x36F8FFFF,
 572        /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
 573        .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
 574                    (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
 575        .CP1_fcr31 = 0,
 576        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 577        .SEGBITS = 42,
 578        .PABITS = 36,
 579        .insn_flags = CPU_MIPS64,
 580        .mmu_type = MMU_TYPE_R4000,
 581    },
 582    {
 583        .name = "20Kc",
 584        /* We emulate a later version of the 20Kc, earlier ones had a broken
 585           WAIT instruction. */
 586        .CP0_PRid = 0x000182a0,
 587        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
 588                    (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
 589        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
 590                       (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 591                       (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 592                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 593        .CP0_Config2 = MIPS_CONFIG2,
 594        .CP0_Config3 = MIPS_CONFIG3,
 595        .CP0_LLAddr_rw_bitmask = 0,
 596        .CP0_LLAddr_shift = 0,
 597        .SYNCI_Step = 32,
 598        .CCRes = 1,
 599        .CP0_Status_rw_bitmask = 0x36FBFFFF,
 600        /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
 601        .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
 602                    (1 << FCR0_D) | (1 << FCR0_S) |
 603                    (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
 604        .CP1_fcr31 = 0,
 605        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 606        .SEGBITS = 40,
 607        .PABITS = 36,
 608        .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
 609        .mmu_type = MMU_TYPE_R4000,
 610    },
 611    {
 612        /* A generic CPU providing MIPS64 Release 2 features.
 613           FIXME: Eventually this should be replaced by a real CPU model. */
 614        .name = "MIPS64R2-generic",
 615        .CP0_PRid = 0x00010000,
 616        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 617                       (MMU_TYPE_R4000 << CP0C0_MT),
 618        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
 619                       (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 620                       (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 621                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 622        .CP0_Config2 = MIPS_CONFIG2,
 623        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
 624        .CP0_LLAddr_rw_bitmask = 0,
 625        .CP0_LLAddr_shift = 0,
 626        .SYNCI_Step = 32,
 627        .CCRes = 2,
 628        .CP0_Status_rw_bitmask = 0x36FBFFFF,
 629        .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
 630        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
 631                    (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
 632                    (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
 633        .CP1_fcr31 = 0,
 634        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 635        .SEGBITS = 42,
 636        .PABITS = 36,
 637        .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
 638        .mmu_type = MMU_TYPE_R4000,
 639    },
 640    {
 641        .name = "5KEc",
 642        .CP0_PRid = 0x00018900,
 643        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 644                       (MMU_TYPE_R4000 << CP0C0_MT),
 645        .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
 646                       (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 647                       (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 648                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 649        .CP0_Config2 = MIPS_CONFIG2,
 650        .CP0_Config3 = MIPS_CONFIG3,
 651        .CP0_LLAddr_rw_bitmask = 0,
 652        .CP0_LLAddr_shift = 4,
 653        .SYNCI_Step = 32,
 654        .CCRes = 2,
 655        .CP0_Status_rw_bitmask = 0x12F8FFFF,
 656        .SEGBITS = 42,
 657        .PABITS = 36,
 658        .insn_flags = CPU_MIPS64R2,
 659        .mmu_type = MMU_TYPE_R4000,
 660    },
 661    {
 662        .name = "5KEf",
 663        .CP0_PRid = 0x00018900,
 664        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 665                       (MMU_TYPE_R4000 << CP0C0_MT),
 666        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
 667                       (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
 668                       (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
 669                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 670        .CP0_Config2 = MIPS_CONFIG2,
 671        .CP0_Config3 = MIPS_CONFIG3,
 672        .CP0_LLAddr_rw_bitmask = 0,
 673        .CP0_LLAddr_shift = 4,
 674        .SYNCI_Step = 32,
 675        .CCRes = 2,
 676        .CP0_Status_rw_bitmask = 0x36F8FFFF,
 677        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
 678                    (1 << FCR0_D) | (1 << FCR0_S) |
 679                    (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
 680        .SEGBITS = 42,
 681        .PABITS = 36,
 682        .insn_flags = CPU_MIPS64R2,
 683        .mmu_type = MMU_TYPE_R4000,
 684    },
 685    {
 686        .name = "I6400",
 687        .CP0_PRid = 0x1A900,
 688        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 689                       (MMU_TYPE_R4000 << CP0C0_MT),
 690        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 691                       (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
 692                       (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
 693                       (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 694        .CP0_Config2 = MIPS_CONFIG2,
 695        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
 696                       (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
 697                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
 698                       (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
 699        .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
 700                       (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
 701        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
 702                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
 703        .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
 704                                  (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
 705        .CP0_LLAddr_rw_bitmask = 0,
 706        .CP0_LLAddr_shift = 0,
 707        .SYNCI_Step = 32,
 708        .CCRes = 2,
 709        .CP0_Status_rw_bitmask = 0x30D8FFFF,
 710        .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
 711                         (1U << CP0PG_RIE),
 712        .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
 713        .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
 714        .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
 715                    (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
 716                    (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
 717        .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
 718        .CP1_fcr31_rw_bitmask = 0x0103FFFF,
 719        .MSAIR = 0x03 << MSAIR_ProcID,
 720        .SEGBITS = 48,
 721        .PABITS = 48,
 722        .insn_flags = CPU_MIPS64R6 | ASE_MSA,
 723        .mmu_type = MMU_TYPE_R4000,
 724    },
 725    {
 726        .name = "I6500",
 727        .CP0_PRid = 0x1B000,
 728        .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 729                       (MMU_TYPE_R4000 << CP0C0_MT),
 730        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
 731                       (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
 732                       (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
 733                       (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 734        .CP0_Config2 = MIPS_CONFIG2,
 735        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
 736                       (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
 737                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
 738                       (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
 739        .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
 740                       (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
 741        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
 742                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
 743        .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
 744                                  (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
 745        .CP0_LLAddr_rw_bitmask = 0,
 746        .CP0_LLAddr_shift = 0,
 747        .SYNCI_Step = 64,
 748        .CCRes = 2,
 749        .CP0_Status_rw_bitmask = 0x30D8FFFF,
 750        .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
 751                         (1U << CP0PG_RIE),
 752        .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
 753        .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
 754        .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
 755                    (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
 756                    (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
 757        .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
 758        .CP1_fcr31_rw_bitmask = 0x0103FFFF,
 759        .MSAIR = 0x03 << MSAIR_ProcID,
 760        .SEGBITS = 48,
 761        .PABITS = 48,
 762        .insn_flags = CPU_MIPS64R6 | ASE_MSA,
 763        .mmu_type = MMU_TYPE_R4000,
 764    },
 765    {
 766        .name = "Loongson-2E",
 767        .CP0_PRid = 0x6302,
 768        /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
 769        .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
 770                       (0x1<<5) | (0x1<<4) | (0x1<<1),
 771        /* Note: Config1 is only used internally,
 772           Loongson-2E has only Config0.  */
 773        .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
 774        .SYNCI_Step = 16,
 775        .CCRes = 2,
 776        .CP0_Status_rw_bitmask = 0x35D0FFFF,
 777        .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
 778        .CP1_fcr31 = 0,
 779        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 780        .SEGBITS = 40,
 781        .PABITS = 40,
 782        .insn_flags = CPU_LOONGSON2E,
 783        .mmu_type = MMU_TYPE_R4000,
 784    },
 785    {
 786        .name = "Loongson-2F",
 787        .CP0_PRid = 0x6303,
 788        /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
 789        .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
 790                       (0x1<<5) | (0x1<<4) | (0x1<<1),
 791        /* Note: Config1 is only used internally,
 792           Loongson-2F has only Config0.  */
 793        .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
 794        .SYNCI_Step = 16,
 795        .CCRes = 2,
 796        .CP0_Status_rw_bitmask = 0xF5D0FF1F,   /* Bits 7:5 not writable.  */
 797        .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
 798        .CP1_fcr31 = 0,
 799        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 800        .SEGBITS = 40,
 801        .PABITS = 40,
 802        .insn_flags = CPU_LOONGSON2F,
 803        .mmu_type = MMU_TYPE_R4000,
 804    },
 805    {
 806        .name = "Loongson-3A1000",
 807        .CP0_PRid = 0x6305,
 808        /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
 809        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 810                       (MMU_TYPE_R4000 << CP0C0_MT),
 811        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
 812                       (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 813                       (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 814                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 815        .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) |
 816                       (3 << CP0C2_SA),
 817        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
 818        .CP0_LLAddr_rw_bitmask = 0,
 819        .SYNCI_Step = 32,
 820        .CCRes = 2,
 821        .CP0_Status_rw_bitmask = 0x74D8FFFF,
 822        .CP0_PageGrain = (1 << CP0PG_ELPA),
 823        .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
 824        .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
 825                    (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
 826                    (0x1 << FCR0_D) | (0x1 << FCR0_S),
 827        .CP1_fcr31 = 0,
 828        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 829        .SEGBITS = 42,
 830        .PABITS = 48,
 831        .insn_flags = CPU_LOONGSON3A,
 832        .mmu_type = MMU_TYPE_R4000,
 833    },
 834    {
 835        .name = "Loongson-3A4000",
 836        .CP0_PRid = 0x14C000,
 837        /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size.  */
 838        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 839                       (MMU_TYPE_R4000 << CP0C0_MT),
 840        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
 841                       (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
 842                       (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
 843                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 844        .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) |
 845                       (15 << CP0C2_SA),
 846        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
 847                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
 848                       (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
 849        .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
 850                       (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist),
 851        .CP0_Config4_rw_bitmask = 0,
 852        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists),
 853        .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
 854                                  (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
 855                                  (1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
 856        .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) |
 857                       (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) |
 858                       (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF),
 859        .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) |
 860                       (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) |
 861                       (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) |
 862                       (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) |
 863                       (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) |
 864                       (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) |
 865                       (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) |
 866                       (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) |
 867                       (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) |
 868                       (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) |
 869                       (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) |
 870                       (1 << CP0C6_DATAPREF),
 871        .CP0_Config7 = 0,
 872        .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) |
 873                                  (1 << CP0C7_VFPUCGEN),
 874        .CP0_LLAddr_rw_bitmask = 1,
 875        .SYNCI_Step = 16,
 876        .CCRes = 2,
 877        .CP0_Status_rw_bitmask = 0x7DDBFFFF,
 878        .CP0_PageGrain = (1 << CP0PG_ELPA),
 879        .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
 880                    (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
 881        .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
 882                    (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
 883                    (0x1 << FCR0_D) | (0x1 << FCR0_S),
 884        .CP1_fcr31 = 0,
 885        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 886        .SEGBITS = 48,
 887        .PABITS = 48,
 888        .insn_flags = CPU_LOONGSON3A,
 889        .mmu_type = MMU_TYPE_R4000,
 890    },
 891    {
 892        /* A generic CPU providing MIPS64 DSP R2 ASE features.
 893           FIXME: Eventually this should be replaced by a real CPU model. */
 894        .name = "mips64dspr2",
 895        .CP0_PRid = 0x00010000,
 896        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
 897                       (MMU_TYPE_R4000 << CP0C0_MT),
 898        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
 899                       (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
 900                       (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
 901                       (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
 902        .CP0_Config2 = MIPS_CONFIG2,
 903        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
 904                       (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
 905        .CP0_LLAddr_rw_bitmask = 0,
 906        .CP0_LLAddr_shift = 0,
 907        .SYNCI_Step = 32,
 908        .CCRes = 2,
 909        .CP0_Status_rw_bitmask = 0x37FBFFFF,
 910        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
 911                    (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
 912                    (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
 913        .CP1_fcr31 = 0,
 914        .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
 915        .SEGBITS = 42,
 916        .PABITS = 36,
 917        .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
 918        .mmu_type = MMU_TYPE_R4000,
 919    },
 920
 921#endif
 922};
 923const int mips_defs_number = ARRAY_SIZE(mips_defs);
 924
 925void mips_cpu_list(void)
 926{
 927    int i;
 928
 929    for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
 930        qemu_printf("MIPS '%s'\n", mips_defs[i].name);
 931    }
 932}
 933
 934#ifndef CONFIG_USER_ONLY
 935static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 936{
 937    env->tlb->nb_tlb = 1;
 938    env->tlb->map_address = &no_mmu_map_address;
 939}
 940
 941static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 942{
 943    env->tlb->nb_tlb = 1;
 944    env->tlb->map_address = &fixed_mmu_map_address;
 945}
 946
 947static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 948{
 949    env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
 950    env->tlb->map_address = &r4k_map_address;
 951    env->tlb->helper_tlbwi = r4k_helper_tlbwi;
 952    env->tlb->helper_tlbwr = r4k_helper_tlbwr;
 953    env->tlb->helper_tlbp = r4k_helper_tlbp;
 954    env->tlb->helper_tlbr = r4k_helper_tlbr;
 955    env->tlb->helper_tlbinv = r4k_helper_tlbinv;
 956    env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
 957}
 958
 959static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
 960{
 961    env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
 962
 963    switch (def->mmu_type) {
 964        case MMU_TYPE_NONE:
 965            no_mmu_init(env, def);
 966            break;
 967        case MMU_TYPE_R4000:
 968            r4k_mmu_init(env, def);
 969            break;
 970        case MMU_TYPE_FMT:
 971            fixed_mmu_init(env, def);
 972            break;
 973        case MMU_TYPE_R3000:
 974        case MMU_TYPE_R6000:
 975        case MMU_TYPE_R8000:
 976        default:
 977            cpu_abort(env_cpu(env), "MMU type not supported\n");
 978    }
 979}
 980#endif /* CONFIG_USER_ONLY */
 981
 982static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
 983{
 984    int i;
 985
 986    for (i = 0; i < MIPS_FPU_MAX; i++)
 987        env->fpus[i].fcr0 = def->CP1_fcr0;
 988
 989    memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
 990}
 991
 992static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
 993{
 994    env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
 995
 996    /* MVPConf1 implemented, TLB sharable, no gating storage support,
 997       programmable cache partitioning implemented, number of allocatable
 998       and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
 999       implemented, 5 TCs implemented. */
1000    env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
1001                             (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
1002// TODO: actually do 2 VPEs.
1003//                             (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
1004//                             (0x04 << CP0MVPC0_PTC);
1005                             (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
1006                             (0x00 << CP0MVPC0_PTC);
1007#if !defined(CONFIG_USER_ONLY)
1008    /* Usermode has no TLB support */
1009    env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
1010#endif
1011
1012    /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
1013       no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
1014    env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
1015                             (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
1016                             (0x1 << CP0MVPC1_PCP1);
1017}
1018
1019static void msa_reset(CPUMIPSState *env)
1020{
1021#ifdef CONFIG_USER_ONLY
1022    /* MSA access enabled */
1023    env->CP0_Config5 |= 1 << CP0C5_MSAEn;
1024    env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
1025#endif
1026
1027    /* MSA CSR:
1028       - non-signaling floating point exception mode off (NX bit is 0)
1029       - Cause, Enables, and Flags are all 0
1030       - round to nearest / ties to even (RM bits are 0) */
1031    env->active_tc.msacsr = 0;
1032
1033    restore_msa_fp_status(env);
1034
1035    /* tininess detected after rounding.*/
1036    set_float_detect_tininess(float_tininess_after_rounding,
1037                              &env->active_tc.msa_fp_status);
1038
1039    /* clear float_status exception flags */
1040    set_float_exception_flags(0, &env->active_tc.msa_fp_status);
1041
1042    /* clear float_status nan mode */
1043    set_default_nan_mode(0, &env->active_tc.msa_fp_status);
1044
1045    /* set proper signanling bit meaning ("1" means "quiet") */
1046    set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
1047}
1048