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21#include "qemu/osdep.h"
22#include "qemu/log.h"
23#include "hw/qdev-properties.h"
24#include "hw/core/cpu.h"
25#include "hw/boards.h"
26#include "hw/pci/msi.h"
27#include "target/riscv/cpu_bits.h"
28#include "target/riscv/cpu.h"
29#include "hw/intc/ibex_plic.h"
30
31static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
32{
33 uint32_t end = base + (num * 0x04);
34
35 if (addr >= base && addr < end) {
36 return true;
37 }
38
39 return false;
40}
41
42static void ibex_plic_irqs_set_pending(IbexPlicState *s, int irq, bool level)
43{
44 int pending_num = irq / 32;
45
46 if (!level) {
47
48
49
50 s->hidden_pending[pending_num] &= ~(1 << (irq % 32));
51 }
52
53 if (s->claimed[pending_num] & 1 << (irq % 32)) {
54
55
56
57
58
59 s->hidden_pending[pending_num] |= level << (irq % 32);
60 } else {
61 s->pending[pending_num] |= level << (irq % 32);
62 }
63}
64
65static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
66{
67 int i;
68 uint32_t max_irq = 0;
69 uint32_t max_prio = s->threshold;
70
71 for (i = 0; i < s->pending_num; i++) {
72 uint32_t irq_num = ctz64(s->pending[i]) + (i * 32);
73
74 if (!(s->pending[i] & s->enable[i])) {
75
76 continue;
77 }
78
79 if (s->priority[irq_num] > max_prio) {
80 max_irq = irq_num;
81 max_prio = s->priority[irq_num];
82 }
83 }
84
85 if (max_irq) {
86 s->claim = max_irq;
87 return true;
88 }
89
90 return false;
91}
92
93static void ibex_plic_update(IbexPlicState *s)
94{
95 CPUState *cpu;
96 int level, i;
97
98 for (i = 0; i < s->num_cpus; i++) {
99 cpu = qemu_get_cpu(i);
100
101 if (!cpu) {
102 continue;
103 }
104
105 level = ibex_plic_irqs_pending(s, 0);
106
107 riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
108 }
109}
110
111static void ibex_plic_reset(DeviceState *dev)
112{
113 IbexPlicState *s = IBEX_PLIC(dev);
114
115 s->threshold = 0x00000000;
116 s->claim = 0x00000000;
117}
118
119static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
120 unsigned int size)
121{
122 IbexPlicState *s = opaque;
123 int offset;
124 uint32_t ret = 0;
125
126 if (addr_between(addr, s->pending_base, s->pending_num)) {
127 offset = (addr - s->pending_base) / 4;
128 ret = s->pending[offset];
129 } else if (addr_between(addr, s->source_base, s->source_num)) {
130 qemu_log_mask(LOG_UNIMP,
131 "%s: Interrupt source mode not supported\n", __func__);
132 } else if (addr_between(addr, s->priority_base, s->priority_num)) {
133 offset = (addr - s->priority_base) / 4;
134 ret = s->priority[offset];
135 } else if (addr_between(addr, s->enable_base, s->enable_num)) {
136 offset = (addr - s->enable_base) / 4;
137 ret = s->enable[offset];
138 } else if (addr_between(addr, s->threshold_base, 1)) {
139 ret = s->threshold;
140 } else if (addr_between(addr, s->claim_base, 1)) {
141 int pending_num = s->claim / 32;
142 s->pending[pending_num] &= ~(1 << (s->claim % 32));
143
144
145 s->claimed[pending_num] |= 1 << (s->claim % 32);
146
147
148 ret = s->claim;
149
150
151 s->claim = 0x00000000;
152
153
154 ibex_plic_update(s);
155 }
156
157 return ret;
158}
159
160static void ibex_plic_write(void *opaque, hwaddr addr,
161 uint64_t value, unsigned int size)
162{
163 IbexPlicState *s = opaque;
164
165 if (addr_between(addr, s->pending_base, s->pending_num)) {
166 qemu_log_mask(LOG_GUEST_ERROR,
167 "%s: Pending registers are read only\n", __func__);
168 } else if (addr_between(addr, s->source_base, s->source_num)) {
169 qemu_log_mask(LOG_UNIMP,
170 "%s: Interrupt source mode not supported\n", __func__);
171 } else if (addr_between(addr, s->priority_base, s->priority_num)) {
172 uint32_t irq = ((addr - s->priority_base) >> 2) + 1;
173 s->priority[irq] = value & 7;
174 ibex_plic_update(s);
175 } else if (addr_between(addr, s->enable_base, s->enable_num)) {
176 uint32_t enable_reg = (addr - s->enable_base) / 4;
177
178 s->enable[enable_reg] = value;
179 } else if (addr_between(addr, s->threshold_base, 1)) {
180 s->threshold = value & 3;
181 } else if (addr_between(addr, s->claim_base, 1)) {
182 if (s->claim == value) {
183
184 s->claim = 0;
185 }
186 if (s->claimed[value / 32] & 1 << (value % 32)) {
187 int pending_num = value / 32;
188
189
190 s->claimed[pending_num] &= ~(1 << (value % 32));
191
192 if (s->hidden_pending[pending_num] & (1 << (value % 32))) {
193
194
195
196
197
198
199
200 s->pending[pending_num] |= 1 << (value % 32);
201 }
202 }
203 }
204
205 ibex_plic_update(s);
206}
207
208static const MemoryRegionOps ibex_plic_ops = {
209 .read = ibex_plic_read,
210 .write = ibex_plic_write,
211 .endianness = DEVICE_NATIVE_ENDIAN,
212 .valid = {
213 .min_access_size = 4,
214 .max_access_size = 4
215 }
216};
217
218static void ibex_plic_irq_request(void *opaque, int irq, int level)
219{
220 IbexPlicState *s = opaque;
221
222 ibex_plic_irqs_set_pending(s, irq, level > 0);
223 ibex_plic_update(s);
224}
225
226static Property ibex_plic_properties[] = {
227 DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
228 DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
229
230 DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
231 DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
232
233 DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
234 DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
235
236 DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
237 DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
238
239 DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
240 DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
241
242 DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
243
244 DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
245 DEFINE_PROP_END_OF_LIST(),
246};
247
248static void ibex_plic_init(Object *obj)
249{
250 IbexPlicState *s = IBEX_PLIC(obj);
251
252 memory_region_init_io(&s->mmio, obj, &ibex_plic_ops, s,
253 TYPE_IBEX_PLIC, 0x400);
254 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
255}
256
257static void ibex_plic_realize(DeviceState *dev, Error **errp)
258{
259 IbexPlicState *s = IBEX_PLIC(dev);
260 int i;
261
262 s->pending = g_new0(uint32_t, s->pending_num);
263 s->hidden_pending = g_new0(uint32_t, s->pending_num);
264 s->claimed = g_new0(uint32_t, s->pending_num);
265 s->source = g_new0(uint32_t, s->source_num);
266 s->priority = g_new0(uint32_t, s->priority_num);
267 s->enable = g_new0(uint32_t, s->enable_num);
268
269 qdev_init_gpio_in(dev, ibex_plic_irq_request, s->num_sources);
270
271
272
273
274
275
276
277 MachineState *ms = MACHINE(qdev_get_machine());
278 unsigned int smp_cpus = ms->smp.cpus;
279 for (i = 0; i < smp_cpus; i++) {
280 RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(i));
281 if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
282 error_report("SEIP already claimed");
283 exit(1);
284 }
285 }
286
287 msi_nonbroken = true;
288}
289
290static void ibex_plic_class_init(ObjectClass *klass, void *data)
291{
292 DeviceClass *dc = DEVICE_CLASS(klass);
293
294 dc->reset = ibex_plic_reset;
295 device_class_set_props(dc, ibex_plic_properties);
296 dc->realize = ibex_plic_realize;
297}
298
299static const TypeInfo ibex_plic_info = {
300 .name = TYPE_IBEX_PLIC,
301 .parent = TYPE_SYS_BUS_DEVICE,
302 .instance_size = sizeof(IbexPlicState),
303 .instance_init = ibex_plic_init,
304 .class_init = ibex_plic_class_init,
305};
306
307static void ibex_plic_register_types(void)
308{
309 type_register_static(&ibex_plic_info);
310}
311
312type_init(ibex_plic_register_types)
313