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20#include "qemu/osdep.h"
21#include "qemu/units.h"
22
23#include "hw/boards.h"
24#include "hw/char/serial.h"
25#include "hw/ide/pci.h"
26#include "hw/ide/ahci.h"
27#include "hw/loader.h"
28#include "hw/loader-fit.h"
29#include "hw/mips/bootloader.h"
30#include "hw/mips/cps.h"
31#include "hw/pci-host/xilinx-pcie.h"
32#include "hw/qdev-clock.h"
33#include "hw/qdev-properties.h"
34#include "qapi/error.h"
35#include "qemu/error-report.h"
36#include "qemu/log.h"
37#include "chardev/char.h"
38#include "sysemu/device_tree.h"
39#include "sysemu/sysemu.h"
40#include "sysemu/qtest.h"
41#include "sysemu/runstate.h"
42
43#include <libfdt.h>
44#include "qom/object.h"
45
46#define TYPE_BOSTON "mips-boston"
47typedef struct BostonState BostonState;
48DECLARE_INSTANCE_CHECKER(BostonState, BOSTON,
49 TYPE_BOSTON)
50
51struct BostonState {
52 SysBusDevice parent_obj;
53
54 MachineState *mach;
55 MIPSCPSState cps;
56 SerialMM *uart;
57 Clock *cpuclk;
58
59 CharBackend lcd_display;
60 char lcd_content[8];
61 bool lcd_inited;
62
63 hwaddr kernel_entry;
64 hwaddr fdt_base;
65};
66
67enum boston_plat_reg {
68 PLAT_FPGA_BUILD = 0x00,
69 PLAT_CORE_CL = 0x04,
70 PLAT_WRAPPER_CL = 0x08,
71 PLAT_SYSCLK_STATUS = 0x0c,
72 PLAT_SOFTRST_CTL = 0x10,
73#define PLAT_SOFTRST_CTL_SYSRESET (1 << 4)
74 PLAT_DDR3_STATUS = 0x14,
75#define PLAT_DDR3_STATUS_LOCKED (1 << 0)
76#define PLAT_DDR3_STATUS_CALIBRATED (1 << 2)
77 PLAT_PCIE_STATUS = 0x18,
78#define PLAT_PCIE_STATUS_PCIE0_LOCKED (1 << 0)
79#define PLAT_PCIE_STATUS_PCIE1_LOCKED (1 << 8)
80#define PLAT_PCIE_STATUS_PCIE2_LOCKED (1 << 16)
81 PLAT_FLASH_CTL = 0x1c,
82 PLAT_SPARE0 = 0x20,
83 PLAT_SPARE1 = 0x24,
84 PLAT_SPARE2 = 0x28,
85 PLAT_SPARE3 = 0x2c,
86 PLAT_MMCM_DIV = 0x30,
87#define PLAT_MMCM_DIV_CLK0DIV_SHIFT 0
88#define PLAT_MMCM_DIV_INPUT_SHIFT 8
89#define PLAT_MMCM_DIV_MUL_SHIFT 16
90#define PLAT_MMCM_DIV_CLK1DIV_SHIFT 24
91 PLAT_BUILD_CFG = 0x34,
92#define PLAT_BUILD_CFG_IOCU_EN (1 << 0)
93#define PLAT_BUILD_CFG_PCIE0_EN (1 << 1)
94#define PLAT_BUILD_CFG_PCIE1_EN (1 << 2)
95#define PLAT_BUILD_CFG_PCIE2_EN (1 << 3)
96 PLAT_DDR_CFG = 0x38,
97#define PLAT_DDR_CFG_SIZE (0xf << 0)
98#define PLAT_DDR_CFG_MHZ (0xfff << 4)
99 PLAT_NOC_PCIE0_ADDR = 0x3c,
100 PLAT_NOC_PCIE1_ADDR = 0x40,
101 PLAT_NOC_PCIE2_ADDR = 0x44,
102 PLAT_SYS_CTL = 0x48,
103};
104
105static void boston_lcd_event(void *opaque, QEMUChrEvent event)
106{
107 BostonState *s = opaque;
108 if (event == CHR_EVENT_OPENED && !s->lcd_inited) {
109 qemu_chr_fe_printf(&s->lcd_display, " ");
110 s->lcd_inited = true;
111 }
112}
113
114static uint64_t boston_lcd_read(void *opaque, hwaddr addr,
115 unsigned size)
116{
117 BostonState *s = opaque;
118 uint64_t val = 0;
119
120 switch (size) {
121 case 8:
122 val |= (uint64_t)s->lcd_content[(addr + 7) & 0x7] << 56;
123 val |= (uint64_t)s->lcd_content[(addr + 6) & 0x7] << 48;
124 val |= (uint64_t)s->lcd_content[(addr + 5) & 0x7] << 40;
125 val |= (uint64_t)s->lcd_content[(addr + 4) & 0x7] << 32;
126
127 case 4:
128 val |= (uint64_t)s->lcd_content[(addr + 3) & 0x7] << 24;
129 val |= (uint64_t)s->lcd_content[(addr + 2) & 0x7] << 16;
130
131 case 2:
132 val |= (uint64_t)s->lcd_content[(addr + 1) & 0x7] << 8;
133
134 case 1:
135 val |= (uint64_t)s->lcd_content[(addr + 0) & 0x7];
136 break;
137 }
138
139 return val;
140}
141
142static void boston_lcd_write(void *opaque, hwaddr addr,
143 uint64_t val, unsigned size)
144{
145 BostonState *s = opaque;
146
147 switch (size) {
148 case 8:
149 s->lcd_content[(addr + 7) & 0x7] = val >> 56;
150 s->lcd_content[(addr + 6) & 0x7] = val >> 48;
151 s->lcd_content[(addr + 5) & 0x7] = val >> 40;
152 s->lcd_content[(addr + 4) & 0x7] = val >> 32;
153
154 case 4:
155 s->lcd_content[(addr + 3) & 0x7] = val >> 24;
156 s->lcd_content[(addr + 2) & 0x7] = val >> 16;
157
158 case 2:
159 s->lcd_content[(addr + 1) & 0x7] = val >> 8;
160
161 case 1:
162 s->lcd_content[(addr + 0) & 0x7] = val;
163 break;
164 }
165
166 qemu_chr_fe_printf(&s->lcd_display,
167 "\r%-8.8s", s->lcd_content);
168}
169
170static const MemoryRegionOps boston_lcd_ops = {
171 .read = boston_lcd_read,
172 .write = boston_lcd_write,
173 .endianness = DEVICE_NATIVE_ENDIAN,
174};
175
176static uint64_t boston_platreg_read(void *opaque, hwaddr addr,
177 unsigned size)
178{
179 BostonState *s = opaque;
180 uint32_t gic_freq, val;
181
182 if (size != 4) {
183 qemu_log_mask(LOG_UNIMP, "%uB platform register read\n", size);
184 return 0;
185 }
186
187 switch (addr & 0xffff) {
188 case PLAT_FPGA_BUILD:
189 case PLAT_CORE_CL:
190 case PLAT_WRAPPER_CL:
191 return 0;
192 case PLAT_DDR3_STATUS:
193 return PLAT_DDR3_STATUS_LOCKED | PLAT_DDR3_STATUS_CALIBRATED;
194 case PLAT_MMCM_DIV:
195 gic_freq = mips_gictimer_get_freq(s->cps.gic.gic_timer) / 1000000;
196 val = gic_freq << PLAT_MMCM_DIV_INPUT_SHIFT;
197 val |= 1 << PLAT_MMCM_DIV_MUL_SHIFT;
198 val |= 1 << PLAT_MMCM_DIV_CLK0DIV_SHIFT;
199 val |= 1 << PLAT_MMCM_DIV_CLK1DIV_SHIFT;
200 return val;
201 case PLAT_BUILD_CFG:
202 val = PLAT_BUILD_CFG_PCIE0_EN;
203 val |= PLAT_BUILD_CFG_PCIE1_EN;
204 val |= PLAT_BUILD_CFG_PCIE2_EN;
205 return val;
206 case PLAT_DDR_CFG:
207 val = s->mach->ram_size / GiB;
208 assert(!(val & ~PLAT_DDR_CFG_SIZE));
209 val |= PLAT_DDR_CFG_MHZ;
210 return val;
211 default:
212 qemu_log_mask(LOG_UNIMP, "Read platform register 0x%" HWADDR_PRIx "\n",
213 addr & 0xffff);
214 return 0;
215 }
216}
217
218static void boston_platreg_write(void *opaque, hwaddr addr,
219 uint64_t val, unsigned size)
220{
221 if (size != 4) {
222 qemu_log_mask(LOG_UNIMP, "%uB platform register write\n", size);
223 return;
224 }
225
226 switch (addr & 0xffff) {
227 case PLAT_FPGA_BUILD:
228 case PLAT_CORE_CL:
229 case PLAT_WRAPPER_CL:
230 case PLAT_DDR3_STATUS:
231 case PLAT_PCIE_STATUS:
232 case PLAT_MMCM_DIV:
233 case PLAT_BUILD_CFG:
234 case PLAT_DDR_CFG:
235
236 break;
237 case PLAT_SOFTRST_CTL:
238 if (val & PLAT_SOFTRST_CTL_SYSRESET) {
239 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
240 }
241 break;
242 default:
243 qemu_log_mask(LOG_UNIMP, "Write platform register 0x%" HWADDR_PRIx
244 " = 0x%" PRIx64 "\n", addr & 0xffff, val);
245 break;
246 }
247}
248
249static const MemoryRegionOps boston_platreg_ops = {
250 .read = boston_platreg_read,
251 .write = boston_platreg_write,
252 .endianness = DEVICE_NATIVE_ENDIAN,
253};
254
255static void mips_boston_instance_init(Object *obj)
256{
257 BostonState *s = BOSTON(obj);
258
259 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk");
260 clock_set_hz(s->cpuclk, 1000000000);
261}
262
263static const TypeInfo boston_device = {
264 .name = TYPE_BOSTON,
265 .parent = TYPE_SYS_BUS_DEVICE,
266 .instance_size = sizeof(BostonState),
267 .instance_init = mips_boston_instance_init,
268};
269
270static void boston_register_types(void)
271{
272 type_register_static(&boston_device);
273}
274type_init(boston_register_types)
275
276static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
277{
278 const uint32_t cm_base = 0x16100000;
279 const uint32_t gic_base = 0x16120000;
280 const uint32_t cpc_base = 0x16200000;
281
282
283 bl_gen_write_ulong(&p,
284 cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS),
285 cm_base);
286
287
288 bl_gen_write_ulong(&p,
289 cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS),
290 gic_base | GCR_GIC_BASE_GICEN_MSK);
291
292
293 bl_gen_write_ulong(&p,
294 cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS),
295 cpc_base | GCR_CPC_BASE_CPCEN_MSK);
296
297
298
299
300
301
302
303
304
305 bl_gen_jump_kernel(&p, 0, (int32_t)-2, fdt_addr, 0, 0, kernel_entry);
306}
307
308static const void *boston_fdt_filter(void *opaque, const void *fdt_orig,
309 const void *match_data, hwaddr *load_addr)
310{
311 BostonState *s = BOSTON(opaque);
312 MachineState *machine = s->mach;
313 const char *cmdline;
314 int err;
315 size_t ram_low_sz, ram_high_sz;
316 size_t fdt_sz = fdt_totalsize(fdt_orig) * 2;
317 g_autofree void *fdt = g_malloc0(fdt_sz);
318
319 err = fdt_open_into(fdt_orig, fdt, fdt_sz);
320 if (err) {
321 fprintf(stderr, "unable to open FDT\n");
322 return NULL;
323 }
324
325 cmdline = (machine->kernel_cmdline && machine->kernel_cmdline[0])
326 ? machine->kernel_cmdline : " ";
327 err = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
328 if (err < 0) {
329 fprintf(stderr, "couldn't set /chosen/bootargs\n");
330 return NULL;
331 }
332
333 ram_low_sz = MIN(256 * MiB, machine->ram_size);
334 ram_high_sz = machine->ram_size - ram_low_sz;
335 qemu_fdt_setprop_sized_cells(fdt, "/memory@0", "reg",
336 1, 0x00000000, 1, ram_low_sz,
337 1, 0x90000000, 1, ram_high_sz);
338
339 fdt = g_realloc(fdt, fdt_totalsize(fdt));
340 qemu_fdt_dumpdtb(fdt, fdt_sz);
341
342 s->fdt_base = *load_addr;
343
344 return g_steal_pointer(&fdt);
345}
346
347static const void *boston_kernel_filter(void *opaque, const void *kernel,
348 hwaddr *load_addr, hwaddr *entry_addr)
349{
350 BostonState *s = BOSTON(opaque);
351
352 s->kernel_entry = *entry_addr;
353
354 return kernel;
355}
356
357static const struct fit_loader_match boston_matches[] = {
358 { "img,boston" },
359 { NULL },
360};
361
362static const struct fit_loader boston_fit_loader = {
363 .matches = boston_matches,
364 .addr_to_phys = cpu_mips_kseg0_to_phys,
365 .fdt_filter = boston_fdt_filter,
366 .kernel_filter = boston_kernel_filter,
367};
368
369static inline XilinxPCIEHost *
370xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,
371 hwaddr cfg_base, uint64_t cfg_size,
372 hwaddr mmio_base, uint64_t mmio_size,
373 qemu_irq irq, bool link_up)
374{
375 DeviceState *dev;
376 MemoryRegion *cfg, *mmio;
377
378 dev = qdev_new(TYPE_XILINX_PCIE_HOST);
379
380 qdev_prop_set_uint32(dev, "bus_nr", bus_nr);
381 qdev_prop_set_uint64(dev, "cfg_base", cfg_base);
382 qdev_prop_set_uint64(dev, "cfg_size", cfg_size);
383 qdev_prop_set_uint64(dev, "mmio_base", mmio_base);
384 qdev_prop_set_uint64(dev, "mmio_size", mmio_size);
385 qdev_prop_set_bit(dev, "link_up", link_up);
386
387 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
388
389 cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
390 memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);
391
392 mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
393 memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);
394
395 qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq);
396
397 return XILINX_PCIE_HOST(dev);
398}
399
400static void boston_mach_init(MachineState *machine)
401{
402 DeviceState *dev;
403 BostonState *s;
404 MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg;
405 MemoryRegion *sys_mem = get_system_memory();
406 XilinxPCIEHost *pcie2;
407 PCIDevice *ahci;
408 DriveInfo *hd[6];
409 Chardev *chr;
410 int fw_size, fit_err;
411
412 if ((machine->ram_size % GiB) ||
413 (machine->ram_size > (2 * GiB))) {
414 error_report("Memory size must be 1GB or 2GB");
415 exit(1);
416 }
417
418 dev = qdev_new(TYPE_BOSTON);
419 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
420
421 s = BOSTON(dev);
422 s->mach = machine;
423
424 if (!cpu_type_supports_cps_smp(machine->cpu_type)) {
425 error_report("Boston requires CPUs which support CPS");
426 exit(1);
427 }
428
429 object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS);
430 object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type,
431 &error_fatal);
432 object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus,
433 &error_fatal);
434 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in",
435 qdev_get_clock_out(dev, "cpu-refclk"));
436 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
437
438 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
439
440 flash = g_new(MemoryRegion, 1);
441 memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB,
442 &error_fatal);
443 memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0);
444
445 memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0);
446
447 ddr_low_alias = g_new(MemoryRegion, 1);
448 memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr",
449 machine->ram, 0,
450 MIN(machine->ram_size, (256 * MiB)));
451 memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0);
452
453 xilinx_pcie_init(sys_mem, 0,
454 0x10000000, 32 * MiB,
455 0x40000000, 1 * GiB,
456 get_cps_irq(&s->cps, 2), false);
457
458 xilinx_pcie_init(sys_mem, 1,
459 0x12000000, 32 * MiB,
460 0x20000000, 512 * MiB,
461 get_cps_irq(&s->cps, 1), false);
462
463 pcie2 = xilinx_pcie_init(sys_mem, 2,
464 0x14000000, 32 * MiB,
465 0x16000000, 1 * MiB,
466 get_cps_irq(&s->cps, 0), true);
467
468 platreg = g_new(MemoryRegion, 1);
469 memory_region_init_io(platreg, NULL, &boston_platreg_ops, s,
470 "boston-platregs", 0x1000);
471 memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0);
472
473 s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2,
474 get_cps_irq(&s->cps, 3), 10000000,
475 serial_hd(0), DEVICE_NATIVE_ENDIAN);
476
477 lcd = g_new(MemoryRegion, 1);
478 memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8);
479 memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0);
480
481 chr = qemu_chr_new("lcd", "vc:320x240", NULL);
482 qemu_chr_fe_init(&s->lcd_display, chr, NULL);
483 qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL,
484 boston_lcd_event, NULL, s, NULL, true);
485
486 ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus,
487 PCI_DEVFN(0, 0),
488 true, TYPE_ICH9_AHCI);
489 g_assert(ARRAY_SIZE(hd) == ahci_get_num_ports(ahci));
490 ide_drive_get(hd, ahci_get_num_ports(ahci));
491 ahci_ide_create_devs(ahci, hd);
492
493 if (machine->firmware) {
494 fw_size = load_image_targphys(machine->firmware,
495 0x1fc00000, 4 * MiB);
496 if (fw_size == -1) {
497 error_report("unable to load firmware image '%s'",
498 machine->firmware);
499 exit(1);
500 }
501 } else if (machine->kernel_filename) {
502 fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s);
503 if (fit_err) {
504 error_report("unable to load FIT image");
505 exit(1);
506 }
507
508 gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000,
509 s->kernel_entry, s->fdt_base);
510 } else if (!qtest_enabled()) {
511 error_report("Please provide either a -kernel or -bios argument");
512 exit(1);
513 }
514}
515
516static void boston_mach_class_init(MachineClass *mc)
517{
518 mc->desc = "MIPS Boston";
519 mc->init = boston_mach_init;
520 mc->block_default_type = IF_IDE;
521 mc->default_ram_size = 1 * GiB;
522 mc->default_ram_id = "boston.ddr";
523 mc->max_cpus = 16;
524 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400");
525}
526
527DEFINE_MACHINE("boston", boston_mach_class_init)
528
