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22#include "qemu/osdep.h"
23#include "hw/irq.h"
24#include "hw/block/flash.h"
25#include "hw/arm/omap.h"
26#include "exec/memory.h"
27#include "exec/address-spaces.h"
28
29
30struct omap_gpmc_s {
31 qemu_irq irq;
32 qemu_irq drq;
33 MemoryRegion iomem;
34 int accept_256;
35
36 uint8_t revision;
37 uint8_t sysconfig;
38 uint16_t irqst;
39 uint16_t irqen;
40 uint16_t lastirq;
41 uint16_t timeout;
42 uint16_t config;
43 struct omap_gpmc_cs_file_s {
44 uint32_t config[7];
45 MemoryRegion *iomem;
46 MemoryRegion container;
47 MemoryRegion nandiomem;
48 DeviceState *dev;
49 } cs_file[8];
50 int ecc_cs;
51 int ecc_ptr;
52 uint32_t ecc_cfg;
53 ECCState ecc[9];
54 struct prefetch {
55 uint32_t config1;
56 uint32_t transfercount;
57 int startengine;
58 int fifopointer;
59 int count;
60 MemoryRegion iomem;
61 uint8_t fifo[64];
62 } prefetch;
63};
64
65#define OMAP_GPMC_8BIT 0
66#define OMAP_GPMC_16BIT 1
67#define OMAP_GPMC_NOR 0
68#define OMAP_GPMC_NAND 2
69
70static int omap_gpmc_devtype(struct omap_gpmc_cs_file_s *f)
71{
72 return (f->config[0] >> 10) & 3;
73}
74
75static int omap_gpmc_devsize(struct omap_gpmc_cs_file_s *f)
76{
77
78
79
80
81 return (f->config[0] >> 12) & 1;
82}
83
84
85static int prefetch_cs(uint32_t config1)
86{
87 return (config1 >> 24) & 7;
88}
89
90static int prefetch_threshold(uint32_t config1)
91{
92 return (config1 >> 8) & 0x7f;
93}
94
95static void omap_gpmc_int_update(struct omap_gpmc_s *s)
96{
97
98
99
100
101
102
103
104
105
106 if (s->prefetch.fifopointer >= prefetch_threshold(s->prefetch.config1)) {
107 s->irqst |= 1;
108 }
109 if ((s->irqen & s->irqst) != s->lastirq) {
110 s->lastirq = s->irqen & s->irqst;
111 qemu_set_irq(s->irq, s->lastirq);
112 }
113}
114
115static void omap_gpmc_dma_update(struct omap_gpmc_s *s, int value)
116{
117 if (s->prefetch.config1 & 4) {
118 qemu_set_irq(s->drq, value);
119 }
120}
121
122
123
124
125
126static uint64_t omap_nand_read(void *opaque, hwaddr addr,
127 unsigned size)
128{
129 struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
130 uint64_t v;
131 nand_setpins(f->dev, 0, 0, 0, 1, 0);
132 switch (omap_gpmc_devsize(f)) {
133 case OMAP_GPMC_8BIT:
134 v = nand_getio(f->dev);
135 if (size == 1) {
136 return v;
137 }
138 v |= (nand_getio(f->dev) << 8);
139 if (size == 2) {
140 return v;
141 }
142 v |= (nand_getio(f->dev) << 16);
143 v |= (nand_getio(f->dev) << 24);
144 return v;
145 case OMAP_GPMC_16BIT:
146 v = nand_getio(f->dev);
147 if (size == 1) {
148
149 return v & 0xff;
150 }
151 if (size == 2) {
152 return v;
153 }
154 v |= (nand_getio(f->dev) << 16);
155 return v;
156 default:
157 abort();
158 }
159}
160
161static void omap_nand_setio(DeviceState *dev, uint64_t value,
162 int nandsize, int size)
163{
164
165
166
167 switch (nandsize) {
168 case OMAP_GPMC_8BIT:
169 switch (size) {
170 case 1:
171 nand_setio(dev, value & 0xff);
172 break;
173 case 2:
174 nand_setio(dev, value & 0xff);
175 nand_setio(dev, (value >> 8) & 0xff);
176 break;
177 case 4:
178 default:
179 nand_setio(dev, value & 0xff);
180 nand_setio(dev, (value >> 8) & 0xff);
181 nand_setio(dev, (value >> 16) & 0xff);
182 nand_setio(dev, (value >> 24) & 0xff);
183 break;
184 }
185 break;
186 case OMAP_GPMC_16BIT:
187 switch (size) {
188 case 1:
189
190
191
192 case 2:
193 nand_setio(dev, value & 0xffff);
194 break;
195 case 4:
196 default:
197 nand_setio(dev, value & 0xffff);
198 nand_setio(dev, (value >> 16) & 0xffff);
199 break;
200 }
201 break;
202 }
203}
204
205static void omap_nand_write(void *opaque, hwaddr addr,
206 uint64_t value, unsigned size)
207{
208 struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
209 nand_setpins(f->dev, 0, 0, 0, 1, 0);
210 omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
211}
212
213static const MemoryRegionOps omap_nand_ops = {
214 .read = omap_nand_read,
215 .write = omap_nand_write,
216 .endianness = DEVICE_NATIVE_ENDIAN,
217};
218
219static void fill_prefetch_fifo(struct omap_gpmc_s *s)
220{
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235 int fptr;
236 int cs = prefetch_cs(s->prefetch.config1);
237 int is16bit = (((s->cs_file[cs].config[0] >> 12) & 3) != 0);
238 int bytes;
239
240
241
242
243 bytes = 64 - s->prefetch.fifopointer;
244 if (bytes > s->prefetch.count) {
245 bytes = s->prefetch.count;
246 }
247 if (is16bit) {
248 bytes &= ~1;
249 }
250
251 s->prefetch.count -= bytes;
252 s->prefetch.fifopointer += bytes;
253 fptr = 64 - s->prefetch.fifopointer;
254
255
256
257 while (fptr < (64 - bytes)) {
258 s->prefetch.fifo[fptr] = s->prefetch.fifo[fptr + bytes];
259 fptr++;
260 }
261 while (fptr < 64) {
262 if (is16bit) {
263 uint32_t v = omap_nand_read(&s->cs_file[cs], 0, 2);
264 s->prefetch.fifo[fptr++] = v & 0xff;
265 s->prefetch.fifo[fptr++] = (v >> 8) & 0xff;
266 } else {
267 s->prefetch.fifo[fptr++] = omap_nand_read(&s->cs_file[cs], 0, 1);
268 }
269 }
270 if (s->prefetch.startengine && (s->prefetch.count == 0)) {
271
272 s->irqst |= 2;
273 s->prefetch.startengine = 0;
274 }
275
276
277
278
279
280 if (s->prefetch.fifopointer != 0) {
281 omap_gpmc_dma_update(s, 1);
282 }
283 omap_gpmc_int_update(s);
284}
285
286
287
288
289
290static uint64_t omap_gpmc_prefetch_read(void *opaque, hwaddr addr,
291 unsigned size)
292{
293 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
294 uint32_t data;
295 if (s->prefetch.config1 & 1) {
296
297
298
299
300 return 0;
301 }
302
303 if (s->prefetch.fifopointer) {
304 s->prefetch.fifopointer--;
305 }
306 data = s->prefetch.fifo[63 - s->prefetch.fifopointer];
307 if (s->prefetch.fifopointer ==
308 (64 - prefetch_threshold(s->prefetch.config1))) {
309
310
311
312
313 omap_gpmc_dma_update(s, 0);
314 fill_prefetch_fifo(s);
315 }
316 omap_gpmc_int_update(s);
317 return data;
318}
319
320static void omap_gpmc_prefetch_write(void *opaque, hwaddr addr,
321 uint64_t value, unsigned size)
322{
323 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
324 int cs = prefetch_cs(s->prefetch.config1);
325 if ((s->prefetch.config1 & 1) == 0) {
326
327
328
329
330 return;
331 }
332 if (s->prefetch.count == 0) {
333
334
335
336 return;
337 }
338
339
340
341
342
343 int is16bit = (((s->cs_file[cs].config[0] >> 12) & 3) != 0);
344 if (is16bit) {
345
346
347
348 if (s->prefetch.fifopointer == 64) {
349 s->prefetch.fifo[0] = value;
350 s->prefetch.fifopointer--;
351 } else {
352 value = (value << 8) | s->prefetch.fifo[0];
353 omap_nand_write(&s->cs_file[cs], 0, value, 2);
354 s->prefetch.count--;
355 s->prefetch.fifopointer = 64;
356 }
357 } else {
358
359 omap_nand_write(&s->cs_file[cs], 0, value, 1);
360 s->prefetch.count--;
361 }
362 if (s->prefetch.count == 0) {
363
364 s->irqst |= 2;
365 s->prefetch.startengine = 0;
366 }
367 omap_gpmc_int_update(s);
368}
369
370static const MemoryRegionOps omap_prefetch_ops = {
371 .read = omap_gpmc_prefetch_read,
372 .write = omap_gpmc_prefetch_write,
373 .endianness = DEVICE_NATIVE_ENDIAN,
374 .impl.min_access_size = 1,
375 .impl.max_access_size = 1,
376};
377
378static MemoryRegion *omap_gpmc_cs_memregion(struct omap_gpmc_s *s, int cs)
379{
380
381 struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
382 if (omap_gpmc_devtype(f) == OMAP_GPMC_NOR) {
383 return f->iomem;
384 }
385 if ((s->prefetch.config1 & 0x80) &&
386 (prefetch_cs(s->prefetch.config1) == cs)) {
387
388 return &s->prefetch.iomem;
389 }
390 return &f->nandiomem;
391}
392
393static void omap_gpmc_cs_map(struct omap_gpmc_s *s, int cs)
394{
395 struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
396 uint32_t mask = (f->config[6] >> 8) & 0xf;
397 uint32_t base = f->config[6] & 0x3f;
398 uint32_t size;
399
400 if (!f->iomem && !f->dev) {
401 return;
402 }
403
404 if (!(f->config[6] & (1 << 6))) {
405
406 return;
407 }
408
409
410 if (mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf
411 && !(s->accept_256 && !mask)) {
412 fprintf(stderr, "%s: invalid chip-select mask address (0x%x)\n",
413 __func__, mask);
414 }
415
416 base <<= 24;
417 size = (0x0fffffff & ~(mask << 24)) + 1;
418
419
420
421
422 memory_region_init(&f->container, NULL, "omap-gpmc-file", size);
423 memory_region_add_subregion(&f->container, 0,
424 omap_gpmc_cs_memregion(s, cs));
425 memory_region_add_subregion(get_system_memory(), base,
426 &f->container);
427}
428
429static void omap_gpmc_cs_unmap(struct omap_gpmc_s *s, int cs)
430{
431 struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
432 if (!(f->config[6] & (1 << 6))) {
433
434 return;
435 }
436 if (!f->iomem && !f->dev) {
437 return;
438 }
439 memory_region_del_subregion(get_system_memory(), &f->container);
440 memory_region_del_subregion(&f->container, omap_gpmc_cs_memregion(s, cs));
441 object_unparent(OBJECT(&f->container));
442}
443
444void omap_gpmc_reset(struct omap_gpmc_s *s)
445{
446 int i;
447
448 s->sysconfig = 0;
449 s->irqst = 0;
450 s->irqen = 0;
451 omap_gpmc_int_update(s);
452 for (i = 0; i < 8; i++) {
453
454
455
456 omap_gpmc_cs_unmap(s, i);
457 }
458 s->timeout = 0;
459 s->config = 0xa00;
460 s->prefetch.config1 = 0x00004000;
461 s->prefetch.transfercount = 0x00000000;
462 s->prefetch.startengine = 0;
463 s->prefetch.fifopointer = 0;
464 s->prefetch.count = 0;
465 for (i = 0; i < 8; i ++) {
466 s->cs_file[i].config[1] = 0x101001;
467 s->cs_file[i].config[2] = 0x020201;
468 s->cs_file[i].config[3] = 0x10031003;
469 s->cs_file[i].config[4] = 0x10f1111;
470 s->cs_file[i].config[5] = 0;
471 s->cs_file[i].config[6] = 0xf00;
472
473
474
475
476 if (i == 0) {
477 s->cs_file[i].config[0] &= 0x00433e00;
478 s->cs_file[i].config[6] |= 1 << 6;
479 omap_gpmc_cs_map(s, i);
480 } else {
481 s->cs_file[i].config[0] &= 0x00403c00;
482 }
483 }
484 s->ecc_cs = 0;
485 s->ecc_ptr = 0;
486 s->ecc_cfg = 0x3fcff000;
487 for (i = 0; i < 9; i ++)
488 ecc_reset(&s->ecc[i]);
489}
490
491static int gpmc_wordaccess_only(hwaddr addr)
492{
493
494
495
496
497
498 if (addr >= 0x60 && addr <= 0x1d4) {
499 int cs = (addr - 0x60) / 0x30;
500 addr -= cs * 0x30;
501 if (addr >= 0x7c && addr < 0x88) {
502
503 return 0;
504 }
505 }
506 return 1;
507}
508
509static uint64_t omap_gpmc_read(void *opaque, hwaddr addr,
510 unsigned size)
511{
512 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
513 int cs;
514 struct omap_gpmc_cs_file_s *f;
515
516 if (size != 4 && gpmc_wordaccess_only(addr)) {
517 return omap_badwidth_read32(opaque, addr);
518 }
519
520 switch (addr) {
521 case 0x000:
522 return s->revision;
523
524 case 0x010:
525 return s->sysconfig;
526
527 case 0x014:
528 return 1;
529
530 case 0x018:
531 return s->irqst;
532
533 case 0x01c:
534 return s->irqen;
535
536 case 0x040:
537 return s->timeout;
538
539 case 0x044:
540 case 0x048:
541 return 0;
542
543 case 0x050:
544 return s->config;
545
546 case 0x054:
547 return 0x001;
548
549 case 0x060 ... 0x1d4:
550 cs = (addr - 0x060) / 0x30;
551 addr -= cs * 0x30;
552 f = s->cs_file + cs;
553 switch (addr) {
554 case 0x60:
555 return f->config[0];
556 case 0x64:
557 return f->config[1];
558 case 0x68:
559 return f->config[2];
560 case 0x6c:
561 return f->config[3];
562 case 0x70:
563 return f->config[4];
564 case 0x74:
565 return f->config[5];
566 case 0x78:
567 return f->config[6];
568 case 0x84 ... 0x87:
569 if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
570 return omap_nand_read(f, 0, size);
571 }
572 return 0;
573 }
574 break;
575
576 case 0x1e0:
577 return s->prefetch.config1;
578 case 0x1e4:
579 return s->prefetch.transfercount;
580 case 0x1ec:
581 return s->prefetch.startengine;
582 case 0x1f0:
583
584
585
586
587
588
589
590 return (s->prefetch.fifopointer << 24) |
591 ((s->prefetch.fifopointer >=
592 ((s->prefetch.config1 >> 8) & 0x7f) ? 1 : 0) << 16) |
593 s->prefetch.count;
594
595 case 0x1f4:
596 return s->ecc_cs;
597 case 0x1f8:
598 return s->ecc_ptr;
599 case 0x1fc:
600 return s->ecc_cfg;
601 case 0x200 ... 0x220:
602 cs = (addr & 0x1f) >> 2;
603
604 return
605 ((s->ecc[cs].cp & 0x07) << 0) |
606 ((s->ecc[cs].cp & 0x38) << 13) |
607 ((s->ecc[cs].lp[0] & 0x1ff) << 3) |
608 ((s->ecc[cs].lp[1] & 0x1ff) << 19);
609
610 case 0x230:
611 return 0;
612 case 0x234:
613 case 0x238:
614 return 0x00000000;
615 }
616
617 OMAP_BAD_REG(addr);
618 return 0;
619}
620
621static void omap_gpmc_write(void *opaque, hwaddr addr,
622 uint64_t value, unsigned size)
623{
624 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
625 int cs;
626 struct omap_gpmc_cs_file_s *f;
627
628 if (size != 4 && gpmc_wordaccess_only(addr)) {
629 omap_badwidth_write32(opaque, addr, value);
630 return;
631 }
632
633 switch (addr) {
634 case 0x000:
635 case 0x014:
636 case 0x054:
637 case 0x1f0:
638 case 0x200 ... 0x220:
639 case 0x234:
640 case 0x238:
641 OMAP_RO_REG(addr);
642 break;
643
644 case 0x010:
645 if ((value >> 3) == 0x3)
646 fprintf(stderr, "%s: bad SDRAM idle mode %"PRIi64"\n",
647 __func__, value >> 3);
648 if (value & 2)
649 omap_gpmc_reset(s);
650 s->sysconfig = value & 0x19;
651 break;
652
653 case 0x018:
654 s->irqst &= ~value;
655 omap_gpmc_int_update(s);
656 break;
657
658 case 0x01c:
659 s->irqen = value & 0xf03;
660 omap_gpmc_int_update(s);
661 break;
662
663 case 0x040:
664 s->timeout = value & 0x1ff1;
665 break;
666
667 case 0x044:
668 case 0x048:
669 break;
670
671 case 0x050:
672 s->config = value & 0xf13;
673 break;
674
675 case 0x060 ... 0x1d4:
676 cs = (addr - 0x060) / 0x30;
677 addr -= cs * 0x30;
678 f = s->cs_file + cs;
679 switch (addr) {
680 case 0x60:
681 f->config[0] = value & 0xffef3e13;
682 break;
683 case 0x64:
684 f->config[1] = value & 0x001f1f8f;
685 break;
686 case 0x68:
687 f->config[2] = value & 0x001f1f8f;
688 break;
689 case 0x6c:
690 f->config[3] = value & 0x1f8f1f8f;
691 break;
692 case 0x70:
693 f->config[4] = value & 0x0f1f1f1f;
694 break;
695 case 0x74:
696 f->config[5] = value & 0x00000fcf;
697 break;
698 case 0x78:
699 if ((f->config[6] ^ value) & 0xf7f) {
700 omap_gpmc_cs_unmap(s, cs);
701 f->config[6] = value & 0x00000f7f;
702 omap_gpmc_cs_map(s, cs);
703 }
704 break;
705 case 0x7c ... 0x7f:
706 if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
707 nand_setpins(f->dev, 1, 0, 0, 1, 0);
708 omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
709 }
710 break;
711 case 0x80 ... 0x83:
712 if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
713 nand_setpins(f->dev, 0, 1, 0, 1, 0);
714 omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
715 }
716 break;
717 case 0x84 ... 0x87:
718 if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
719 omap_nand_write(f, 0, value, size);
720 }
721 break;
722 default:
723 goto bad_reg;
724 }
725 break;
726
727 case 0x1e0:
728 if (!s->prefetch.startengine) {
729 uint32_t newconfig1 = value & 0x7f8f7fbf;
730 uint32_t changed;
731 changed = newconfig1 ^ s->prefetch.config1;
732 if (changed & (0x80 | 0x7000000)) {
733
734
735
736
737
738
739
740
741 int oldcs = prefetch_cs(s->prefetch.config1);
742 int newcs = prefetch_cs(newconfig1);
743 omap_gpmc_cs_unmap(s, oldcs);
744 if (oldcs != newcs) {
745 omap_gpmc_cs_unmap(s, newcs);
746 }
747 s->prefetch.config1 = newconfig1;
748 omap_gpmc_cs_map(s, oldcs);
749 if (oldcs != newcs) {
750 omap_gpmc_cs_map(s, newcs);
751 }
752 } else {
753 s->prefetch.config1 = newconfig1;
754 }
755 }
756 break;
757
758 case 0x1e4:
759 if (!s->prefetch.startengine) {
760 s->prefetch.transfercount = value & 0x3fff;
761 }
762 break;
763
764 case 0x1ec:
765 if (s->prefetch.startengine != (value & 1)) {
766 s->prefetch.startengine = value & 1;
767 if (s->prefetch.startengine) {
768
769 s->prefetch.count = s->prefetch.transfercount;
770 if (s->prefetch.config1 & 1) {
771
772 s->prefetch.fifopointer = 64;
773 } else {
774
775 s->prefetch.fifopointer = 0;
776 fill_prefetch_fifo(s);
777 }
778 } else {
779
780
781
782
783
784
785
786 s->prefetch.count = 0;
787 }
788 omap_gpmc_int_update(s);
789 }
790 break;
791
792 case 0x1f4:
793 s->ecc_cs = 0x8f;
794 break;
795 case 0x1f8:
796 if (value & (1 << 8))
797 for (cs = 0; cs < 9; cs ++)
798 ecc_reset(&s->ecc[cs]);
799 s->ecc_ptr = value & 0xf;
800 if (s->ecc_ptr == 0 || s->ecc_ptr > 9) {
801 s->ecc_ptr = 0;
802 s->ecc_cs &= ~1;
803 }
804 break;
805 case 0x1fc:
806 s->ecc_cfg = value & 0x3fcff1ff;
807 break;
808 case 0x230:
809 if (value & 7)
810 fprintf(stderr, "%s: test mode enable attempt\n", __func__);
811 break;
812
813 default:
814 bad_reg:
815 OMAP_BAD_REG(addr);
816 return;
817 }
818}
819
820static const MemoryRegionOps omap_gpmc_ops = {
821 .read = omap_gpmc_read,
822 .write = omap_gpmc_write,
823 .endianness = DEVICE_NATIVE_ENDIAN,
824};
825
826struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
827 hwaddr base,
828 qemu_irq irq, qemu_irq drq)
829{
830 int cs;
831 struct omap_gpmc_s *s = g_new0(struct omap_gpmc_s, 1);
832
833 memory_region_init_io(&s->iomem, NULL, &omap_gpmc_ops, s, "omap-gpmc", 0x1000);
834 memory_region_add_subregion(get_system_memory(), base, &s->iomem);
835
836 s->irq = irq;
837 s->drq = drq;
838 s->accept_256 = cpu_is_omap3630(mpu);
839 s->revision = cpu_class_omap3(mpu) ? 0x50 : 0x20;
840 s->lastirq = 0;
841 omap_gpmc_reset(s);
842
843
844
845
846
847
848
849 for (cs = 0; cs < 8; cs++) {
850 memory_region_init_io(&s->cs_file[cs].nandiomem, NULL,
851 &omap_nand_ops,
852 &s->cs_file[cs],
853 "omap-nand",
854 256 * 1024 * 1024);
855 }
856
857 memory_region_init_io(&s->prefetch.iomem, NULL, &omap_prefetch_ops, s,
858 "omap-gpmc-prefetch", 256 * 1024 * 1024);
859 return s;
860}
861
862void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem)
863{
864 struct omap_gpmc_cs_file_s *f;
865 assert(iomem);
866
867 if (cs < 0 || cs >= 8) {
868 fprintf(stderr, "%s: bad chip-select %i\n", __func__, cs);
869 exit(-1);
870 }
871 f = &s->cs_file[cs];
872
873 omap_gpmc_cs_unmap(s, cs);
874 f->config[0] &= ~(0xf << 10);
875 f->iomem = iomem;
876 omap_gpmc_cs_map(s, cs);
877}
878
879void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand)
880{
881 struct omap_gpmc_cs_file_s *f;
882 assert(nand);
883
884 if (cs < 0 || cs >= 8) {
885 fprintf(stderr, "%s: bad chip-select %i\n", __func__, cs);
886 exit(-1);
887 }
888 f = &s->cs_file[cs];
889
890 omap_gpmc_cs_unmap(s, cs);
891 f->config[0] &= ~(0xf << 10);
892 f->config[0] |= (OMAP_GPMC_NAND << 10);
893 f->dev = nand;
894 if (nand_getbuswidth(f->dev) == 16) {
895 f->config[0] |= OMAP_GPMC_16BIT << 12;
896 }
897 omap_gpmc_cs_map(s, cs);
898}
899