LXR qemu/hw/misc/xilinx-serdes.c

   1/*
   2 * QEMU model of the SERDES t16ffllp
   3 *
   4 * Copyright (c) 2015 - 2019 Xilinx Inc.
   5 *
   6 * Autogenerated by xregqemu.py 2019-12-09.
   7 *
   8 * Permission is hereby granted, free of charge, to any person obtaining a copy
   9 * of this software and associated documentation files (the "Software"), to deal
  10 * in the Software without restriction, including without limitation the rights
  11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12 * copies of the Software, and to permit persons to whom the Software is
  13 * furnished to do so, subject to the following conditions:
  14 *
  15 * The above copyright notice and this permission notice shall be included in
  16 * all copies or substantial portions of the Software.
  17 *
  18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24 * THE SOFTWARE.
  25 */
  26
  27#include "qemu/osdep.h"
  28#include "hw/sysbus.h"
  29#include "hw/register.h"
  30#include "qemu/bitops.h"
  31#include "qemu/log.h"
  32#include "migration/vmstate.h"
  33#include "hw/qdev-properties.h"
  34
  35#ifndef XILINX_SERDES_ERR_DEBUG
  36#define XILINX_SERDES_ERR_DEBUG 0
  37#endif
  38
  39#define TYPE_XILINX_SERDES "xlnx.zynqmp-serdes"
  40
  41#define XILINX_SERDES(obj) \
  42     OBJECT_CHECK(SERDES, (obj), TYPE_XILINX_SERDES)
  43
  44REG32(L0_TX_ANA_TM_0, 0x0)
  45    FIELD(L0_TX_ANA_TM_0, TX_ANA_TM_0_31_8_RSVD, 24, 8)
  46    FIELD(L0_TX_ANA_TM_0, ANA_BYP0_7_6_RSVD, 6, 2)
  47    FIELD(L0_TX_ANA_TM_0, PIPE_TX_DN_RXDET, 5, 1)
  48    FIELD(L0_TX_ANA_TM_0, FORCE_PIPE_TX_DN_RXDET, 4, 1)
  49    FIELD(L0_TX_ANA_TM_0, PIPE_TX_DP_RXDET, 3, 1)
  50    FIELD(L0_TX_ANA_TM_0, FORCE_PIPE_TX_DP_RXDET, 2, 1)
  51    FIELD(L0_TX_ANA_TM_0, ANA_BYP0_1_0_RSVD, 0, 2)
  52REG32(L0_TX_ANA_TM_3, 0xc)
  53    FIELD(L0_TX_ANA_TM_3, TX_ANA_TM_3_31_8_RSVD, 24, 8)
  54    FIELD(L0_TX_ANA_TM_3, TX_HS_SER_RSTB, 7, 1)
  55    FIELD(L0_TX_ANA_TM_3, FORCE_TX_HS_SER_RSTB, 6, 1)
  56    FIELD(L0_TX_ANA_TM_3, TX_HS_BURST, 5, 1)
  57    FIELD(L0_TX_ANA_TM_3, FORCE_TX_HS_BURST, 4, 1)
  58    FIELD(L0_TX_ANA_TM_3, TX_SERIALIZER_ENABLE, 3, 1)
  59    FIELD(L0_TX_ANA_TM_3, FORCE_TX_SERIALIZER_ENABLE, 2, 1)
  60    FIELD(L0_TX_ANA_TM_3, TX_ENABLE_SUPPLY_SERIALIZER, 1, 1)
  61    FIELD(L0_TX_ANA_TM_3, FORCE_TX_ENABLE_SUPPLY_SERIALIZER, 0, 1)
  62REG32(L0_TX_ANA_TM_4, 0x10)
  63    FIELD(L0_TX_ANA_TM_4, TX_ANA_TM_4_31_8_RSVD, 24, 8)
  64    FIELD(L0_TX_ANA_TM_4, ANA_BYP4_7_RSVD, 7, 1)
  65    FIELD(L0_TX_ANA_TM_4, TX_LSEG_DN_RESCAL_CODE, 1, 6)
  66    FIELD(L0_TX_ANA_TM_4, FORCE_TX_LSEG_DN_RESCAL_CODE, 0, 1)
  67REG32(L0_TX_ANA_TM_5, 0x14)
  68    FIELD(L0_TX_ANA_TM_5, TX_ANA_TM_5_31_8_RSVD, 24, 8)
  69    FIELD(L0_TX_ANA_TM_5, ANA_BYP5_7_RSVD, 7, 1)
  70    FIELD(L0_TX_ANA_TM_5, TX_USEG_DP_RESCAL_CODE, 1, 6)
  71    FIELD(L0_TX_ANA_TM_5, FORCE_TX_USEG_DP_RESCAL_CODE, 0, 1)
  72REG32(L0_TX_ANA_TM_9, 0x24)
  73    FIELD(L0_TX_ANA_TM_9, TX_ANA_TM_9_31_8_RSVD, 24, 8)
  74    FIELD(L0_TX_ANA_TM_9, MPHY_TX_HS_SLEWRATE, 0, 8)
  75REG32(L0_TX_ANA_TM_10, 0x28)
  76    FIELD(L0_TX_ANA_TM_10, TX_ANA_TM_10_31_8_RSVD, 24, 8)
  77    FIELD(L0_TX_ANA_TM_10, MPHY_HS_POWERUP_TIME, 4, 4)
  78    FIELD(L0_TX_ANA_TM_10, MPHY_TX_HS_EQUALIZER_SETTING, 1, 3)
  79    FIELD(L0_TX_ANA_TM_10, FORCE_MPHY_TX_HS_EQUALIZER_SETTING, 0, 1)
  80REG32(L0_TX_ANA_TM_13, 0x34)
  81    FIELD(L0_TX_ANA_TM_13, TX_ANA_TM_13_31_8_RSVD, 24, 8)
  82    FIELD(L0_TX_ANA_TM_13, ANA_BYP13_7_4_RSVD, 4, 4)
  83    FIELD(L0_TX_ANA_TM_13, TX_SWAP_POLARITY, 3, 1)
  84    FIELD(L0_TX_ANA_TM_13, FORCE_TX_SWAP_POLARITY, 2, 1)
  85    FIELD(L0_TX_ANA_TM_13, MPHY_TX_TRISTATE, 1, 1)
  86    FIELD(L0_TX_ANA_TM_13, FORCE_MPHY_TX_TRISTATE, 0, 1)
  87REG32(L0_TX_ANA_TM_14, 0x38)
  88    FIELD(L0_TX_ANA_TM_14, TX_ANA_TM_14_31_8_RSVD, 24, 8)
  89    FIELD(L0_TX_ANA_TM_14, ANA_BYP14_7_6_RSVD, 6, 2)
  90    FIELD(L0_TX_ANA_TM_14, PIPE_TX_FAST_EST_COMMON_MODE, 5, 1)
  91    FIELD(L0_TX_ANA_TM_14, FORCE_PIPE_TX_FAST_EST_COMMON_MODE, 4, 1)
  92    FIELD(L0_TX_ANA_TM_14, ANA_BYP14_3_0_RSVD, 0, 4)
  93REG32(L0_TX_ANA_TM_15, 0x3c)
  94    FIELD(L0_TX_ANA_TM_15, TX_ANA_TM_15_31_8_RSVD, 24, 8)
  95    FIELD(L0_TX_ANA_TM_15, PIPE_TX_SWING, 7, 1)
  96    FIELD(L0_TX_ANA_TM_15, FORCE_PIPE_TX_SWING, 6, 1)
  97    FIELD(L0_TX_ANA_TM_15, PIPE_TX_RXDET_DISCHARGE, 5, 1)
  98    FIELD(L0_TX_ANA_TM_15, FORCE_PIPE_TX_RXDET_DISCHARGE, 4, 1)
  99    FIELD(L0_TX_ANA_TM_15, PIPE_TX_RXDET_CHARGE, 3, 1)
 100    FIELD(L0_TX_ANA_TM_15, FORCE_PIPE_TX_RXDET_CHARGE, 2, 1)
 101    FIELD(L0_TX_ANA_TM_15, PIPE_TX_ENABLE_RXDET, 1, 1)
 102    FIELD(L0_TX_ANA_TM_15, FORCE_PIPE_TX_ENABLE_RXDET, 0, 1)
 103REG32(L0_TX_ANA_TM_16, 0x40)
 104    FIELD(L0_TX_ANA_TM_16, TX_ANA_TM_16_31_8_RSVD, 24, 8)
 105    FIELD(L0_TX_ANA_TM_16, ANA_BYP16_7_4_RSVD, 4, 4)
 106    FIELD(L0_TX_ANA_TM_16, PIPE_TX_MARGIN, 1, 3)
 107    FIELD(L0_TX_ANA_TM_16, FORCE_PIPE_TX_MARGIN, 0, 1)
 108REG32(L0_TX_ANA_TM_18, 0x48)
 109    FIELD(L0_TX_ANA_TM_18, TX_ANA_TM_18_31_8_RSVD, 24, 8)
 110    FIELD(L0_TX_ANA_TM_18, PIPE_TX_DEEMPH_7_0, 0, 8)
 111REG32(L0_TX_ANA_TM_19, 0x4c)
 112    FIELD(L0_TX_ANA_TM_19, TX_ANA_TM_19_31_8_RSVD, 24, 8)
 113    FIELD(L0_TX_ANA_TM_19, PIPE_TX_DEEMPH_15_8, 0, 8)
 114REG32(L0_TX_ANA_TM_20, 0x50)
 115    FIELD(L0_TX_ANA_TM_20, TX_ANA_TM_20_31_8_RSVD, 24, 8)
 116    FIELD(L0_TX_ANA_TM_20, ANA_BYP20_7_5_RSVD, 5, 3)
 117    FIELD(L0_TX_ANA_TM_20, TX_SERIALIZER_RST_REL, 4, 1)
 118    FIELD(L0_TX_ANA_TM_20, FORCE_TX_SERIALIZER_RST_REL, 3, 1)
 119    FIELD(L0_TX_ANA_TM_20, FORCE_MPHY_TX_HS_SLEWRATE, 2, 1)
 120    FIELD(L0_TX_ANA_TM_20, PIPE_TX_DEEMPH_17_16, 0, 2)
 121REG32(L0_TX_ANA_TM_21, 0x54)
 122    FIELD(L0_TX_ANA_TM_21, TX_ANA_TM_21_31_8_RSVD, 24, 8)
 123    FIELD(L0_TX_ANA_TM_21, ANA_BYP21_7_6_RSVD, 6, 2)
 124    FIELD(L0_TX_ANA_TM_21, PIPE_TX_COEF_CALC_CLK, 5, 1)
 125    FIELD(L0_TX_ANA_TM_21, FORCE_PIPE_TX_COEF_CALC_CLK, 4, 1)
 126    FIELD(L0_TX_ANA_TM_21, PIPE_TX_COEF_CALC_FSM_RESET_B, 3, 1)
 127    FIELD(L0_TX_ANA_TM_21, FORCE_PIPE_TX_COEF_CALC_FSM_RESET_B, 2, 1)
 128    FIELD(L0_TX_ANA_TM_21, PIPE_TX_DEEMPH_CTRL_SEL, 1, 1)
 129    FIELD(L0_TX_ANA_TM_21, FORCE_PIPE_TX_DEEMPH_CTRL_SEL, 0, 1)
 130REG32(L0_TX_DIG_TM_61, 0xf4)
 131    FIELD(L0_TX_DIG_TM_61, TX_DIG_TM_61_31_8_RSVD, 24, 8)
 132    FIELD(L0_TX_DIG_TM_61, MPHY_PLL_GEAR, 6, 2)
 133    FIELD(L0_TX_DIG_TM_61, DIG_BYP1_5_4_RSVD, 4, 2)
 134    FIELD(L0_TX_DIG_TM_61, BYPASS_ENC, 3, 1)
 135    FIELD(L0_TX_DIG_TM_61, DIG_BYP1_2_RSVD, 2, 1)
 136    FIELD(L0_TX_DIG_TM_61, BYPASS_SCRAM, 1, 1)
 137    FIELD(L0_TX_DIG_TM_61, FORCE_BYPASS_SCRAM, 0, 1)
 138REG32(L0_TX_DIG_TM_62, 0xf8)
 139    FIELD(L0_TX_DIG_TM_62, TX_DIG_TM_62_31_8_RSVD, 24, 8)
 140    FIELD(L0_TX_DIG_TM_62, G0_BIT_PER_CNT, 0, 8)
 141REG32(L0_TX_DIG_TM_65, 0x104)
 142    FIELD(L0_TX_DIG_TM_65, TX_DIG_TM_65_31_8_RSVD, 24, 8)
 143    FIELD(L0_TX_DIG_TM_65, FORCE_TX_RXDET_PROBE_THRESHOLD, 7, 1)
 144    FIELD(L0_TX_DIG_TM_65, FORCE_TX_RXDET_END_CH_THRESHOLD, 6, 1)
 145    FIELD(L0_TX_DIG_TM_65, FORCE_TX_RXDET_START_CH_THRESHOLD, 5, 1)
 146    FIELD(L0_TX_DIG_TM_65, FORCE_TX_RXDET_END_DCH_THRESHOLD, 4, 1)
 147    FIELD(L0_TX_DIG_TM_65, FORCE_TX_RXDET_START_DCH_THRESHOLD, 3, 1)
 148    FIELD(L0_TX_DIG_TM_65, TX_EN_FULL_CALIB, 2, 1)
 149    FIELD(L0_TX_DIG_TM_65, FORCE_TX_EN_FULL_CALIB, 1, 1)
 150    FIELD(L0_TX_DIG_TM_65, DIG_BYP5_0_RSVD, 0, 1)
 151REG32(L0_TX_DIG_TM_67, 0x10c)
 152    FIELD(L0_TX_DIG_TM_67, TX_DIG_TM_67_31_8_RSVD, 24, 8)
 153    FIELD(L0_TX_DIG_TM_67, TX_MPHY_SER_THRESHOLD, 0, 8)
 154REG32(L0_TX_DIG_TM_68, 0x110)
 155    FIELD(L0_TX_DIG_TM_68, TX_DIG_TM_68_31_8_RSVD, 24, 8)
 156    FIELD(L0_TX_DIG_TM_68, TX_SER_SUP_THRESHOLD, 0, 8)
 157REG32(L0_TX_DIG_TM_69, 0x114)
 158    FIELD(L0_TX_DIG_TM_69, TX_DIG_TM_69_31_8_RSVD, 24, 8)
 159    FIELD(L0_TX_DIG_TM_69, TX_MPHY_SUP_THRESHOLD, 0, 8)
 160REG32(L0_TX_DIG_TM_76, 0x130)
 161    FIELD(L0_TX_DIG_TM_76, TX_DIG_TM_76_31_8_RSVD, 24, 8)
 162    FIELD(L0_TX_DIG_TM_76, TX_RXDET_START_DCH_THRESHOLD_7_0, 0, 8)
 163REG32(L0_TX_DIG_TM_77, 0x134)
 164    FIELD(L0_TX_DIG_TM_77, TX_DIG_TM_77_31_8_RSVD, 24, 8)
 165    FIELD(L0_TX_DIG_TM_77, TX_RXDET_END_DCH_THRESHOLD_11_8, 4, 4)
 166    FIELD(L0_TX_DIG_TM_77, TX_RXDET_START_DCH_THRESHOLD_11_8, 0, 4)
 167REG32(L0_TX_DIG_TM_78, 0x138)
 168    FIELD(L0_TX_DIG_TM_78, TX_DIG_TM_78_31_8_RSVD, 24, 8)
 169    FIELD(L0_TX_DIG_TM_78, TX_RXDET_END_DCH_THRESHOLD_7_0, 0, 8)
 170REG32(L0_TX_DIG_TM_79, 0x13c)
 171    FIELD(L0_TX_DIG_TM_79, TX_DIG_TM_79_31_8_RSVD, 24, 8)
 172    FIELD(L0_TX_DIG_TM_79, TX_RXDET_START_CH_THRESHOLD_7_0, 0, 8)
 173REG32(L0_TX_DIG_TM_80, 0x140)
 174    FIELD(L0_TX_DIG_TM_80, TX_DIG_TM_80_31_8_RSVD, 24, 8)
 175    FIELD(L0_TX_DIG_TM_80, TX_RXDET_END_CH_THRESHOLD_11_8, 4, 4)
 176    FIELD(L0_TX_DIG_TM_80, TX_RXDET_START_CH_THRESHOLD_11_8, 0, 4)
 177REG32(L0_TX_DIG_TM_81, 0x144)
 178    FIELD(L0_TX_DIG_TM_81, TX_DIG_TM_81_31_8_RSVD, 24, 8)
 179    FIELD(L0_TX_DIG_TM_81, TX_RXDET_END_CH_THRESHOLD_7_0, 0, 8)
 180REG32(L0_TX_DIG_TM_82, 0x148)
 181    FIELD(L0_TX_DIG_TM_82, TX_DIG_TM_82_31_8_RSVD, 24, 8)
 182    FIELD(L0_TX_DIG_TM_82, TX_RXDET_PROBE_THRESHOLD_7_0, 0, 8)
 183REG32(L0_TX_DIG_TM_83, 0x14c)
 184    FIELD(L0_TX_DIG_TM_83, TX_DIG_TM_83_31_8_RSVD, 24, 8)
 185    FIELD(L0_TX_DIG_TM_83, DIG_BYP23_7_4_RSVD, 4, 4)
 186    FIELD(L0_TX_DIG_TM_83, TX_RXDET_PROBE_THRESHOLD_11_8, 0, 4)
 187REG32(L0_TX_DIG_TM_84, 0x150)
 188    FIELD(L0_TX_DIG_TM_84, TX_DIG_TM_84_31_8_RSVD, 24, 8)
 189    FIELD(L0_TX_DIG_TM_84, TX_DIF_P, 7, 1)
 190    FIELD(L0_TX_DIG_TM_84, TX_DITHER_1P, 6, 1)
 191    FIELD(L0_TX_DIG_TM_84, TX_DITHER_1N, 5, 1)
 192    FIELD(L0_TX_DIG_TM_84, TX_DITHER_EN, 4, 1)
 193    FIELD(L0_TX_DIG_TM_84, DIG_BYP24_3_RSVD, 3, 1)
 194    FIELD(L0_TX_DIG_TM_84, TX_PHYDIRDY_SOC_MODE, 2, 1)
 195    FIELD(L0_TX_DIG_TM_84, DIG_BYP24_1_RSVD, 1, 1)
 196    FIELD(L0_TX_DIG_TM_84, TX_READ_SHADOW, 0, 1)
 197REG32(L0_TX_ANA_TM_85, 0x154)
 198    FIELD(L0_TX_ANA_TM_85, TX_ANA_TM_85_31_8_RSVD, 24, 8)
 199    FIELD(L0_TX_ANA_TM_85, DIG_BYP25_7_6_RSVD, 6, 2)
 200    FIELD(L0_TX_ANA_TM_85, TX_HIBERN8_CTRL, 5, 1)
 201    FIELD(L0_TX_ANA_TM_85, TX_ALLOW_INLNCFG_FROM_TOP, 4, 1)
 202    FIELD(L0_TX_ANA_TM_85, DIG_BYP25_3_RSVD, 3, 1)
 203    FIELD(L0_TX_ANA_TM_85, TX_SEND_MSB_FIRST, 2, 1)
 204    FIELD(L0_TX_ANA_TM_85, DIG_BYP25_1_RSVD, 1, 1)
 205    FIELD(L0_TX_ANA_TM_85, TX_DIF_N, 0, 1)
 206REG32(L0_TX_ANA_TM_87, 0x15c)
 207    FIELD(L0_TX_ANA_TM_87, TX_ANA_TM_87_31_8_RSVD, 24, 8)
 208    FIELD(L0_TX_ANA_TM_87, DIG_BYP27_7_4_RSVD, 4, 4)
 209    FIELD(L0_TX_ANA_TM_87, TX_SM_STATUS, 0, 4)
 210REG32(L0_TX_ANA_TM_88, 0x160)
 211    FIELD(L0_TX_ANA_TM_88, TX_ANA_TM_88_31_8_RSVD, 24, 8)
 212    FIELD(L0_TX_ANA_TM_88, TX_COMP_PAT_HIGH_TIME_REGS, 0, 8)
 213REG32(L0_TX_ANA_TM_89, 0x164)
 214    FIELD(L0_TX_ANA_TM_89, TX_ANA_TM_89_31_8_RSVD, 24, 8)
 215    FIELD(L0_TX_ANA_TM_89, DIG_BYP29_7_6_RSVD, 6, 2)
 216    FIELD(L0_TX_ANA_TM_89, TX_DATAPATH_CTRL_1_REGS, 5, 1)
 217    FIELD(L0_TX_ANA_TM_89, DIG_BYP29_4_3_RSVD, 3, 2)
 218    FIELD(L0_TX_ANA_TM_89, INITIAL_DISPARITY, 2, 1)
 219    FIELD(L0_TX_ANA_TM_89, SCRAMBLER_ENABLE, 1, 1)
 220    FIELD(L0_TX_ANA_TM_89, DIG_BYP29_0_RSVD, 0, 1)
 221REG32(L0_TX_ANA_TM_90, 0x168)
 222    FIELD(L0_TX_ANA_TM_90, TX_ANA_TM_90_31_8_RSVD, 24, 8)
 223    FIELD(L0_TX_ANA_TM_90, DIG_BYP30_7_6_RSVD, 6, 2)
 224    FIELD(L0_TX_ANA_TM_90, TX_BYPASS_BCNT_LPBACK_REGS, 5, 1)
 225    FIELD(L0_TX_ANA_TM_90, DIG_BYP30_4_0_RSVD, 0, 5)
 226REG32(L0_TX_DIG_TM_91, 0x16c)
 227    FIELD(L0_TX_DIG_TM_91, TX_DIG_TM_91_31_8_RSVD, 24, 8)
 228    FIELD(L0_TX_DIG_TM_91, TX_CFGCLK_FREQ, 0, 8)
 229REG32(L0_TX_DIG_TM_92, 0x170)
 230    FIELD(L0_TX_DIG_TM_92, TX_DIG_TM_92_31_8_RSVD, 24, 8)
 231    FIELD(L0_TX_DIG_TM_92, TX_PHYDIRDY_PULL_UP_LATENCY, 0, 8)
 232REG32(L0_TX_ANA_TM_95, 0x17c)
 233    FIELD(L0_TX_ANA_TM_95, TX_ANA_TM_95_31_8_RSVD, 24, 8)
 234    FIELD(L0_TX_ANA_TM_95, ANA_BYP63_7_6_RSVD, 6, 2)
 235    FIELD(L0_TX_ANA_TM_95, TX_TM_EN_PROG_SYNC_PATTERN, 5, 1)
 236    FIELD(L0_TX_ANA_TM_95, TX_EXTRA_HS_BURST_IN_LCC, 2, 3)
 237    FIELD(L0_TX_ANA_TM_95, ANA_BYP22_1_0_RSVD, 0, 2)
 238REG32(L0_TX_ANA_TM_96, 0x180)
 239    FIELD(L0_TX_ANA_TM_96, TX_ANA_TM_96_31_8_RSVD, 24, 8)
 240    FIELD(L0_TX_ANA_TM_96, TX_TM_PROG_SYNC_PATTERN1, 0, 8)
 241REG32(L0_TX_ANA_TM_97, 0x184)
 242    FIELD(L0_TX_ANA_TM_97, TX_ANA_TM_97_31_8_RSVD, 24, 8)
 243    FIELD(L0_TX_ANA_TM_97, TX_TM_PROG_SYNC_PATTERN2, 0, 8)
 244REG32(L0_TX_DIG_TM_98, 0x188)
 245    FIELD(L0_TX_DIG_TM_98, TX_DIG_TM_98_31_8_RSVD, 24, 8)
 246    FIELD(L0_TX_DIG_TM_98, DIG_BYP33_7_6_RSVD, 6, 2)
 247    FIELD(L0_TX_DIG_TM_98, FORCE_RD_VALUE, 5, 1)
 248    FIELD(L0_TX_DIG_TM_98, FORCE_RD, 4, 1)
 249    FIELD(L0_TX_DIG_TM_98, TX_SER_ISO_CTRL_BAR, 3, 1)
 250    FIELD(L0_TX_DIG_TM_98, FORCE_TX_SER_ISO_CTRL_BAR, 2, 1)
 251    FIELD(L0_TX_DIG_TM_98, TX_ISO_CTRL_BAR, 1, 1)
 252    FIELD(L0_TX_DIG_TM_98, FORCE_TX_ISO_CTRL_BAR, 0, 1)
 253REG32(L0_TX_DIG_TM_99, 0x18c)
 254    FIELD(L0_TX_DIG_TM_99, TX_DIG_TM_99_31_8_RSVD, 24, 8)
 255    FIELD(L0_TX_DIG_TM_99, TX_PIPE_SUPPLY_ENABLE_THRESHOLD, 0, 8)
 256REG32(L0_TX_DIG_TM_100, 0x190)
 257    FIELD(L0_TX_DIG_TM_100, TX_DIG_TM_100_31_8_RSVD, 24, 8)
 258    FIELD(L0_TX_DIG_TM_100, TX_SERIALISER_SUPPLY_ENABLE_THRESHOLD, 0, 8)
 259REG32(L0_TX_DIG_TM_101, 0x194)
 260    FIELD(L0_TX_DIG_TM_101, TX_DIG_TM_101_31_8_RSVD, 24, 8)
 261    FIELD(L0_TX_DIG_TM_101, TX_SERIALISER_ENABLE_THRESHOLD, 0, 8)
 262REG32(L0_TX_DIG_TM_102, 0x198)
 263    FIELD(L0_TX_DIG_TM_102, TX_DIG_TM_102_31_8_RSVD, 24, 8)
 264    FIELD(L0_TX_DIG_TM_102, FORCE_TX_ANA_LL_EN, 7, 1)
 265    FIELD(L0_TX_DIG_TM_102, TX_ANA_LL_EN, 6, 1)
 266    FIELD(L0_TX_DIG_TM_102, FORCE_DELAY_CNT_THRESHOLD, 5, 1)
 267    FIELD(L0_TX_DIG_TM_102, FORCE_TX_MPHY_TRST_THRESHOLD, 4, 1)
 268    FIELD(L0_TX_DIG_TM_102, FORCE_TX_LDO_THRESHOLD, 3, 1)
 269    FIELD(L0_TX_DIG_TM_102, FORCE_TX_SERIALISER_ENABLE_THRESHOLD, 2, 1)
 270    FIELD(L0_TX_DIG_TM_102, FORCE_TX_SERIALISER_SUPPLY_ENABLE_THRESHOLD, 1, 1)
 271    FIELD(L0_TX_DIG_TM_102, FORCE_TX_PIPE_SUPPLY_ENABLE_THRESHOLD, 0, 1)
 272REG32(L0_TX_DIG_TM_103, 0x19c)
 273    FIELD(L0_TX_DIG_TM_103, TX_DIG_TM_103_31_8_RSVD, 24, 8)
 274    FIELD(L0_TX_DIG_TM_103, FORCE_BG_EN, 7, 1)
 275    FIELD(L0_TX_DIG_TM_103, FORCE_CALIB_EN, 6, 1)
 276    FIELD(L0_TX_DIG_TM_103, FORCE_PLL_EN, 5, 1)
 277    FIELD(L0_TX_DIG_TM_103, FORCE_PSO, 4, 1)
 278    FIELD(L0_TX_DIG_TM_103, BG_EN, 3, 1)
 279    FIELD(L0_TX_DIG_TM_103, CALIB_EN, 2, 1)
 280    FIELD(L0_TX_DIG_TM_103, PLL_EN, 1, 1)
 281    FIELD(L0_TX_DIG_TM_103, PSO, 0, 1)
 282REG32(L0_TX_DIG_TM_104, 0x1a0)
 283    FIELD(L0_TX_DIG_TM_104, TX_DIG_TM_104_31_8_RSVD, 24, 8)
 284    FIELD(L0_TX_DIG_TM_104, TX_LDO_THRESHOLD, 0, 8)
 285REG32(L0_TX_DIG_TM_105, 0x1a4)
 286    FIELD(L0_TX_DIG_TM_105, TX_DIG_TM_105_31_8_RSVD, 24, 8)
 287    FIELD(L0_TX_DIG_TM_105, TX_MPHY_TRST_THRESHOLD, 0, 8)
 288REG32(L0_TX_DIG_TM_106, 0x1a8)
 289    FIELD(L0_TX_DIG_TM_106, TX_DIG_TM_106_31_8_RSVD, 24, 8)
 290    FIELD(L0_TX_DIG_TM_106, DELAY_CNT_THRESHOLD, 0, 8)
 291REG32(L0_TX_DIG_TM_107, 0x1ac)
 292    FIELD(L0_TX_DIG_TM_107, TX_DIG_TM_107_31_8_RSVD, 24, 8)
 293    FIELD(L0_TX_DIG_TM_107, DIG_BYP42_7_RSVD, 7, 1)
 294    FIELD(L0_TX_DIG_TM_107, FORCE_P3TOP0_PHYSTATUS_PULSE, 6, 1)
 295    FIELD(L0_TX_DIG_TM_107, ENABLE_HS_CLK_DIVISION, 5, 1)
 296    FIELD(L0_TX_DIG_TM_107, TESTDIGOUT_SEL, 1, 4)
 297    FIELD(L0_TX_DIG_TM_107, FORCE_TESTDIGOUT_SEL, 0, 1)
 298REG32(L0_TX_DIG_TM_108, 0x1b0)
 299    FIELD(L0_TX_DIG_TM_108, TX_DIG_TM_108_31_8_RSVD, 24, 8)
 300    FIELD(L0_TX_DIG_TM_108, ANA_BYP43_7_RSVD, 7, 1)
 301    FIELD(L0_TX_DIG_TM_108, TX_EXT_DATA_DELAY, 3, 4)
 302    FIELD(L0_TX_DIG_TM_108, FORCE_TX_EXT_DATA_DELAY, 2, 1)
 303    FIELD(L0_TX_DIG_TM_108, FORCE_TX_DATA_DELAY, 1, 1)
 304    FIELD(L0_TX_DIG_TM_108, FORCE_UPHY_TXPMA_OPMODE, 0, 1)
 305REG32(L0_TX_DIG_TM_109, 0x1b4)
 306    FIELD(L0_TX_DIG_TM_109, TX_DIG_TM_109_31_8_RSVD, 24, 8)
 307    FIELD(L0_TX_DIG_TM_109, UPHY_TXPMA_OPMODE, 0, 8)
 308REG32(L0_TX_DIG_TM_110, 0x1b8)
 309    FIELD(L0_TX_DIG_TM_110, TX_DIG_TM_110_31_8_RSVD, 24, 8)
 310    FIELD(L0_TX_DIG_TM_110, TX_DATA_DELAY, 0, 8)
 311REG32(L0_TX_DIG_TM_111, 0x1bc)
 312    FIELD(L0_TX_DIG_TM_111, TX_DIG_TM_111_31_8_RSVD, 24, 8)
 313    FIELD(L0_TX_DIG_TM_111, TX_DA_SPARE, 0, 8)
 314REG32(L0_TX_ANA_TM_112, 0x1c0)
 315    FIELD(L0_TX_ANA_TM_112, TX_ANA_TM_112_31_8_RSVD, 24, 8)
 316    FIELD(L0_TX_ANA_TM_112, ANA_BYP25_7_6_RSVD, 6, 2)
 317    FIELD(L0_TX_ANA_TM_112, PIPE_TX_ENABLE_LFPS, 4, 2)
 318    FIELD(L0_TX_ANA_TM_112, FORCE_PIPE_TX_ENABLE_LFPS, 3, 1)
 319    FIELD(L0_TX_ANA_TM_112, PIPE_TX_ENABLE_IDLE_MODE, 1, 2)
 320    FIELD(L0_TX_ANA_TM_112, FORCE_PIPE_TX_ENABLE_IDLE_MODE, 0, 1)
 321REG32(L0_TX_ANA_TM_113, 0x1c4)
 322    FIELD(L0_TX_ANA_TM_113, TX_ANA_TM_113_31_8_RSVD, 24, 8)
 323    FIELD(L0_TX_ANA_TM_113, MPHY_TX_DRIVERLDO_PROG, 0, 8)
 324REG32(L0_TX_ANA_TM_114, 0x1c8)
 325    FIELD(L0_TX_ANA_TM_114, TX_ANA_TM_114_31_8_RSVD, 24, 8)
 326    FIELD(L0_TX_ANA_TM_114, ANA_BYP27_7_5_RSVD, 5, 3)
 327    FIELD(L0_TX_ANA_TM_114, FORCE_MPHY_TX_DRIVERLDO_PROG, 4, 1)
 328    FIELD(L0_TX_ANA_TM_114, MPHY_TX_DRIVERLDO_PROG, 0, 4)
 329REG32(L0_TX_ANA_TM_115, 0x1cc)
 330    FIELD(L0_TX_ANA_TM_115, TX_ANA_TM_115_31_8_RSVD, 24, 8)
 331    FIELD(L0_TX_ANA_TM_115, ANA_BYP28_7_RSVD, 7, 1)
 332    FIELD(L0_TX_ANA_TM_115, PIPE_TX_GETLOCALPRESETCOEFFICIENTS, 6, 1)
 333    FIELD(L0_TX_ANA_TM_115, FORCE_PIPE_TX_GETLOCALPRESETCOEFFICIENTS, 5, 1)
 334    FIELD(L0_TX_ANA_TM_115, TX_PMADIG_DIGITAL_RESET_N, 4, 1)
 335    FIELD(L0_TX_ANA_TM_115, FORCE_TX_PMADIG_DIGITAL_RESET_N, 3, 1)
 336    FIELD(L0_TX_ANA_TM_115, TX_ANA_IF_RATE, 1, 2)
 337    FIELD(L0_TX_ANA_TM_115, FORCE_TX_ANA_IF_RATE, 0, 1)
 338REG32(L0_TX_ANA_TM_116, 0x1d0)
 339    FIELD(L0_TX_ANA_TM_116, TX_ANA_TM_116_31_8_RSVD, 24, 8)
 340    FIELD(L0_TX_ANA_TM_116, ANA_BYP29_7_RSVD, 7, 1)
 341    FIELD(L0_TX_ANA_TM_116, PIPE_TX_LOCALPRESETINDEX, 3, 4)
 342    FIELD(L0_TX_ANA_TM_116, FORCE_PIPE_TX_LOCALPRESETINDEX, 2, 1)
 343    FIELD(L0_TX_ANA_TM_116, MPHY_TX_EN_LANE_LS_CLK, 1, 1)
 344    FIELD(L0_TX_ANA_TM_116, FORCE_MPHY_TX_EN_LANE_LS_CLK, 0, 1)
 345REG32(L0_TX_ANA_TM_117, 0x1d4)
 346    FIELD(L0_TX_ANA_TM_117, TX_ANA_TM_117_31_8_RSVD, 24, 8)
 347    FIELD(L0_TX_ANA_TM_117, MULTILANE_BYP1_7_6_RSVD, 6, 2)
 348    FIELD(L0_TX_ANA_TM_117, TX_PCIE_4X_CFG_EN, 5, 1)
 349    FIELD(L0_TX_ANA_TM_117, FORCE_TX_PCIE_4X_CFG_EN, 4, 1)
 350    FIELD(L0_TX_ANA_TM_117, TX_PCIE_2X_CFG_EN, 3, 1)
 351    FIELD(L0_TX_ANA_TM_117, FORCE_TX_PCIE_2X_CFG_EN, 2, 1)
 352    FIELD(L0_TX_ANA_TM_117, TX_DP_MULTILANE_CFG_EN, 1, 1)
 353    FIELD(L0_TX_ANA_TM_117, FORCE_TX_DP_MULTILANE_CFG_EN, 0, 1)
 354REG32(L0_TX_ANA_TM_118, 0x1d8)
 355    FIELD(L0_TX_ANA_TM_118, TX_ANA_TM_118_31_8_RSVD, 24, 8)
 356    FIELD(L0_TX_ANA_TM_118, ANA_BYP30_7_4_RSVD, 4, 4)
 357    FIELD(L0_TX_ANA_TM_118, FORCE_TX_DEEMPH_17_12, 3, 1)
 358    FIELD(L0_TX_ANA_TM_118, FORCE_TX_DEEMPH_11_6, 2, 1)
 359    FIELD(L0_TX_ANA_TM_118, FORCE_TX_DEEMPH_5_0, 1, 1)
 360    FIELD(L0_TX_ANA_TM_118, FORCE_TX_DEEMPH_17_0, 0, 1)
 361REG32(L0_TXPMA_TM_0, 0x800)
 362    FIELD(L0_TXPMA_TM_0, TXPMA_TM_0_31_8_RSVD, 24, 8)
 363    FIELD(L0_TXPMA_TM_0, TM_TX_ENABLE_SUPPLY_MPHY, 7, 1)
 364    FIELD(L0_TXPMA_TM_0, TM_FORCE_TX_ENABLE_SUPPLY_MPHY, 6, 1)
 365    FIELD(L0_TXPMA_TM_0, TM_MPHY_TX_ENABLE_SUPPLY_LS_CLOCK, 5, 1)
 366    FIELD(L0_TXPMA_TM_0, TM_FORCE_MPHY_TX_ENABLE_SUPPLY_LS_CLOCK, 4, 1)
 367    FIELD(L0_TXPMA_TM_0, TM_MPHY_TX_ENABLE_SA_MODE, 3, 1)
 368    FIELD(L0_TXPMA_TM_0, TM_FORCE_MPHY_TX_ENABLE_SA_MODE, 2, 1)
 369    FIELD(L0_TXPMA_TM_0, TM_MPHY_TX_ENABLE_HS_NT, 1, 1)
 370    FIELD(L0_TXPMA_TM_0, TM_FORCE_MPHY_TX_ENABLE_HS_NT, 0, 1)
 371REG32(L0_TXPMA_TM_1, 0x804)
 372    FIELD(L0_TXPMA_TM_1, TXPMA_TM_1_31_8_RSVD, 24, 8)
 373    FIELD(L0_TXPMA_TM_1, ANA_MPHY_BYP1_7_4_RSVD, 4, 4)
 374    FIELD(L0_TXPMA_TM_1, TM_MPHY_TX_HS_DITHER_VAL, 1, 3)
 375    FIELD(L0_TXPMA_TM_1, TM_FORCE_MPHY_TX_HS_DITHER_VAL, 0, 1)
 376REG32(L0_TXPMA_TM_2, 0x808)
 377    FIELD(L0_TXPMA_TM_2, TXPMA_TM_2_31_8_RSVD, 24, 8)
 378    FIELD(L0_TXPMA_TM_2, TM_MPHY_TX_DRIVERLDO_PROG_6_0, 1, 7)
 379    FIELD(L0_TXPMA_TM_2, TM_FORCE_MPHY_TX_DRIVERLDO_PROG, 0, 1)
 380REG32(L0_TXPMA_TM_3, 0x80c)
 381    FIELD(L0_TXPMA_TM_3, TXPMA_TM_3_31_8_RSVD, 24, 8)
 382    FIELD(L0_TXPMA_TM_3, ANA_MPHY_BYP3_7_5_RSVD, 5, 3)
 383    FIELD(L0_TXPMA_TM_3, TM_MPHY_TX_DRIVERLDO_PROG_11_7, 0, 5)
 384REG32(L0_TXPMA_TM_4, 0x810)
 385    FIELD(L0_TXPMA_TM_4, TXPMA_TM_4_31_8_RSVD, 24, 8)
 386    FIELD(L0_TXPMA_TM_4, TM_PIPE_TX_TX_DATA_WIDTH, 5, 3)
 387    FIELD(L0_TXPMA_TM_4, TM_FORCE_PIPE_TX_TX_DATA_WIDTH, 4, 1)
 388    FIELD(L0_TXPMA_TM_4, TM_PIPE_TX_POWERDOWN_VCM_HOLD, 3, 1)
 389    FIELD(L0_TXPMA_TM_4, TM_FORCE_PIPE_TX_POWERDOWN_VCM_HOLD, 2, 1)
 390    FIELD(L0_TXPMA_TM_4, TM_PIPE_TX_ANABOOST_POWERDOWN, 1, 1)
 391    FIELD(L0_TXPMA_TM_4, ANA_PIPE_BYP0_0_RSVD, 0, 1)
 392REG32(L0_TXPMA_TM_5, 0x814)
 393    FIELD(L0_TXPMA_TM_5, TXPMA_TM_5_31_8_RSVD, 24, 8)
 394    FIELD(L0_TXPMA_TM_5, ANA_BSCAN_BYP0_7_4_RSVD, 4, 4)
 395    FIELD(L0_TXPMA_TM_5, TM_TX_BSCAN_SEL, 3, 1)
 396    FIELD(L0_TXPMA_TM_5, TM_FORCE_TX_BSCAN_SEL, 2, 1)
 397    FIELD(L0_TXPMA_TM_5, TM_TX_BSCAN_DATA, 1, 1)
 398    FIELD(L0_TXPMA_TM_5, TM_FORCE_TX_BSCAN_DATA, 0, 1)
 399REG32(L0_TXPMA_TM_6, 0x818)
 400    FIELD(L0_TXPMA_TM_6, TXPMA_TM_6_31_8_RSVD, 24, 8)
 401    FIELD(L0_TXPMA_TM_6, TM_TX_ENABLE_ISI_LPBK, 7, 1)
 402    FIELD(L0_TXPMA_TM_6, TM_FORCE_TX_ENABLE_ISI_LPBK, 6, 1)
 403    FIELD(L0_TXPMA_TM_6, TM_TX_ENABLE_SER_LPBK, 5, 1)
 404    FIELD(L0_TXPMA_TM_6, TM_FORCE_TX_ENABLE_SER_LPBK, 4, 1)
 405    FIELD(L0_TXPMA_TM_6, TM_TX_ENABLE_RX_LIN_LPBK, 3, 1)
 406    FIELD(L0_TXPMA_TM_6, TM_FORCE_TX_ENABLE_RX_LIN_LPBK, 2, 1)
 407    FIELD(L0_TXPMA_TM_6, TM_TX_ENABLE_RCRVD_DATA_LPBK, 1, 1)
 408    FIELD(L0_TXPMA_TM_6, TM_FORCE_TX_ENABLE_RCRVD_DATA_LPBK, 0, 1)
 409REG32(L0_TXPMA_TM_7, 0x81c)
 410    FIELD(L0_TXPMA_TM_7, TXPMA_TM_7_31_8_RSVD, 24, 8)
 411    FIELD(L0_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_UPHY, 7, 1)
 412    FIELD(L0_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_UPHY, 6, 1)
 413    FIELD(L0_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_SERIALIZER, 5, 1)
 414    FIELD(L0_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_SERIALIZER, 4, 1)
 415    FIELD(L0_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_PIPE, 3, 1)
 416    FIELD(L0_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_PIPE, 2, 1)
 417    FIELD(L0_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_HSCLK, 1, 1)
 418    FIELD(L0_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_HSCLK, 0, 1)
 419REG32(L0_TXPMA_TM_8, 0x820)
 420    FIELD(L0_TXPMA_TM_8, TXPMA_TM_8_31_8_RSVD, 24, 8)
 421    FIELD(L0_TXPMA_TM_8, ANA_LS_LFPS_BYP0_7_2_RSVD, 2, 6)
 422    FIELD(L0_TXPMA_TM_8, TM_TX_LS_LFPS_DATA, 1, 1)
 423    FIELD(L0_TXPMA_TM_8, TM_FORCE_TX_LS_LFPS_DATA, 0, 1)
 424REG32(L0_TXPMA_TM_9, 0x824)
 425    FIELD(L0_TXPMA_TM_9, TXPMA_TM_9_31_8_RSVD, 24, 8)
 426    FIELD(L0_TXPMA_TM_9, ANA_MISC0_7_RSVD, 7, 1)
 427    FIELD(L0_TXPMA_TM_9, TM_TX_SERIALIZER_MODE, 6, 1)
 428    FIELD(L0_TXPMA_TM_9, TM_FORCE_TX_SERIALIZER_MODE, 5, 1)
 429    FIELD(L0_TXPMA_TM_9, TM_TX_ENABLE_HSCLK_DIVISION, 3, 2)
 430    FIELD(L0_TXPMA_TM_9, TM_FORCE_TX_ENABLE_HSCLK_DIVISION, 2, 1)
 431    FIELD(L0_TXPMA_TM_9, TM_TX_DRIVER_POLARITY, 1, 1)
 432    FIELD(L0_TXPMA_TM_9, TM_FORCE_TX_DRIVER_POLARITY, 0, 1)
 433REG32(L0_TXPMA_TM_10, 0x828)
 434    FIELD(L0_TXPMA_TM_10, TXPMA_TM_10_31_8_RSVD, 24, 8)
 435    FIELD(L0_TXPMA_TM_10, ANA_MISC1_7_6_RSVD, 6, 2)
 436    FIELD(L0_TXPMA_TM_10, TM_TX_ENABLE_LOWLEAKAGE, 5, 1)
 437    FIELD(L0_TXPMA_TM_10, TM_FORCE_TX_ENABLE_LOWLEAKAGE, 4, 1)
 438    FIELD(L0_TXPMA_TM_10, TM_TX_ENABLE_REF, 3, 1)
 439    FIELD(L0_TXPMA_TM_10, TM_FORCE_TX_ENABLE_REF, 2, 1)
 440    FIELD(L0_TXPMA_TM_10, TM_TX_ENABLE_LDO, 1, 1)
 441    FIELD(L0_TXPMA_TM_10, TM_FORCE_TX_ENABLE_LDO, 0, 1)
 442REG32(L0_TXPMA_TM_11, 0x82c)
 443    FIELD(L0_TXPMA_TM_11, TXPMA_TM_11_31_8_RSVD, 24, 8)
 444    FIELD(L0_TXPMA_TM_11, ANA_VCM_BYP0_7_5_RSVD, 5, 3)
 445    FIELD(L0_TXPMA_TM_11, TM_TX_VCMHOLD_PROG, 1, 4)
 446    FIELD(L0_TXPMA_TM_11, TM_TX_VCMHOLD_OBSRV, 0, 1)
 447REG32(L0_TXPMA_TM_12, 0x830)
 448    FIELD(L0_TXPMA_TM_12, TXPMA_TM_12_31_8_RSVD, 24, 8)
 449    FIELD(L0_TXPMA_TM_12, TM_TX_SER_POWERISLAND_OBSRV, 5, 3)
 450    FIELD(L0_TXPMA_TM_12, TM_TX_CLK_POWERISLAND_OBSRV, 1, 4)
 451    FIELD(L0_TXPMA_TM_12, ANA_PWR_ISLAND_BYP0_0_RSVD, 0, 1)
 452REG32(L0_TXPMA_TM_13, 0x834)
 453    FIELD(L0_TXPMA_TM_13, TXPMA_TM_13_31_8_RSVD, 24, 8)
 454    FIELD(L0_TXPMA_TM_13, TM_TX_POWERISLAND_OBSRV, 0, 8)
 455REG32(L0_TXPMA_TM_14, 0x838)
 456    FIELD(L0_TXPMA_TM_14, TXPMA_TM_14_31_8_RSVD, 24, 8)
 457    FIELD(L0_TXPMA_TM_14, ANA_MISC2_7_5_RSVD, 5, 3)
 458    FIELD(L0_TXPMA_TM_14, TM_TX_POWERISLAND_OBSRV, 3, 2)
 459    FIELD(L0_TXPMA_TM_14, PIPE_TM_TX_ANABOOST_POWER_OBSRV, 2, 1)
 460    FIELD(L0_TXPMA_TM_14, MPHY_TM_TX_ENABLE_DRIVERLDO_OBSRV, 1, 1)
 461    FIELD(L0_TXPMA_TM_14, MPHY_TM_TX_DRIVERLDO_REDC_SINKIQ, 0, 1)
 462REG32(L0_TXPMA_TM_15, 0x83c)
 463    FIELD(L0_TXPMA_TM_15, TXPMA_TM_15_31_8_RSVD, 24, 8)
 464    FIELD(L0_TXPMA_TM_15, PIPE_TM_TX_ANABOOST_PROG_7_0, 0, 8)
 465REG32(L0_TXPMA_TM_16, 0x840)
 466    FIELD(L0_TXPMA_TM_16, TXPMA_TM_16_31_8_RSVD, 24, 8)
 467    FIELD(L0_TXPMA_TM_16, PIPE_TM_TX_ANABOOST_PROG_15_8, 0, 8)
 468REG32(L0_TXPMA_TM_17, 0x844)
 469    FIELD(L0_TXPMA_TM_17, TXPMA_TM_17_31_8_RSVD, 24, 8)
 470    FIELD(L0_TXPMA_TM_17, TM_TX_RSVD2, 0, 8)
 471REG32(L0_TXPMA_TM_18, 0x848)
 472    FIELD(L0_TXPMA_TM_18, TXPMA_TM_18_31_8_RSVD, 24, 8)
 473    FIELD(L0_TXPMA_TM_18, TM_TX_ENABLE_VDDREF_CORE, 7, 1)
 474    FIELD(L0_TXPMA_TM_18, TM_FORCE_TX_ENABLE_VDDREF_CORE, 6, 1)
 475    FIELD(L0_TXPMA_TM_18, TM_TX_ENABLE_RBYRFB_CORE, 5, 1)
 476    FIELD(L0_TXPMA_TM_18, TM_FORCE_TX_ENABLE_RBYRFB_CORE, 4, 1)
 477    FIELD(L0_TXPMA_TM_18, TM_TX_ENABLE_BGREF_CORE, 3, 1)
 478    FIELD(L0_TXPMA_TM_18, TM_FORCE_TX_ENABLE_BGREF_CORE, 2, 1)
 479    FIELD(L0_TXPMA_TM_18, TM_TX_ENABLE_BGFB_CORE, 1, 1)
 480    FIELD(L0_TXPMA_TM_18, TM_FORCE_TX_ENABLE_BGFB_CORE, 0, 1)
 481REG32(L0_TXPMA_TM_19, 0x84c)
 482    FIELD(L0_TXPMA_TM_19, TXPMA_TM_19_31_8_RSVD, 24, 8)
 483    FIELD(L0_TXPMA_TM_19, ANA_SATA_BYP0_RSVD, 6, 2)
 484    FIELD(L0_TXPMA_TM_19, TM_ZDIF_TX_SATA_OFFSET, 0, 6)
 485REG32(L0_TXPMA_TM_20, 0x850)
 486    FIELD(L0_TXPMA_TM_20, TXPMA_TM_20_31_8_RSVD, 24, 8)
 487    FIELD(L0_TXPMA_TM_20, TM_TX_ELEC_IDLE_DELAY_ENTRY, 0, 8)
 488REG32(L0_TXPMA_TM_21, 0x854)
 489    FIELD(L0_TXPMA_TM_21, TXPMA_TM_21_31_8_RSVD, 24, 8)
 490    FIELD(L0_TXPMA_TM_21, TM_TX_ELEC_IDLE_DELAY_EXIT, 0, 8)
 491REG32(L0_TXPMA_TM_22, 0x858)
 492    FIELD(L0_TXPMA_TM_22, TXPMA_TM_22_31_8_RSVD, 24, 8)
 493    FIELD(L0_TXPMA_TM_22, TM_TX_ENABLE_LFPS_DELAY_ENTRY, 0, 8)
 494REG32(L0_TXPMA_TM_23, 0x85c)
 495    FIELD(L0_TXPMA_TM_23, TXPMA_TM_23_31_8_RSVD, 24, 8)
 496    FIELD(L0_TXPMA_TM_23, TM_TX_ENABLE_LFPS_DELAY_EXIT, 0, 8)
 497REG32(L0_TXPMA_TM_24, 0x860)
 498    FIELD(L0_TXPMA_TM_24, TXPMA_TM_24_31_8_RSVD, 24, 8)
 499    FIELD(L0_TXPMA_TM_24, ANA_MISC6_7_RSVD, 7, 1)
 500    FIELD(L0_TXPMA_TM_24, TM_TX_EN_ANA_SUBLP_MODE, 6, 1)
 501    FIELD(L0_TXPMA_TM_24, TM_FORCE_TX_EN_ANA_SUBLP_MODE, 5, 1)
 502    FIELD(L0_TXPMA_TM_24, TM_TX_EN_DIG_SUBLP_MODE, 4, 1)
 503    FIELD(L0_TXPMA_TM_24, TM_FORCE_TX_EN_DIG_SUBLP_MODE, 3, 1)
 504    FIELD(L0_TXPMA_TM_24, TM_TX_DP_LVLDB0_OVRRD, 2, 1)
 505    FIELD(L0_TXPMA_TM_24, TM_FORCE_TX_DP_LVLDB0_OVRRD, 1, 1)
 506    FIELD(L0_TXPMA_TM_24, TM_TX_CLOCK_STOP_REQ, 0, 1)
 507REG32(L0_TXPMA_TM_25, 0x864)
 508    FIELD(L0_TXPMA_TM_25, TXPMA_TM_25_31_8_RSVD, 24, 8)
 509    FIELD(L0_TXPMA_TM_25, ANA_MISC6_7_6_RSVD, 6, 2)
 510    FIELD(L0_TXPMA_TM_25, TM_TX_WRRD_SYNC_SUP_OBSRV_PLL, 5, 1)
 511    FIELD(L0_TXPMA_TM_25, TM_TX_WRRD_SYNC_SUP_OBSRV_RX, 4, 1)
 512    FIELD(L0_TXPMA_TM_25, TM_TX_LANE_LNG, 3, 1)
 513    FIELD(L0_TXPMA_TM_25, TM_FORCE_TX_LANE_LNG, 2, 1)
 514    FIELD(L0_TXPMA_TM_25, TM_TX_LANE_MASTER, 1, 1)
 515    FIELD(L0_TXPMA_TM_25, TM_FORCE_TX_LANE_MASTER, 0, 1)
 516REG32(L0_TXPMA_TM_26, 0x868)
 517    FIELD(L0_TXPMA_TM_26, TXPMA_TM_26_31_8_RSVD, 24, 8)
 518    FIELD(L0_TXPMA_TM_26, TM_TXPMD_APB_RESET_DELAY, 0, 8)
 519REG32(L0_TXPMA_TM_27, 0x86c)
 520    FIELD(L0_TXPMA_TM_27, TXPMA_TM_27_31_8_RSVD, 24, 8)
 521    FIELD(L0_TXPMA_TM_27, TM_BSCAN_MODE_EN, 7, 1)
 522    FIELD(L0_TXPMA_TM_27, TM_FORCE_BSCAN_MODE_EN, 6, 1)
 523    FIELD(L0_TXPMA_TM_27, TM_PIPE_TX_FAST_EST_COMMON_MODE, 5, 1)
 524    FIELD(L0_TXPMA_TM_27, TM_FORCE_PIPE_TX_FAST_EST_COMMON_MODE, 4, 1)
 525    FIELD(L0_TXPMA_TM_27, TM_TX_PIPE_TX_ENABLE_LFPS, 3, 1)
 526    FIELD(L0_TXPMA_TM_27, TM_FORCE_TX_PIPE_TX_ENABLE_LFPS, 2, 1)
 527    FIELD(L0_TXPMA_TM_27, TM_TX_PIPE_TX_ENABLE_IDLE_MODE, 1, 1)
 528    FIELD(L0_TXPMA_TM_27, TM_FORCE_TX_PIPE_TX_ENABLE_IDLE_MODE, 0, 1)
 529REG32(L0_TXPMA_ST_0, 0xb00)
 530    FIELD(L0_TXPMA_ST_0, TXPMA_ST_0_31_8_RSVD, 24, 8)
 531    FIELD(L0_TXPMA_ST_0, TX_PHY_MODE, 4, 4)
 532    FIELD(L0_TXPMA_ST_0, TX_PHY_GEAR, 0, 4)
 533REG32(L0_TXPMA_ST_1, 0xb04)
 534    FIELD(L0_TXPMA_ST_1, TXPMA_ST_1_31_8_RSVD, 24, 8)
 535    FIELD(L0_TXPMA_ST_1, TX_ENABLE_HSCLK_DIVISION, 6, 2)
 536    FIELD(L0_TXPMA_ST_1, PIPE_TX_TRISTATE, 5, 1)
 537    FIELD(L0_TXPMA_ST_1, TX_ENABLE_SUPPLY_SERIALIZER, 4, 1)
 538    FIELD(L0_TXPMA_ST_1, TX_ENABLE_SUPPLY_HSCLK, 3, 1)
 539    FIELD(L0_TXPMA_ST_1, TX_ENABLE_SUPPLY_MPHY, 2, 1)
 540    FIELD(L0_TXPMA_ST_1, TX_ENABLE_SUPPLY_PIPE, 1, 1)
 541    FIELD(L0_TXPMA_ST_1, TX_ENABLE_SUPPLY_UPHY, 0, 1)
 542REG32(L0_TXPMA_ST_2, 0xb08)
 543    FIELD(L0_TXPMA_ST_2, TXPMA_ST_2_31_8_RSVD, 24, 8)
 544    FIELD(L0_TXPMA_ST_2, ANA_ST2_7_5_SPARE, 5, 3)
 545    FIELD(L0_TXPMA_ST_2, PIPE_TX_ENABLE_RXDET, 4, 1)
 546    FIELD(L0_TXPMA_ST_2, PIPE_TX_ENABLE_IDLE_MODE, 2, 2)
 547    FIELD(L0_TXPMA_ST_2, PIPE_TX_ENABLE_LFPS, 0, 2)
 548REG32(L0_TXPMA_ST_3, 0xb0c)
 549    FIELD(L0_TXPMA_ST_3, TXPMA_ST_3_31_8_RSVD, 24, 8)
 550    FIELD(L0_TXPMA_ST_3, ANA_ST3_7_6_SPARE, 6, 2)
 551    FIELD(L0_TXPMA_ST_3, TX_LSEG_DN_RESCAL_CODE, 0, 6)
 552REG32(L0_TXPMA_ST_4, 0xb10)
 553    FIELD(L0_TXPMA_ST_4, TXPMA_ST_4_31_8_RSVD, 24, 8)
 554    FIELD(L0_TXPMA_ST_4, ANA_ST4_7_6_SPARE, 6, 2)
 555    FIELD(L0_TXPMA_ST_4, TX_USEG_DP_RESCAL_CODE, 0, 6)
 556REG32(L0_TXPMA_ST_5, 0xb14)
 557    FIELD(L0_TXPMA_ST_5, TXPMA_ST_5_31_8_RSVD, 24, 8)
 558    FIELD(L0_TXPMA_ST_5, ANA_ST5_7_6_SPARE, 6, 2)
 559    FIELD(L0_TXPMA_ST_5, PIPE_TX_LOCALFS, 0, 6)
 560REG32(L0_TXPMA_ST_6, 0xb18)
 561    FIELD(L0_TXPMA_ST_6, TXPMA_ST_6_31_8_RSVD, 24, 8)
 562    FIELD(L0_TXPMA_ST_6, ANA_ST6_7_SPARE, 7, 1)
 563    FIELD(L0_TXPMA_ST_6, PIPE_TX_LOCALTXCOEFFICIENTSVALID, 6, 1)
 564    FIELD(L0_TXPMA_ST_6, PIPE_TX_LOCALLF, 0, 6)
 565REG32(L0_TXPMA_ST_7, 0xb1c)
 566    FIELD(L0_TXPMA_ST_7, TXPMA_ST_7_31_8_RSVD, 24, 8)
 567    FIELD(L0_TXPMA_ST_7, PIPE_TX_LOCALTXPRESETCOEFFICIENTS_7_0, 0, 8)
 568REG32(L0_TXPMA_ST_8, 0xb20)
 569    FIELD(L0_TXPMA_ST_8, TXPMA_ST_8_31_8_RSVD, 24, 8)
 570    FIELD(L0_TXPMA_ST_8, PIPE_TX_LOCALTXPRESETCOEFFICIENTS_15_8, 0, 8)
 571REG32(L0_TXPMA_ST_9, 0xb24)
 572    FIELD(L0_TXPMA_ST_9, TXPMA_ST_9_31_8_RSVD, 24, 8)
 573    FIELD(L0_TXPMA_ST_9, ANA_ST9_7_2_SPARE, 2, 6)
 574    FIELD(L0_TXPMA_ST_9, PIPE_TX_LOCALTXPRESETCOEFFICIENTS_17_16, 0, 2)
 575REG32(L0_TXPMD_TM_0, 0xc00)
 576    FIELD(L0_TXPMD_TM_0, TXPMD_TM_0_31_8_RSVD, 24, 8)
 577    FIELD(L0_TXPMD_TM_0, PIPE_TM_TX_USEG_POST_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
 578    FIELD(L0_TXPMD_TM_0, PIPE_TM_TX_USEG_POST_DISABLE_ENDPOS, 0, 5)
 579REG32(L0_TXPMD_TM_1, 0xc04)
 580    FIELD(L0_TXPMD_TM_1, TXPMD_TM_1_31_8_RSVD, 24, 8)
 581    FIELD(L0_TXPMD_TM_1, PIPE_TM_TX_USEG_POST_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
 582    FIELD(L0_TXPMD_TM_1, PIPE_TM_TX_USEG_POST_DISABLE_STARTPOS, 0, 5)
 583REG32(L0_TXPMD_TM_2, 0xc08)
 584    FIELD(L0_TXPMD_TM_2, TXPMD_TM_2_31_8_RSVD, 24, 8)
 585    FIELD(L0_TXPMD_TM_2, PIPE_TM_TX_USEG_POST_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
 586    FIELD(L0_TXPMD_TM_2, PIPE_TM_TX_USEG_POST_EMPHASIS_ENDPOS, 0, 5)
 587REG32(L0_TXPMD_TM_3, 0xc0c)
 588    FIELD(L0_TXPMD_TM_3, TXPMD_TM_3_31_8_RSVD, 24, 8)
 589    FIELD(L0_TXPMD_TM_3, PIPE_TM_TX_USEG_POST_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
 590    FIELD(L0_TXPMD_TM_3, PIPE_TM_TX_USEG_POST_EMPHASIS_STARTPOS, 0, 5)
 591REG32(L0_TXPMD_TM_4, 0xc10)
 592    FIELD(L0_TXPMD_TM_4, TXPMD_TM_4_31_8_RSVD, 24, 8)
 593    FIELD(L0_TXPMD_TM_4, PIPE_TM_TX_USEG_POST_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
 594    FIELD(L0_TXPMD_TM_4, PIPE_TM_TX_USEG_POST_MAINSEL_ENDPOS, 0, 5)
 595REG32(L0_TXPMD_TM_5, 0xc14)
 596    FIELD(L0_TXPMD_TM_5, TXPMD_TM_5_31_8_RSVD, 24, 8)
 597    FIELD(L0_TXPMD_TM_5, PIPE_TM_TX_USEG_POST_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
 598    FIELD(L0_TXPMD_TM_5, PIPE_TM_TX_USEG_POST_MAINSEL_STARTPOS, 0, 5)
 599REG32(L0_TXPMD_TM_6, 0xc18)
 600    FIELD(L0_TXPMD_TM_6, TXPMD_TM_6_31_8_RSVD, 24, 8)
 601    FIELD(L0_TXPMD_TM_6, PIPE_TM_TX_USEG_POST_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
 602    FIELD(L0_TXPMD_TM_6, PIPE_TM_TX_USEG_POST_MARGIN_ENDPOS, 0, 5)
 603REG32(L0_TXPMD_TM_7, 0xc1c)
 604    FIELD(L0_TXPMD_TM_7, TXPMD_TM_7_31_8_RSVD, 24, 8)
 605    FIELD(L0_TXPMD_TM_7, PIPE_TM_TX_USEG_POST_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
 606    FIELD(L0_TXPMD_TM_7, PIPE_TM_TX_USEG_POST_MARGIN_STARTPOS, 0, 5)
 607REG32(L0_TXPMD_TM_8, 0xc20)
 608    FIELD(L0_TXPMD_TM_8, TXPMD_TM_8_31_8_RSVD, 24, 8)
 609    FIELD(L0_TXPMD_TM_8, PIPE_TM_TX_USEG_PRE_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
 610    FIELD(L0_TXPMD_TM_8, PIPE_TM_TX_USEG_PRE_DISABLE_ENDPOS, 0, 5)
 611REG32(L0_TXPMD_TM_9, 0xc24)
 612    FIELD(L0_TXPMD_TM_9, TXPMD_TM_9_31_8_RSVD, 24, 8)
 613    FIELD(L0_TXPMD_TM_9, PIPE_TM_TX_USEG_PRE_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
 614    FIELD(L0_TXPMD_TM_9, PIPE_TM_TX_USEG_PRE_DISABLE_STARTPOS, 0, 5)
 615REG32(L0_TXPMD_TM_10, 0xc28)
 616    FIELD(L0_TXPMD_TM_10, TXPMD_TM_10_31_8_RSVD, 24, 8)
 617    FIELD(L0_TXPMD_TM_10, PIPE_TM_TX_USEG_PRE_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
 618    FIELD(L0_TXPMD_TM_10, PIPE_TM_TX_USEG_PRE_EMPHASIS_ENDPOS, 0, 5)
 619REG32(L0_TXPMD_TM_11, 0xc2c)
 620    FIELD(L0_TXPMD_TM_11, TXPMD_TM_11_31_8_RSVD, 24, 8)
 621    FIELD(L0_TXPMD_TM_11, PIPE_TM_TX_USEG_PRE_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
 622    FIELD(L0_TXPMD_TM_11, PIPE_TM_TX_USEG_PRE_EMPHASIS_STARTPOS, 0, 5)
 623REG32(L0_TXPMD_TM_12, 0xc30)
 624    FIELD(L0_TXPMD_TM_12, TXPMD_TM_12_31_8_RSVD, 24, 8)
 625    FIELD(L0_TXPMD_TM_12, PIPE_TM_TX_USEG_PRE_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
 626    FIELD(L0_TXPMD_TM_12, PIPE_TM_TX_USEG_PRE_MAINSEL_ENDPOS, 0, 5)
 627REG32(L0_TXPMD_TM_13, 0xc34)
 628    FIELD(L0_TXPMD_TM_13, TXPMD_TM_13_31_8_RSVD, 24, 8)
 629    FIELD(L0_TXPMD_TM_13, PIPE_TM_TX_USEG_PRE_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
 630    FIELD(L0_TXPMD_TM_13, PIPE_TM_TX_USEG_PRE_MAINSEL_STARTPOS, 0, 5)
 631REG32(L0_TXPMD_TM_14, 0xc38)
 632    FIELD(L0_TXPMD_TM_14, TXPMD_TM_14_31_8_RSVD, 24, 8)
 633    FIELD(L0_TXPMD_TM_14, PIPE_TM_TX_USEG_PRE_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
 634    FIELD(L0_TXPMD_TM_14, PIPE_TM_TX_USEG_PRE_MARGIN_ENDPOS, 0, 5)
 635REG32(L0_TXPMD_TM_15, 0xc3c)
 636    FIELD(L0_TXPMD_TM_15, TXPMD_TM_15_31_8_RSVD, 24, 8)
 637    FIELD(L0_TXPMD_TM_15, PIPE_TM_TX_USEG_PRE_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
 638    FIELD(L0_TXPMD_TM_15, PIPE_TM_TX_USEG_PRE_MARGIN_STARTPOS, 0, 5)
 639REG32(L0_TXPMD_TM_16, 0xc40)
 640    FIELD(L0_TXPMD_TM_16, TXPMD_TM_16_31_8_RSVD, 24, 8)
 641    FIELD(L0_TXPMD_TM_16, PIPE_TM_TX_LSEG_POST_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
 642    FIELD(L0_TXPMD_TM_16, PIPE_TM_TX_LSEG_POST_DISABLE_ENDPOS, 0, 5)
 643REG32(L0_TXPMD_TM_17, 0xc44)
 644    FIELD(L0_TXPMD_TM_17, TXPMD_TM_17_31_8_RSVD, 24, 8)
 645    FIELD(L0_TXPMD_TM_17, PIPE_TM_TX_LSEG_POST_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
 646    FIELD(L0_TXPMD_TM_17, PIPE_TM_TX_LSEG_POST_DISABLE_STARTPOS, 0, 5)
 647REG32(L0_TXPMD_TM_18, 0xc48)
 648    FIELD(L0_TXPMD_TM_18, TXPMD_TM_18_31_8_RSVD, 24, 8)
 649    FIELD(L0_TXPMD_TM_18, PIPE_TM_TX_LSEG_POST_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
 650    FIELD(L0_TXPMD_TM_18, PIPE_TM_TX_LSEG_POST_EMPHASIS_ENDPOS, 0, 5)
 651REG32(L0_TXPMD_TM_19, 0xc4c)
 652    FIELD(L0_TXPMD_TM_19, TXPMD_TM_19_31_8_RSVD, 24, 8)
 653    FIELD(L0_TXPMD_TM_19, PIPE_TM_TX_LSEG_POST_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
 654    FIELD(L0_TXPMD_TM_19, PIPE_TM_TX_LSEG_POST_EMPHASIS_STARTPOS, 0, 5)
 655REG32(L0_TXPMD_TM_20, 0xc50)
 656    FIELD(L0_TXPMD_TM_20, TXPMD_TM_20_31_8_RSVD, 24, 8)
 657    FIELD(L0_TXPMD_TM_20, PIPE_TM_TX_LSEG_POST_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
 658    FIELD(L0_TXPMD_TM_20, PIPE_TM_TX_LSEG_POST_MAINSEL_ENDPOS, 0, 5)
 659REG32(L0_TXPMD_TM_21, 0xc54)
 660    FIELD(L0_TXPMD_TM_21, TXPMD_TM_21_31_8_RSVD, 24, 8)
 661    FIELD(L0_TXPMD_TM_21, PIPE_TM_TX_LSEG_POST_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
 662    FIELD(L0_TXPMD_TM_21, PIPE_TM_TX_LSEG_POST_MAINSEL_STARTPOS, 0, 5)
 663REG32(L0_TXPMD_TM_22, 0xc58)
 664    FIELD(L0_TXPMD_TM_22, TXPMD_TM_22_31_8_RSVD, 24, 8)
 665    FIELD(L0_TXPMD_TM_22, PIPE_TM_TX_LSEG_POST_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
 666    FIELD(L0_TXPMD_TM_22, PIPE_TM_TX_LSEG_POST_MARGIN_ENDPOS, 0, 5)
 667REG32(L0_TXPMD_TM_23, 0xc5c)
 668    FIELD(L0_TXPMD_TM_23, TXPMD_TM_23_31_8_RSVD, 24, 8)
 669    FIELD(L0_TXPMD_TM_23, PIPE_TM_TX_LSEG_POST_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
 670    FIELD(L0_TXPMD_TM_23, PIPE_TM_TX_LSEG_POST_MARGIN_STARTPOS, 0, 5)
 671REG32(L0_TXPMD_TM_24, 0xc60)
 672    FIELD(L0_TXPMD_TM_24, TXPMD_TM_24_31_8_RSVD, 24, 8)
 673    FIELD(L0_TXPMD_TM_24, PIPE_TM_TX_LSEG_PRE_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
 674    FIELD(L0_TXPMD_TM_24, PIPE_TM_TX_LSEG_PRE_DISABLE_ENDPOS, 0, 5)
 675REG32(L0_TXPMD_TM_25, 0xc64)
 676    FIELD(L0_TXPMD_TM_25, TXPMD_TM_25_31_8_RSVD, 24, 8)
 677    FIELD(L0_TXPMD_TM_25, PIPE_TM_TX_LSEG_PRE_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
 678    FIELD(L0_TXPMD_TM_25, PIPE_TM_TX_LSEG_PRE_DISABLE_STARTPOS, 0, 5)
 679REG32(L0_TXPMD_TM_26, 0xc68)
 680    FIELD(L0_TXPMD_TM_26, TXPMD_TM_26_31_8_RSVD, 24, 8)
 681    FIELD(L0_TXPMD_TM_26, PIPE_TM_TX_LSEG_PRE_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
 682    FIELD(L0_TXPMD_TM_26, PIPE_TM_TX_LSEG_PRE_EMPHASIS_ENDPOS, 0, 5)
 683REG32(L0_TXPMD_TM_27, 0xc6c)
 684    FIELD(L0_TXPMD_TM_27, TXPMD_TM_27_31_8_RSVD, 24, 8)
 685    FIELD(L0_TXPMD_TM_27, PIPE_TM_TX_LSEG_PRE_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
 686    FIELD(L0_TXPMD_TM_27, PIPE_TM_TX_LSEG_PRE_EMPHASIS_STARTPOS, 0, 5)
 687REG32(L0_TXPMD_TM_28, 0xc70)
 688    FIELD(L0_TXPMD_TM_28, TXPMD_TM_28_31_8_RSVD, 24, 8)
 689    FIELD(L0_TXPMD_TM_28, PIPE_TM_TX_LSEG_PRE_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
 690    FIELD(L0_TXPMD_TM_28, PIPE_TM_TX_LSEG_PRE_MAINSEL_ENDPOS, 0, 5)
 691REG32(L0_TXPMD_TM_29, 0xc74)
 692    FIELD(L0_TXPMD_TM_29, TXPMD_TM_29_31_8_RSVD, 24, 8)
 693    FIELD(L0_TXPMD_TM_29, PIPE_TM_TX_LSEG_PRE_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
 694    FIELD(L0_TXPMD_TM_29, PIPE_TM_TX_LSEG_PRE_MAINSEL_STARTPOS, 0, 5)
 695REG32(L0_TXPMD_TM_30, 0xc78)
 696    FIELD(L0_TXPMD_TM_30, TXPMD_TM_30_31_8_RSVD, 24, 8)
 697    FIELD(L0_TXPMD_TM_30, PIPE_TM_TX_LSEG_PRE_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
 698    FIELD(L0_TXPMD_TM_30, PIPE_TM_TX_LSEG_PRE_MARGIN_ENDPOS, 0, 5)
 699REG32(L0_TXPMD_TM_31, 0xc7c)
 700    FIELD(L0_TXPMD_TM_31, TXPMD_TM_31_31_8_RSVD, 24, 8)
 701    FIELD(L0_TXPMD_TM_31, PIPE_TM_TX_LSEG_PRE_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
 702    FIELD(L0_TXPMD_TM_31, PIPE_TM_TX_LSEG_PRE_MARGIN_STARTPOS, 0, 5)
 703REG32(L0_TXPMD_TM_32, 0xc80)
 704    FIELD(L0_TXPMD_TM_32, TXPMD_TM_32_31_8_RSVD, 24, 8)
 705    FIELD(L0_TXPMD_TM_32, PIPE_TM_TX_PRE_FS_DIVISION_COEF_7_0, 0, 8)
 706REG32(L0_TXPMD_TM_33, 0xc84)
 707    FIELD(L0_TXPMD_TM_33, TXPMD_TM_33_31_8_RSVD, 24, 8)
 708    FIELD(L0_TXPMD_TM_33, PIPE_TM_TX_PRE_FS_DIVISION_COEF_15_8, 0, 8)
 709REG32(L0_TXPMD_TM_34, 0xc88)
 710    FIELD(L0_TXPMD_TM_34, TXPMD_TM_34_31_8_RSVD, 24, 8)
 711    FIELD(L0_TXPMD_TM_34, PIPE_TM_TX_MAIN_FS_DIVISION_COEF_7_0, 0, 8)
 712REG32(L0_TXPMD_TM_35, 0xc8c)
 713    FIELD(L0_TXPMD_TM_35, TXPMD_TM_35_31_8_RSVD, 24, 8)
 714    FIELD(L0_TXPMD_TM_35, PIPE_TM_TX_MAIN_FS_DIVISION_COEF_15_8, 0, 8)
 715REG32(L0_TXPMD_TM_36, 0xc90)
 716    FIELD(L0_TXPMD_TM_36, TXPMD_TM_36_31_8_RSVD, 24, 8)
 717    FIELD(L0_TXPMD_TM_36, PIPE_TM_TX_POST_FS_DIVISION_COEF_7_0, 0, 8)
 718REG32(L0_TXPMD_TM_37, 0xc94)
 719    FIELD(L0_TXPMD_TM_37, TXPMD_TM_37_31_8_RSVD, 24, 8)
 720    FIELD(L0_TXPMD_TM_37, PIPE_TM_TX_POST_FS_DIVISION_COEF_15_8, 0, 8)
 721REG32(L0_TXPMD_TM_38, 0xc98)
 722    FIELD(L0_TXPMD_TM_38, TXPMD_TM_38_31_8_RSVD, 24, 8)
 723    FIELD(L0_TXPMD_TM_38, ANA_MISC0_7_RSVD, 7, 1)
 724    FIELD(L0_TXPMD_TM_38, PIPE_TM_TX_ENABLE_SWNW_CNTRL_BYP, 6, 1)
 725    FIELD(L0_TXPMD_TM_38, PIPE_TM_TX_ENABLE_TRISTATE_BYP, 5, 1)
 726    FIELD(L0_TXPMD_TM_38, PIPE_TM_TX_TRISTATE, 4, 1)
 727    FIELD(L0_TXPMD_TM_38, TM_TX_DRIVERLDO_RXDET_BYP, 3, 1)
 728    FIELD(L0_TXPMD_TM_38, TM_TX_DRIVERLDO_IDLE_BYP, 2, 1)
 729    FIELD(L0_TXPMD_TM_38, TM_TX_DRIVERLDO_EN_RXDET_BYP, 1, 1)
 730    FIELD(L0_TXPMD_TM_38, TM_TX_DRIVERLDO_EN_IDLE_BYP, 0, 1)
 731REG32(L0_TXPMD_TM_39, 0xc9c)
 732    FIELD(L0_TXPMD_TM_39, TXPMD_TM_39_31_8_RSVD, 24, 8)
 733    FIELD(L0_TXPMD_TM_39, ANA_MPHY_BYP0_7_3_RSVD, 3, 5)
 734    FIELD(L0_TXPMD_TM_39, MPHY_TM_TX_OVRD_DEEMPH_TRIM, 2, 1)
 735    FIELD(L0_TXPMD_TM_39, MPHY_TM_TX_ENABLE_DEEMPH, 1, 1)
 736    FIELD(L0_TXPMD_TM_39, MPHY_TM_TX_OVRD_ENABLE_DEEMPH, 0, 1)
 737REG32(L0_TXPMD_TM_40, 0xca0)
 738    FIELD(L0_TXPMD_TM_40, TXPMD_TM_40_31_8_RSVD, 24, 8)
 739    FIELD(L0_TXPMD_TM_40, MPHY_TM_TX_DEEMPH_TRIM_7_0, 0, 8)
 740REG32(L0_TXPMD_TM_41, 0xca4)
 741    FIELD(L0_TXPMD_TM_41, TXPMD_TM_41_31_8_RSVD, 24, 8)
 742    FIELD(L0_TXPMD_TM_41, MPHY_TM_TX_DEEMPH_TRIM_15_8, 0, 8)
 743REG32(L0_TXPMD_TM_42, 0xca8)
 744    FIELD(L0_TXPMD_TM_42, TXPMD_TM_42_31_8_RSVD, 24, 8)
 745    FIELD(L0_TXPMD_TM_42, ANA_MPHY_BYP3_7_5_RSVD, 5, 3)
 746    FIELD(L0_TXPMD_TM_42, MPHY_TM_TX_OVRD_LS_DATA, 1, 4)
 747    FIELD(L0_TXPMD_TM_42, MPHY_TM_TX_ENABLE_OVRD_LS_DATA, 0, 1)
 748REG32(L0_TXPMD_TM_43, 0xcac)
 749    FIELD(L0_TXPMD_TM_43, TXPMD_TM_43_31_8_RSVD, 24, 8)
 750    FIELD(L0_TXPMD_TM_43, ANA_MPHY_BYP4_7_4_RSVD, 4, 4)
 751    FIELD(L0_TXPMD_TM_43, MPHY_TM_TX_OVRD_LS_DATA_BAR, 0, 4)
 752REG32(L0_TXPMD_TM_44, 0xcb0)
 753    FIELD(L0_TXPMD_TM_44, TXPMD_TM_44_31_8_RSVD, 24, 8)
 754    FIELD(L0_TXPMD_TM_44, ANA_PIPE_BYP38_7_6_RSVD, 6, 2)
 755    FIELD(L0_TXPMD_TM_44, PIPE_TM_TX_EN_PRE_LFPS_PATH, 5, 1)
 756    FIELD(L0_TXPMD_TM_44, PIPE_TM_TX_OVRD_EN_PRE_LFPS_PATH, 4, 1)
 757    FIELD(L0_TXPMD_TM_44, PIPE_TM_TX_EN_POST_LFPS_PATH, 3, 1)
 758    FIELD(L0_TXPMD_TM_44, PIPE_TM_TX_OVRD_EN_POST_LFPS_PATH, 2, 1)
 759    FIELD(L0_TXPMD_TM_44, PIPE_TM_TX_EN_MAIN_LFPS_PATH, 1, 1)
 760    FIELD(L0_TXPMD_TM_44, PIPE_TM_TX_OVRD_EN_MAIN_LFPS_PATH, 0, 1)
 761REG32(L0_TXPMD_TM_45, 0xcb4)
 762    FIELD(L0_TXPMD_TM_45, TXPMD_TM_45_31_8_RSVD, 24, 8)
 763    FIELD(L0_TXPMD_TM_45, ANA_DP_BYP0_7_6_RSVD, 6, 2)
 764    FIELD(L0_TXPMD_TM_45, DP_TM_TX_DP_ENABLE_POST2_PATH, 5, 1)
 765    FIELD(L0_TXPMD_TM_45, DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH, 4, 1)
 766    FIELD(L0_TXPMD_TM_45, DP_TM_TX_DP_ENABLE_POST1_PATH, 3, 1)
 767    FIELD(L0_TXPMD_TM_45, DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH, 2, 1)
 768    FIELD(L0_TXPMD_TM_45, DP_TM_TX_DP_ENABLE_MAIN_PATH, 1, 1)
 769    FIELD(L0_TXPMD_TM_45, DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH, 0, 1)
 770REG32(L0_TXPMD_TM_46, 0xcb8)
 771    FIELD(L0_TXPMD_TM_46, TXPMD_TM_46_31_8_RSVD, 24, 8)
 772    FIELD(L0_TXPMD_TM_46, ANA_PIPE_BYP39_7_6_RSVD, 6, 2)
 773    FIELD(L0_TXPMD_TM_46, PIPE_TM_TX_PIPE_ENABLE_PRE_PATH, 5, 1)
 774    FIELD(L0_TXPMD_TM_46, PIPE_TM_TX_OVRD_PIPE_ENABLE_PRE_PATH, 4, 1)
 775    FIELD(L0_TXPMD_TM_46, PIPE_TM_TX_PIPE_ENABLE_POST_PATH, 3, 1)
 776    FIELD(L0_TXPMD_TM_46, PIPE_TM_TX_OVRD_PIPE_ENABLE_POST_PATH, 2, 1)
 777    FIELD(L0_TXPMD_TM_46, PIPE_TM_TX_PIPE_ENABLE_MAIN_PATH, 1, 1)
 778    FIELD(L0_TXPMD_TM_46, PIPE_TM_TX_OVRD_PIPE_ENABLE_MAIN_PATH, 0, 1)
 779REG32(L0_TXPMD_TM_47, 0xcbc)
 780    FIELD(L0_TXPMD_TM_47, TXPMD_TM_47_31_8_RSVD, 24, 8)
 781    FIELD(L0_TXPMD_TM_47, TM_TX_RSVD1, 0, 8)
 782REG32(L0_TXPMD_TM_48, 0xcc0)
 783    FIELD(L0_TXPMD_TM_48, TXPMD_TM_48_31_8_RSVD, 24, 8)
 784    FIELD(L0_TXPMD_TM_48, ANA_MISC2_7_6_RSVD, 6, 2)
 785    FIELD(L0_TXPMD_TM_48, TM_FORCE_RESULTANT_MARGINING_FACTOR, 5, 1)
 786    FIELD(L0_TXPMD_TM_48, TM_RESULTANT_MARGINING_FACTOR, 0, 5)
 787REG32(L0_TM_ANA_BYP_1, 0x1004)
 788    FIELD(L0_TM_ANA_BYP_1, TM_ANA_BYP_1_31_8_RSVD, 24, 8)
 789    FIELD(L0_TM_ANA_BYP_1, MPHY_PWM_DES_PDZ, 7, 1)
 790    FIELD(L0_TM_ANA_BYP_1, FORCE_MPHY_PWM_DES_PDZ, 6, 1)
 791    FIELD(L0_TM_ANA_BYP_1, MPHY_PWMB_SYS_ENABLE, 5, 1)
 792    FIELD(L0_TM_ANA_BYP_1, FORCE_MPHY_PWMB_SYS_ENABLE, 4, 1)
 793    FIELD(L0_TM_ANA_BYP_1, MPHY_PSO_SQUELCH, 3, 1)
 794    FIELD(L0_TM_ANA_BYP_1, FORCE_MPHY_PSO_SQUELCH, 2, 1)
 795    FIELD(L0_TM_ANA_BYP_1, MPHY_PSO_LSRX, 1, 1)
 796    FIELD(L0_TM_ANA_BYP_1, FORCE_MPHY_PSO_LSRX, 0, 1)
 797REG32(L0_TM_ANA_BYP_2, 0x1008)
 798    FIELD(L0_TM_ANA_BYP_2, TM_ANA_BYP_2_31_8_RSVD, 24, 8)
 799    FIELD(L0_TM_ANA_BYP_2, MPHY_PWM_LSPREAMP_PD, 7, 1)
 800    FIELD(L0_TM_ANA_BYP_2, FORCE_MPHY_PWM_LSPREAMP_PD, 6, 1)
 801    FIELD(L0_TM_ANA_BYP_2, MPHY_PWM_GEAR_SEL, 3, 3)
 802    FIELD(L0_TM_ANA_BYP_2, FORCE_MPHY_PWM_GEAR_SEL, 2, 1)
 803    FIELD(L0_TM_ANA_BYP_2, MPHY_PWM_DET_PD, 1, 1)
 804    FIELD(L0_TM_ANA_BYP_2, FORCE_MPHY_PWM_DET_PD, 0, 1)
 805REG32(L0_TM_ANA_BYP_3, 0x100c)
 806    FIELD(L0_TM_ANA_BYP_3, TM_ANA_BYP_3_31_8_RSVD, 24, 8)
 807    FIELD(L0_TM_ANA_BYP_3, MPHY_RX_MASK_BURST_START, 7, 1)
 808    FIELD(L0_TM_ANA_BYP_3, FORCE_MPHY_RX_MASK_BURST_START, 6, 1)
 809    FIELD(L0_TM_ANA_BYP_3, MPHY_RX_GATE_SYMBOL_CLK, 5, 1)
 810    FIELD(L0_TM_ANA_BYP_3, FORCE_MPHY_RX_GATE_SYMBOL_CLK, 4, 1)
 811    FIELD(L0_TM_ANA_BYP_3, MPHY_PWM_PREAMP_BIAS_PD, 3, 1)
 812    FIELD(L0_TM_ANA_BYP_3, FORCE_MPHY_PWM_PREAMP_BIAS_PD, 2, 1)
 813    FIELD(L0_TM_ANA_BYP_3, MPHY_PWM_LSPREAMP_STANDBYSLEEPSTALL, 1, 1)
 814    FIELD(L0_TM_ANA_BYP_3, FORCE_MPHY_PWM_LSPREAMP_STANDBYSLEEPSTAL, 0, 1)
 815REG32(L0_TM_ANA_BYP_4, 0x1010)
 816    FIELD(L0_TM_ANA_BYP_4, TM_ANA_BYP_4_31_8_RSVD, 24, 8)
 817    FIELD(L0_TM_ANA_BYP_4, HSRX_RSTB, 7, 1)
 818    FIELD(L0_TM_ANA_BYP_4, FORCE_HSRX_RSTB, 6, 1)
 819    FIELD(L0_TM_ANA_BYP_4, MPHY_RX_TERM_ENABLE, 5, 1)
 820    FIELD(L0_TM_ANA_BYP_4, FORCE_MPHY_RX_TERM_ENABLE, 4, 1)
 821    FIELD(L0_TM_ANA_BYP_4, MPHY_RX_MUX_TYP1B_TYP2, 3, 1)
 822    FIELD(L0_TM_ANA_BYP_4, FORCE_MPHY_RX_MUX_TYP1B_TYP2, 2, 1)
 823    FIELD(L0_TM_ANA_BYP_4, MPHY_RX_MUX_HSB_LS, 1, 1)
 824    FIELD(L0_TM_ANA_BYP_4, FORCE_MPHY_RX_MUX_HSB_LS, 0, 1)
 825REG32(L0_TM_ANA_BYP_5, 0x1014)
 826    FIELD(L0_TM_ANA_BYP_5, TM_ANA_BYP_5_31_8_RSVD, 24, 8)
 827    FIELD(L0_TM_ANA_BYP_5, MPHY_SQ_SWAP_POLARITY, 5, 1)
 828    FIELD(L0_TM_ANA_BYP_5, FORCE_MPHY_SQ_SWAP_POLARITY, 4, 1)
 829    FIELD(L0_TM_ANA_BYP_5, MPHY_SQ_PD, 3, 1)
 830    FIELD(L0_TM_ANA_BYP_5, FORCE_MPHY_SQ_PD, 2, 1)
 831    FIELD(L0_TM_ANA_BYP_5, MPHY_SQ_DETECTOR_PD, 1, 1)
 832    FIELD(L0_TM_ANA_BYP_5, FORCE_MPHY_SQ_DETECTOR_PD, 0, 1)
 833REG32(L0_TM_ANA_BYP_7, 0x1018)
 834    FIELD(L0_TM_ANA_BYP_7, TM_ANA_BYP_7_31_8_RSVD, 24, 8)
 835    FIELD(L0_TM_ANA_BYP_7, PIPE_RXEQTRAINING, 7, 1)
 836    FIELD(L0_TM_ANA_BYP_7, FORCE_PIPE_RXEQTRAINING, 6, 1)
 837    FIELD(L0_TM_ANA_BYP_7, PIPE_RX_TERM_ENABLE, 5, 1)
 838    FIELD(L0_TM_ANA_BYP_7, FORCE_PIPE_RX_TERM_ENABLE, 4, 1)
 839REG32(L0_TM_ANA_BYP_8, 0x101c)
 840    FIELD(L0_TM_ANA_BYP_8, TM_ANA_BYP_8_31_8_RSVD, 24, 8)
 841    FIELD(L0_TM_ANA_BYP_8, UPHY_BIASGEN_IRCONST_IO_MIRROR_ENABLE, 7, 1)
 842    FIELD(L0_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_IRCONST_IO_MIRROR_ENABLE, 6, 1)
 843    FIELD(L0_TM_ANA_BYP_8, UPHY_BIASGEN_IRCONST_CORE_MIRROR_ENABLE, 5, 1)
 844    FIELD(L0_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_IRCONST_CORE_MIRROR_ENABLE, 4, 1)
 845    FIELD(L0_TM_ANA_BYP_8, UPHY_BIASGEN_ICONST_IO_MIRROR_ENABLE, 3, 1)
 846    FIELD(L0_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_ICONST_IO_MIRROR_ENABLE, 2, 1)
 847    FIELD(L0_TM_ANA_BYP_8, UPHY_BIASGEN_ICONST_CORE_MIRROR_ENABLE, 1, 1)
 848    FIELD(L0_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_ICONST_CORE_MIRROR_ENABLE, 0, 1)
 849REG32(L0_TM_ANA_BYP_9, 0x1020)
 850    FIELD(L0_TM_ANA_BYP_9, TM_ANA_BYP_9_31_8_RSVD, 24, 8)
 851    FIELD(L0_TM_ANA_BYP_9, UPHY_RECLPBK_CLK_DATAZ_ENABLE_CORE, 7, 1)
 852    FIELD(L0_TM_ANA_BYP_9, FORCE_UPHY_RECLPBK_CLK_DATAZ_ENABLE_CORE, 6, 1)
 853    FIELD(L0_TM_ANA_BYP_9, UPHY_PSO_SAMP_LPBK, 5, 1)
 854    FIELD(L0_TM_ANA_BYP_9, FORCE_UPHY_PSO_SAMP_LPBK, 4, 1)
 855    FIELD(L0_TM_ANA_BYP_9, UPHY_EQ_LPBK_ENABLE_CORE, 3, 1)
 856    FIELD(L0_TM_ANA_BYP_9, FORCE_UPHY_EQ_LPBK_ENABLE_CORE, 2, 1)
 857    FIELD(L0_TM_ANA_BYP_9, UPHY_EQ_AC_DCZ_COUPLED_CORE, 1, 1)
 858    FIELD(L0_TM_ANA_BYP_9, FORCE_UPHY_EQ_AC_DCZ_COUPLED_CORE, 0, 1)
 859REG32(L0_TM_ANA_BYP_10, 0x1024)
 860    FIELD(L0_TM_ANA_BYP_10, TM_ANA_BYP_10_31_8_RSVD, 24, 8)
 861    FIELD(L0_TM_ANA_BYP_10, UPHY_LPBK_CLK_DATA_SEL, 5, 1)
 862    FIELD(L0_TM_ANA_BYP_10, UPHY_LPBK_CENTRE_EDGEZ_ENABLE_CORE, 4, 1)
 863    FIELD(L0_TM_ANA_BYP_10, UPHY_HSRX_LPBK_SEL, 1, 3)
 864    FIELD(L0_TM_ANA_BYP_10, FORCE_UPHY_HSRX_LPBK_SEL, 0, 1)
 865REG32(L0_TM_ANA_BYP_11, 0x1028)
 866    FIELD(L0_TM_ANA_BYP_11, TM_ANA_BYP_11_31_8_RSVD, 24, 8)
 867    FIELD(L0_TM_ANA_BYP_11, UPHY_PD_PI_DIV_PATH, 5, 1)
 868    FIELD(L0_TM_ANA_BYP_11, UPHY_PSO_CLK_LANE, 4, 1)
 869    FIELD(L0_TM_ANA_BYP_11, FORCE_UPHY_PSO_CLK_LANE, 3, 1)
 870    FIELD(L0_TM_ANA_BYP_11, UPHY_HSCLK_DIVISION_FACTOR, 1, 2)
 871    FIELD(L0_TM_ANA_BYP_11, FORCE_UPHY_HSCLK_DIVISION_FACTOR, 0, 1)
 872REG32(L0_TM_ANA_BYP_12, 0x102c)
 873    FIELD(L0_TM_ANA_BYP_12, TM_ANA_BYP_12_31_8_RSVD, 24, 8)
 874    FIELD(L0_TM_ANA_BYP_12, UPHY_PSO_HSRXDIG, 7, 1)
 875    FIELD(L0_TM_ANA_BYP_12, FORCE_UPHY_PSO_HSRXDIG, 6, 1)
 876    FIELD(L0_TM_ANA_BYP_12, UPHY_PDN_HS_DES, 5, 1)
 877    FIELD(L0_TM_ANA_BYP_12, FORCE_UPHY_PDN_HS_DES, 4, 1)
 878    FIELD(L0_TM_ANA_BYP_12, UPHY_RST_GF_MUX, 3, 1)
 879    FIELD(L0_TM_ANA_BYP_12, FORCE_UPHY_RST_GF_MUX, 2, 1)
 880    FIELD(L0_TM_ANA_BYP_12, UPHY_ENABLE_CDR, 1, 1)
 881    FIELD(L0_TM_ANA_BYP_12, FORCE_UPHY_ENABLE_CDR, 0, 1)
 882REG32(L0_TM_ANA_BYP_13, 0x1030)
 883    FIELD(L0_TM_ANA_BYP_13, TM_ANA_BYP_13_31_8_RSVD, 24, 8)
 884    FIELD(L0_TM_ANA_BYP_13, UPHY_PSO_SAMP_FLOPS, 1, 1)
 885    FIELD(L0_TM_ANA_BYP_13, FORCE_UPHY_PSO_SAMP_FLOPS, 0, 1)
 886REG32(L0_TM_ANA_BYP_14, 0x1034)
 887    FIELD(L0_TM_ANA_BYP_14, TM_ANA_BYP_14_31_8_RSVD, 24, 8)
 888    FIELD(L0_TM_ANA_BYP_14, UPHY_PSO_EPI, 7, 1)
 889    FIELD(L0_TM_ANA_BYP_14, FORCE_UPHY_PSO_EPI, 6, 1)
 890    FIELD(L0_TM_ANA_BYP_14, UPHY_PD_SAMP_C2C_ECLK, 5, 1)
 891    FIELD(L0_TM_ANA_BYP_14, FORCE_UPHY_PD_SAMP_C2C_ECLK, 4, 1)
 892    FIELD(L0_TM_ANA_BYP_14, UPHY_PSO_IQPI, 1, 1)
 893    FIELD(L0_TM_ANA_BYP_14, FORCE_UPHY_PSO_IQPI, 0, 1)
 894REG32(L0_TM_ANA_BYP_15, 0x1038)
 895    FIELD(L0_TM_ANA_BYP_15, TM_ANA_BYP_15_31_8_RSVD, 24, 8)
 896    FIELD(L0_TM_ANA_BYP_15, UPHY_ENABLE_LOW_LEAKAGE, 7, 1)
 897    FIELD(L0_TM_ANA_BYP_15, FORCE_UPHY_ENABLE_LOW_LEAKAGE, 6, 1)
 898    FIELD(L0_TM_ANA_BYP_15, UPHY_PD_SAMP_C2C, 5, 1)
 899    FIELD(L0_TM_ANA_BYP_15, FORCE_UPHY_PD_SAMP_C2C, 4, 1)
 900    FIELD(L0_TM_ANA_BYP_15, UPHY_PSO_CORE_EQ, 3, 1)
 901    FIELD(L0_TM_ANA_BYP_15, FORCE_UPHY_PSO_CORE_EQ, 2, 1)
 902    FIELD(L0_TM_ANA_BYP_15, UPHY_PSO_IO_EQ, 1, 1)
 903    FIELD(L0_TM_ANA_BYP_15, FORCE_UPHY_PSO_IO_EQ, 0, 1)
 904REG32(L0_TM_ANA_BYP_16, 0x103c)
 905    FIELD(L0_TM_ANA_BYP_16, TM_ANA_BYP_16_31_8_RSVD, 24, 8)
 906    FIELD(L0_TM_ANA_BYP_16, UPHY_PSO_SIGDET, 7, 1)
 907    FIELD(L0_TM_ANA_BYP_16, FORCE_UPHY_PSO_SIGDET, 6, 1)
 908    FIELD(L0_TM_ANA_BYP_16, UPHY_RX_LANE_POLARITY_SWAP, 5, 1)
 909    FIELD(L0_TM_ANA_BYP_16, FORCE_UPHY_RX_LANE_POLARITY_SWAP, 4, 1)
 910    FIELD(L0_TM_ANA_BYP_16, UPHY_RUN_CALIB, 3, 1)
 911    FIELD(L0_TM_ANA_BYP_16, FORCE_UPHY_RUN_CALIB, 2, 1)
 912    FIELD(L0_TM_ANA_BYP_16, UPHY_RESTORE_CALCODE, 1, 1)
 913    FIELD(L0_TM_ANA_BYP_16, FORCE_UPHY_RESTORE_CALCODE, 0, 1)
 914REG32(L0_TM_ANA_BYP_17, 0x1040)
 915    FIELD(L0_TM_ANA_BYP_17, TM_ANA_BYP_17_31_8_RSVD, 24, 8)
 916    FIELD(L0_TM_ANA_BYP_17, UPHY_STARTLOOP_PLL, 6, 1)
 917    FIELD(L0_TM_ANA_BYP_17, FORCE_UPHY_STARTLOOP_PLL, 5, 1)
 918    FIELD(L0_TM_ANA_BYP_17, UPHY_RX_RESCALIB_CODE, 1, 4)
 919    FIELD(L0_TM_ANA_BYP_17, FORCE_UPHY_RX_RESCALIB_CODE, 0, 1)
 920REG32(L0_TM_ANA_BYP_18, 0x1044)
 921    FIELD(L0_TM_ANA_BYP_18, TM_ANA_BYP_18_31_8_RSVD, 24, 8)
 922    FIELD(L0_TM_ANA_BYP_18, FORCE_UPHY_RESTORE_CALCODE_DATA, 3, 1)
 923    FIELD(L0_TM_ANA_BYP_18, FORCE_UPHY_RX_PMA_OPMODE, 2, 1)
 924    FIELD(L0_TM_ANA_BYP_18, UPHY_PSO_LFPSBCN, 1, 1)
 925    FIELD(L0_TM_ANA_BYP_18, FORCE_UPHY_PSO_LFPSBCN, 0, 1)
 926REG32(L0_TM_ANA_BYP_20, 0x1048)
 927    FIELD(L0_TM_ANA_BYP_20, TM_ANA_BYP_20_31_8_RSVD, 24, 8)
 928    FIELD(L0_TM_ANA_BYP_20, UPHY_RX_PMA_OPMODE, 0, 8)
 929REG32(L0_TM_ANA_BYP_21, 0x104c)
 930    FIELD(L0_TM_ANA_BYP_21, TM_ANA_BYP_21_31_8_RSVD, 24, 8)
 931    FIELD(L0_TM_ANA_BYP_21, UPHY_RESTORE_CALCODE_DATA, 0, 8)
 932REG32(L0_TM_ANA_BYP_22, 0x1050)
 933    FIELD(L0_TM_ANA_BYP_22, TM_ANA_BYP_22_31_8_RSVD, 24, 8)
 934    FIELD(L0_TM_ANA_BYP_22, ISO_HSRX_CTRL_BAR, 7, 1)
 935    FIELD(L0_TM_ANA_BYP_22, FORCE_ISO_HSRX_CTRL_BAR, 6, 1)
 936    FIELD(L0_TM_ANA_BYP_22, HSRX_CLOCK_STOP_REQ, 5, 1)
 937    FIELD(L0_TM_ANA_BYP_22, FORCE_HSRX_CLOCK_STOP_REQ, 4, 1)
 938    FIELD(L0_TM_ANA_BYP_22, UPHY_SBRX_RUN_CALIB, 3, 1)
 939    FIELD(L0_TM_ANA_BYP_22, FORCE_UPHY_SBRX_RUN_CALIB, 2, 1)
 940    FIELD(L0_TM_ANA_BYP_22, RXPMA_RSTB, 1, 1)
 941    FIELD(L0_TM_ANA_BYP_22, FORCE_RXPMA_RSTB, 0, 1)
 942REG32(L0_TM_ANA_BYP_23, 0x1054)
 943    FIELD(L0_TM_ANA_BYP_23, TM_ANA_BYP_23_31_8_RSVD, 24, 8)
 944    FIELD(L0_TM_ANA_BYP_23, ISO_SIGDET_CTRL_BAR, 7, 1)
 945    FIELD(L0_TM_ANA_BYP_23, FORCE_ISO_SIGDET_CTRL_BAR, 6, 1)
 946    FIELD(L0_TM_ANA_BYP_23, ISO_LFPS_CTRL_BAR, 5, 1)
 947    FIELD(L0_TM_ANA_BYP_23, FORCE_ISO_LFPS_CTRL_BAR, 4, 1)
 948    FIELD(L0_TM_ANA_BYP_23, ISO_MPHY_LSRX_CTRL_BAR, 3, 1)
 949    FIELD(L0_TM_ANA_BYP_23, FORCE_ISO_MPHY_LSRX_CTRL_BAR, 2, 1)
 950    FIELD(L0_TM_ANA_BYP_23, ISO_MPHY_SQUELCH_CTRL_BAR, 1, 1)
 951    FIELD(L0_TM_ANA_BYP_23, FORCE_ISO_MPHY_SQUELCH_CTRL_BAR, 0, 1)
 952REG32(L0_TM_DIG_1, 0x1058)
 953    FIELD(L0_TM_DIG_1, TM_DIG_1_31_8_RSVD, 24, 8)
 954    FIELD(L0_TM_DIG_1, EN_TXRX_DIFGEAR, 7, 1)
 955    FIELD(L0_TM_DIG_1, MPHY_HS_TERM_PT_SEL, 6, 1)
 956    FIELD(L0_TM_DIG_1, TX_ALLOW_INLNCFG_FROM_TOP, 5, 1)
 957    FIELD(L0_TM_DIG_1, BYPASS_MARKER_DETECTOR, 4, 1)
 958    FIELD(L0_TM_DIG_1, BYPASS_EXIT_VAL, 0, 4)
 959REG32(L0_TM_DIG_2, 0x105c)
 960    FIELD(L0_TM_DIG_2, TM_DIG_2_31_8_RSVD, 24, 8)
 961    FIELD(L0_TM_DIG_2, MPHY_SYM_STATE, 1, 5)
 962    FIELD(L0_TM_DIG_2, FORCE_MPHY_SYM_STATE, 0, 1)
 963REG32(L0_TM_DIG_3, 0x1060)
 964    FIELD(L0_TM_DIG_3, TM_DIG_3_31_8_RSVD, 24, 8)
 965    FIELD(L0_TM_DIG_3, MPHY_SQUELCH_DETECT, 7, 1)
 966    FIELD(L0_TM_DIG_3, FORCE_MPHY_SQUELCH_DETECT, 6, 1)
 967    FIELD(L0_TM_DIG_3, MPHY_CFG_STATE, 1, 5)
 968    FIELD(L0_TM_DIG_3, FORCE_MPHY_CFG_STATE, 0, 1)
 969REG32(L0_TM_DIG_4, 0x1064)
 970    FIELD(L0_TM_DIG_4, TM_DIG_4_31_8_RSVD, 24, 8)
 971    FIELD(L0_TM_DIG_4, STATUS_REG_VAL, 4, 4)
 972    FIELD(L0_TM_DIG_4, READ_SHADOW, 3, 1)
 973REG32(L0_TM_DIG_5, 0x1068)
 974    FIELD(L0_TM_DIG_5, TM_DIG_5_31_8_RSVD, 24, 8)
 975    FIELD(L0_TM_DIG_5, SYMBOL_CLK_ALWAYS_ON_N, 2, 1)
 976    FIELD(L0_TM_DIG_5, BYPASS_DIFN_DETECT, 1, 1)
 977    FIELD(L0_TM_DIG_5, HIBERN8_CTRL, 0, 1)
 978REG32(L0_TM_DIG_6, 0x106c)
 979    FIELD(L0_TM_DIG_6, TM_DIG_6_31_8_RSVD, 24, 8)
 980    FIELD(L0_TM_DIG_6, FORCE_BYPASS_ON_ERR, 6, 1)
 981    FIELD(L0_TM_DIG_6, SUPPRESS_ERR, 5, 1)
 982    FIELD(L0_TM_DIG_6, BYPASS_OHC, 4, 1)
 983    FIELD(L0_TM_DIG_6, BYPASS_DECODER, 3, 1)
 984    FIELD(L0_TM_DIG_6, FORCE_BYPASS_DEC, 2, 1)
 985    FIELD(L0_TM_DIG_6, BYPASS_DESCRAM, 1, 1)
 986    FIELD(L0_TM_DIG_6, FORCE_BYPASS_DESCRAM, 0, 1)
 987REG32(L0_TM_DIG_7, 0x1070)
 988    FIELD(L0_TM_DIG_7, TM_DIG_7_31_8_RSVD, 24, 8)
 989    FIELD(L0_TM_DIG_7, BYPASS_ON_ERR_CHAR, 0, 8)
 990REG32(L0_TM_DIG_8, 0x1074)
 991    FIELD(L0_TM_DIG_8, TM_DIG_8_31_8_RSVD, 24, 8)
 992    FIELD(L0_TM_DIG_8, EYESURF_ENABLE, 4, 1)
 993    FIELD(L0_TM_DIG_8, USE_EB_IN_MPHY, 3, 1)
 994    FIELD(L0_TM_DIG_8, BYPASS_EB, 2, 1)
 995    FIELD(L0_TM_DIG_8, EB_MODE, 1, 1)
 996    FIELD(L0_TM_DIG_8, FORCE_EB_MODE, 0, 1)
 997REG32(L0_TM_DIG_9, 0x1078)
 998    FIELD(L0_TM_DIG_9, TM_DIG_9_31_8_RSVD, 24, 8)
 999    FIELD(L0_TM_DIG_9, FLIP_ENDIAN, 3, 1)
1000    FIELD(L0_TM_DIG_9, DEC_ERR_CNT_THRESHOLD, 0, 3)

1001REG32(L0_TM_DIG_10, 0x107c)
1002    FIELD(L0_TM_DIG_10, TM_DIG_10_31_8_RSVD, 24, 8)
1003    FIELD(L0_TM_DIG_10, CDR_BIT_LOCK_TIME, 0, 4)
1004REG32(L0_TM_DIG_11, 0x1080)
1005    FIELD(L0_TM_DIG_11, TM_DIG_11_31_8_RSVD, 24, 8)
1006    FIELD(L0_TM_DIG_11, BYPASS_CDR_ERR_MASK, 7, 1)
1007    FIELD(L0_TM_DIG_11, SYMB_ERR_SEL, 5, 2)
1008    FIELD(L0_TM_DIG_11, SYMB_ERR, 4, 1)
1009REG32(L0_TM_DIG_12, 0x1084)
1010    FIELD(L0_TM_DIG_12, TM_DIG_12_31_8_RSVD, 24, 8)
1011    FIELD(L0_TM_DIG_12, FLIP_ENDIAN_EB_DATA_OUT, 5, 1)
1012    FIELD(L0_TM_DIG_12, FLIP_ENDIAN_EB_DATA_IN, 4, 1)
1013    FIELD(L0_TM_DIG_12, OVERFLOW_BYP, 3, 1)
1014    FIELD(L0_TM_DIG_12, UNDERFLOW_BYP, 2, 1)
1015    FIELD(L0_TM_DIG_12, OVERFLOW_BYP_VAL, 1, 1)
1016    FIELD(L0_TM_DIG_12, UNDERFLOW_BYP_VAL, 0, 1)
1017REG32(L0_TM_DIG_13, 0x1088)
1018    FIELD(L0_TM_DIG_13, TM_DIG_13_31_8_RSVD, 24, 8)
1019    FIELD(L0_TM_DIG_13, OMC_PRESENTN, 6, 1)
1020    FIELD(L0_TM_DIG_13, CFG_CLK_FREQ, 0, 6)
1021REG32(L0_TM_DIG_14, 0x108c)
1022    FIELD(L0_TM_DIG_14, TM_DIG_14_31_8_RSVD, 24, 8)
1023    FIELD(L0_TM_DIG_14, LFPS_OUTPUT_SEL, 6, 2)
1024    FIELD(L0_TM_DIG_14, LFPS_STRETCH, 4, 2)
1025REG32(L0_TM_DIG_15, 0x1090)
1026    FIELD(L0_TM_DIG_15, TM_DIG_15_31_8_RSVD, 24, 8)
1027    FIELD(L0_TM_DIG_15, FORCE_LFPS_FILTER_THRESH, 5, 1)
1028    FIELD(L0_TM_DIG_15, LFPS_FILTER_THRESH, 0, 5)
1029REG32(L0_TM_DIG_16, 0x1094)
1030    FIELD(L0_TM_DIG_16, TM_DIG_16_31_8_RSVD, 24, 8)
1031    FIELD(L0_TM_DIG_16, TESTDIGOUT_SEL, 1, 4)
1032    FIELD(L0_TM_DIG_16, FORCE_TESTDIGOUT_SEL, 0, 1)
1033REG32(L0_TM_DIG_17, 0x1098)
1034    FIELD(L0_TM_DIG_17, TM_DIG_17_31_8_RSVD, 24, 8)
1035    FIELD(L0_TM_DIG_17, FORCE_SATA_RX_VALID_CNT, 4, 1)
1036    FIELD(L0_TM_DIG_17, SATA_RX_VALID_CNT, 0, 4)
1037REG32(L0_TM_DIG_18, 0x109c)
1038    FIELD(L0_TM_DIG_18, TM_DIG_18_31_8_RSVD, 24, 8)
1039    FIELD(L0_TM_DIG_18, CLK_DIST_SETTLE_TIME, 4, 4)
1040    FIELD(L0_TM_DIG_18, BIASGEN_SETTLE_TIME, 0, 4)
1041REG32(L0_TM_DIG_19, 0x10a0)
1042    FIELD(L0_TM_DIG_19, TM_DIG_19_31_8_RSVD, 24, 8)
1043    FIELD(L0_TM_DIG_19, HSRX_ANA_SETTLE_TIME, 4, 4)
1044    FIELD(L0_TM_DIG_19, SBRX_ANA_SETTLE_TIME, 0, 4)
1045REG32(L0_TM_DIG_20, 0x10a4)
1046    FIELD(L0_TM_DIG_20, TM_DIG_20_31_8_RSVD, 24, 8)
1047    FIELD(L0_TM_DIG_20, HSRX_COOLING_TIME, 3, 4)
1048    FIELD(L0_TM_DIG_20, FORCE_RX_CAL, 2, 1)
1049    FIELD(L0_TM_DIG_20, BYPASS_HSRX_CAL, 1, 1)
1050    FIELD(L0_TM_DIG_20, BYPASS_SBRX_CAL, 0, 1)
1051REG32(L0_TM_DIG_21, 0x10a8)
1052    FIELD(L0_TM_DIG_21, TM_DIG_21_31_8_RSVD, 24, 8)
1053    FIELD(L0_TM_DIG_21, COMMA_LOCATION_RST, 4, 1)
1054    FIELD(L0_TM_DIG_21, SSC_WAIT_CNT, 2, 2)
1055    FIELD(L0_TM_DIG_21, COMMA_PRE_LOCK_THRESH, 0, 2)
1056REG32(L0_TM_DIG_22, 0x10ac)
1057    FIELD(L0_TM_DIG_22, TM_DIG_22_31_8_RSVD, 24, 8)
1058    FIELD(L0_TM_DIG_22, DIS_DEFAULT_CDR_GATE_LOGIC, 5, 1)
1059    FIELD(L0_TM_DIG_22, INV_POL_SIGDET_HIGH, 4, 1)
1060    FIELD(L0_TM_DIG_22, INV_POL_SIGDET_LOW, 3, 1)
1061    FIELD(L0_TM_DIG_22, SIGDET_LFPS_BAR_EN, 2, 1)
1062    FIELD(L0_TM_DIG_22, OBSRV_SIGDET_OUTPUT, 1, 1)
1063    FIELD(L0_TM_DIG_22, RX_SIGDET_EN, 0, 1)
1064REG32(L0_TM_DIG_23, 0x10b0)
1065    FIELD(L0_TM_DIG_23, TM_DIG_23_31_8_RSVD, 24, 8)
1066    FIELD(L0_TM_DIG_23, DELAY_TIMER_LOAD_VAL_HIGH_1, 6, 2)
1067    FIELD(L0_TM_DIG_23, FORCE_RX_SIGDET_SEL, 5, 1)
1068    FIELD(L0_TM_DIG_23, RX_SIGDET_SEL_VAL, 4, 1)
1069    FIELD(L0_TM_DIG_23, FORCE_RX_SIG_DET_FILT_FUNC_SEL, 3, 1)
1070    FIELD(L0_TM_DIG_23, RX_SIG_DET_FILT_FUNC_SEL, 0, 3)
1071REG32(L0_TM_DIG_24, 0x10b4)
1072    FIELD(L0_TM_DIG_24, TM_DIG_24_31_8_RSVD, 24, 8)
1073    FIELD(L0_TM_DIG_24, FILTER_TIMER_LOAD_VAL_HIGH_1, 6, 2)
1074    FIELD(L0_TM_DIG_24, MIN_TIMER_LOAD_VAL_HIGH_1, 4, 2)
1075    FIELD(L0_TM_DIG_24, FILTER_TIMER_LOAD_VAL_LOW_1, 2, 2)
1076    FIELD(L0_TM_DIG_24, MIN_TIMER_LOAD_VAL_LOW_1, 0, 2)
1077REG32(L0_TM_DIG_25, 0x10b8)
1078    FIELD(L0_TM_DIG_25, TM_DIG_25_31_8_RSVD, 24, 8)
1079    FIELD(L0_TM_DIG_25, FILTER_TIMER_LOAD_VAL_HIGH_0, 0, 8)
1080REG32(L0_TM_DIG_26, 0x10bc)
1081    FIELD(L0_TM_DIG_26, TM_DIG_26_31_8_RSVD, 24, 8)
1082    FIELD(L0_TM_DIG_26, DELAY_TIMER_LOAD_VAL_HIGH_0, 0, 8)
1083REG32(L0_TM_DIG_27, 0x10c0)
1084    FIELD(L0_TM_DIG_27, TM_DIG_27_31_8_RSVD, 24, 8)
1085    FIELD(L0_TM_DIG_27, MIN_TIMER_LOAD_VAL_HIGH_0, 0, 8)
1086REG32(L0_TM_DIG_28, 0x10c4)
1087    FIELD(L0_TM_DIG_28, TM_DIG_28_31_8_RSVD, 24, 8)
1088    FIELD(L0_TM_DIG_28, FILTER_TIMER_LOAD_VAL_LOW_0, 0, 8)
1089REG32(L0_TM_DIG_29, 0x10c8)
1090    FIELD(L0_TM_DIG_29, TM_DIG_29_31_8_RSVD, 24, 8)
1091    FIELD(L0_TM_DIG_29, MIN_TIMER_LOAD_VAL_LOW_0, 0, 8)
1092REG32(L0_TM_AUX_0, 0x10cc)
1093    FIELD(L0_TM_AUX_0, TM_AUX_0_31_8_RSVD, 24, 8)
1094    FIELD(L0_TM_AUX_0, BIT_0, 7, 1)
1095    FIELD(L0_TM_AUX_0, BIT_1, 6, 1)
1096    FIELD(L0_TM_AUX_0, BIT_2, 5, 1)
1097    FIELD(L0_TM_AUX_0, BIT_3, 4, 1)
1098    FIELD(L0_TM_AUX_0, BIT_4, 3, 1)
1099    FIELD(L0_TM_AUX_0, BIT_5, 2, 1)
1100    FIELD(L0_TM_AUX_0, BIT_6, 1, 1)
1101    FIELD(L0_TM_AUX_0, BIT_7, 0, 1)
1102REG32(L0_TM_AUX_1, 0x10d0)
1103    FIELD(L0_TM_AUX_1, TM_AUX_1_31_8_RSVD, 24, 8)
1104    FIELD(L0_TM_AUX_1, BIT_0, 7, 1)
1105    FIELD(L0_TM_AUX_1, BIT_1, 6, 1)
1106    FIELD(L0_TM_AUX_1, BIT_2, 5, 1)
1107    FIELD(L0_TM_AUX_1, BIT_3, 4, 1)
1108    FIELD(L0_TM_AUX_1, BIT_4, 3, 1)
1109    FIELD(L0_TM_AUX_1, BIT_5, 2, 1)
1110    FIELD(L0_TM_AUX_1, BIT_6, 1, 1)
1111    FIELD(L0_TM_AUX_1, BIT_7, 0, 1)
1112REG32(L0_TM_AUX_2, 0x10d4)
1113    FIELD(L0_TM_AUX_2, TM_AUX_2_31_8_RSVD, 24, 8)
1114    FIELD(L0_TM_AUX_2, BIT_0, 7, 1)
1115    FIELD(L0_TM_AUX_2, BIT_1, 6, 1)
1116    FIELD(L0_TM_AUX_2, BIT_2, 5, 1)
1117    FIELD(L0_TM_AUX_2, BIT_3, 4, 1)
1118    FIELD(L0_TM_AUX_2, BIT_4, 3, 1)
1119    FIELD(L0_TM_AUX_2, BIT_5, 2, 1)
1120    FIELD(L0_TM_AUX_2, BIT_6, 1, 1)
1121    FIELD(L0_TM_AUX_2, BIT_7, 0, 1)
1122REG32(L0_TM_AUX_3, 0x10d8)
1123    FIELD(L0_TM_AUX_3, TM_AUX_3_31_8_RSVD, 24, 8)
1124    FIELD(L0_TM_AUX_3, BIT_0, 7, 1)
1125    FIELD(L0_TM_AUX_3, BIT_1, 6, 1)
1126    FIELD(L0_TM_AUX_3, BIT_2, 5, 1)
1127    FIELD(L0_TM_AUX_3, BIT_3, 4, 1)
1128    FIELD(L0_TM_AUX_3, BIT_4, 3, 1)
1129    FIELD(L0_TM_AUX_3, BIT_5, 2, 1)
1130    FIELD(L0_TM_AUX_3, BIT_6, 1, 1)
1131    FIELD(L0_TM_AUX_3, BIT_7, 0, 1)
1132REG32(L0_TM_AUX_4, 0x10dc)
1133    FIELD(L0_TM_AUX_4, TM_AUX_4_31_8_RSVD, 24, 8)
1134    FIELD(L0_TM_AUX_4, BIT_0, 7, 1)
1135    FIELD(L0_TM_AUX_4, BIT_1, 6, 1)
1136    FIELD(L0_TM_AUX_4, BIT_2, 5, 1)
1137    FIELD(L0_TM_AUX_4, BIT_3, 4, 1)
1138    FIELD(L0_TM_AUX_4, BIT_4, 3, 1)
1139    FIELD(L0_TM_AUX_4, BIT_5, 2, 1)
1140    FIELD(L0_TM_AUX_4, BIT_6, 1, 1)
1141    FIELD(L0_TM_AUX_4, BIT_7, 0, 1)
1142REG32(L0_TM_DIG_30, 0x10e0)
1143    FIELD(L0_TM_DIG_30, TM_DIG_30_31_8_RSVD, 24, 8)
1144    FIELD(L0_TM_DIG_30, SD_LD_BAR_FILTER_TIME_VAL_1, 4, 2)
1145    FIELD(L0_TM_DIG_30, SD_LD_BAR_DLY_TIME_VAL_1, 2, 2)
1146    FIELD(L0_TM_DIG_30, SD_LD_BAR_MIN_TIMER_VAL_1, 0, 2)
1147REG32(L0_TM_DIG_31, 0x10e4)
1148    FIELD(L0_TM_DIG_31, TM_DIG_31_31_8_RSVD, 24, 8)
1149    FIELD(L0_TM_DIG_31, SD_LD_BAR_FILTER_TIME_VAL_0, 0, 8)
1150REG32(L0_TM_DIG_32, 0x10e8)
1151    FIELD(L0_TM_DIG_32, TM_DIG_32_31_8_RSVD, 24, 8)
1152    FIELD(L0_TM_DIG_32, SD_LD_BAR_DLY_TIME_VAL_0, 0, 8)
1153REG32(L0_TM_DIG_33, 0x10ec)
1154    FIELD(L0_TM_DIG_33, TM_DIG_33_31_8_RSVD, 24, 8)
1155    FIELD(L0_TM_DIG_33, SD_LD_BAR_MIN_TIMER_VAL_0, 0, 8)
1156REG32(L0_TM_DIG_34, 0x10f0)
1157    FIELD(L0_TM_DIG_34, TM_DIG_34_31_8_RSVD, 24, 8)
1158    FIELD(L0_TM_DIG_34, SATA_JUNK_DATA_TIMEOUT_VAL, 0, 6)
1159REG32(L0_TM_DIG_35, 0x10f4)
1160    FIELD(L0_TM_DIG_35, TM_DIG_35_31_8_RSVD, 24, 8)
1161    FIELD(L0_TM_DIG_35, SATA_CDR_LOCK_WAIT_TIMEOUT_VAL, 0, 6)
1162REG32(L0_TM_DIG_36, 0x10f8)
1163    FIELD(L0_TM_DIG_36, TM_DIG_36_31_8_RSVD, 24, 8)
1164    FIELD(L0_TM_DIG_36, COM_DET_THRESH_VAL_0, 0, 8)
1165REG32(L0_TM_DIG_37, 0x10fc)
1166    FIELD(L0_TM_DIG_37, TM_DIG_37_31_8_RSVD, 24, 8)
1167    FIELD(L0_TM_DIG_37, FORCE_COM_DETECT_THRESH, 4, 1)
1168    FIELD(L0_TM_DIG_37, COM_DET_THRESH_VAL_1, 0, 4)
1169REG32(L0_TM_LFPS_1, 0x1800)
1170    FIELD(L0_TM_LFPS_1, TM_LFPS_1_31_8_RSVD, 24, 8)
1171    FIELD(L0_TM_LFPS_1, PROG_REFP, 4, 4)
1172    FIELD(L0_TM_LFPS_1, PROG_REFM, 0, 4)
1173REG32(L0_TM_LFPS_2, 0x1804)
1174    FIELD(L0_TM_LFPS_2, TM_LFPS_2_31_8_RSVD, 24, 8)
1175    FIELD(L0_TM_LFPS_2, PROG_VCM, 4, 3)
1176    FIELD(L0_TM_LFPS_2, PROG_FILTER_CAP, 0, 4)
1177REG32(L0_TM_LFPS_3, 0x1808)
1178    FIELD(L0_TM_LFPS_3, TM_LFPS_3_31_8_RSVD, 24, 8)
1179    FIELD(L0_TM_LFPS_3, PROG_C2, 5, 3)
1180    FIELD(L0_TM_LFPS_3, PROG_C1, 2, 3)
1181    FIELD(L0_TM_LFPS_3, PROG_PADINTF, 0, 2)
1182REG32(L0_TM_LFPS_4, 0x180c)
1183    FIELD(L0_TM_LFPS_4, TM_LFPS_4_31_8_RSVD, 24, 8)
1184    FIELD(L0_TM_LFPS_4, TESTBIT, 0, 6)
1185REG32(L0_TM_RXPMA_1, 0x1810)
1186    FIELD(L0_TM_RXPMA_1, TM_RXPMA_1_31_8_RSVD, 24, 8)
1187    FIELD(L0_TM_RXPMA_1, UPHY_TESTBIT, 0, 8)
1188REG32(L0_TM_BSCAN_1, 0x1814)
1189    FIELD(L0_TM_BSCAN_1, TM_BSCAN_1_31_8_RSVD, 24, 8)
1190    FIELD(L0_TM_BSCAN_1, BSCAN_LPF_RES, 0, 3)
1191REG32(L0_TM_MPHY_SQ_1, 0x1818)
1192    FIELD(L0_TM_MPHY_SQ_1, TM_MPHY_SQ_1_31_8_RSVD, 24, 8)
1193    FIELD(L0_TM_MPHY_SQ_1, TB_REDUCE_OFFSET, 4, 1)
1194    FIELD(L0_TM_MPHY_SQ_1, TB_INCREASE_OFFSET, 3, 1)
1195    FIELD(L0_TM_MPHY_SQ_1, TB_DRIVE_RES_SEL, 1, 2)
1196    FIELD(L0_TM_MPHY_SQ_1, TB_BYPASS_HYST, 0, 1)
1197REG32(L0_TM_LSRX_1, 0x181c)
1198    FIELD(L0_TM_LSRX_1, TM_LSRX_1_31_8_RSVD, 24, 8)
1199    FIELD(L0_TM_LSRX_1, LSRX_TESTBITS_0, 0, 8)
1200REG32(L0_TM_LSRX_2, 0x1820)
1201    FIELD(L0_TM_LSRX_2, TM_LSRX_2_31_8_RSVD, 24, 8)
1202    FIELD(L0_TM_LSRX_2, LSRX_TESTBITS_1, 0, 6)
1203REG32(L0_TM_SIGDET_1, 0x1824)
1204    FIELD(L0_TM_SIGDET_1, TM_SIGDET_1_31_8_RSVD, 24, 8)
1205    FIELD(L0_TM_SIGDET_1, BIASTRIM, 4, 3)
1206    FIELD(L0_TM_SIGDET_1, RELIABPROT, 2, 2)
1207    FIELD(L0_TM_SIGDET_1, STRESSPORT, 0, 2)
1208REG32(L0_TM_SIGDET_2, 0x1828)
1209    FIELD(L0_TM_SIGDET_2, TM_SIGDET_2_31_8_RSVD, 24, 8)
1210    FIELD(L0_TM_SIGDET_2, VSENSETRIM, 0, 8)
1211REG32(L0_TM_DFT_1, 0x182c)
1212    FIELD(L0_TM_DFT_1, TM_DFT_1_31_8_RSVD, 24, 8)
1213    FIELD(L0_TM_DFT_1, LFPS_DFT_SEL_P, 4, 4)
1214    FIELD(L0_TM_DFT_1, LFPS_DFT_ENABLE, 3, 1)
1215REG32(L0_TM_DFT_2, 0x1830)
1216    FIELD(L0_TM_DFT_2, TM_DFT_2_31_8_RSVD, 24, 8)
1217    FIELD(L0_TM_DFT_2, SIGDET_DFT_SEL_P, 0, 3)
1218REG32(L0_TM_DFT_3, 0x1834)
1219    FIELD(L0_TM_DFT_3, TM_DFT_3_31_8_RSVD, 24, 8)
1220    FIELD(L0_TM_DFT_3, BSCAN_DFT_ENABLE, 4, 1)
1221    FIELD(L0_TM_DFT_3, BSCAN_DFT_SEL_P, 0, 4)
1222REG32(L0_TM_DFT_4, 0x1838)
1223    FIELD(L0_TM_DFT_4, TM_DFT_4_31_8_RSVD, 24, 8)
1224    FIELD(L0_TM_DFT_4, IQPI_DFT_ENABLE, 1, 1)
1225    FIELD(L0_TM_DFT_4, EPI_DFT_ENABLE, 0, 1)
1226REG32(L0_TM_DFT_5, 0x183c)
1227    FIELD(L0_TM_DFT_5, TM_DFT_5_31_8_RSVD, 24, 8)
1228    FIELD(L0_TM_DFT_5, IQPI_DFT_SEL, 0, 8)
1229REG32(L0_TM_DFT_6, 0x1840)
1230    FIELD(L0_TM_DFT_6, TM_DFT_6_31_8_RSVD, 24, 8)
1231    FIELD(L0_TM_DFT_6, EPI_DFT_SEL, 0, 8)
1232REG32(L0_TM_DFT_7, 0x1844)
1233    FIELD(L0_TM_DFT_7, TM_DFT_7_31_8_RSVD, 24, 8)
1234    FIELD(L0_TM_DFT_7, EQ_DFT_ENABLE, 4, 1)
1235    FIELD(L0_TM_DFT_7, EQ_DFT_SEL_P, 0, 4)
1236REG32(L0_TM_DFT_8, 0x1848)
1237    FIELD(L0_TM_DFT_8, TM_DFT_8_31_8_RSVD, 24, 8)
1238    FIELD(L0_TM_DFT_8, LSRX_DFT_ENABLE, 4, 1)
1239    FIELD(L0_TM_DFT_8, LSRX_DFT_SEL_P, 0, 4)
1240REG32(L0_TM_DFT_9, 0x184c)
1241    FIELD(L0_TM_DFT_9, TM_DFT_9_31_8_RSVD, 24, 8)
1242    FIELD(L0_TM_DFT_9, SAMP_DFT_SEL_P_0, 0, 8)
1243REG32(L0_TM_DFT_10, 0x1850)
1244    FIELD(L0_TM_DFT_10, TM_DFT_10_31_8_RSVD, 24, 8)
1245    FIELD(L0_TM_DFT_10, CLKLANE_DFT_SEL, 2, 2)
1246    FIELD(L0_TM_DFT_10, SAMP_DFT_SEL_P_1, 0, 2)
1247REG32(L0_TM_BG_1, 0x1854)
1248    FIELD(L0_TM_BG_1, TM_BG_1_31_8_RSVD, 24, 8)
1249    FIELD(L0_TM_BG_1, BIASGEN_CURRENT_PROG_0, 0, 8)
1250REG32(L0_TM_BG_2, 0x1858)
1251    FIELD(L0_TM_BG_2, TM_BG_2_31_8_RSVD, 24, 8)
1252    FIELD(L0_TM_BG_2, BIASGEN_CURRENT_PROG_1, 0, 8)
1253REG32(L0_TM_BG_3, 0x185c)
1254    FIELD(L0_TM_BG_3, TM_BG_3_31_8_RSVD, 24, 8)
1255    FIELD(L0_TM_BG_3, BIASGEN_CURRENT_PROG_2, 0, 8)
1256REG32(L0_TM_BG_4, 0x1860)
1257    FIELD(L0_TM_BG_4, TM_BG_4_31_8_RSVD, 24, 8)
1258    FIELD(L0_TM_BG_4, BIASGEN_CURRENT_PROG_3, 0, 8)
1259REG32(L0_TM_BG_5, 0x1864)
1260    FIELD(L0_TM_BG_5, TM_BG_5_31_8_RSVD, 24, 8)
1261    FIELD(L0_TM_BG_5, BIASGEN_CURRENT_PROG_4, 0, 8)
1262REG32(L0_TM_BG_6, 0x1868)
1263    FIELD(L0_TM_BG_6, TM_BG_6_31_8_RSVD, 24, 8)
1264    FIELD(L0_TM_BG_6, BIASGEN_CURRENT_PROG_5, 0, 8)
1265REG32(L0_TM_BG_7, 0x186c)
1266    FIELD(L0_TM_BG_7, TM_BG_7_31_8_RSVD, 24, 8)
1267    FIELD(L0_TM_BG_7, BIASGEN_CURRENT_PROG_6, 0, 8)
1268REG32(L0_TM_BG_8, 0x1870)
1269    FIELD(L0_TM_BG_8, TM_BG_8_31_8_RSVD, 24, 8)
1270    FIELD(L0_TM_BG_8, BIASGEN_CURRENT_PROG_7, 0, 8)
1271REG32(L0_TM_BG_9, 0x1874)
1272    FIELD(L0_TM_BG_9, TM_BG_9_31_8_RSVD, 24, 8)
1273    FIELD(L0_TM_BG_9, BIASGEN_CURRENT_PROG_8, 0, 8)
1274REG32(L0_TM_BG_10, 0x1878)
1275    FIELD(L0_TM_BG_10, TM_BG_10_31_8_RSVD, 24, 8)
1276    FIELD(L0_TM_BG_10, BIASGEN_CURRENT_PROG_9, 0, 8)
1277REG32(L0_TM_SD0, 0x187c)
1278    FIELD(L0_TM_SD0, TM_SD0_31_8_RSVD, 24, 8)
1279    FIELD(L0_TM_SD0, SD_CAL_OVERRIDE_CODE, 2, 6)
1280    FIELD(L0_TM_SD0, SD_CAL_OVERRIDE_EN, 1, 1)
1281    FIELD(L0_TM_SD0, SD_CAL_DIR, 0, 1)
1282REG32(L0_TM_SD1, 0x1880)
1283    FIELD(L0_TM_SD1, TM_SD1_31_8_RSVD, 24, 8)
1284    FIELD(L0_TM_SD1, SD_BYPASS_ANA_CAL_EN_VAL, 7, 1)
1285    FIELD(L0_TM_SD1, SD_BYPASS_ANA_CAL_EN, 6, 1)
1286    FIELD(L0_TM_SD1, SD_CAL_CODE_START, 0, 6)
1287REG32(L0_TM_SD2, 0x1884)
1288    FIELD(L0_TM_SD2, TM_SD2_31_8_RSVD, 24, 8)
1289    FIELD(L0_TM_SD2, SD_CAL_FORCE_CAL, 7, 1)
1290    FIELD(L0_TM_SD2, SD_CAL_CODE_TUNE_BYP, 6, 1)
1291    FIELD(L0_TM_SD2, SD_CAL_CODE_TUNE, 0, 6)
1292REG32(L0_TM_SD3, 0x1888)
1293    FIELD(L0_TM_SD3, TM_SD3_31_8_RSVD, 24, 8)
1294    FIELD(L0_TM_SD3, SD_CAL_ITER_WAIT_0, 0, 8)
1295REG32(L0_TM_SD4, 0x188c)
1296    FIELD(L0_TM_SD4, TM_SD4_31_8_RSVD, 24, 8)
1297    FIELD(L0_TM_SD4, SD_CAL_ITER_WAIT_BYPASS, 4, 1)
1298    FIELD(L0_TM_SD4, SD_CAL_ITER_WAIT_1, 0, 4)
1299REG32(L0_TM_SD5, 0x1890)
1300    FIELD(L0_TM_SD5, TM_SD5_31_8_RSVD, 24, 8)
1301    FIELD(L0_TM_SD5, SD_CAL_INIT_WAIT_0, 0, 8)
1302REG32(L0_TM_SD6, 0x1894)
1303    FIELD(L0_TM_SD6, TM_SD6_31_8_RSVD, 24, 8)
1304    FIELD(L0_TM_SD6, SD_CAL_INIT_WAIT_BYPASS, 4, 1)
1305    FIELD(L0_TM_SD6, SD_CAL_INIT_WAIT_1, 0, 4)
1306REG32(L0_TM_MISC1, 0x1898)
1307    FIELD(L0_TM_MISC1, TM_MISC1_31_8_RSVD, 24, 8)
1308    FIELD(L0_TM_MISC1, HSRX_POLARITY_FLIP, 7, 1)
1309    FIELD(L0_TM_MISC1, RXTERM_BIAS_PROG, 3, 4)
1310    FIELD(L0_TM_MISC1, LSRX_OR_SYS_POLARITY_FLIP, 2, 1)
1311    FIELD(L0_TM_MISC1, FORCE_SATAG1_DCC_MODE, 1, 1)
1312    FIELD(L0_TM_MISC1, SATAG1_DCC_MODE_VAL, 0, 1)
1313REG32(L0_TM_MISC2, 0x189c)
1314    FIELD(L0_TM_MISC2, TM_MISC2_31_8_RSVD, 24, 8)
1315    FIELD(L0_TM_MISC2, ILL_CAL_BYPASS_COUNTS, 7, 1)
1316    FIELD(L0_TM_MISC2, PWR_SEQ_SAMP_CAL_ALWAYS, 6, 1)
1317    FIELD(L0_TM_MISC2, PWR_SEQ_BYP_CAL_DONE, 5, 1)
1318    FIELD(L0_TM_MISC2, PWR_SEQ_BYP_CAL_DONE_VAL, 4, 1)
1319    FIELD(L0_TM_MISC2, SAMP_BYPASS_CAL_TO_EQ, 3, 1)
1320    FIELD(L0_TM_MISC2, SAMP_BYPASS_CAL_TO_EQ_VAL, 2, 1)
1321    FIELD(L0_TM_MISC2, UNUSED, 0, 2)
1322REG32(L0_TM_EYE_SURF0, 0x18a0)
1323    FIELD(L0_TM_EYE_SURF0, TM_EYE_SURF0_31_8_RSVD, 24, 8)
1324    FIELD(L0_TM_EYE_SURF0, UNUSED, 7, 1)
1325    FIELD(L0_TM_EYE_SURF0, EYE_SURF_RUN, 6, 1)
1326    FIELD(L0_TM_EYE_SURF0, COORD_EW_DIR, 5, 1)
1327    FIELD(L0_TM_EYE_SURF0, COORD_EW_OFFSET, 0, 5)
1328REG32(L0_TM_EYE_SURF1, 0x18a4)
1329    FIELD(L0_TM_EYE_SURF1, TM_EYE_SURF1_31_8_RSVD, 24, 8)
1330    FIELD(L0_TM_EYE_SURF1, COORD_NS_DIR, 7, 1)
1331    FIELD(L0_TM_EYE_SURF1, COORD_NS_OFFSET, 0, 7)
1332REG32(L0_TM_EYE_SURF2, 0x18a8)
1333    FIELD(L0_TM_EYE_SURF2, TM_EYE_SURF2_31_8_RSVD, 24, 8)
1334    FIELD(L0_TM_EYE_SURF2, TIMER_DELAY_TIME0, 0, 8)
1335REG32(L0_TM_EYE_SURF3, 0x18ac)
1336    FIELD(L0_TM_EYE_SURF3, TM_EYE_SURF3_31_8_RSVD, 24, 8)
1337    FIELD(L0_TM_EYE_SURF3, TIMER_DELAY_TIME1, 0, 8)
1338REG32(L0_TM_EYE_SURF4, 0x18b0)
1339    FIELD(L0_TM_EYE_SURF4, TM_EYE_SURF4_31_8_RSVD, 24, 8)
1340    FIELD(L0_TM_EYE_SURF4, TIMER_DELAY_TIME2, 0, 8)
1341REG32(L0_TM_EYE_SURF5, 0x18b4)
1342    FIELD(L0_TM_EYE_SURF5, TM_EYE_SURF5_31_8_RSVD, 24, 8)
1343    FIELD(L0_TM_EYE_SURF5, TIMER_DELAY_TIME3, 0, 8)
1344REG32(L0_TM_EYE_SURF6, 0x18b8)
1345    FIELD(L0_TM_EYE_SURF6, TM_EYE_SURF6_31_8_RSVD, 24, 8)
1346    FIELD(L0_TM_EYE_SURF6, TIMER_TEST_TIME0, 0, 8)
1347REG32(L0_TM_EYE_SURF7, 0x18bc)
1348    FIELD(L0_TM_EYE_SURF7, TM_EYE_SURF7_31_8_RSVD, 24, 8)
1349    FIELD(L0_TM_EYE_SURF7, TIMER_TEST_TIME1, 0, 8)
1350REG32(L0_TM_EYE_SURF8, 0x18c0)
1351    FIELD(L0_TM_EYE_SURF8, TM_EYE_SURF8_31_8_RSVD, 24, 8)
1352    FIELD(L0_TM_EYE_SURF8, TIMER_TEST_TIME2, 0, 8)
1353REG32(L0_TM_EYE_SURF9, 0x18c4)
1354    FIELD(L0_TM_EYE_SURF9, TM_EYE_SURF9_31_8_RSVD, 24, 8)
1355    FIELD(L0_TM_EYE_SURF9, TIMER_TEST_TIME3, 0, 8)
1356REG32(L0_TM_SPARE, 0x18c8)
1357    FIELD(L0_TM_SPARE, TM_SPARE_31_8_RSVD, 24, 8)
1358    FIELD(L0_TM_SPARE, RXDA_SPARE_PORT, 0, 8)
1359REG32(L0_TM_ANA_EQ1, 0x18cc)
1360    FIELD(L0_TM_ANA_EQ1, TM_ANA_EQ1_31_8_RSVD, 24, 8)
1361    FIELD(L0_TM_ANA_EQ1, UNUSED, 5, 3)
1362    FIELD(L0_TM_ANA_EQ1, EQ_INPUT_CM_PROG, 2, 3)
1363    FIELD(L0_TM_ANA_EQ1, EQ_PADINTF_HQ_PROG, 0, 2)
1364REG32(L0_TM_ANA_E_PI0, 0x18d0)
1365    FIELD(L0_TM_ANA_E_PI0, TM_ANA_E_PI0_31_8_RSVD, 24, 8)
1366    FIELD(L0_TM_ANA_E_PI0, EPI_BIASTRIM, 5, 3)
1367    FIELD(L0_TM_ANA_E_PI0, UNUSED, 0, 5)
1368REG32(L0_TM_ANA_IQ_PI0, 0x18d4)
1369    FIELD(L0_TM_ANA_IQ_PI0, TM_ANA_IQ_PI0_31_8_RSVD, 24, 8)
1370    FIELD(L0_TM_ANA_IQ_PI0, IQPI_BIASTRIM, 5, 3)
1371    FIELD(L0_TM_ANA_IQ_PI0, UNUSED, 0, 5)
1372REG32(L0_TM_ANA_MISC0, 0x18d8)
1373    FIELD(L0_TM_ANA_MISC0, TM_ANA_MISC0_31_8_RSVD, 24, 8)
1374    FIELD(L0_TM_ANA_MISC0, EPI_CALIB_EN, 7, 1)
1375    FIELD(L0_TM_ANA_MISC0, IQPI_CALIB_EN, 6, 1)
1376    FIELD(L0_TM_ANA_MISC0, UNUSED, 0, 6)
1377REG32(L0_TM_SAMP_CODE_IQ_PH0, 0x18dc)
1378    FIELD(L0_TM_SAMP_CODE_IQ_PH0, TM_SAMP_CODE_IQ_PH0_31_8_RSVD, 24, 8)
1379    FIELD(L0_TM_SAMP_CODE_IQ_PH0, UNUSED, 7, 1)
1380    FIELD(L0_TM_SAMP_CODE_IQ_PH0, SAMP_CALIB_BYP, 6, 1)
1381    FIELD(L0_TM_SAMP_CODE_IQ_PH0, IQ_PH0_SAMP_CODE, 0, 6)
1382REG32(L0_TM_SAMP_CODE_IQ_PH90, 0x18e0)
1383    FIELD(L0_TM_SAMP_CODE_IQ_PH90, TM_SAMP_CODE_IQ_PH90_31_8_RSVD, 24, 8)
1384    FIELD(L0_TM_SAMP_CODE_IQ_PH90, CALIB_SWEEP_DIR, 6, 2)
1385    FIELD(L0_TM_SAMP_CODE_IQ_PH90, IQ_PH90_SAMP_CODE, 0, 6)
1386REG32(L0_TM_SAMP_CODE_IQ_PH180, 0x18e4)
1387    FIELD(L0_TM_SAMP_CODE_IQ_PH180, TM_SAMP_CODE_IQ_PH180_31_8_RSVD, 24, 8)
1388    FIELD(L0_TM_SAMP_CODE_IQ_PH180, UNUSED, 6, 2)
1389    FIELD(L0_TM_SAMP_CODE_IQ_PH180, IQ_PH180_SAMP_CODE, 0, 6)
1390REG32(L0_TM_SAMP_CODE_IQ_PH270, 0x18e8)
1391    FIELD(L0_TM_SAMP_CODE_IQ_PH270, TM_SAMP_CODE_IQ_PH270_31_8_RSVD, 24, 8)
1392    FIELD(L0_TM_SAMP_CODE_IQ_PH270, HSRX_DBG_BUS_SEL, 6, 2)
1393    FIELD(L0_TM_SAMP_CODE_IQ_PH270, IQ_PH270_SAMP_CODE, 0, 6)
1394REG32(L0_TM_SAMP_CODE_E_PH0, 0x18ec)
1395    FIELD(L0_TM_SAMP_CODE_E_PH0, TM_SAMP_CODE_E_PH0_31_8_RSVD, 24, 8)
1396    FIELD(L0_TM_SAMP_CODE_E_PH0, UNUSED, 6, 2)
1397    FIELD(L0_TM_SAMP_CODE_E_PH0, E_PH90_SAMP_CODE, 0, 6)
1398REG32(L0_TM_SAMP_CODE_E_PH180, 0x18f0)
1399    FIELD(L0_TM_SAMP_CODE_E_PH180, TM_SAMP_CODE_E_PH180_31_8_RSVD, 24, 8)
1400    FIELD(L0_TM_SAMP_CODE_E_PH180, UNUSED, 6, 2)
1401    FIELD(L0_TM_SAMP_CODE_E_PH180, E_PH270_SAMP_CODE, 0, 6)
1402REG32(L0_TM_IQ_ILL0, 0x18f4)
1403    FIELD(L0_TM_IQ_ILL0, TM_IQ_ILL0_31_8_RSVD, 24, 8)
1404    FIELD(L0_TM_IQ_ILL0, ILL_BYPASS_IQ_CAL_EN, 7, 1)
1405    FIELD(L0_TM_IQ_ILL0, IQ_ILL_PLOADTRIM_BYP_VAL, 2, 5)
1406    FIELD(L0_TM_IQ_ILL0, IQ_ILL_PLOADTRIM_BYP, 1, 1)
1407    FIELD(L0_TM_IQ_ILL0, ILL_BYPASS_IQ_CODES, 0, 1)
1408REG32(L0_TM_IQ_ILL1, 0x18f8)
1409    FIELD(L0_TM_IQ_ILL1, TM_IQ_ILL1_31_8_RSVD, 24, 8)
1410    FIELD(L0_TM_IQ_ILL1, ILL_BYPASS_IQ_CALCODE_F0, 0, 8)
1411REG32(L0_TM_IQ_ILL2, 0x18fc)
1412    FIELD(L0_TM_IQ_ILL2, TM_IQ_ILL2_31_8_RSVD, 24, 8)
1413    FIELD(L0_TM_IQ_ILL2, ILL_BYPASS_IQ_CALCODE_F1, 0, 8)
1414REG32(L0_TM_IQ_ILL3, 0x1900)
1415    FIELD(L0_TM_IQ_ILL3, TM_IQ_ILL3_31_8_RSVD, 24, 8)
1416    FIELD(L0_TM_IQ_ILL3, ILL_BYPASS_IQ_CALCODE_F2, 0, 8)
1417REG32(L0_TM_IQ_ILL4, 0x1904)
1418    FIELD(L0_TM_IQ_ILL4, TM_IQ_ILL4_31_8_RSVD, 24, 8)
1419    FIELD(L0_TM_IQ_ILL4, ILL_BYPASS_IQ_CALCODE_F3, 0, 8)
1420REG32(L0_TM_IQ_ILL5, 0x1908)
1421    FIELD(L0_TM_IQ_ILL5, TM_IQ_ILL5_31_8_RSVD, 24, 8)
1422    FIELD(L0_TM_IQ_ILL5, ILL_BYPASS_IQ_CALCODE_F4, 0, 8)
1423REG32(L0_TM_IQ_ILL6, 0x190c)
1424    FIELD(L0_TM_IQ_ILL6, TM_IQ_ILL6_31_8_RSVD, 24, 8)
1425    FIELD(L0_TM_IQ_ILL6, ILL_BYPASS_IQ_CALCODE_F5, 0, 8)
1426REG32(L0_TM_IQ_ILL7, 0x1910)
1427    FIELD(L0_TM_IQ_ILL7, TM_IQ_ILL7_31_8_RSVD, 24, 8)
1428    FIELD(L0_TM_IQ_ILL7, ILL_BYPASS_IQ_CNSTGMTRIM_VAL, 0, 8)
1429REG32(L0_TM_IQ_ILL8, 0x1914)
1430    FIELD(L0_TM_IQ_ILL8, TM_IQ_ILL8_31_8_RSVD, 24, 8)
1431    FIELD(L0_TM_IQ_ILL8, ILL_BYPASS_IQ_POLYTRIM_VAL, 0, 8)
1432REG32(L0_TM_IQ_ILL9, 0x1918)
1433    FIELD(L0_TM_IQ_ILL9, TM_IQ_ILL9_31_8_RSVD, 24, 8)
1434    FIELD(L0_TM_IQ_ILL9, UNUSED, 4, 4)
1435    FIELD(L0_TM_IQ_ILL9, ILL_BYPASS_IQ_LFEN, 3, 1)
1436    FIELD(L0_TM_IQ_ILL9, ILL_BYPASS_IQ_LFEN_VAL, 2, 1)
1437    FIELD(L0_TM_IQ_ILL9, ILL_BYPASS_IQ_CNSTGMTRIM, 1, 1)
1438    FIELD(L0_TM_IQ_ILL9, ILL_BYPASS_IQ_POLYTIM, 0, 1)
1439REG32(L0_TM_IQ_ILL10, 0x191c)
1440    FIELD(L0_TM_IQ_ILL10, TM_IQ_ILL10_31_8_RSVD, 24, 8)
1441    FIELD(L0_TM_IQ_ILL10, UNUSED, 6, 2)
1442    FIELD(L0_TM_IQ_ILL10, IQPI_CALCTRIM, 4, 2)
1443    FIELD(L0_TM_IQ_ILL10, IQPI_REPLICATRIM, 0, 4)
1444REG32(L0_TM_E_ILL0, 0x1920)
1445    FIELD(L0_TM_E_ILL0, TM_E_ILL0_31_8_RSVD, 24, 8)
1446    FIELD(L0_TM_E_ILL0, E_ILL_CALIB_CTRL, 7, 1)
1447    FIELD(L0_TM_E_ILL0, E_ILL_PLOADTRIM_BYP_VAL, 2, 5)
1448    FIELD(L0_TM_E_ILL0, E_ILL_PLOADTRIM_BYP, 1, 1)
1449    FIELD(L0_TM_E_ILL0, E_ILL_CALIB_BYP, 0, 1)
1450REG32(L0_TM_E_ILL1, 0x1924)
1451    FIELD(L0_TM_E_ILL1, TM_E_ILL1_31_8_RSVD, 24, 8)
1452    FIELD(L0_TM_E_ILL1, ILL_BYPASS_E_CALCODE_F0, 0, 8)
1453REG32(L0_TM_E_ILL2, 0x1928)
1454    FIELD(L0_TM_E_ILL2, TM_E_ILL2_31_8_RSVD, 24, 8)
1455    FIELD(L0_TM_E_ILL2, ILL_BYPASS_E_CALCODE_F1, 0, 8)
1456REG32(L0_TM_E_ILL3, 0x192c)
1457    FIELD(L0_TM_E_ILL3, TM_E_ILL3_31_8_RSVD, 24, 8)
1458    FIELD(L0_TM_E_ILL3, ILL_BYPASS_E_CALCODE_F2, 0, 8)
1459REG32(L0_TM_E_ILL4, 0x1930)
1460    FIELD(L0_TM_E_ILL4, TM_E_ILL4_31_8_RSVD, 24, 8)
1461    FIELD(L0_TM_E_ILL4, ILL_BYPASS_E_CALCODE_F3, 0, 8)
1462REG32(L0_TM_E_ILL5, 0x1934)
1463    FIELD(L0_TM_E_ILL5, TM_E_ILL5_31_8_RSVD, 24, 8)
1464    FIELD(L0_TM_E_ILL5, ILL_BYPASS_E_CALCODE_F4, 0, 8)
1465REG32(L0_TM_E_ILL6, 0x1938)
1466    FIELD(L0_TM_E_ILL6, TM_E_ILL6_31_8_RSVD, 24, 8)
1467    FIELD(L0_TM_E_ILL6, ILL_BYPASS_E_CALCODE_F5, 0, 8)
1468REG32(L0_TM_E_ILL7, 0x193c)
1469    FIELD(L0_TM_E_ILL7, TM_E_ILL7_31_8_RSVD, 24, 8)
1470    FIELD(L0_TM_E_ILL7, ILL_BYPASS_E_CNSTGMTRIM_VAL, 0, 8)
1471REG32(L0_TM_E_ILL8, 0x1940)
1472    FIELD(L0_TM_E_ILL8, TM_E_ILL8_31_8_RSVD, 24, 8)
1473    FIELD(L0_TM_E_ILL8, ILL_BYPASS_E_POLYTRIM_VAL, 0, 8)
1474REG32(L0_TM_E_ILL9, 0x1944)
1475    FIELD(L0_TM_E_ILL9, TM_E_ILL9_31_8_RSVD, 24, 8)
1476    FIELD(L0_TM_E_ILL9, UNUSED, 4, 4)
1477    FIELD(L0_TM_E_ILL9, ILL_BYPASS_E_LFEN, 3, 1)
1478    FIELD(L0_TM_E_ILL9, ILL_BYPASS_E_LFEN_VAL, 2, 1)
1479    FIELD(L0_TM_E_ILL9, ILL_BYPASS_E_CNSTGMTRIM, 1, 1)
1480    FIELD(L0_TM_E_ILL9, ILL_BYPASS_E_POLYTIM, 0, 1)
1481REG32(L0_TM_E_ILL10, 0x1948)
1482    FIELD(L0_TM_E_ILL10, TM_E_ILL10_31_8_RSVD, 24, 8)
1483    FIELD(L0_TM_E_ILL10, UNUSED, 6, 2)
1484    FIELD(L0_TM_E_ILL10, EPI_CALCTRIM, 4, 2)
1485    FIELD(L0_TM_E_ILL10, EPI_REPLICATRIM, 0, 4)
1486REG32(L0_TM_EQ0, 0x194c)
1487    FIELD(L0_TM_EQ0, TM_EQ0_31_8_RSVD, 24, 8)
1488    FIELD(L0_TM_EQ0, EQ_STG1_RL_PROG_MSB, 7, 1)
1489    FIELD(L0_TM_EQ0, EQ_STG1_CTRL_BYP, 6, 1)
1490    FIELD(L0_TM_EQ0, EQ_STG2_CTRL_BYP, 5, 1)
1491    FIELD(L0_TM_EQ0, EQ_ADAPTATION_FORCE, 4, 1)
1492    FIELD(L0_TM_EQ0, EQ_ADAPTATION_FORCE_VAL, 3, 1)
1493    FIELD(L0_TM_EQ0, EQ_ISOURCE_EN_VAL, 0, 3)
1494REG32(L0_TM_EQ1, 0x1950)
1495    FIELD(L0_TM_EQ1, TM_EQ1_31_8_RSVD, 24, 8)
1496    FIELD(L0_TM_EQ1, EQ_STG1_PREAMP_MODE_VAL, 7, 1)
1497    FIELD(L0_TM_EQ1, EQ_STG1_RL_PROG, 5, 2)
1498    FIELD(L0_TM_EQ1, EQ_STG2_CM_PROG, 3, 2)
1499    FIELD(L0_TM_EQ1, EQ_STG2_PREAMP_MODE_VAL, 2, 1)
1500    FIELD(L0_TM_EQ1, EQ_STG2_RL_PROG, 0, 2)
1501REG32(L0_TM_EQ2, 0x1954)
1502    FIELD(L0_TM_EQ2, TM_EQ2_31_8_RSVD, 24, 8)
1503    FIELD(L0_TM_EQ2, UNUSED, 7, 1)
1504    FIELD(L0_TM_EQ2, EQ_EN_BACKGND_ADAPT, 6, 1)
1505    FIELD(L0_TM_EQ2, EQ_COUNT_STRAYS, 5, 1)
1506    FIELD(L0_TM_EQ2, EQ_WINDOW_SIZE, 3, 2)
1507    FIELD(L0_TM_EQ2, EQ_MAJ_THRESH, 1, 2)
1508    FIELD(L0_TM_EQ2, EQ_BIAS_CTRL_BYP, 0, 1)
1509REG32(L0_TM_EQ3, 0x1958)
1510    FIELD(L0_TM_EQ3, TM_EQ3_31_8_RSVD, 24, 8)
1511    FIELD(L0_TM_EQ3, UNUSED, 5, 3)
1512    FIELD(L0_TM_EQ3, EQ_BYPASS_ISINK_ENZ_VAL, 0, 5)
1513REG32(L0_TM_EQ4, 0x195c)
1514    FIELD(L0_TM_EQ4, TM_EQ4_31_8_RSVD, 24, 8)
1515    FIELD(L0_TM_EQ4, UNUSED, 5, 3)
1516    FIELD(L0_TM_EQ4, BYPASS_EQ_C_STG1, 4, 1)
1517    FIELD(L0_TM_EQ4, BYPASS_EQ_C_VAL_STG1, 0, 4)
1518REG32(L0_TM_EQ5, 0x1960)
1519    FIELD(L0_TM_EQ5, TM_EQ5_31_8_RSVD, 24, 8)
1520    FIELD(L0_TM_EQ5, UNUSED, 6, 2)
1521    FIELD(L0_TM_EQ5, BYPASS_EQ_R_STG1, 5, 1)
1522    FIELD(L0_TM_EQ5, BYPASS_EQ_R_VAL_STG1, 0, 5)
1523REG32(L0_TM_EQ6, 0x1964)
1524    FIELD(L0_TM_EQ6, TM_EQ6_31_8_RSVD, 24, 8)
1525    FIELD(L0_TM_EQ6, UNUSED, 5, 3)
1526    FIELD(L0_TM_EQ6, BYPASS_EQ_C_STG2, 4, 1)
1527    FIELD(L0_TM_EQ6, BYPASS_EQ_C_VAL_STG2, 0, 4)
1528REG32(L0_TM_EQ7, 0x1968)
1529    FIELD(L0_TM_EQ7, TM_EQ7_31_8_RSVD, 24, 8)
1530    FIELD(L0_TM_EQ7, UNUSED, 6, 2)
1531    FIELD(L0_TM_EQ7, BYPASS_EQ_R_STG2, 5, 1)
1532    FIELD(L0_TM_EQ7, BYPASS_EQ_R_VAL_STG2, 0, 5)
1533REG32(L0_TM_EQ8, 0x196c)
1534    FIELD(L0_TM_EQ8, TM_EQ8_31_8_RSVD, 24, 8)
1535    FIELD(L0_TM_EQ8, EQ_BYPASS_CALIB, 7, 1)
1536    FIELD(L0_TM_EQ8, EQ_SWEEP, 5, 2)
1537    FIELD(L0_TM_EQ8, SEL_SAMP, 2, 3)
1538    FIELD(L0_TM_EQ8, BYPASS_EQ_CAL, 1, 1)
1539    FIELD(L0_TM_EQ8, BYPASS_EQ_CAL_VAL, 0, 1)
1540REG32(L0_TM_EQ9, 0x1970)
1541    FIELD(L0_TM_EQ9, TM_EQ9_31_8_RSVD, 24, 8)
1542    FIELD(L0_TM_EQ9, UNUSED, 7, 1)
1543    FIELD(L0_TM_EQ9, EQ_BYPASS_CALIB_CODE, 0, 7)
1544REG32(L0_TM_EQ10, 0x1974)
1545    FIELD(L0_TM_EQ10, TM_EQ10_31_8_RSVD, 24, 8)
1546    FIELD(L0_TM_EQ10, UNUSED, 7, 1)
1547    FIELD(L0_TM_EQ10, OFFSET_COEF_SCALER, 4, 3)
1548    FIELD(L0_TM_EQ10, DIAG_OUTPUT_SEL, 0, 4)
1549REG32(L0_TM_EQ11, 0x1978)
1550    FIELD(L0_TM_EQ11, TM_EQ11_31_8_RSVD, 24, 8)
1551    FIELD(L0_TM_EQ11, EQ_CALIB_CLK_DIV_FORCE, 7, 1)
1552    FIELD(L0_TM_EQ11, EDGE_IS_FIRST, 6, 1)
1553    FIELD(L0_TM_EQ11, FORCE_EQ_OFFS_ON, 5, 1)
1554    FIELD(L0_TM_EQ11, FORCE_EQ_OFFS_OFF, 4, 1)
1555    FIELD(L0_TM_EQ11, EQ_OFFS_WITH_ADAPT, 3, 1)
1556    FIELD(L0_TM_EQ11, OFFSET_VOTER_OVERRIDE_EN, 2, 1)
1557    FIELD(L0_TM_EQ11, OFFSET_VOTER_OVERRIDE_NEG, 1, 1)
1558    FIELD(L0_TM_EQ11, OFFSET_VOTER_OVERRIDE_POS, 0, 1)
1559REG32(L0_TM_ILL7, 0x197c)
1560    FIELD(L0_TM_ILL7, TM_ILL7_31_8_RSVD, 24, 8)
1561    FIELD(L0_TM_ILL7, ILL_CAL_INIT_WAIT, 0, 8)
1562REG32(L0_TM_ILL8, 0x1980)
1563    FIELD(L0_TM_ILL8, TM_ILL8_31_8_RSVD, 24, 8)
1564    FIELD(L0_TM_ILL8, ILL_CAL_ITER_WAIT, 0, 8)
1565REG32(L0_TM_ILL9, 0x1984)
1566    FIELD(L0_TM_ILL9, TM_ILL9_31_8_RSVD, 24, 8)
1567    FIELD(L0_TM_ILL9, ILL_CAL_BYPASS_CAP_START, 7, 1)
1568    FIELD(L0_TM_ILL9, ILL_CAL_CAP_START_VAL, 0, 7)
1569REG32(L0_TM_ILL10, 0x1988)
1570    FIELD(L0_TM_ILL10, TM_ILL10_31_8_RSVD, 24, 8)
1571    FIELD(L0_TM_ILL10, G3A_USB3_PCIEG2_PLL_CTR_11_8_BYP_VAL, 4, 4)
1572    FIELD(L0_TM_ILL10, G3B_PLL_CTR_11_8_BYP_VAL, 0, 4)
1573REG32(L0_TM_ILL11, 0x198c)
1574    FIELD(L0_TM_ILL11, TM_ILL11_31_8_RSVD, 24, 8)
1575    FIELD(L0_TM_ILL11, G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL, 4, 4)
1576    FIELD(L0_TM_ILL11, G2B_PLL_CTR_11_8_BYP_VAL, 0, 4)
1577REG32(L0_TM_ILL12, 0x1990)
1578    FIELD(L0_TM_ILL12, TM_ILL12_31_8_RSVD, 24, 8)
1579    FIELD(L0_TM_ILL12, G1A_PLL_CTR_BYP_VAL, 0, 8)
1580REG32(L0_TM_ILL13, 0x1994)
1581    FIELD(L0_TM_ILL13, TM_ILL13_31_8_RSVD, 24, 8)
1582    FIELD(L0_TM_ILL13, ILL_CAL_IDLE_VAL_REFCNT, 0, 3)
1583REG32(L0_TM_ILL14, 0x1998)
1584    FIELD(L0_TM_ILL14, TM_ILL14_31_8_RSVD, 24, 8)
1585    FIELD(L0_TM_ILL14, ILL_CALIB_WAIT, 4, 4)
1586    FIELD(L0_TM_ILL14, ILL_CHG_WAIT, 0, 4)
1587REG32(L0_TM_FRZ_FSM0, 0x199c)
1588    FIELD(L0_TM_FRZ_FSM0, TM_FRZ_FSM0_31_8_RSVD, 24, 8)
1589    FIELD(L0_TM_FRZ_FSM0, FREEZE_HSRX_PWR_SEQ_FSM, 0, 8)
1590REG32(L0_TM_FRZ_FSM1, 0x19a0)
1591    FIELD(L0_TM_FRZ_FSM1, TM_FRZ_FSM1_31_8_RSVD, 24, 8)
1592    FIELD(L0_TM_FRZ_FSM1, UNUSED, 6, 2)
1593    FIELD(L0_TM_FRZ_FSM1, FREEZE_ILL_CALIB_FSM, 0, 6)
1594REG32(L0_TM_RST_DLY, 0x19a4)
1595    FIELD(L0_TM_RST_DLY, TM_RST_DLY_31_8_RSVD, 24, 8)
1596    FIELD(L0_TM_RST_DLY, APB_RST_DLY, 0, 8)
1597REG32(L0_TM_ILL15, 0x19a8)
1598    FIELD(L0_TM_ILL15, TM_ILL15_31_8_RSVD, 24, 8)
1599    FIELD(L0_TM_ILL15, ILL_CAL_REF_CTR_MSB_REG1, 0, 8)
1600REG32(L0_TM_MISC3, 0x19ac)
1601    FIELD(L0_TM_MISC3, TM_MISC3_31_8_RSVD, 24, 8)
1602    FIELD(L0_TM_MISC3, AUX0_BIT_7, 7, 1)
1603    FIELD(L0_TM_MISC3, AUX0_BIT_6, 6, 1)
1604    FIELD(L0_TM_MISC3, AUX0_BIT_5, 5, 1)
1605    FIELD(L0_TM_MISC3, DBG_BUS_SEL, 2, 3)
1606    FIELD(L0_TM_MISC3, CDR_EN_FPL, 1, 1)
1607    FIELD(L0_TM_MISC3, CDR_EN_FFL, 0, 1)
1608REG32(L0_TM_EQ_OFFS1, 0x19b0)
1609    FIELD(L0_TM_EQ_OFFS1, TM_EQ_OFFS1_31_8_RSVD, 24, 8)
1610    FIELD(L0_TM_EQ_OFFS1, EQ_OFFSET_CORR_BYP, 1, 7)
1611    FIELD(L0_TM_EQ_OFFS1, AUX1_BIT_7, 0, 1)
1612REG32(L0_TM_SAMP0, 0x19b4)
1613    FIELD(L0_TM_SAMP0, TM_SAMP0_31_8_RSVD, 24, 8)
1614    FIELD(L0_TM_SAMP0, SAMP_CALIB_CLK_DIV_FACTOR, 1, 7)
1615    FIELD(L0_TM_SAMP0, SAMP_CALIB_CLK_DIV_FORCE, 0, 1)
1616REG32(L0_TM_EQ12, 0x19b8)
1617    FIELD(L0_TM_EQ12, TM_EQ12_31_8_RSVD, 24, 8)
1618    FIELD(L0_TM_EQ12, EQ_CALIB_CLK_DIV_FACTOR, 0, 8)
1619REG32(L0_TM_MISC4, 0x19bc)
1620    FIELD(L0_TM_MISC4, TM_MISC4_31_8_RSVD, 24, 8)
1621    FIELD(L0_TM_MISC4, PSO_CLK_LANE_FRM_PCS, 2, 1)
1622    FIELD(L0_TM_MISC4, BSCAN_MODE_VAL, 1, 1)
1623    FIELD(L0_TM_MISC4, BSCAN_FORCE_MODE, 0, 1)
1624REG32(L0_TM_SAMP_STATUS0, 0x1a80)
1625    FIELD(L0_TM_SAMP_STATUS0, TM_SAMP_STATUS0_31_8_RSVD, 24, 8)
1626    FIELD(L0_TM_SAMP_STATUS0, IQ_SAMP_PH0_CALIB_CODE, 0, 6)
1627REG32(L0_TM_SAMP_STATUS1, 0x1a84)
1628    FIELD(L0_TM_SAMP_STATUS1, TM_SAMP_STATUS1_31_8_RSVD, 24, 8)
1629    FIELD(L0_TM_SAMP_STATUS1, IQ_SAMP_PH90_CALIB_CODE, 0, 6)
1630REG32(L0_TM_SAMP_STATUS2, 0x1a88)
1631    FIELD(L0_TM_SAMP_STATUS2, TM_SAMP_STATUS2_31_8_RSVD, 24, 8)
1632    FIELD(L0_TM_SAMP_STATUS2, IQ_SAMP_PH180_CALIB_CODE, 0, 6)
1633REG32(L0_TM_SAMP_STATUS3, 0x1a8c)
1634    FIELD(L0_TM_SAMP_STATUS3, TM_SAMP_STATUS3_31_8_RSVD, 24, 8)
1635    FIELD(L0_TM_SAMP_STATUS3, IQ_SAMP_PH270_CALIB_CODE, 0, 6)
1636REG32(L0_TM_SAMP_STATUS4, 0x1a90)
1637    FIELD(L0_TM_SAMP_STATUS4, TM_SAMP_STATUS4_31_8_RSVD, 24, 8)
1638    FIELD(L0_TM_SAMP_STATUS4, E_SAMP_PH0_CALIB_CODE, 0, 6)
1639REG32(L0_TM_SAMP_STATUS5, 0x1a94)
1640    FIELD(L0_TM_SAMP_STATUS5, TM_SAMP_STATUS5_31_8_RSVD, 24, 8)
1641    FIELD(L0_TM_SAMP_STATUS5, E_SAMP_PH180_CALIB_CODE, 0, 6)
1642REG32(L0_TM_ILL_STATUS0, 0x1a98)
1643    FIELD(L0_TM_ILL_STATUS0, TM_ILL_STATUS0_31_8_RSVD, 24, 8)
1644    FIELD(L0_TM_ILL_STATUS0, IQ_F0_CALCODE_CALIB_VAL, 0, 7)
1645REG32(L0_TM_ILL_STATUS1, 0x1a9c)
1646    FIELD(L0_TM_ILL_STATUS1, TM_ILL_STATUS1_31_8_RSVD, 24, 8)
1647    FIELD(L0_TM_ILL_STATUS1, IQ_F1_CALCODE_CALIB_VAL, 0, 7)
1648REG32(L0_TM_ILL_STATUS2, 0x1aa0)
1649    FIELD(L0_TM_ILL_STATUS2, TM_ILL_STATUS2_31_8_RSVD, 24, 8)
1650    FIELD(L0_TM_ILL_STATUS2, IQ_F2_CALCODE_CALIB_VAL, 0, 7)
1651REG32(L0_TM_ILL_STATUS3, 0x1aa4)
1652    FIELD(L0_TM_ILL_STATUS3, TM_ILL_STATUS3_31_8_RSVD, 24, 8)
1653    FIELD(L0_TM_ILL_STATUS3, IQ_F3_CALCODE_CALIB_VAL, 0, 7)
1654REG32(L0_TM_ILL_STATUS4, 0x1aa8)
1655    FIELD(L0_TM_ILL_STATUS4, TM_ILL_STATUS4_31_8_RSVD, 24, 8)
1656    FIELD(L0_TM_ILL_STATUS4, IQ_F4_CALCODE_CALIB_VAL, 0, 7)
1657REG32(L0_TM_ILL_STATUS5, 0x1aac)
1658    FIELD(L0_TM_ILL_STATUS5, TM_ILL_STATUS5_31_8_RSVD, 24, 8)
1659    FIELD(L0_TM_ILL_STATUS5, IQ_F5_CALCODE_CALIB_VAL, 0, 7)
1660REG32(L0_TM_ILL_STATUS6, 0x1ab0)
1661    FIELD(L0_TM_ILL_STATUS6, TM_ILL_STATUS6_31_8_RSVD, 24, 8)
1662    FIELD(L0_TM_ILL_STATUS6, E_F0_CALCODE_CALIB_VAL, 0, 7)
1663REG32(L0_TM_ILL_STATUS7, 0x1ab4)
1664    FIELD(L0_TM_ILL_STATUS7, TM_ILL_STATUS7_31_8_RSVD, 24, 8)
1665    FIELD(L0_TM_ILL_STATUS7, E_F1_CALCODE_CALIB_VAL, 0, 7)
1666REG32(L0_TM_ILL_STATUS8, 0x1ab8)
1667    FIELD(L0_TM_ILL_STATUS8, TM_ILL_STATUS8_31_8_RSVD, 24, 8)
1668    FIELD(L0_TM_ILL_STATUS8, E_F2_CALCODE_CALIB_VAL, 0, 7)
1669REG32(L0_TM_ILL_STATUS9, 0x1abc)
1670    FIELD(L0_TM_ILL_STATUS9, TM_ILL_STATUS9_31_8_RSVD, 24, 8)
1671    FIELD(L0_TM_ILL_STATUS9, E_F3_CALCODE_CALIB_VAL, 0, 7)
1672REG32(L0_TM_ILL_STATUS10, 0x1ac0)
1673    FIELD(L0_TM_ILL_STATUS10, TM_ILL_STATUS10_31_8_RSVD, 24, 8)
1674    FIELD(L0_TM_ILL_STATUS10, E_F4_CALCODE_CALIB_VAL, 0, 7)
1675REG32(L0_TM_ILL_STATUS11, 0x1ac4)
1676    FIELD(L0_TM_ILL_STATUS11, TM_ILL_STATUS11_31_8_RSVD, 24, 8)
1677    FIELD(L0_TM_ILL_STATUS11, E_F5_CALCODE_CALIB_VAL, 0, 7)
1678REG32(L0_TM_MISC_ST_0, 0x1ac8)
1679    FIELD(L0_TM_MISC_ST_0, TM_MISC_ST_0_31_8_RSVD, 24, 8)
1680    FIELD(L0_TM_MISC_ST_0, EYE_SURF_DONE, 5, 1)
1681    FIELD(L0_TM_MISC_ST_0, SD_CAL_DONE, 4, 1)
1682    FIELD(L0_TM_MISC_ST_0, SAMP_CAL_DONE, 3, 1)
1683    FIELD(L0_TM_MISC_ST_0, ILL_CAL_DONE, 2, 1)
1684    FIELD(L0_TM_MISC_ST_0, EQ_CAL_DONE, 1, 1)
1685    FIELD(L0_TM_MISC_ST_0, EQ_VALID_ADAPT_CODE, 0, 1)
1686REG32(L0_TM_SD_ST_0, 0x1acc)
1687    FIELD(L0_TM_SD_ST_0, TM_SD_ST_0_31_8_RSVD, 24, 8)
1688    FIELD(L0_TM_SD_ST_0, SD_CAL_CODE, 0, 6)
1689REG32(L0_TM_EYESURF_ST0, 0x1ad0)
1690    FIELD(L0_TM_EYESURF_ST0, TM_EYESURF_ST0_31_8_RSVD, 24, 8)
1691    FIELD(L0_TM_EYESURF_ST0, ERROR_COUNT0, 0, 8)
1692REG32(L0_TM_EYESURF_ST1, 0x1ad4)
1693    FIELD(L0_TM_EYESURF_ST1, TM_EYESURF_ST1_31_8_RSVD, 24, 8)
1694    FIELD(L0_TM_EYESURF_ST1, ERROR_COUNT1, 0, 8)
1695REG32(L0_TM_EQ_ST0, 0x1ad8)
1696    FIELD(L0_TM_EQ_ST0, TM_EQ_ST0_31_8_RSVD, 24, 8)
1697    FIELD(L0_TM_EQ_ST0, EQ_ADAPT_CODE0, 0, 8)
1698REG32(L0_TM_EQ_ST1, 0x1adc)
1699    FIELD(L0_TM_EQ_ST1, TM_EQ_ST1_31_8_RSVD, 24, 8)
1700    FIELD(L0_TM_EQ_ST1, EQ_ADAPT_CODE1, 0, 8)
1701REG32(L0_TM_EQ_ST2, 0x1ae0)
1702    FIELD(L0_TM_EQ_ST2, TM_EQ_ST2_31_8_RSVD, 24, 8)
1703    FIELD(L0_TM_EQ_ST2, EQ_CALIB_CODE, 0, 7)
1704REG32(L0_TM_RXPMA_ST1, 0x1ae4)
1705    FIELD(L0_TM_RXPMA_ST1, TM_RXPMA_ST1_31_8_RSVD, 24, 8)
1706    FIELD(L0_TM_RXPMA_ST1, HSRX_OPMODE_STATUS, 0, 8)
1707REG32(L0_TM_CDR0, 0x1c00)
1708    FIELD(L0_TM_CDR0, TM_CDR0_31_8_RSVD, 24, 8)
1709    FIELD(L0_TM_CDR0, FAST_PHASE_LOCK_FORCE, 7, 1)
1710    FIELD(L0_TM_CDR0, UNUSED, 5, 2)
1711    FIELD(L0_TM_CDR0, CDR_LOOP_CTRL, 2, 3)
1712    FIELD(L0_TM_CDR0, SECOND_ORDER_LOOP_DIS, 1, 1)
1713    FIELD(L0_TM_CDR0, FIRST_ORDER_LOOP_DIS, 0, 1)
1714REG32(L0_TM_CDR1, 0x1c04)
1715    FIELD(L0_TM_CDR1, TM_CDR1_31_8_RSVD, 24, 8)
1716    FIELD(L0_TM_CDR1, RESET_DELAY_2OL, 0, 8)
1717REG32(L0_TM_CDR2, 0x1c08)
1718    FIELD(L0_TM_CDR2, TM_CDR2_31_8_RSVD, 24, 8)
1719    FIELD(L0_TM_CDR2, CLK_SEL_2OL, 6, 2)
1720    FIELD(L0_TM_CDR2, INTEGRATOR_THRESH_2OL, 0, 6)
1721REG32(L0_TM_CDR3, 0x1c0c)
1722    FIELD(L0_TM_CDR3, TM_CDR3_31_8_RSVD, 24, 8)
1723    FIELD(L0_TM_CDR3, UNUSED, 7, 1)
1724    FIELD(L0_TM_CDR3, SIGNAL_THRESH_1OL, 0, 7)
1725REG32(L0_TM_CDR4, 0x1c10)
1726    FIELD(L0_TM_CDR4, TM_CDR4_31_8_RSVD, 24, 8)
1727    FIELD(L0_TM_CDR4, UNUSED, 7, 1)
1728    FIELD(L0_TM_CDR4, SIGNAL_THRESH_2OL, 0, 7)
1729REG32(L0_TM_CDR5, 0x1c14)
1730    FIELD(L0_TM_CDR5, TM_CDR5_31_8_RSVD, 24, 8)
1731    FIELD(L0_TM_CDR5, FPHL_FSM_ACC_CYCLES, 5, 3)
1732    FIELD(L0_TM_CDR5, FFL_PH0_INT_GAIN, 0, 5)
1733REG32(L0_TM_CDR6, 0x1c18)
1734    FIELD(L0_TM_CDR6, TM_CDR6_31_8_RSVD, 24, 8)
1735    FIELD(L0_TM_CDR6, FPHL_FSM_DELAY_CYCLES, 5, 3)
1736    FIELD(L0_TM_CDR6, FFL_PH1_INT_GAIN, 0, 5)
1737REG32(L0_TM_CDR7, 0x1c1c)
1738    FIELD(L0_TM_CDR7, TM_CDR7_31_8_RSVD, 24, 8)
1739    FIELD(L0_TM_CDR7, FPHL_FSM_TRIGGER1_WAIT_CYCLES, 5, 3)
1740    FIELD(L0_TM_CDR7, FFL_PH2_INT_GAIN, 0, 5)
1741REG32(L0_TM_CDR8, 0x1c20)
1742    FIELD(L0_TM_CDR8, TM_CDR8_31_8_RSVD, 24, 8)
1743    FIELD(L0_TM_CDR8, FPHL_FSM_TRIGGER2_WAIT_CYCLES, 5, 3)
1744    FIELD(L0_TM_CDR8, FFL_PH3_INT_GAIN, 0, 5)
1745REG32(L0_TM_CDR9, 0x1c24)
1746    FIELD(L0_TM_CDR9, TM_CDR9_31_8_RSVD, 24, 8)
1747    FIELD(L0_TM_CDR9, FPHL_FSM_TRIGGER3_WAIT_CYCLES, 5, 3)
1748    FIELD(L0_TM_CDR9, FFL_PH4_INT_GAIN, 0, 5)
1749REG32(L0_TM_CDR10, 0x1c28)
1750    FIELD(L0_TM_CDR10, TM_CDR10_31_8_RSVD, 24, 8)
1751    FIELD(L0_TM_CDR10, FFL_TIME_PER_PHASE_10_8, 5, 3)
1752    FIELD(L0_TM_CDR10, FFL_PH5_INT_GAIN, 0, 5)
1753REG32(L0_TM_CDR11, 0x1c2c)
1754    FIELD(L0_TM_CDR11, TM_CDR11_31_8_RSVD, 24, 8)
1755    FIELD(L0_TM_CDR11, UNUSED, 5, 3)
1756    FIELD(L0_TM_CDR11, FFL_PH6_INT_GAIN, 0, 5)
1757REG32(L0_TM_CDR12, 0x1c30)
1758    FIELD(L0_TM_CDR12, TM_CDR12_31_8_RSVD, 24, 8)
1759    FIELD(L0_TM_CDR12, CDRLF_RESET_ON_EN_CDR, 7, 1)
1760    FIELD(L0_TM_CDR12, CDRLF_RESET_ON_INT_MAX_2OL, 6, 1)
1761    FIELD(L0_TM_CDR12, CDRLF_RESET_ON_MODE_CHG, 5, 1)
1762    FIELD(L0_TM_CDR12, FFL_PH7_INT_GAIN, 0, 5)
1763REG32(L0_TM_CDR13, 0x1c34)
1764    FIELD(L0_TM_CDR13, TM_CDR13_31_8_RSVD, 24, 8)
1765    FIELD(L0_TM_CDR13, FFL_TIME_PER_PHASE_7_0, 0, 8)
1766REG32(L0_TM_CDR14, 0x1c38)
1767    FIELD(L0_TM_CDR14, TM_CDR14_31_8_RSVD, 24, 8)
1768    FIELD(L0_TM_CDR14, FFL_PH3_POST_INT_GAIN, 6, 2)
1769    FIELD(L0_TM_CDR14, FFL_PH2_POST_INT_GAIN, 4, 2)
1770    FIELD(L0_TM_CDR14, FFL_PH1_POST_INT_GAIN, 2, 2)
1771    FIELD(L0_TM_CDR14, FFL_PH0_POST_INT_GAIN, 0, 2)
1772REG32(L0_TM_CDR15, 0x1c3c)
1773    FIELD(L0_TM_CDR15, TM_CDR15_31_8_RSVD, 24, 8)
1774    FIELD(L0_TM_CDR15, FFL_PH7_POST_INT_GAIN, 6, 2)
1775    FIELD(L0_TM_CDR15, FFL_PH6_POST_INT_GAIN, 4, 2)
1776    FIELD(L0_TM_CDR15, FFL_PH5_POST_INT_GAIN, 2, 2)
1777    FIELD(L0_TM_CDR15, FFL_PH4_POST_INT_GAIN, 0, 2)
1778REG32(L0_TM_CDR16, 0x1c40)
1779    FIELD(L0_TM_CDR16, TM_CDR16_31_8_RSVD, 24, 8)
1780    FIELD(L0_TM_CDR16, UNUSED, 5, 3)
1781    FIELD(L0_TM_CDR16, FFL_PH0_PROP_GAIN, 0, 5)
1782REG32(L0_TM_CDR17, 0x1c44)
1783    FIELD(L0_TM_CDR17, TM_CDR17_31_8_RSVD, 24, 8)
1784    FIELD(L0_TM_CDR17, UNUSED, 5, 3)
1785    FIELD(L0_TM_CDR17, FFL_PH1_PROP_GAIN, 0, 5)
1786REG32(L0_TM_CDR18, 0x1c48)
1787    FIELD(L0_TM_CDR18, TM_CDR18_31_8_RSVD, 24, 8)
1788    FIELD(L0_TM_CDR18, UNUSED, 5, 3)
1789    FIELD(L0_TM_CDR18, FFL_PH2_PROP_GAIN, 0, 5)
1790REG32(L0_TM_CDR19, 0x1c4c)
1791    FIELD(L0_TM_CDR19, TM_CDR19_31_8_RSVD, 24, 8)
1792    FIELD(L0_TM_CDR19, UNUSED, 5, 3)
1793    FIELD(L0_TM_CDR19, FFL_PH3_PROP_GAIN, 0, 5)
1794REG32(L0_TM_CDR20, 0x1c50)
1795    FIELD(L0_TM_CDR20, TM_CDR20_31_8_RSVD, 24, 8)
1796    FIELD(L0_TM_CDR20, UNUSED, 5, 3)
1797    FIELD(L0_TM_CDR20, FFL_PH4_PROP_GAIN, 0, 5)
1798REG32(L0_TM_CDR21, 0x1c54)
1799    FIELD(L0_TM_CDR21, TM_CDR21_31_8_RSVD, 24, 8)
1800    FIELD(L0_TM_CDR21, UNUSED, 5, 3)
1801    FIELD(L0_TM_CDR21, FFL_PH5_PROP_GAIN, 0, 5)
1802REG32(L0_TM_CDR22, 0x1c58)
1803    FIELD(L0_TM_CDR22, TM_CDR22_31_8_RSVD, 24, 8)
1804    FIELD(L0_TM_CDR22, UNUSED, 5, 3)
1805    FIELD(L0_TM_CDR22, FFL_PH6_PROP_GAIN, 0, 5)
1806REG32(L0_TM_CDR23, 0x1c5c)
1807    FIELD(L0_TM_CDR23, TM_CDR23_31_8_RSVD, 24, 8)
1808    FIELD(L0_TM_CDR23, UNUSED, 7, 1)
1809    FIELD(L0_TM_CDR23, PHASE_LAG_LEAD_RESPONSE, 5, 2)
1810    FIELD(L0_TM_CDR23, FFL_PH7_PROP_GAIN, 0, 5)
1811REG32(L0_TM_MISC0, 0x1c60)
1812    FIELD(L0_TM_MISC0, TM_MISC0_31_8_RSVD, 24, 8)
1813    FIELD(L0_TM_MISC0, UNUSED, 2, 6)
1814    FIELD(L0_TM_MISC0, DBG0_SEL, 0, 2)
1815REG32(L0_TM_HSRX_ST0, 0x1c64)
1816    FIELD(L0_TM_HSRX_ST0, TM_HSRX_ST0_31_8_RSVD, 24, 8)
1817    FIELD(L0_TM_HSRX_ST0, FAST_LOCK_STATUS, 0, 1)
1818REG32(L0_TM_PLL_LS_CLOCK, 0x2000)
1819    FIELD(L0_TM_PLL_LS_CLOCK, TM_PLL_LS_CLOCK_31_8_RSVD, 24, 8)
1820    FIELD(L0_TM_PLL_LS_CLOCK, TM_PLL_LS_CLOCK, 0, 8)
1821REG32(L0_TM_PLL_LOOP_FILT, 0x2004)
1822    FIELD(L0_TM_PLL_LOOP_FILT, TM_PLL_LOOP_FILT_31_8_RSVD, 24, 8)
1823    FIELD(L0_TM_PLL_LOOP_FILT, TM_FORCE_RES_SW_ON, 7, 1)
1824    FIELD(L0_TM_PLL_LOOP_FILT, TM_MPHY_USB3_R2_HIGH_RES_SW_ON, 6, 1)
1825    FIELD(L0_TM_PLL_LOOP_FILT, TM_MPHY_USB3_R2_LOW_RES_SW_ON, 5, 1)
1826    FIELD(L0_TM_PLL_LOOP_FILT, TM_PCIE_R1_DEFAULT_RES_SW_ON, 4, 1)
1827    FIELD(L0_TM_PLL_LOOP_FILT, TM_PCIE_R1_HIGH_RES_SW_ON, 3, 1)
1828    FIELD(L0_TM_PLL_LOOP_FILT, TM_PCIE_R1_LOW_RES_SW_ON, 2, 1)
1829    FIELD(L0_TM_PLL_LOOP_FILT, TM_BYPASS_SEC_LOOP_FILTER, 1, 1)
1830    FIELD(L0_TM_PLL_LOOP_FILT, TM_SEC_LOOP, 0, 1)
1831REG32(L0_TM_PLL_DIG2, 0x2008)
1832    FIELD(L0_TM_PLL_DIG2, TM_PLL_DIG2_31_8_RSVD, 24, 8)
1833    FIELD(L0_TM_PLL_DIG2, TM_FBDIV_0_LSB, 7, 1)
1834    FIELD(L0_TM_PLL_DIG2, TM_PLL_HS_CLOCK_0, 0, 7)
1835REG32(L0_TM_PLL_FBDIV, 0x200c)
1836    FIELD(L0_TM_PLL_FBDIV, TM_PLL_FBDIV_31_8_RSVD, 24, 8)
1837    FIELD(L0_TM_PLL_FBDIV, TM_FBDIV_1, 0, 8)
1838REG32(L0_TM_PLL_DIG4, 0x2010)
1839    FIELD(L0_TM_PLL_DIG4, TM_PLL_DIG4_31_8_RSVD, 24, 8)
1840    FIELD(L0_TM_PLL_DIG4, TM_VCO_CLOCK_PULDN, 7, 1)
1841    FIELD(L0_TM_PLL_DIG4, TM_FORCE_ANA_COARSEDONE, 6, 1)
1842    FIELD(L0_TM_PLL_DIG4, TM_ANA_COARSEDONE, 5, 1)
1843    FIELD(L0_TM_PLL_DIG4, TM_FORCE_COARSE_DONE_INT, 4, 1)
1844    FIELD(L0_TM_PLL_DIG4, TM_COARSE_DONE_INT, 3, 1)
1845    FIELD(L0_TM_PLL_DIG4, TM_FORCE_FBDIV, 2, 1)
1846    FIELD(L0_TM_PLL_DIG4, TM_FBDIV_2, 0, 2)
1847REG32(L0_TM_PLL_DIG5, 0x2014)
1848    FIELD(L0_TM_PLL_DIG5, TM_PLL_DIG5_31_8_RSVD, 24, 8)
1849    FIELD(L0_TM_PLL_DIG5, TM_PD_6GHZ_LOWNOISE_RING, 7, 1)
1850    FIELD(L0_TM_PLL_DIG5, TM_PD_6GHZ_RING, 6, 1)
1851    FIELD(L0_TM_PLL_DIG5, TM_COARSE_PROG, 1, 5)
1852    FIELD(L0_TM_PLL_DIG5, TM_FORCE_VCO_CLOCK_PULDN, 0, 1)
1853REG32(L0_TM_PLL_DIG6, 0x2018)
1854    FIELD(L0_TM_PLL_DIG6, TM_PLL_DIG6_31_8_RSVD, 24, 8)
1855    FIELD(L0_TM_PLL_DIG6, TM_CONFG_CHNG_CYCLES_0_LSB, 7, 1)
1856    FIELD(L0_TM_PLL_DIG6, TM_VCO_SETTLE_CYCLES, 5, 2)
1857    FIELD(L0_TM_PLL_DIG6, TM_INITIAL_WAIT_CYCLES, 3, 2)
1858    FIELD(L0_TM_PLL_DIG6, TM_FORCE_COARSE_PROG_PD_RING, 2, 1)
1859    FIELD(L0_TM_PLL_DIG6, TM_PD_1P5GHZ_RING, 1, 1)
1860    FIELD(L0_TM_PLL_DIG6, TM_PD_3GHZ_RING, 0, 1)
1861REG32(L0_TM_PLL_DIG7, 0x201c)
1862    FIELD(L0_TM_PLL_DIG7, TM_PLL_DIG7_31_8_RSVD, 24, 8)
1863    FIELD(L0_TM_PLL_DIG7, TM_CPUMP_CODE_0_LSB, 7, 1)
1864    FIELD(L0_TM_PLL_DIG7, TM_FORCE_ANA_START_LOOP, 6, 1)
1865    FIELD(L0_TM_PLL_DIG7, TM_ANA_START_LOOP, 5, 1)
1866    FIELD(L0_TM_PLL_DIG7, TM_PLL_LOCK_CYCLES, 3, 2)
1867    FIELD(L0_TM_PLL_DIG7, TM_STAND_BY_SETTLE_CYCLES, 1, 2)
1868    FIELD(L0_TM_PLL_DIG7, TM_CONFG_CHNG_CYCLES_1_MSB, 0, 1)
1869REG32(L0_TM_PLL_CPUMP_CODE_1, 0x2020)
1870    FIELD(L0_TM_PLL_CPUMP_CODE_1, TM_PLL_CPUMP_CODE_1_31_8_RSVD, 24, 8)
1871    FIELD(L0_TM_PLL_CPUMP_CODE_1, TM_CPUMP_CODE_1, 0, 8)
1872REG32(L0_TM_PLL_DIG9, 0x2024)
1873    FIELD(L0_TM_PLL_DIG9, TM_PLL_DIG9_31_8_RSVD, 24, 8)
1874    FIELD(L0_TM_PLL_DIG9, TM_PLL_RSVD, 6, 2)
1875    FIELD(L0_TM_PLL_DIG9, TM_FB_BY2_BYPASS, 5, 1)
1876    FIELD(L0_TM_PLL_DIG9, TM_FORCE_CP_CODE, 4, 1)
1877    FIELD(L0_TM_PLL_DIG9, TM_CPUMP_CODE_2_MSB, 0, 4)
1878REG32(L0_TM_PLL_COARSE_CODE_LSB, 0x2028)
1879    FIELD(L0_TM_PLL_COARSE_CODE_LSB, TM_PLL_COARSE_CODE_LSB_31_8_RSVD, 24, 8)
1880    FIELD(L0_TM_PLL_COARSE_CODE_LSB, TM_COARSE_CODE_LSB, 0, 8)
1881REG32(L0_TM_PLL_DIG11, 0x202c)
1882    FIELD(L0_TM_PLL_DIG11, TM_PLL_DIG11_31_8_RSVD, 24, 8)
1883    FIELD(L0_TM_PLL_DIG11, TM_CONST_NDAC_CNTRL, 4, 4)
1884    FIELD(L0_TM_PLL_DIG11, TM_FORCE_COARSE_CODE, 3, 1)
1885    FIELD(L0_TM_PLL_DIG11, TM_COARSE_CODE_MSB, 0, 3)
1886REG32(L0_TM_PLL_DIG12, 0x2030)
1887    FIELD(L0_TM_PLL_DIG12, TM_PLL_DIG12_31_8_RSVD, 24, 8)
1888    FIELD(L0_TM_PLL_DIG12, TM_FORCE_PTAT_NDAC_CNTRL, 7, 1)
1889    FIELD(L0_TM_PLL_DIG12, TM_PTAT_NDAC_CNTRL, 1, 6)
1890    FIELD(L0_TM_PLL_DIG12, TM_FORCE_CONST_NDAC_CNTRL, 0, 1)
1891REG32(L0_TM_PLL_CONST_PMOS, 0x2034)
1892    FIELD(L0_TM_PLL_CONST_PMOS, TM_PLL_CONST_PMOS_31_8_RSVD, 24, 8)
1893    FIELD(L0_TM_PLL_CONST_PMOS, TM_CONST_PMOS_CNTRL, 0, 8)
1894REG32(L0_TM_PLL_DIG14, 0x2038)
1895    FIELD(L0_TM_PLL_DIG14, TM_PLL_DIG14_31_8_RSVD, 24, 8)
1896    FIELD(L0_TM_PLL_DIG14, TM_COARSE_CODE_AFTER_V2I_0_LSB, 1, 7)
1897    FIELD(L0_TM_PLL_DIG14, TM_FORCE_CONST_PMOS_CNTRL, 0, 1)
1898REG32(L0_TM_PLL_DIG15, 0x203c)
1899    FIELD(L0_TM_PLL_DIG15, TM_PLL_DIG15_31_8_RSVD, 24, 8)
1900    FIELD(L0_TM_PLL_DIG15, TM_V2I_CODE_0_LSB, 5, 3)
1901    FIELD(L0_TM_PLL_DIG15, TM_FORCE_COARSE_CODE_AFTER_V2I, 4, 1)
1902    FIELD(L0_TM_PLL_DIG15, TM_COARSE_CODE_AFTER_V2I_1_MSB, 0, 4)
1903REG32(L0_TM_PLL_DIG16, 0x2040)
1904    FIELD(L0_TM_PLL_DIG16, TM_PLL_DIG16_31_8_RSVD, 24, 8)
1905    FIELD(L0_TM_PLL_DIG16, TM_FORCE_PLL_LOCK, 7, 1)
1906    FIELD(L0_TM_PLL_DIG16, TM_PLL_LOCK, 6, 1)
1907    FIELD(L0_TM_PLL_DIG16, TM_FORCE_SS_NO_STEPS_STEP_SIZE, 5, 1)
1908    FIELD(L0_TM_PLL_DIG16, TM_PLL_RSVD, 4, 1)
1909    FIELD(L0_TM_PLL_DIG16, TM_FORCE_V2I_CODE, 3, 1)
1910    FIELD(L0_TM_PLL_DIG16, TM_V2I_CODE_1_MSB, 0, 3)
1911REG32(L0_TM_PLL_DIG17, 0x2044)
1912    FIELD(L0_TM_PLL_DIG17, TM_PLL_DIG17_31_8_RSVD, 24, 8)
1913    FIELD(L0_TM_PLL_DIG17, TM_FB_CLK, 6, 2)
1914    FIELD(L0_TM_PLL_DIG17, TM_MODE_DEPTH, 3, 3)
1915    FIELD(L0_TM_PLL_DIG17, TM_MODE_RATE, 0, 3)
1916REG32(L0_TM_PLL_DIG18, 0x2048)
1917    FIELD(L0_TM_PLL_DIG18, TM_PLL_DIG18_31_8_RSVD, 24, 8)
1918    FIELD(L0_TM_PLL_DIG18, TM_PLL_LOCK_PULDN, 7, 1)
1919    FIELD(L0_TM_PLL_DIG18, TM_STEP_SIZE_CNTRL, 5, 2)
1920    FIELD(L0_TM_PLL_DIG18, TM_SD_GSHIFT, 3, 2)
1921    FIELD(L0_TM_PLL_DIG18, TM_SD_DITHER, 1, 2)
1922    FIELD(L0_TM_PLL_DIG18, TM_PLL_LOCK_INT, 0, 1)
1923REG32(L0_TM_PLL_DIG19, 0x204c)
1924    FIELD(L0_TM_PLL_DIG19, TM_PLL_DIG19_31_8_RSVD, 24, 8)
1925    FIELD(L0_TM_PLL_DIG19, TM_FORCE_EN_CLOCK_HS_DIV_2, 7, 1)
1926    FIELD(L0_TM_PLL_DIG19, TM_EN_CLOCK_HS_DIV_2, 6, 1)
1927    FIELD(L0_TM_PLL_DIG19, TM_PLL_HS_CLOCK_1, 3, 3)
1928    FIELD(L0_TM_PLL_DIG19, TM_PD_PFD, 2, 1)
1929    FIELD(L0_TM_PLL_DIG19, TM_FORCE_PD_PFD, 1, 1)
1930    FIELD(L0_TM_PLL_DIG19, TM_SELECT_PCI_2P5, 0, 1)
1931REG32(L0_TM_PLL_DIG20, 0x2050)
1932    FIELD(L0_TM_PLL_DIG20, TM_PLL_DIG20_31_8_RSVD, 24, 8)
1933    FIELD(L0_TM_PLL_DIG20, TM_PLL_HALF_FULL_RATE, 7, 1)
1934    FIELD(L0_TM_PLL_DIG20, TM_PLL_RSVD, 6, 1)
1935    FIELD(L0_TM_PLL_DIG20, TM_V2I_PROG, 1, 5)
1936    FIELD(L0_TM_PLL_DIG20, TM_FORCE_V2I_PROG, 0, 1)
1937REG32(L0_TM_PLL_DIG21, 0x2054)
1938    FIELD(L0_TM_PLL_DIG21, TM_PLL_DIG21_31_8_RSVD, 24, 8)
1939    FIELD(L0_TM_PLL_DIG21, TM_FORCE_EN_PLL_LDO_0P9_REF, 7, 1)
1940    FIELD(L0_TM_PLL_DIG21, ANA_TM_EN_PLL_0P9_FORCE_SW, 6, 1)
1941    FIELD(L0_TM_PLL_DIG21, TM_PLL_PD_OPDIV_SYM, 5, 1)
1942    FIELD(L0_TM_PLL_DIG21, TM_FORCE_PLL_PD_OPDIV_SYM, 4, 1)
1943    FIELD(L0_TM_PLL_DIG21, TM_PLL_RSVD_1, 3, 1)
1944    FIELD(L0_TM_PLL_DIG21, TM_PLL_RSVD_2, 2, 1)
1945    FIELD(L0_TM_PLL_DIG21, TM_PLL_EN, 1, 1)
1946    FIELD(L0_TM_PLL_DIG21, TM_FORCE_PLL_EN, 0, 1)
1947REG32(L0_TM_PLL_DIG22, 0x2058)
1948    FIELD(L0_TM_PLL_DIG22, TM_PLL_DIG22_31_8_RSVD, 24, 8)
1949    FIELD(L0_TM_PLL_DIG22, TM_PLL_RSVD, 7, 1)
1950    FIELD(L0_TM_PLL_DIG22, TM_EN_PLL_LDO_0P9_REF_CP, 6, 1)
1951    FIELD(L0_TM_PLL_DIG22, TM_FORCE_EN_PLL_LDO_0P9_REF_CP, 5, 1)
1952    FIELD(L0_TM_PLL_DIG22, TM_FORCE_COARSE_START, 4, 1)
1953    FIELD(L0_TM_PLL_DIG22, TM_FORCE_PD_PLL_LDO_1P4, 3, 1)
1954    FIELD(L0_TM_PLL_DIG22, TM_FORCE_ANA_EN_LL_DELAYED, 2, 1)
1955    FIELD(L0_TM_PLL_DIG22, TM_FORCE_ANA_EN_LL, 1, 1)
1956    FIELD(L0_TM_PLL_DIG22, TM_EN_PLL_LDO_0P9_REF, 0, 1)
1957REG32(L0_TM_PLL_DIG23, 0x205c)
1958    FIELD(L0_TM_PLL_DIG23, TM_PLL_DIG23_31_8_RSVD, 24, 8)
1959    FIELD(L0_TM_PLL_DIG23, BF_7, 7, 1)
1960    FIELD(L0_TM_PLL_DIG23, PLL_TM_VCO_LDO_BYPASS, 6, 1)
1961    FIELD(L0_TM_PLL_DIG23, TM_ANA_EN_LL_DELAYED, 5, 1)
1962    FIELD(L0_TM_PLL_DIG23, TM_ANA_EN_LL, 4, 1)
1963    FIELD(L0_TM_PLL_DIG23, TM_ANA_PD_PLL, 3, 1)
1964    FIELD(L0_TM_PLL_DIG23, TM_FORCE_PLL_PD, 2, 1)
1965    FIELD(L0_TM_PLL_DIG23, TM_ANA_COARSE_START, 1, 1)
1966    FIELD(L0_TM_PLL_DIG23, TM_PD_PLL_LDO_1P4, 0, 1)
1967REG32(L0_TM_PLL_DIG24, 0x2060)
1968    FIELD(L0_TM_PLL_DIG24, TM_PLL_DIG24_31_8_RSVD, 24, 8)
1969    FIELD(L0_TM_PLL_DIG24, TM_PLL_RSVD, 7, 1)
1970    FIELD(L0_TM_PLL_DIG24, PLL_TM_VCO_LDO, 1, 6)
1971    FIELD(L0_TM_PLL_DIG24, PLL_TM_VCO_LDO_BYPASS_WITH_SEQUENCE, 0, 1)
1972REG32(L0_TM_PLL_DIG25, 0x2064)
1973    FIELD(L0_TM_PLL_DIG25, TM_PLL_DIG25_31_8_RSVD, 24, 8)
1974    FIELD(L0_TM_PLL_DIG25, TM_FORCE_RST_N_HSRIPPLE, 7, 1)
1975    FIELD(L0_TM_PLL_DIG25, TM_RST_N_HSRIPPLE, 6, 1)
1976    FIELD(L0_TM_PLL_DIG25, TM_PLL_ATB_CNTRL, 1, 5)
1977    FIELD(L0_TM_PLL_DIG25, TM_PLL_OBSERVE_PTAT_10U, 0, 1)
1978REG32(L0_TM_PLL_DIG26, 0x2068)
1979    FIELD(L0_TM_PLL_DIG26, TM_PLL_DIG26_31_8_RSVD, 24, 8)
1980    FIELD(L0_TM_PLL_DIG26, TM_PLL_RSVD, 7, 1)
1981    FIELD(L0_TM_PLL_DIG26, TM_PD_PLL_PTAT, 6, 1)
1982    FIELD(L0_TM_PLL_DIG26, TM_FORCE_PD_PLL_PTAT, 5, 1)
1983    FIELD(L0_TM_PLL_DIG26, TM_USB3_R2_HIGH_RES_SW_ON, 4, 1)
1984    FIELD(L0_TM_PLL_DIG26, TM_PLL_SEL_VCO_DIV2_LOOP_OUT, 3, 1)
1985    FIELD(L0_TM_PLL_DIG26, TM_PLL_SEL_VCO_DIRECT_LOOP_OUT, 2, 1)
1986    FIELD(L0_TM_PLL_DIG26, TM_PLL_SEL_VCO_HISPEED_DIV2_LOOP_OUT, 1, 1)
1987    FIELD(L0_TM_PLL_DIG26, TM_FORCE_LOOP_PATH, 0, 1)
1988REG32(L0_TM_PLL_CLK_DIST_NTRIM_LSB, 0x206c)
1989    FIELD(L0_TM_PLL_CLK_DIST_NTRIM_LSB, TM_PLL_CLK_DIST_NTRIM_LSB_31_8_RSVD, 24, 8)
1990    FIELD(L0_TM_PLL_CLK_DIST_NTRIM_LSB, TM_CLKDIST_BIAS_NTRIM_LSB, 0, 8)
1991REG32(L0_TM_PLL_CLK_DIST_PTRIM_LSB, 0x2070)
1992    FIELD(L0_TM_PLL_CLK_DIST_PTRIM_LSB, TM_PLL_CLK_DIST_PTRIM_LSB_31_8_RSVD, 24, 8)
1993    FIELD(L0_TM_PLL_CLK_DIST_PTRIM_LSB, TM_CLKDIST_BIAS_PTRIM_LSB, 0, 8)
1994REG32(L0_TM_PLL_DIG_29, 0x2074)
1995    FIELD(L0_TM_PLL_DIG_29, TM_PLL_DIG_29_31_8_RSVD, 24, 8)
1996    FIELD(L0_TM_PLL_DIG_29, TM_CLKDIST_OBSRV_MRSTBUF_SUP, 7, 1)
1997    FIELD(L0_TM_PLL_DIG_29, TM_CLKDIST_OBSRV_LRSTBUF_SUP, 6, 1)
1998    FIELD(L0_TM_PLL_DIG_29, TM_CLKDIST_ENABLE_RST_RPTR, 5, 1)
1999    FIELD(L0_TM_PLL_DIG_29, TM_FORCE_CLKDIST_ENABLE_RST_RPTR, 4, 1)
2000    FIELD(L0_TM_PLL_DIG_29, TM_CLKDIST_ENABLE_CLK_RPTR, 3, 1)

2001    FIELD(L0_TM_PLL_DIG_29, TM_FORCE_CLKDIST_ENABLE_CLK_RPTR, 2, 1)
2002    FIELD(L0_TM_PLL_DIG_29, TM_CLKDIST_BIAS_PTRIM_MSB, 1, 1)
2003    FIELD(L0_TM_PLL_DIG_29, TM_CLKDIST_BIAS_NTRIM_MSB, 0, 1)
2004REG32(L0_TM_PLL_DIG_30, 0x2078)
2005    FIELD(L0_TM_PLL_DIG_30, TM_PLL_DIG_30_31_8_RSVD, 24, 8)
2006    FIELD(L0_TM_PLL_DIG_30, TM_CLKDIST_ENABLE_BIAS, 7, 1)
2007    FIELD(L0_TM_PLL_DIG_30, TM_FORCE_CLKDIST_ENABLE_BIAS, 6, 1)
2008    FIELD(L0_TM_PLL_DIG_30, TM_CLKDIST_ENABLE_CMN_BIAS, 5, 1)
2009    FIELD(L0_TM_PLL_DIG_30, TM_FORCE_CLKDIST_ENABLE_CMN_BIAS, 4, 1)
2010    FIELD(L0_TM_PLL_DIG_30, TM_CLKDIST_SUP_OBSRV, 3, 1)
2011    FIELD(L0_TM_PLL_DIG_30, TM_CLKDIST_OBSRV_RSTMUX_SUP, 2, 1)
2012    FIELD(L0_TM_PLL_DIG_30, TM_CLKDIST_OBSRV_RPTR_RSTBUF_SUP, 1, 1)
2013    FIELD(L0_TM_PLL_DIG_30, TM_CLKDIST_OBSRV_MUS_SUP, 0, 1)
2014REG32(L0_TM_PLL_DIG_31, 0x207c)
2015    FIELD(L0_TM_PLL_DIG_31, TM_PLL_DIG_31_31_8_RSVD, 24, 8)
2016    FIELD(L0_TM_PLL_DIG_31, TM_CLKDIST_ENABLE_MASTER_CLK_DRIVE, 7, 1)
2017    FIELD(L0_TM_PLL_DIG_31, TM_FORCE_CLKDIST_ENABLE_MASTER_CLK_DRIVE, 6, 1)
2018    FIELD(L0_TM_PLL_DIG_31, TM_CLKDIST_ENABLE_LANE_RST_DRIVE, 5, 1)
2019    FIELD(L0_TM_PLL_DIG_31, TM_FORCE_CLKDIST_ENABLE_LANE_RST_DRIVE, 4, 1)
2020    FIELD(L0_TM_PLL_DIG_31, TM_CLKDIST_ENABLE_LANE_CLK_DRIVE, 3, 1)
2021    FIELD(L0_TM_PLL_DIG_31, TM_FORCE_CLKDIST_ENABLE_LANE_CLK_DRIVE, 2, 1)
2022    FIELD(L0_TM_PLL_DIG_31, TM_CLKDIST_BIAS_RATE_SEL, 1, 1)
2023    FIELD(L0_TM_PLL_DIG_31, TM_FORCE_CLKDIST_BIAS_RATE_SEL, 0, 1)
2024REG32(L0_TM_PLL_DIG_32, 0x2080)
2025    FIELD(L0_TM_PLL_DIG_32, TM_PLL_DIG_32_31_8_RSVD, 24, 8)
2026    FIELD(L0_TM_PLL_DIG_32, TM_CLKDIST_MUX_XVCR_CLK_EN, 7, 1)
2027    FIELD(L0_TM_PLL_DIG_32, TM_FORCE_CLKDIST_MUX_XVCR_CLK_EN, 6, 1)
2028    FIELD(L0_TM_PLL_DIG_32, TM_FORCE_LOAD_FBDIV, 5, 1)
2029    FIELD(L0_TM_PLL_DIG_32, TM_LOAD_FBDIV, 4, 1)
2030    FIELD(L0_TM_PLL_DIG_32, TM_FORCE_RST_FDBK_DIV, 3, 1)
2031    FIELD(L0_TM_PLL_DIG_32, TM_RST_FDBK_DIV, 2, 1)
2032    FIELD(L0_TM_PLL_DIG_32, TM_CLKDIST_ENABLE_MASTER_RST_DRIVE, 1, 1)
2033    FIELD(L0_TM_PLL_DIG_32, TM_FORCE_CLKDIST_ENABLE_MASTER_RST_DRIVE, 0, 1)
2034REG32(L0_TM_PLL_DIG_33, 0x2084)
2035    FIELD(L0_TM_PLL_DIG_33, TM_PLL_DIG_33_31_8_RSVD, 24, 8)
2036    FIELD(L0_TM_PLL_DIG_33, TM_FORCE_TX_CLK_RST_REL, 7, 1)
2037    FIELD(L0_TM_PLL_DIG_33, TM_TX_CLK_RST_REL, 6, 1)
2038    FIELD(L0_TM_PLL_DIG_33, TM_CLKDIST_MUX_XCVR_MASTER_RST_EN, 5, 1)
2039    FIELD(L0_TM_PLL_DIG_33, TM_FORCE_CLKDIST_MUX_XCVR_MASTER_RST_EN, 4, 1)
2040    FIELD(L0_TM_PLL_DIG_33, TM_CLKDIST_MUX_MASTER_CLK_SEL, 3, 1)
2041    FIELD(L0_TM_PLL_DIG_33, TM_FORCE_CLKDIST_MUX_MASTER_CLK_SEL, 2, 1)
2042    FIELD(L0_TM_PLL_DIG_33, TM_CLKDIST_MUX_LOCAL_CLK_SEL, 1, 1)
2043    FIELD(L0_TM_PLL_DIG_33, TM_FORCE_CLKDIST_MUX_LOCAL_CLK_SEL, 0, 1)
2044REG32(L0_TM_PLL_DIG_34, 0x2088)
2045    FIELD(L0_TM_PLL_DIG_34, TM_PLL_DIG_34_31_8_RSVD, 24, 8)
2046    FIELD(L0_TM_PLL_DIG_34, TM_PLL_RSVD, 7, 1)
2047    FIELD(L0_TM_PLL_DIG_34, TM_FBDIV_3_MSB, 2, 5)
2048    FIELD(L0_TM_PLL_DIG_34, TM_SEL_VCO_OUT, 1, 1)
2049    FIELD(L0_TM_PLL_DIG_34, TM_FORCE_SEL_VCO_OUT, 0, 1)
2050REG32(L0_TM_PLL_DIG_35, 0x208c)
2051    FIELD(L0_TM_PLL_DIG_35, TM_PLL_DIG_35_31_8_RSVD, 24, 8)
2052    FIELD(L0_TM_PLL_DIG_35, TM_CLKDIST_BIAS_SPARE, 6, 2)
2053    FIELD(L0_TM_PLL_DIG_35, TM_CLKDIST_DRVR_SPARE, 4, 2)
2054    FIELD(L0_TM_PLL_DIG_35, TM_CLKDIST_MUX_SPARE, 2, 2)
2055    FIELD(L0_TM_PLL_DIG_35, TM_CLKDIST_RPTR_SPARE, 0, 2)
2056REG32(L0_TM_PLL_DIG_36, 0x2090)
2057    FIELD(L0_TM_PLL_DIG_36, TM_PLL_DIG_36_31_8_RSVD, 24, 8)
2058    FIELD(L0_TM_PLL_DIG_36, CLKDIST_BIAS_SPARE, 6, 2)
2059    FIELD(L0_TM_PLL_DIG_36, CLKDIST_DRVR_SPARE, 4, 2)
2060    FIELD(L0_TM_PLL_DIG_36, CLKDIST_MUX_SPARE, 2, 2)
2061    FIELD(L0_TM_PLL_DIG_36, CLKDIST_RPTR_SPARE, 0, 2)
2062REG32(L0_TM_PLL_DIG_37, 0x2094)
2063    FIELD(L0_TM_PLL_DIG_37, TM_PLL_DIG_37_31_8_RSVD, 24, 8)
2064    FIELD(L0_TM_PLL_DIG_37, TM_COARSE_CODE_SAT_VALUE_LSB, 5, 3)
2065    FIELD(L0_TM_PLL_DIG_37, TM_ENABLE_COARSE_SATURATION, 4, 1)
2066    FIELD(L0_TM_PLL_DIG_37, W_SPARE_OUTPUTS, 2, 2)
2067    FIELD(L0_TM_PLL_DIG_37, TM_FORCE_EN_IP_DIV_BYPASS, 1, 1)
2068    FIELD(L0_TM_PLL_DIG_37, TM_EN_IP_DIV_BYPASS, 0, 1)
2069REG32(L0_TM_PLL_COARSE_CODE_SAT_MSB, 0x2098)
2070    FIELD(L0_TM_PLL_COARSE_CODE_SAT_MSB, TM_PLL_COARSE_CODE_SAT_MSB_31_8_RSVD, 24, 8)
2071    FIELD(L0_TM_PLL_COARSE_CODE_SAT_MSB, TM_COARSE_CODE_SAT_VALUE_MSB, 0, 8)
2072REG32(L0_MPHY_CFG_HIB8, 0x2300)
2073    FIELD(L0_MPHY_CFG_HIB8, MPHY_CFG_HIB8_31_8_RSVD, 24, 8)
2074    FIELD(L0_MPHY_CFG_HIB8, MPHY_HIBERN8_RSVD, 1, 7)
2075    FIELD(L0_MPHY_CFG_HIB8, MPHY_HIBERN8, 0, 1)
2076REG32(L0_MPHY_CFG_MODE, 0x2304)
2077    FIELD(L0_MPHY_CFG_MODE, MPHY_CFG_MODE_31_8_RSVD, 24, 8)
2078    FIELD(L0_MPHY_CFG_MODE, MPHY_HS_LS_MODE_RSVD, 2, 6)
2079    FIELD(L0_MPHY_CFG_MODE, MPHY_HS_LS_MODE, 0, 2)
2080REG32(L0_MPHY_CFG_HS_GEAR, 0x2308)
2081    FIELD(L0_MPHY_CFG_HS_GEAR, MPHY_CFG_HS_GEAR_31_8_RSVD, 24, 8)
2082    FIELD(L0_MPHY_CFG_HS_GEAR, MPHY_HS_GEAR_RSVD, 2, 6)
2083    FIELD(L0_MPHY_CFG_HS_GEAR, MPHY_HS_GEAR, 0, 2)
2084REG32(L0_MPHY_CFG_HS_RATE, 0x230c)
2085    FIELD(L0_MPHY_CFG_HS_RATE, MPHY_CFG_HS_RATE_31_8_RSVD, 24, 8)
2086    FIELD(L0_MPHY_CFG_HS_RATE, MPHY_RATE_RSVD, 1, 7)
2087    FIELD(L0_MPHY_CFG_HS_RATE, MPHY_RATE, 0, 1)
2088REG32(L0_MPHY_CFG_PWM, 0x2310)
2089    FIELD(L0_MPHY_CFG_PWM, MPHY_CFG_PWM_31_8_RSVD, 24, 8)
2090    FIELD(L0_MPHY_CFG_PWM, MPHY_PWM_GEAR_RSVD, 3, 5)
2091    FIELD(L0_MPHY_CFG_PWM, MPHY_PWM_GEAR, 0, 3)
2092REG32(L0_PLL_OPDIV_LS, 0x2314)
2093    FIELD(L0_PLL_OPDIV_LS, PLL_OPDIV_LS_31_8_RSVD, 24, 8)
2094    FIELD(L0_PLL_OPDIV_LS, TM_SEL_OPDIV_FOR_REFCLK, 7, 1)
2095    FIELD(L0_PLL_OPDIV_LS, ANA_OPDIV_LS, 0, 7)
2096REG32(L0_MPHY_CFG_UPDT, 0x2318)
2097    FIELD(L0_MPHY_CFG_UPDT, MPHY_CFG_UPDT_31_8_RSVD, 24, 8)
2098    FIELD(L0_MPHY_CFG_UPDT, MPHY_CFGUPDT_RSVD, 1, 7)
2099    FIELD(L0_MPHY_CFG_UPDT, MPHY_CFGUPDT, 0, 1)
2100REG32(L0_PLL_TM_DIV_CNTRLS, 0x231c)
2101    FIELD(L0_PLL_TM_DIV_CNTRLS, PLL_TM_DIV_CNTRLS_31_8_RSVD, 24, 8)
2102    FIELD(L0_PLL_TM_DIV_CNTRLS, TM_FORCE_PD_OPDIV_LS, 7, 1)
2103    FIELD(L0_PLL_TM_DIV_CNTRLS, TM_PD_OPDIV_LS, 6, 1)
2104    FIELD(L0_PLL_TM_DIV_CNTRLS, PLL_TM_DIV_CNTRLS_RSVD, 5, 1)
2105    FIELD(L0_PLL_TM_DIV_CNTRLS, TM_BYPASS_OPDIV_LS_MOD, 4, 1)
2106    FIELD(L0_PLL_TM_DIV_CNTRLS, TM_FORCE_PLL_PD_HS, 3, 1)
2107    FIELD(L0_PLL_TM_DIV_CNTRLS, TM_PLL_PD_HS, 2, 1)
2108    FIELD(L0_PLL_TM_DIV_CNTRLS, SEL_IP_MUX_CONTROL, 1, 1)
2109    FIELD(L0_PLL_TM_DIV_CNTRLS, TM_SWAP_OP_MUX_CONTROL, 0, 1)
2110REG32(L0_PLL_FBDIV_G1A_LSB, 0x2320)
2111    FIELD(L0_PLL_FBDIV_G1A_LSB, PLL_FBDIV_G1A_LSB_31_8_RSVD, 24, 8)
2112    FIELD(L0_PLL_FBDIV_G1A_LSB, FBDIV_G1A_LSB, 0, 8)
2113REG32(L0_PLL_FBDIV_G1B_LSB, 0x2324)
2114    FIELD(L0_PLL_FBDIV_G1B_LSB, PLL_FBDIV_G1B_LSB_31_8_RSVD, 24, 8)
2115    FIELD(L0_PLL_FBDIV_G1B_LSB, FBDIV_G1B_LSB, 0, 8)
2116REG32(L0_PLL_FBDIV_G2A_LSB, 0x2328)
2117    FIELD(L0_PLL_FBDIV_G2A_LSB, PLL_FBDIV_G2A_LSB_31_8_RSVD, 24, 8)
2118    FIELD(L0_PLL_FBDIV_G2A_LSB, FBDIV_G2A_LSB, 0, 8)
2119REG32(L0_PLL_FBDIV_G2B_LSB, 0x232c)
2120    FIELD(L0_PLL_FBDIV_G2B_LSB, PLL_FBDIV_G2B_LSB_31_8_RSVD, 24, 8)
2121    FIELD(L0_PLL_FBDIV_G2B_LSB, FBDIV_G2B_LSB, 0, 8)
2122REG32(L0_PLL_FBDIV_G3A_LSB, 0x2330)
2123    FIELD(L0_PLL_FBDIV_G3A_LSB, PLL_FBDIV_G3A_LSB_31_8_RSVD, 24, 8)
2124    FIELD(L0_PLL_FBDIV_G3A_LSB, FBDIV_G3A_LSB, 0, 8)
2125REG32(L0_PLL_FBDIV_G3B_LSB, 0x2334)
2126    FIELD(L0_PLL_FBDIV_G3B_LSB, PLL_FBDIV_G3B_LSB_31_8_RSVD, 24, 8)
2127    FIELD(L0_PLL_FBDIV_G3B_LSB, FBDIV_G3B_LSB, 0, 8)
2128REG32(L0_PLL_FBDIV_G1A_MSB, 0x2338)
2129    FIELD(L0_PLL_FBDIV_G1A_MSB, PLL_FBDIV_G1A_MSB_31_8_RSVD, 24, 8)
2130    FIELD(L0_PLL_FBDIV_G1A_MSB, FBDIV_G1A_MSB, 0, 8)
2131REG32(L0_PLL_FBDIV_G1B_MSB, 0x233c)
2132    FIELD(L0_PLL_FBDIV_G1B_MSB, PLL_FBDIV_G1B_MSB_31_8_RSVD, 24, 8)
2133    FIELD(L0_PLL_FBDIV_G1B_MSB, FBDIV_G1B_MSB, 0, 8)
2134REG32(L0_PLL_FBDIV_G2A_MSB, 0x2340)
2135    FIELD(L0_PLL_FBDIV_G2A_MSB, PLL_FBDIV_G2A_MSB_31_8_RSVD, 24, 8)
2136    FIELD(L0_PLL_FBDIV_G2A_MSB, FBDIV_G2A_MSB, 0, 8)
2137REG32(L0_PLL_FBDIV_G2B_MSB, 0x2344)
2138    FIELD(L0_PLL_FBDIV_G2B_MSB, PLL_FBDIV_G2B_MSB_31_8_RSVD, 24, 8)
2139    FIELD(L0_PLL_FBDIV_G2B_MSB, FBDIV_G2B_MSB, 0, 8)
2140REG32(L0_PLL_FBDIV_G3A_MSB, 0x2348)
2141    FIELD(L0_PLL_FBDIV_G3A_MSB, PLL_FBDIV_G3A_MSB_31_8_RSVD, 24, 8)
2142    FIELD(L0_PLL_FBDIV_G3A_MSB, FBDIV_G3A_MSB, 0, 8)
2143REG32(L0_PLL_FBDIV_G3B_MSB, 0x234c)
2144    FIELD(L0_PLL_FBDIV_G3B_MSB, PLL_FBDIV_G3B_MSB_31_8_RSVD, 24, 8)
2145    FIELD(L0_PLL_FBDIV_G3B_MSB, FBDIV_G3B_MSB, 0, 8)
2146REG32(L0_PLL_IPDIV, 0x2350)
2147    FIELD(L0_PLL_IPDIV, PLL_IPDIV_31_8_RSVD, 24, 8)
2148    FIELD(L0_PLL_IPDIV, PLL_IPDIV, 0, 8)
2149REG32(L0_PLL_FBDIV_FRAC_0_LSB, 0x2354)
2150    FIELD(L0_PLL_FBDIV_FRAC_0_LSB, PLL_FBDIV_FRAC_0_LSB_31_8_RSVD, 24, 8)
2151    FIELD(L0_PLL_FBDIV_FRAC_0_LSB, FBDIV_FRAC_0_LSB, 0, 8)
2152REG32(L0_PLL_FBDIV_FRAC_1, 0x2358)
2153    FIELD(L0_PLL_FBDIV_FRAC_1, PLL_FBDIV_FRAC_1_31_8_RSVD, 24, 8)
2154    FIELD(L0_PLL_FBDIV_FRAC_1, FBDIV_FRAC_1, 0, 8)
2155REG32(L0_PLL_FBDIV_FRAC_2, 0x235c)
2156    FIELD(L0_PLL_FBDIV_FRAC_2, PLL_FBDIV_FRAC_2_31_8_RSVD, 24, 8)
2157    FIELD(L0_PLL_FBDIV_FRAC_2, FBDIV_FRAC_2, 0, 8)
2158REG32(L0_PLL_FBDIV_FRAC_3_MSB, 0x2360)
2159    FIELD(L0_PLL_FBDIV_FRAC_3_MSB, PLL_FBDIV_FRAC_3_MSB_31_8_RSVD, 24, 8)
2160    FIELD(L0_PLL_FBDIV_FRAC_3_MSB, PLL_FBDIV_FRAC_3_MSV_RSVD, 7, 1)
2161    FIELD(L0_PLL_FBDIV_FRAC_3_MSB, TM_FORCE_EN_FRAC, 6, 1)
2162    FIELD(L0_PLL_FBDIV_FRAC_3_MSB, TM_EN_FRAC, 5, 1)
2163    FIELD(L0_PLL_FBDIV_FRAC_3_MSB, FBDIV_FRAC_3_MSB_RSVD, 3, 2)
2164    FIELD(L0_PLL_FBDIV_FRAC_3_MSB, FBDIV_FRAC_3_MSB, 0, 3)
2165REG32(L0_PLL_PWR_SEQ_WAIT_TIME, 0x2364)
2166    FIELD(L0_PLL_PWR_SEQ_WAIT_TIME, PLL_PWR_SEQ_WAIT_TIME_31_8_RSVD, 24, 8)
2167    FIELD(L0_PLL_PWR_SEQ_WAIT_TIME, TM_PLL_SETTLING, 6, 2)
2168    FIELD(L0_PLL_PWR_SEQ_WAIT_TIME, TM_PLL_BIAS_SETTLING, 4, 2)
2169    FIELD(L0_PLL_PWR_SEQ_WAIT_TIME, TM_LDO_SETTLING, 2, 2)
2170    FIELD(L0_PLL_PWR_SEQ_WAIT_TIME, TM_LDO_RELIABILITY, 0, 2)
2171REG32(L0_PLL_SS_STEPS_0_LSB, 0x2368)
2172    FIELD(L0_PLL_SS_STEPS_0_LSB, PLL_SS_STEPS_0_LSB_31_8_RSVD, 24, 8)
2173    FIELD(L0_PLL_SS_STEPS_0_LSB, SS_NUM_OF_STEPS_0_LSB, 0, 8)
2174REG32(L0_PLL_SS_STEPS_1_MSB, 0x236c)
2175    FIELD(L0_PLL_SS_STEPS_1_MSB, PLL_SS_STEPS_1_MSB_31_8_RSVD, 24, 8)
2176    FIELD(L0_PLL_SS_STEPS_1_MSB, SS_NUM_OF_STEPS_1_MSB_RSVD, 3, 5)
2177    FIELD(L0_PLL_SS_STEPS_1_MSB, SS_NUM_OF_STEPS_1_MSB, 0, 3)
2178REG32(L0_PLL_SS_STEP_SIZE_0_LSB, 0x2370)
2179    FIELD(L0_PLL_SS_STEP_SIZE_0_LSB, PLL_SS_STEP_SIZE_0_LSB_31_8_RSVD, 24, 8)
2180    FIELD(L0_PLL_SS_STEP_SIZE_0_LSB, SS_STEP_SIZE_0_LSB, 0, 8)
2181REG32(L0_PLL_SS_STEP_SIZE_1, 0x2374)
2182    FIELD(L0_PLL_SS_STEP_SIZE_1, PLL_SS_STEP_SIZE_1_31_8_RSVD, 24, 8)
2183    FIELD(L0_PLL_SS_STEP_SIZE_1, SS_STEP_SIZE_1, 0, 8)
2184REG32(L0_PLL_SS_STEP_SIZE_2, 0x2378)
2185    FIELD(L0_PLL_SS_STEP_SIZE_2, PLL_SS_STEP_SIZE_2_31_8_RSVD, 24, 8)
2186    FIELD(L0_PLL_SS_STEP_SIZE_2, SS_STEP_SIZE_2, 0, 8)
2187REG32(L0_PLL_SS_STEP_SIZE_3_MSB, 0x237c)
2188    FIELD(L0_PLL_SS_STEP_SIZE_3_MSB, PLL_SS_STEP_SIZE_3_MSB_31_8_RSVD, 24, 8)
2189    FIELD(L0_PLL_SS_STEP_SIZE_3_MSB, TM_FORCE_EN_SS, 7, 1)
2190    FIELD(L0_PLL_SS_STEP_SIZE_3_MSB, TM_EN_SS, 6, 1)
2191    FIELD(L0_PLL_SS_STEP_SIZE_3_MSB, FORCE_SS_NUM_OF_STEPS, 5, 1)
2192    FIELD(L0_PLL_SS_STEP_SIZE_3_MSB, FORCE_SS_STEP_SIZE, 4, 1)
2193    FIELD(L0_PLL_SS_STEP_SIZE_3_MSB, SS_SPREAD_TYPE, 2, 2)
2194    FIELD(L0_PLL_SS_STEP_SIZE_3_MSB, SS_STEP_SIZE_3_MSB, 0, 2)
2195REG32(L0_TM_MASK_CFG_UPDT, 0x2380)
2196    FIELD(L0_TM_MASK_CFG_UPDT, TM_MASK_CFG_UPDT_31_8_RSVD, 24, 8)
2197    FIELD(L0_TM_MASK_CFG_UPDT, TM_MASK_CFG_UPDT_RSVD, 7, 1)
2198    FIELD(L0_TM_MASK_CFG_UPDT, HIBERN8_MASK_CFG_UPDT, 6, 1)
2199    FIELD(L0_TM_MASK_CFG_UPDT, HS_MODE_MASK_CFG_UPDT, 5, 1)
2200    FIELD(L0_TM_MASK_CFG_UPDT, LS_MODE_MASK_CFG_UPDT, 4, 1)
2201    FIELD(L0_TM_MASK_CFG_UPDT, OPDIV_LS_MASK_CFG_UPDT, 3, 1)
2202    FIELD(L0_TM_MASK_CFG_UPDT, PWM_GEAR_MASK_CFG_UPDT, 2, 1)
2203    FIELD(L0_TM_MASK_CFG_UPDT, HS_GEAR_MASK_CFG_UPDT, 1, 1)
2204    FIELD(L0_TM_MASK_CFG_UPDT, HS_RATE_MASK_CFG_UPDT, 0, 1)
2205REG32(L0_PLL_TM_FORCE_DIV, 0x2384)
2206    FIELD(L0_PLL_TM_FORCE_DIV, PLL_TM_FORCE_DIV_31_8_RSVD, 24, 8)
2207    FIELD(L0_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_FRAC, 7, 1)
2208    FIELD(L0_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G3B, 6, 1)
2209    FIELD(L0_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G3A, 5, 1)
2210    FIELD(L0_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G2B, 4, 1)
2211    FIELD(L0_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G2A, 3, 1)
2212    FIELD(L0_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G1B, 2, 1)
2213    FIELD(L0_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G1A, 1, 1)
2214    FIELD(L0_PLL_TM_FORCE_DIV, TM_FORCE_IPDIV, 0, 1)
2215REG32(L0_PLL_TM_COARSE_CODE_1_LSB, 0x2388)
2216    FIELD(L0_PLL_TM_COARSE_CODE_1_LSB, PLL_TM_COARSE_CODE_1_LSB_31_8_RSVD, 24, 8)
2217    FIELD(L0_PLL_TM_COARSE_CODE_1_LSB, TM_COARSE_CODE_1_LSB, 0, 8)
2218REG32(L0_PLL_TM_COARSE_CODE_2_LSB, 0x238c)
2219    FIELD(L0_PLL_TM_COARSE_CODE_2_LSB, PLL_TM_COARSE_CODE_2_LSB_31_8_RSVD, 24, 8)
2220    FIELD(L0_PLL_TM_COARSE_CODE_2_LSB, TM_COARSE_CODE_2_LSB, 0, 8)
2221REG32(L0_PLL_TM_COARSE_CODE_3_LSB, 0x2390)
2222    FIELD(L0_PLL_TM_COARSE_CODE_3_LSB, PLL_TM_COARSE_CODE_3_LSB_31_8_RSVD, 24, 8)
2223    FIELD(L0_PLL_TM_COARSE_CODE_3_LSB, TM_COARSE_CODE_3_LSB, 0, 8)
2224REG32(L0_PLL_TM_COARSE_CODE_4_LSB, 0x2394)
2225    FIELD(L0_PLL_TM_COARSE_CODE_4_LSB, PLL_TM_COARSE_CODE_4_LSB_31_8_RSVD, 24, 8)
2226    FIELD(L0_PLL_TM_COARSE_CODE_4_LSB, TM_COARSE_CODE_4_LSB, 0, 8)
2227REG32(L0_PLL_TM_COARSE_CODE_5_LSB, 0x2398)
2228    FIELD(L0_PLL_TM_COARSE_CODE_5_LSB, PLL_TM_COARSE_CODE_5_LSB_31_8_RSVD, 24, 8)
2229    FIELD(L0_PLL_TM_COARSE_CODE_5_LSB, TM_COARSE_CODE_5_LSB, 0, 8)
2230REG32(L0_PLL_TM_COARSE_CODE_6_LSB, 0x239c)
2231    FIELD(L0_PLL_TM_COARSE_CODE_6_LSB, PLL_TM_COARSE_CODE_6_LSB_31_8_RSVD, 24, 8)
2232    FIELD(L0_PLL_TM_COARSE_CODE_6_LSB, TM_COARSE_CODE_6_LSB, 0, 8)
2233REG32(L0_PLL_TM_COARSE_CODE_1_2_MSB, 0x23a0)
2234    FIELD(L0_PLL_TM_COARSE_CODE_1_2_MSB, PLL_TM_COARSE_CODE_1_2_MSB_31_8_RSVD, 24, 8)
2235    FIELD(L0_PLL_TM_COARSE_CODE_1_2_MSB, TM_COARSE_CODE_G1_AB_MSB_RSVD, 6, 2)
2236    FIELD(L0_PLL_TM_COARSE_CODE_1_2_MSB, TM_COARSE_CODE_2_MSB, 3, 3)
2237    FIELD(L0_PLL_TM_COARSE_CODE_1_2_MSB, TM_COARSE_CODE_1_MSB, 0, 3)
2238REG32(L0_PLL_TM_COARSE_CODE_3_4_MSB, 0x23a4)
2239    FIELD(L0_PLL_TM_COARSE_CODE_3_4_MSB, PLL_TM_COARSE_CODE_3_4_MSB_31_8_RSVD, 24, 8)
2240    FIELD(L0_PLL_TM_COARSE_CODE_3_4_MSB, TM_COARSE_CODE_G2_AB_MSB_RSVD, 6, 2)
2241    FIELD(L0_PLL_TM_COARSE_CODE_3_4_MSB, TM_COARSE_CODE_4_MSB, 3, 3)
2242    FIELD(L0_PLL_TM_COARSE_CODE_3_4_MSB, TM_COARSE_CODE_3_MSB, 0, 3)
2243REG32(L0_PLL_TM_COARSE_CODE_5_6_MSB, 0x23a8)
2244    FIELD(L0_PLL_TM_COARSE_CODE_5_6_MSB, PLL_TM_COARSE_CODE_5_6_MSB_31_8_RSVD, 24, 8)
2245    FIELD(L0_PLL_TM_COARSE_CODE_5_6_MSB, TM_COARSE_CODE_G3_AB_MSB_RSVD, 6, 2)
2246    FIELD(L0_PLL_TM_COARSE_CODE_5_6_MSB, TM_COARSE_CODE_6_MSB, 3, 3)
2247    FIELD(L0_PLL_TM_COARSE_CODE_5_6_MSB, TM_COARSE_CODE_5_MSB, 0, 3)
2248REG32(L0_PLL_TM_SHARED_0, 0x23ac)
2249    FIELD(L0_PLL_TM_SHARED_0, PLL_TM_SHARED_0_31_8_RSVD, 24, 8)
2250    FIELD(L0_PLL_TM_SHARED_0, TM_FORCE_EXTSIGNAL_FOR_HIBERN8, 7, 1)
2251    FIELD(L0_PLL_TM_SHARED_0, TM_FORCE_REGBIT_FOR_HIBERN8, 6, 1)
2252    FIELD(L0_PLL_TM_SHARED_0, TM_FORCE_PLL_STANDBY, 5, 1)
2253    FIELD(L0_PLL_TM_SHARED_0, TM_PLL_STANDBY, 4, 1)
2254    FIELD(L0_PLL_TM_SHARED_0, TM_SLOWN_FAST_BRING_UP_ALWAYS, 3, 1)
2255    FIELD(L0_PLL_TM_SHARED_0, EN_TM_FOR_BRING_UP_SCHEME, 2, 1)
2256    FIELD(L0_PLL_TM_SHARED_0, SELECT_HS_FB_DIVIDER, 1, 1)
2257    FIELD(L0_PLL_TM_SHARED_0, TM_BYPASS_COARSE_SEARCH, 0, 1)
2258REG32(L0_PLL_TM_FRAC_OFFSET_0, 0x23b0)
2259    FIELD(L0_PLL_TM_FRAC_OFFSET_0, PLL_TM_FRAC_OFFSET_0_31_8_RSVD, 24, 8)
2260    FIELD(L0_PLL_TM_FRAC_OFFSET_0, TM_FRAC_OFFSET_LSB_0, 0, 8)
2261REG32(L0_PLL_TM_FRAC_OFFSET_1, 0x23b4)
2262    FIELD(L0_PLL_TM_FRAC_OFFSET_1, PLL_TM_FRAC_OFFSET_1_31_8_RSVD, 24, 8)
2263    FIELD(L0_PLL_TM_FRAC_OFFSET_1, TM_FRAC_OFFSET_1, 0, 8)
2264REG32(L0_PLL_TM_FRAC_OFFSET_2, 0x23b8)
2265    FIELD(L0_PLL_TM_FRAC_OFFSET_2, PLL_TM_FRAC_OFFSET_2_31_8_RSVD, 24, 8)
2266    FIELD(L0_PLL_TM_FRAC_OFFSET_2, TM_PLL_RSVD, 2, 6)
2267    FIELD(L0_PLL_TM_FRAC_OFFSET_2, TM_FORCE_FBDIV_FRAC_OFFSET, 1, 1)
2268    FIELD(L0_PLL_TM_FRAC_OFFSET_2, TM_FRAC_OFFSET_MSB_2, 0, 1)
2269REG32(L0_PLL_STATUS_READ_0, 0x23e0)
2270    FIELD(L0_PLL_STATUS_READ_0, PLL_STATUS_READ_0_31_8_RSVD, 24, 8)
2271    FIELD(L0_PLL_STATUS_READ_0, PLL_COARSE_CODE_LSB_STATUS_READ, 0, 8)
2272REG32(L0_PLL_STATUS_READ_1, 0x23e4)
2273    FIELD(L0_PLL_STATUS_READ_1, PLL_STATUS_READ_1_31_8_RSVD, 24, 8)
2274    FIELD(L0_PLL_STATUS_READ_1, PLL_STATUS_READ_1_RSVD, 6, 2)
2275    FIELD(L0_PLL_STATUS_READ_1, PLL_START_LOOP_STATUS_READ, 5, 1)
2276    FIELD(L0_PLL_STATUS_READ_1, PLL_LOCK_STATUS_READ, 4, 1)
2277    FIELD(L0_PLL_STATUS_READ_1, PLL_COARSE_DONE_STATUS_READ, 3, 1)
2278    FIELD(L0_PLL_STATUS_READ_1, PLL_COARSE_CODE_MSB_STATUS_READ, 0, 3)
2279REG32(L0_TM_BG_PROG0, 0x2800)
2280    FIELD(L0_TM_BG_PROG0, TM_BG_PROG0_31_8_RSVD, 24, 8)
2281    FIELD(L0_TM_BG_PROG0, TM_BG_PROG0_7_RSVD, 7, 1)
2282    FIELD(L0_TM_BG_PROG0, IRCONST_PAD, 6, 1)
2283    FIELD(L0_TM_BG_PROG0, BG_PDN_OK_CTRL, 5, 1)
2284    FIELD(L0_TM_BG_PROG0, BG_PDN_OK_BYP, 4, 1)
2285    FIELD(L0_TM_BG_PROG0, BG_PTAT_PDN_OK_CTRL, 3, 1)
2286    FIELD(L0_TM_BG_PROG0, BG_PTAT_PDN_OK_BYP, 2, 1)
2287    FIELD(L0_TM_BG_PROG0, BG_PDN_CTRL, 1, 1)
2288    FIELD(L0_TM_BG_PROG0, BG_PDN_BYP, 0, 1)
2289REG32(L0_TM_BG_PROG1, 0x2804)
2290    FIELD(L0_TM_BG_PROG1, TM_BG_PROG1_31_8_RSVD, 24, 8)
2291    FIELD(L0_TM_BG_PROG1, TM_STARTUP_SWITCHOFF, 7, 1)
2292    FIELD(L0_TM_BG_PROG1, TM_FORCE_PULLDOWN, 6, 1)
2293    FIELD(L0_TM_BG_PROG1, TM_DEC_CRUDE_SUPPLY, 5, 1)
2294    FIELD(L0_TM_BG_PROG1, TM_INC_CRUDE_SUPPLY, 4, 1)
2295    FIELD(L0_TM_BG_PROG1, TM_EN_1P2V_SUPPORT, 3, 1)
2296    FIELD(L0_TM_BG_PROG1, TM_EN_VTH_COMP_OUT, 2, 1)
2297    FIELD(L0_TM_BG_PROG1, TM_EN_SEL_CRUDE_SUPPLY, 1, 1)
2298    FIELD(L0_TM_BG_PROG1, TM_EN_OUT_BYP, 0, 1)
2299REG32(L0_TM_ANA_BG_TESTBIT0, 0x2808)
2300    FIELD(L0_TM_ANA_BG_TESTBIT0, TM_ANA_BG_TESTBIT0_31_8_RSVD, 24, 8)
2301    FIELD(L0_TM_ANA_BG_TESTBIT0, BG_ANA_CTRL0, 0, 8)
2302REG32(L0_TM_ANA_BG_TESTBIT1, 0x280c)
2303    FIELD(L0_TM_ANA_BG_TESTBIT1, TM_ANA_BG_TESTBIT1_31_8_RSVD, 24, 8)
2304    FIELD(L0_TM_ANA_BG_TESTBIT1, BG_ANA_CTRL1, 0, 8)
2305REG32(L0_TM_ANA_BG_TESTBIT2, 0x2810)
2306    FIELD(L0_TM_ANA_BG_TESTBIT2, TM_ANA_BG_TESTBIT2_31_8_RSVD, 24, 8)
2307    FIELD(L0_TM_ANA_BG_TESTBIT2, BG_ANA_CTRL2, 0, 8)
2308REG32(L0_TM_ANA_BG_TESTBIT3, 0x2814)
2309    FIELD(L0_TM_ANA_BG_TESTBIT3, TM_ANA_BG_TESTBIT3_31_8_RSVD, 24, 8)
2310    FIELD(L0_TM_ANA_BG_TESTBIT3, BG_ANA_CTRL3, 0, 8)
2311REG32(L0_TM_ANA_BG_TESTBIT4, 0x2818)
2312    FIELD(L0_TM_ANA_BG_TESTBIT4, TM_ANA_BG_TESTBIT4_31_8_RSVD, 24, 8)
2313    FIELD(L0_TM_ANA_BG_TESTBIT4, BG_ANA_CTRL4, 0, 8)
2314REG32(L0_TM_ANA_BG_TESTBIT5, 0x281c)
2315    FIELD(L0_TM_ANA_BG_TESTBIT5, TM_ANA_BG_TESTBIT5_31_8_RSVD, 24, 8)
2316    FIELD(L0_TM_ANA_BG_TESTBIT5, BG_ANA_CTRL5, 0, 8)
2317REG32(L0_TM_ANA_BG_TESTBIT6, 0x2820)
2318    FIELD(L0_TM_ANA_BG_TESTBIT6, TM_ANA_BG_TESTBIT6_31_8_RSVD, 24, 8)
2319    FIELD(L0_TM_ANA_BG_TESTBIT6, BG_ANA_CTRL6, 0, 8)
2320REG32(L0_TM_ANA_BG_TESTBIT7, 0x2824)
2321    FIELD(L0_TM_ANA_BG_TESTBIT7, TM_ANA_BG_TESTBIT7_31_8_RSVD, 24, 8)
2322    FIELD(L0_TM_ANA_BG_TESTBIT7, BG_ANA_CTRL7, 0, 8)
2323REG32(L0_TM_ANA_BG_TESTBIT8, 0x2828)
2324    FIELD(L0_TM_ANA_BG_TESTBIT8, TM_ANA_BG_TESTBIT8_31_8_RSVD, 24, 8)
2325    FIELD(L0_TM_ANA_BG_TESTBIT8, BG_ANA_CTRL8, 0, 8)
2326REG32(L0_TM_ANA_BG_TESTBIT9, 0x282c)
2327    FIELD(L0_TM_ANA_BG_TESTBIT9, TM_ANA_BG_TESTBIT9_31_8_RSVD, 24, 8)
2328    FIELD(L0_TM_ANA_BG_TESTBIT9, BG_ANA_CTRL9, 0, 8)
2329REG32(L0_TM_ANA_BG_TESTBIT10, 0x2830)
2330    FIELD(L0_TM_ANA_BG_TESTBIT10, TM_ANA_BG_TESTBIT10_31_8_RSVD, 24, 8)
2331    FIELD(L0_TM_ANA_BG_TESTBIT10, BG_ANA_CTRL10, 0, 8)
2332REG32(L0_TM_ANA_BG_TESTBIT11, 0x2834)
2333    FIELD(L0_TM_ANA_BG_TESTBIT11, TM_ANA_BG_TESTBIT11_31_8_RSVD, 24, 8)
2334    FIELD(L0_TM_ANA_BG_TESTBIT11, BG_ANA_CTRL11, 0, 8)
2335REG32(L0_TM_ANA_BG_TESTBIT12, 0x2838)
2336    FIELD(L0_TM_ANA_BG_TESTBIT12, TM_ANA_BG_TESTBIT12_31_8_RSVD, 24, 8)
2337    FIELD(L0_TM_ANA_BG_TESTBIT12, BG_ANA_CTRL12, 0, 8)
2338REG32(L0_TM_ANA_BG_TESTBIT13, 0x283c)
2339    FIELD(L0_TM_ANA_BG_TESTBIT13, TM_ANA_BG_TESTBIT13_31_8_RSVD, 24, 8)
2340    FIELD(L0_TM_ANA_BG_TESTBIT13, BG_ANA_CTRL13, 0, 8)
2341REG32(L0_TM_ANA_BG_TESTBIT14, 0x2840)
2342    FIELD(L0_TM_ANA_BG_TESTBIT14, TM_ANA_BG_TESTBIT14_31_8_RSVD, 24, 8)
2343    FIELD(L0_TM_ANA_BG_TESTBIT14, BG_ANA_CTRL14, 0, 8)
2344REG32(L0_TM_ANA_BG_TESTBIT15, 0x2844)
2345    FIELD(L0_TM_ANA_BG_TESTBIT15, TM_ANA_BG_TESTBIT15_31_8_RSVD, 24, 8)
2346    FIELD(L0_TM_ANA_BG_TESTBIT15, BG_ANA_CTRL15, 0, 8)
2347REG32(L0_TM_ANA_BG_TESTBIT16, 0x2848)
2348    FIELD(L0_TM_ANA_BG_TESTBIT16, TM_ANA_BG_TESTBIT16_31_8_RSVD, 24, 8)
2349    FIELD(L0_TM_ANA_BG_TESTBIT16, BG_ANA_CTRL16, 0, 8)
2350REG32(L0_TM_ANA_BG_TESTBIT17, 0x284c)
2351    FIELD(L0_TM_ANA_BG_TESTBIT17, TM_ANA_BG_TESTBIT17_31_8_RSVD, 24, 8)
2352    FIELD(L0_TM_ANA_BG_TESTBIT17, BG_ANA_CTRL17, 0, 8)
2353REG32(L0_TM_ANA_BG_TESTBIT18, 0x2850)
2354    FIELD(L0_TM_ANA_BG_TESTBIT18, TM_ANA_BG_TESTBIT18_31_8_RSVD, 24, 8)
2355    FIELD(L0_TM_ANA_BG_TESTBIT18, BG_ANA_CTRL18, 0, 8)
2356REG32(L0_TM_ANA_BG_TESTBIT19, 0x2854)
2357    FIELD(L0_TM_ANA_BG_TESTBIT19, TM_ANA_BG_TESTBIT19_31_8_RSVD, 24, 8)
2358    FIELD(L0_TM_ANA_BG_TESTBIT19, BG_ANA_CTRL19, 0, 8)
2359REG32(L0_TM_ANA_BG_TESTBIT20, 0x2858)
2360    FIELD(L0_TM_ANA_BG_TESTBIT20, TM_ANA_BG_TESTBIT20_31_8_RSVD, 24, 8)
2361    FIELD(L0_TM_ANA_BG_TESTBIT20, BG_ANA_CTRL20_7_RSVD, 2, 6)
2362    FIELD(L0_TM_ANA_BG_TESTBIT20, BG_ANA_CTRL20, 0, 2)
2363REG32(L0_TM_BG_PROG2, 0x285c)
2364    FIELD(L0_TM_BG_PROG2, TM_BG_PROG2_31_8_RSVD, 24, 8)
2365    FIELD(L0_TM_BG_PROG2, TM_BG_PROG2_6_7_RSVD, 6, 2)
2366    FIELD(L0_TM_BG_PROG2, FORCE_O_BG_UP, 5, 1)
2367    FIELD(L0_TM_BG_PROG2, BYPASS_O_BG_UP, 4, 1)
2368    FIELD(L0_TM_BG_PROG2, FORCE_BG_EN_LL, 3, 1)
2369    FIELD(L0_TM_BG_PROG2, BYPASS_BG_EN_LL, 2, 1)
2370    FIELD(L0_TM_BG_PROG2, CNTRL_BG_EN, 1, 1)
2371    FIELD(L0_TM_BG_PROG2, BYPASS_BG_EN, 0, 1)
2372REG32(L0_L0_REF_CLK_SEL, 0x2860)
2373    FIELD(L0_L0_REF_CLK_SEL, L0_REF_CLK_SEL_31_8_RSVD, 24, 8)
2374    FIELD(L0_L0_REF_CLK_SEL, L0_REF_CLK_LCL_SEL, 7, 1)
2375    FIELD(L0_L0_REF_CLK_SEL, L0_REFCLK_SEL_6_RSVD, 6, 1)
2376    FIELD(L0_L0_REF_CLK_SEL, L0_REFCLK_SEL_5_RSVD, 5, 1)
2377    FIELD(L0_L0_REF_CLK_SEL, L0_REF_CLK_SEL_4, 4, 1)
2378    FIELD(L0_L0_REF_CLK_SEL, L0_REF_CLK_SEL_3, 3, 1)
2379    FIELD(L0_L0_REF_CLK_SEL, L0_REF_CLK_SEL_2, 2, 1)
2380    FIELD(L0_L0_REF_CLK_SEL, L0_REF_CLK_SEL_1, 1, 1)
2381    FIELD(L0_L0_REF_CLK_SEL, L0_REF_CLK_SEL_0, 0, 1)
2382REG32(L0_L1_REF_CLK_SEL, 0x2864)
2383    FIELD(L0_L1_REF_CLK_SEL, L1_REF_CLK_SEL_31_8_RSVD, 24, 8)
2384    FIELD(L0_L1_REF_CLK_SEL, L1_REF_CLK_LCL_SEL, 7, 1)
2385    FIELD(L0_L1_REF_CLK_SEL, L1_REFCLK_SEL_6_RSVD, 6, 1)
2386    FIELD(L0_L1_REF_CLK_SEL, L1_REFCLK_SEL_5_RSVD, 5, 1)
2387    FIELD(L0_L1_REF_CLK_SEL, L1_REF_CLK_SEL_4, 4, 1)
2388    FIELD(L0_L1_REF_CLK_SEL, L1_REF_CLK_SEL_3, 3, 1)
2389    FIELD(L0_L1_REF_CLK_SEL, L1_REF_CLK_SEL_2, 2, 1)
2390    FIELD(L0_L1_REF_CLK_SEL, L1_REF_CLK_SEL_1, 1, 1)
2391    FIELD(L0_L1_REF_CLK_SEL, L1_REF_CLK_SEL_0, 0, 1)
2392REG32(L0_L2_REF_CLK_SEL, 0x2868)
2393    FIELD(L0_L2_REF_CLK_SEL, L2_REF_CLK_SEL_31_8_RSVD, 24, 8)
2394    FIELD(L0_L2_REF_CLK_SEL, L2_REF_CLK_LCL_SEL, 7, 1)
2395    FIELD(L0_L2_REF_CLK_SEL, L2_REFCLK_SEL_6_RSVD, 6, 1)
2396    FIELD(L0_L2_REF_CLK_SEL, L2_REFCLK_SEL_5_RSVD, 5, 1)
2397    FIELD(L0_L2_REF_CLK_SEL, L2_REF_CLK_SEL_4, 4, 1)
2398    FIELD(L0_L2_REF_CLK_SEL, L2_REF_CLK_SEL_3, 3, 1)
2399    FIELD(L0_L2_REF_CLK_SEL, L2_REF_CLK_SEL_2, 2, 1)
2400    FIELD(L0_L2_REF_CLK_SEL, L2_REF_CLK_SEL_1, 1, 1)
2401    FIELD(L0_L2_REF_CLK_SEL, L2_REF_CLK_SEL_0, 0, 1)
2402REG32(L0_L3_REF_CLK_SEL, 0x286c)
2403    FIELD(L0_L3_REF_CLK_SEL, L3_REF_CLK_SEL_31_8_RSVD, 24, 8)
2404    FIELD(L0_L3_REF_CLK_SEL, L3_REF_CLK_LCL_SEL, 7, 1)
2405    FIELD(L0_L3_REF_CLK_SEL, L3_REFCLK_SEL_6_RSVD, 6, 1)
2406    FIELD(L0_L3_REF_CLK_SEL, L3_REFCLK_SEL_5_RSVD, 5, 1)
2407    FIELD(L0_L3_REF_CLK_SEL, L3_REF_CLK_SEL_4, 4, 1)
2408    FIELD(L0_L3_REF_CLK_SEL, L3_REF_CLK_SEL_3, 3, 1)
2409    FIELD(L0_L3_REF_CLK_SEL, L3_REF_CLK_SEL_2, 2, 1)
2410    FIELD(L0_L3_REF_CLK_SEL, L3_REF_CLK_SEL_1, 1, 1)
2411    FIELD(L0_L3_REF_CLK_SEL, L3_REF_CLK_SEL_0, 0, 1)
2412REG32(L0_L0_REF_CLK_PULLDN, 0x2870)
2413    FIELD(L0_L0_REF_CLK_PULLDN, L0_REF_CLK_PULLDN_31_8_RSVD, 24, 8)
2414    FIELD(L0_L0_REF_CLK_PULLDN, L0_REF_CLK_PULLDN_7_4_RSVD, 4, 4)
2415    FIELD(L0_L0_REF_CLK_PULLDN, L0_REF_CLK_TM_PULLDN2, 3, 1)
2416    FIELD(L0_L0_REF_CLK_PULLDN, L0_REF_CLK_TM_EN_PULLDN2, 2, 1)
2417    FIELD(L0_L0_REF_CLK_PULLDN, L0_REF_CLK_TM_PULLDN1, 1, 1)
2418    FIELD(L0_L0_REF_CLK_PULLDN, L0_REF_CLK_TM_EN_PULLDN1, 0, 1)
2419REG32(L0_L1_REF_CLK_PULLDN, 0x2874)
2420    FIELD(L0_L1_REF_CLK_PULLDN, L1_REF_CLK_PULLDN_31_8_RSVD, 24, 8)
2421    FIELD(L0_L1_REF_CLK_PULLDN, L1_REF_CLK_PULLDN_7_4_RSVD, 4, 4)
2422    FIELD(L0_L1_REF_CLK_PULLDN, L1_REF_CLK_TM_PULLDN2, 3, 1)
2423    FIELD(L0_L1_REF_CLK_PULLDN, L1_REF_CLK_TM_EN_PULLDN2, 2, 1)
2424    FIELD(L0_L1_REF_CLK_PULLDN, L1_REF_CLK_TM_PULLDN1, 1, 1)
2425    FIELD(L0_L1_REF_CLK_PULLDN, L1_REF_CLK_TM_EN_PULLDN1, 0, 1)
2426REG32(L0_L2_REF_CLK_PULLDN, 0x2878)
2427    FIELD(L0_L2_REF_CLK_PULLDN, L2_REF_CLK_PULLDN_31_8_RSVD, 24, 8)
2428    FIELD(L0_L2_REF_CLK_PULLDN, L2_REF_CLK_PULLDN_7_4_RSVD, 4, 4)
2429    FIELD(L0_L2_REF_CLK_PULLDN, L2_REF_CLK_TM_PULLDN2, 3, 1)
2430    FIELD(L0_L2_REF_CLK_PULLDN, L2_REF_CLK_TM_EN_PULLDN2, 2, 1)
2431    FIELD(L0_L2_REF_CLK_PULLDN, L2_REF_CLK_TM_PULLDN1, 1, 1)
2432    FIELD(L0_L2_REF_CLK_PULLDN, L2_REF_CLK_TM_EN_PULLDN1, 0, 1)
2433REG32(L0_L3_REF_CLK_PULLDN, 0x287c)
2434    FIELD(L0_L3_REF_CLK_PULLDN, L3_REF_CLK_PULLDN_31_8_RSVD, 24, 8)
2435    FIELD(L0_L3_REF_CLK_PULLDN, L3_REF_CLK_PULLDN_7_4_RSVD, 4, 4)
2436    FIELD(L0_L3_REF_CLK_PULLDN, L3_REF_CLK_TM_PULLDN2, 3, 1)
2437    FIELD(L0_L3_REF_CLK_PULLDN, L3_REF_CLK_TM_EN_PULLDN2, 2, 1)
2438    FIELD(L0_L3_REF_CLK_PULLDN, L3_REF_CLK_TM_PULLDN1, 1, 1)
2439    FIELD(L0_L3_REF_CLK_PULLDN, L3_REF_CLK_TM_EN_PULLDN1, 0, 1)
2440REG32(L0_TM_PG_CTRL0, 0x2880)
2441    FIELD(L0_TM_PG_CTRL0, TM_PG_CTRL0_31_8_RSVD, 24, 8)
2442    FIELD(L0_TM_PG_CTRL0, TM_PG_SPARED, 0, 8)
2443REG32(L0_TM_PG_CTRL1, 0x2884)
2444    FIELD(L0_TM_PG_CTRL1, TM_PG_CTRL1_31_8_RSVD, 24, 8)
2445    FIELD(L0_TM_PG_CTRL1, TM_PG_CTRL2_6_7_RSVD, 6, 2)
2446    FIELD(L0_TM_PG_CTRL1, DVDDCR_OR_VAL, 5, 1)
2447    FIELD(L0_TM_PG_CTRL1, AVDDIO_OR_VAL, 4, 1)
2448    FIELD(L0_TM_PG_CTRL1, AVDDCR_OR_VAL, 3, 1)
2449    FIELD(L0_TM_PG_CTRL1, DVDDCR_OR, 2, 1)
2450    FIELD(L0_TM_PG_CTRL1, AVDDIO_OR, 1, 1)
2451    FIELD(L0_TM_PG_CTRL1, AVDDCR_OR, 0, 1)
2452REG32(L0_TM_SLICER0_CTRL, 0x2888)
2453    FIELD(L0_TM_SLICER0_CTRL, TM_SLICER0_CTRL_31_8_RSVD, 24, 8)
2454    FIELD(L0_TM_SLICER0_CTRL, SLICER0_TM_CONTROL_7_RSVD, 7, 1)
2455    FIELD(L0_TM_SLICER0_CTRL, SLICER0_TM_SELPLLOUT_TESTOUT, 6, 1)
2456    FIELD(L0_TM_SLICER0_CTRL, SLICER0_TM_SELDIGOUT_TESTOUT, 5, 1)
2457    FIELD(L0_TM_SLICER0_CTRL, SLICER0_TM_OBSERVE_SUP, 4, 1)
2458    FIELD(L0_TM_SLICER0_CTRL, SLICER0_TM_OBSERVE_DIGSUP, 3, 1)
2459    FIELD(L0_TM_SLICER0_CTRL, SLICER0_TM_OBSERVE_DIFSUP, 2, 1)
2460    FIELD(L0_TM_SLICER0_CTRL, SLICER0_TM_ENABLE_SINGLE_ENDED, 1, 1)
2461    FIELD(L0_TM_SLICER0_CTRL, REFCLKN01_TM_OBSERVE_SUP, 0, 1)
2462REG32(L0_TM_SLICER01_BIAS_PROG0, 0x288c)
2463    FIELD(L0_TM_SLICER01_BIAS_PROG0, TM_SLICER01_BIAS_PROG0_31_8_RSVD, 24, 8)
2464    FIELD(L0_TM_SLICER01_BIAS_PROG0, SLICER01_TM_BIAS_PROG0, 0, 8)
2465REG32(L0_TM_SLICER01_BIAS_PROG1, 0x2890)
2466    FIELD(L0_TM_SLICER01_BIAS_PROG1, TM_SLICER01_BIAS_PROG1_31_8_RSVD, 24, 8)
2467    FIELD(L0_TM_SLICER01_BIAS_PROG1, SLICER01_TM_BIAS_PROG1_4_7_RSVD, 4, 4)
2468    FIELD(L0_TM_SLICER01_BIAS_PROG1, SLICER01_TM_BIAS_PROG1, 0, 4)
2469REG32(L0_TM_SLICER1_CTRL, 0x2894)
2470    FIELD(L0_TM_SLICER1_CTRL, TM_SLICER1_CTRL_31_8_RSVD, 24, 8)
2471    FIELD(L0_TM_SLICER1_CTRL, SLICER1_TM_CONTROL1_7_RSVD, 7, 1)
2472    FIELD(L0_TM_SLICER1_CTRL, SLICER1_TM_SELPLLOUT_TESTOUT, 6, 1)
2473    FIELD(L0_TM_SLICER1_CTRL, SLICER1_TM_SELDIGOUT_TESTOUT, 5, 1)
2474    FIELD(L0_TM_SLICER1_CTRL, SLICER1_TM_OBSERVE_SUP, 4, 1)
2475    FIELD(L0_TM_SLICER1_CTRL, SLICER1_TM_OBSERVE_DIGSUP, 3, 1)
2476    FIELD(L0_TM_SLICER1_CTRL, SLICER1_TM_OBSERVE_DIFSUP, 2, 1)
2477    FIELD(L0_TM_SLICER1_CTRL, SLICER1_TM_ENABLE_SINGLE_ENDED, 1, 1)
2478    FIELD(L0_TM_SLICER1_CTRL, SLICER1_TM_CONTROL1_0_RSVD, 0, 1)
2479REG32(L0_TM_BG_IPTAT_PROG, 0x2898)
2480    FIELD(L0_TM_BG_IPTAT_PROG, TM_BG_IPTAT_PROG_31_8_RSVD, 24, 8)
2481    FIELD(L0_TM_BG_IPTAT_PROG, BG_TM_BG_IPTAT_PROG, 0, 8)
2482REG32(L0_TM_PG_MUX_SEL, 0x289c)
2483    FIELD(L0_TM_PG_MUX_SEL, TM_PG_MUX_SEL_31_8_RSVD, 24, 8)
2484    FIELD(L0_TM_PG_MUX_SEL, TM_BG_MUX_SEL_5_7_RSVD, 5, 3)
2485    FIELD(L0_TM_PG_MUX_SEL, PG_MUX_SEL_DVDDCR, 4, 1)
2486    FIELD(L0_TM_PG_MUX_SEL, PG_MUX_SEL_AVDDIO, 2, 2)
2487    FIELD(L0_TM_PG_MUX_SEL, PG_MUX_SEL_AVDDCR, 0, 2)
2488REG32(L0_BG_SLICER_SPARE, 0x28a0)
2489    FIELD(L0_BG_SLICER_SPARE, BG_SLICER_SPARE_31_8_RSVD, 24, 8)
2490    FIELD(L0_BG_SLICER_SPARE, BG_SLICER_SPARE_RESERVED, 6, 2)
2491    FIELD(L0_BG_SLICER_SPARE, SLICER1_DA_SPARE, 4, 2)
2492    FIELD(L0_BG_SLICER_SPARE, SLICER0_DA_SPARE, 2, 2)
2493    FIELD(L0_BG_SLICER_SPARE, BG_DA_SPARE, 0, 2)
2494REG32(L0_TM_1US_COUNT, 0x2b00)
2495    FIELD(L0_TM_1US_COUNT, TM_1US_COUNT_31_8_RSVD, 24, 8)
2496    FIELD(L0_TM_1US_COUNT, ONE_US_COUNT, 0, 8)
2497REG32(L0_TM_BG_SETTLING_TIME, 0x2b04)
2498    FIELD(L0_TM_BG_SETTLING_TIME, TM_BG_SETTLING_TIME_31_8_RSVD, 24, 8)
2499    FIELD(L0_TM_BG_SETTLING_TIME, TM_BG_SETTLING_TIME_3_7_RSVD, 3, 5)
2500    FIELD(L0_TM_BG_SETTLING_TIME, BG_SETTLING_TIME, 1, 2)
2501    FIELD(L0_TM_BG_SETTLING_TIME, EN_1US_COUNTER, 0, 1)
2502REG32(L0_SLICER0_ENABLE, 0x2b08)
2503    FIELD(L0_SLICER0_ENABLE, SLICER0_ENABLE_31_8_RSVD, 24, 8)
2504    FIELD(L0_SLICER0_ENABLE, REFCLK01_SUP_EN, 7, 1)
2505    FIELD(L0_SLICER0_ENABLE, SLICER0_ENABLE_TERM, 6, 1)
2506    FIELD(L0_SLICER0_ENABLE, SLICER0_ENABLE_TC_CNTRL, 4, 2)
2507    FIELD(L0_SLICER0_ENABLE, SLICER0_ENABLE_DIVIDER_4TEST, 3, 1)
2508    FIELD(L0_SLICER0_ENABLE, SLICER0_ENABLE_CLK_OUT, 2, 1)
2509    FIELD(L0_SLICER0_ENABLE, SLICER0_ENABLE_BGBIAS, 1, 1)
2510    FIELD(L0_SLICER0_ENABLE, SLICER0_ENABLE, 0, 1)
2511REG32(L0_SLICER1_ENABLE, 0x2b0c)
2512    FIELD(L0_SLICER1_ENABLE, SLICER1_ENABLE_31_8_RSVD, 24, 8)
2513    FIELD(L0_SLICER1_ENABLE, SLICER01_PD_BIAS, 7, 1)
2514    FIELD(L0_SLICER1_ENABLE, SLICER1_ENABLE_TERM, 6, 1)
2515    FIELD(L0_SLICER1_ENABLE, SLICER1_ENABLE_TC_CNTRL, 4, 2)
2516    FIELD(L0_SLICER1_ENABLE, SLICER1_ENABLE_DIVIDER_4TEST, 3, 1)
2517    FIELD(L0_SLICER1_ENABLE, SLICER1_ENABLE_CLK_OUT, 2, 1)
2518    FIELD(L0_SLICER1_ENABLE, SLICER1_ENABLE_BGBIAS, 1, 1)
2519    FIELD(L0_SLICER1_ENABLE, SLICER1_ENABLE, 0, 1)
2520REG32(L0_SLICER0_BYPASS, 0x2b10)
2521    FIELD(L0_SLICER0_BYPASS, SLICER0_BYPASS_31_8_RSVD, 24, 8)
2522    FIELD(L0_SLICER0_BYPASS, SLICER0_BYPASS_7_RSVD, 7, 1)
2523    FIELD(L0_SLICER0_BYPASS, SLICER0_ENABLE_TERM_BYPASS, 6, 1)
2524    FIELD(L0_SLICER0_BYPASS, SLICER0_ENABLE_TC_CNTRL_BYPASS, 5, 1)
2525    FIELD(L0_SLICER0_BYPASS, SLICER0_BYPASS_4_3_RSVD, 3, 2)
2526    FIELD(L0_SLICER0_BYPASS, SLICER0_ENABLE_CLK_OUT_BYPASS, 2, 1)
2527    FIELD(L0_SLICER0_BYPASS, SLICER0_ENABLE_BGBIAS_BYPASS, 1, 1)
2528    FIELD(L0_SLICER0_BYPASS, SLICER0_ENABLE_BYPASS, 0, 1)
2529REG32(L0_SLICER1_BYPASS, 0x2b14)
2530    FIELD(L0_SLICER1_BYPASS, SLICER1_BYPASS_31_8_RSVD, 24, 8)
2531    FIELD(L0_SLICER1_BYPASS, SLICER01_PD_BIAS_BYPASS, 7, 1)
2532    FIELD(L0_SLICER1_BYPASS, SLICER1_ENABLE_TERM_BYPASS, 6, 1)
2533    FIELD(L0_SLICER1_BYPASS, SLICER1_ENABLE_TC_CNTRL_BYPASS, 5, 1)
2534    FIELD(L0_SLICER1_BYPASS, SLICER1_BYPASS_4_3_RSVD, 3, 2)
2535    FIELD(L0_SLICER1_BYPASS, SLICER1_ENABLE_CLK_OUT_BYPASS, 2, 1)
2536    FIELD(L0_SLICER1_BYPASS, SLICER1_ENABLE_BGBIAS_BYPASS, 1, 1)
2537    FIELD(L0_SLICER1_BYPASS, SLICER1_ENABLE_BYPASS, 0, 1)
2538REG32(L0_BG_POWER_GOOD_STATUS, 0x2b18)
2539    FIELD(L0_BG_POWER_GOOD_STATUS, BG_POWER_GOOD_STATUS_31_8_RSVD, 24, 8)
2540    FIELD(L0_BG_POWER_GOOD_STATUS, BG_POWER_GOOD_STATUS_2_7_RSVD, 2, 6)
2541    FIELD(L0_BG_POWER_GOOD_STATUS, BG_UP, 1, 1)
2542    FIELD(L0_BG_POWER_GOOD_STATUS, BG_POWER_GOOD, 0, 1)
2543REG32(L0_SUPPLY_POWER_GOOD_STATUS, 0x2b1c)
2544    FIELD(L0_SUPPLY_POWER_GOOD_STATUS, SUPPLY_POWER_GOOD_STATUS_31_8_RSVD, 24, 8)
2545    FIELD(L0_SUPPLY_POWER_GOOD_STATUS, MUXED_PG_DVDDCR, 7, 1)
2546    FIELD(L0_SUPPLY_POWER_GOOD_STATUS, MUXED_PG_AVDDIO, 6, 1)
2547    FIELD(L0_SUPPLY_POWER_GOOD_STATUS, MUXED_PG_AVDDCR, 5, 1)
2548    FIELD(L0_SUPPLY_POWER_GOOD_STATUS, PG_STATIC_AVDDIO, 4, 1)
2549    FIELD(L0_SUPPLY_POWER_GOOD_STATUS, PG_STATIC_AVDDCR, 3, 1)
2550    FIELD(L0_SUPPLY_POWER_GOOD_STATUS, PG_DVDDCR, 2, 1)
2551    FIELD(L0_SUPPLY_POWER_GOOD_STATUS, PG_AVDDIO, 1, 1)
2552    FIELD(L0_SUPPLY_POWER_GOOD_STATUS, PG_AVDDCR, 0, 1)
2553REG32(L0_BG_ISO_CTRL, 0x2b20)
2554    FIELD(L0_BG_ISO_CTRL, BG_ISO_CTRL_31_8_RSVD, 24, 8)
2555    FIELD(L0_BG_ISO_CTRL, BG_SIO_CONTROL_RSVD, 2, 6)
2556    FIELD(L0_BG_ISO_CTRL, BG_ISO_CTRL_BAR, 1, 1)
2557    FIELD(L0_BG_ISO_CTRL, FORCE_BG_ISO_CTRL_BAR, 0, 1)
2558REG32(L0_UPHY_GLOBAL_CTRL, 0x3000)
2559    FIELD(L0_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_31_8_RSVD, 24, 8)
2560    FIELD(L0_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_7_RSVD, 7, 1)
2561    FIELD(L0_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_6_RSVD, 6, 1)
2562    FIELD(L0_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_5_RSVD, 5, 1)
2563    FIELD(L0_UPHY_GLOBAL_CTRL, PCLK_SELECT, 4, 1)
2564    FIELD(L0_UPHY_GLOBAL_CTRL, MPHY_G3_BIST_ENABLE, 3, 1)
2565    FIELD(L0_UPHY_GLOBAL_CTRL, MULTI_RATE_ENABLE, 2, 1)
2566    FIELD(L0_UPHY_GLOBAL_CTRL, MPHY_GEAR_SELECT, 0, 2)
2567REG32(L0_BIST_CTRL_1, 0x3004)
2568    FIELD(L0_BIST_CTRL_1, BIST_CTRL_1_31_8_RSVD, 24, 8)
2569    FIELD(L0_BIST_CTRL_1, REPETITIVE_PATTERN_ENABLE, 7, 1)
2570    FIELD(L0_BIST_CTRL_1, PRBS_PATTERNS, 5, 2)
2571    FIELD(L0_BIST_CTRL_1, BIST_PATTERN_SELECT, 2, 3)
2572    FIELD(L0_BIST_CTRL_1, BIST_INFINITE_MODE_ENABLE, 1, 1)
2573    FIELD(L0_BIST_CTRL_1, BIST_ENABLE, 0, 1)
2574REG32(L0_BIST_CTRL_2, 0x3008)
2575    FIELD(L0_BIST_CTRL_2, BIST_CTRL_2_31_8_RSVD, 24, 8)
2576    FIELD(L0_BIST_CTRL_2, BIST_CTRL_2_7_3_RSVD, 3, 5)
2577    FIELD(L0_BIST_CTRL_2, BIST_TRAINIG_SEQUENCE_SELECT, 1, 2)
2578    FIELD(L0_BIST_CTRL_2, BIST_ERROR_INJECTION_ENABLE, 0, 1)
2579REG32(L0_BIST_RUN_LEN_L, 0x300c)
2580    FIELD(L0_BIST_RUN_LEN_L, BIST_RUN_LEN_L_31_8_RSVD, 24, 8)
2581    FIELD(L0_BIST_RUN_LEN_L, BIST_RUN_LEN_L, 0, 8)
2582REG32(L0_BIST_ERR_INJ_POINT_L, 0x3010)
2583    FIELD(L0_BIST_ERR_INJ_POINT_L, BIST_ERR_INJ_POINT_L_31_8_RSVD, 24, 8)
2584    FIELD(L0_BIST_ERR_INJ_POINT_L, BIST_ERROR_INJ_POINT_L, 0, 8)
2585REG32(L0_BIST_RUNLEN_ERR_INJ_H, 0x3014)
2586    FIELD(L0_BIST_RUNLEN_ERR_INJ_H, BIST_RUNLEN_ERR_INJ_H_31_8_RSVD, 24, 8)
2587    FIELD(L0_BIST_RUNLEN_ERR_INJ_H, BIST_RUN_LEN_H, 4, 4)
2588    FIELD(L0_BIST_RUNLEN_ERR_INJ_H, BIST_ERROR_INJ_POINT_H, 0, 4)
2589REG32(L0_BIST_IDLE_TIME, 0x3018)
2590    FIELD(L0_BIST_IDLE_TIME, BIST_IDLE_TIME_31_8_RSVD, 24, 8)
2591    FIELD(L0_BIST_IDLE_TIME, BIST_IDLE_TIME, 0, 8)
2592REG32(L0_BIST_MARKER_L, 0x301c)
2593    FIELD(L0_BIST_MARKER_L, BIST_MARKER_L_31_8_RSVD, 24, 8)
2594    FIELD(L0_BIST_MARKER_L, BIST_MARKER_L, 0, 8)
2595REG32(L0_BIST_IDLE_CHAR_L, 0x3020)
2596    FIELD(L0_BIST_IDLE_CHAR_L, BIST_IDLE_CHAR_L_31_8_RSVD, 24, 8)
2597    FIELD(L0_BIST_IDLE_CHAR_L, BIST_IDLE_CHAR_L, 0, 8)
2598REG32(L0_BIST_MARKER_IDLE_H, 0x3024)
2599    FIELD(L0_BIST_MARKER_IDLE_H, BIST_MARKER_IDLE_H_31_8_RSVD, 24, 8)
2600    FIELD(L0_BIST_MARKER_IDLE_H, BIST_MARKER_IDLE_RESERVED_7, 6, 2)
2601    FIELD(L0_BIST_MARKER_IDLE_H, BIST_MARKER_H, 4, 2)
2602    FIELD(L0_BIST_MARKER_IDLE_H, BIST_MARKER_IDLE_RESERVED_3, 2, 2)
2603    FIELD(L0_BIST_MARKER_IDLE_H, BIST_IDLE_CHAR_H, 0, 2)
2604REG32(L0_BIST_LOW_PULSE_TIME, 0x3028)
2605    FIELD(L0_BIST_LOW_PULSE_TIME, BIST_LOW_PULSE_TIME_31_8_RSVD, 24, 8)
2606    FIELD(L0_BIST_LOW_PULSE_TIME, BIST_LOW_PULSE_TIME, 0, 8)
2607REG32(L0_BIST_TOTAL_PULSE_TIME, 0x302c)
2608    FIELD(L0_BIST_TOTAL_PULSE_TIME, BIST_TOTAL_PULSE_TIME_31_8_RSVD, 24, 8)
2609    FIELD(L0_BIST_TOTAL_PULSE_TIME, BIST_TOTAL_PULSE_TIME, 0, 8)
2610REG32(L0_BIST_TEST_PAT_1, 0x3030)
2611    FIELD(L0_BIST_TEST_PAT_1, BIST_TEST_PAT_1_31_8_RSVD, 24, 8)
2612    FIELD(L0_BIST_TEST_PAT_1, BIST_TEST_PAT_1_L, 0, 8)
2613REG32(L0_BIST_TEST_PAT_2, 0x3034)
2614    FIELD(L0_BIST_TEST_PAT_2, BIST_TEST_PAT_2_31_8_RSVD, 24, 8)
2615    FIELD(L0_BIST_TEST_PAT_2, BIST_TEST_PAT_2_L, 0, 8)
2616REG32(L0_BIST_TEST_PAT_3, 0x3038)
2617    FIELD(L0_BIST_TEST_PAT_3, BIST_TEST_PAT_3_31_8_RSVD, 24, 8)
2618    FIELD(L0_BIST_TEST_PAT_3, BIST_TEST_PAT_3_L, 0, 8)
2619REG32(L0_BIST_TEST_PAT_4, 0x303c)
2620    FIELD(L0_BIST_TEST_PAT_4, BIST_TEST_PAT_4_31_8_RSVD, 24, 8)
2621    FIELD(L0_BIST_TEST_PAT_4, BIST_TEST_PAT_4_L, 0, 8)
2622REG32(L0_BIST_TEST_PAT_MSBS, 0x3040)
2623    FIELD(L0_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_MSBS_31_8_RSVD, 24, 8)
2624    FIELD(L0_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_4_H, 6, 2)
2625    FIELD(L0_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_3_H, 4, 2)
2626    FIELD(L0_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_2_H, 2, 2)
2627    FIELD(L0_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_1_H, 0, 2)
2628REG32(L0_BIST_PKT_NUM, 0x3044)
2629    FIELD(L0_BIST_PKT_NUM, BIST_PKT_NUM_31_8_RSVD, 24, 8)
2630    FIELD(L0_BIST_PKT_NUM, BIST_PKT_NUM, 0, 8)
2631REG32(L0_BIST_FRM_IDLE_TIME, 0x3048)
2632    FIELD(L0_BIST_FRM_IDLE_TIME, BIST_FRM_IDLE_TIME_31_8_RSVD, 24, 8)
2633    FIELD(L0_BIST_FRM_IDLE_TIME, BIST_FRM_IDLE_TIME, 0, 8)
2634REG32(L0_BIST_PKT_CTR_L, 0x304c)
2635    FIELD(L0_BIST_PKT_CTR_L, BIST_PKT_CTR_L_31_8_RSVD, 24, 8)
2636    FIELD(L0_BIST_PKT_CTR_L, BIST_PKT_CTR_L, 0, 8)
2637REG32(L0_BIST_PKT_CTR_H, 0x3050)
2638    FIELD(L0_BIST_PKT_CTR_H, BIST_PKT_CTR_H_31_8_RSVD, 24, 8)
2639    FIELD(L0_BIST_PKT_CTR_H, BIST_PKT_CTR_H, 0, 8)
2640REG32(L0_BIST_ERR_CTR_L, 0x3054)
2641    FIELD(L0_BIST_ERR_CTR_L, BIST_ERR_CTR_L_31_8_RSVD, 24, 8)
2642    FIELD(L0_BIST_ERR_CTR_L, BIST_ERR_CTR_L, 0, 8)
2643REG32(L0_BIST_ERR_CTR_H, 0x3058)
2644    FIELD(L0_BIST_ERR_CTR_H, BIST_ERR_CTR_H_31_8_RSVD, 24, 8)
2645    FIELD(L0_BIST_ERR_CTR_H, BIST_ERR_CTR_H, 0, 8)
2646REG32(L0_CLK_DIV_CNT, 0x305c)
2647    FIELD(L0_CLK_DIV_CNT, CLK_DIV_CNT_31_8_RSVD, 24, 8)
2648    FIELD(L0_CLK_DIV_CNT, REF_CLK_BYPASS_GT_50MHZ, 7, 1)
2649    FIELD(L0_CLK_DIV_CNT, SLOW_CNT_REG, 0, 7)
2650REG32(L0_DATA_BUS_WID, 0x3060)
2651    FIELD(L0_DATA_BUS_WID, DATA_BUS_WID_31_8_RSVD, 24, 8)
2652    FIELD(L0_DATA_BUS_WID, RATE_CHANGE_BYPASS, 7, 1)
2653    FIELD(L0_DATA_BUS_WID, PCLK_RATIO_BY_4, 6, 1)
2654    FIELD(L0_DATA_BUS_WID, PCLK_RATIO_BY_2, 5, 1)
2655    FIELD(L0_DATA_BUS_WID, RATE_CHANGE_DELAY_SEL, 4, 1)
2656    FIELD(L0_DATA_BUS_WID, RATE_CHANGE_DELAY_COUNT, 0, 4)
2657REG32(L0_ANADIG_BYPASS, 0x3064)
2658    FIELD(L0_ANADIG_BYPASS, ANADIG_BYPASS_31_8_RSVD, 24, 8)
2659    FIELD(L0_ANADIG_BYPASS, ANA_DIG_COUNTER_SELECT, 7, 1)
2660    FIELD(L0_ANADIG_BYPASS, ANADIG_COUNT, 0, 7)
2661REG32(L0_BIST_FILLER_OUT, 0x3068)
2662    FIELD(L0_BIST_FILLER_OUT, BIST_FILLER_OUT_31_8_RSVD, 24, 8)
2663    FIELD(L0_BIST_FILLER_OUT, BIST_FILLER_OUT_RESERVED, 2, 6)
2664    FIELD(L0_BIST_FILLER_OUT, BIST_FILLER_OUT_ENABLE, 1, 1)
2665    FIELD(L0_BIST_FILLER_OUT, BIST_TX_RX_LOOPBACK_ENABLE, 0, 1)
2666REG32(L0_BIST_FORCE_MK_RST, 0x306c)
2667    FIELD(L0_BIST_FORCE_MK_RST, BIST_FORCE_MK_RST_31_8_RSVD, 24, 8)
2668    FIELD(L0_BIST_FORCE_MK_RST, BIST_FORCE_RESET, 1, 1)
2669    FIELD(L0_BIST_FORCE_MK_RST, BIST_ENABLE_MK_FROM_REG, 0, 1)
2670REG32(L0_SPARE_IN, 0x3070)
2671    FIELD(L0_SPARE_IN, SPARE_IN_31_8_RSVD, 24, 8)
2672    FIELD(L0_SPARE_IN, SPARE_IN, 0, 8)
2673REG32(L0_SPARE_OUT, 0x3074)
2674    FIELD(L0_SPARE_OUT, SPARE_OUT_31_8_RSVD, 24, 8)
2675    FIELD(L0_SPARE_OUT, SPARE_OUT, 0, 8)
2676REG32(L1_TX_ANA_TM_0, 0x4000)
2677    FIELD(L1_TX_ANA_TM_0, TX_ANA_TM_0_31_8_RSVD, 24, 8)
2678    FIELD(L1_TX_ANA_TM_0, ANA_BYP0_7_6_RSVD, 6, 2)
2679    FIELD(L1_TX_ANA_TM_0, PIPE_TX_DN_RXDET, 5, 1)
2680    FIELD(L1_TX_ANA_TM_0, FORCE_PIPE_TX_DN_RXDET, 4, 1)
2681    FIELD(L1_TX_ANA_TM_0, PIPE_TX_DP_RXDET, 3, 1)
2682    FIELD(L1_TX_ANA_TM_0, FORCE_PIPE_TX_DP_RXDET, 2, 1)
2683    FIELD(L1_TX_ANA_TM_0, ANA_BYP0_1_0_RSVD, 0, 2)
2684REG32(L1_TX_ANA_TM_3, 0x400c)
2685    FIELD(L1_TX_ANA_TM_3, TX_ANA_TM_3_31_8_RSVD, 24, 8)
2686    FIELD(L1_TX_ANA_TM_3, TX_HS_SER_RSTB, 7, 1)
2687    FIELD(L1_TX_ANA_TM_3, FORCE_TX_HS_SER_RSTB, 6, 1)
2688    FIELD(L1_TX_ANA_TM_3, TX_HS_BURST, 5, 1)
2689    FIELD(L1_TX_ANA_TM_3, FORCE_TX_HS_BURST, 4, 1)
2690    FIELD(L1_TX_ANA_TM_3, TX_SERIALIZER_ENABLE, 3, 1)
2691    FIELD(L1_TX_ANA_TM_3, FORCE_TX_SERIALIZER_ENABLE, 2, 1)
2692    FIELD(L1_TX_ANA_TM_3, TX_ENABLE_SUPPLY_SERIALIZER, 1, 1)
2693    FIELD(L1_TX_ANA_TM_3, FORCE_TX_ENABLE_SUPPLY_SERIALIZER, 0, 1)
2694REG32(L1_TX_ANA_TM_4, 0x4010)
2695    FIELD(L1_TX_ANA_TM_4, TX_ANA_TM_4_31_8_RSVD, 24, 8)
2696    FIELD(L1_TX_ANA_TM_4, ANA_BYP4_7_RSVD, 7, 1)
2697    FIELD(L1_TX_ANA_TM_4, TX_LSEG_DN_RESCAL_CODE, 1, 6)
2698    FIELD(L1_TX_ANA_TM_4, FORCE_TX_LSEG_DN_RESCAL_CODE, 0, 1)
2699REG32(L1_TX_ANA_TM_5, 0x4014)
2700    FIELD(L1_TX_ANA_TM_5, TX_ANA_TM_5_31_8_RSVD, 24, 8)
2701    FIELD(L1_TX_ANA_TM_5, ANA_BYP5_7_RSVD, 7, 1)
2702    FIELD(L1_TX_ANA_TM_5, TX_USEG_DP_RESCAL_CODE, 1, 6)
2703    FIELD(L1_TX_ANA_TM_5, FORCE_TX_USEG_DP_RESCAL_CODE, 0, 1)
2704REG32(L1_TX_ANA_TM_9, 0x4024)
2705    FIELD(L1_TX_ANA_TM_9, TX_ANA_TM_9_31_8_RSVD, 24, 8)
2706    FIELD(L1_TX_ANA_TM_9, MPHY_TX_HS_SLEWRATE, 0, 8)
2707REG32(L1_TX_ANA_TM_10, 0x4028)
2708    FIELD(L1_TX_ANA_TM_10, TX_ANA_TM_10_31_8_RSVD, 24, 8)
2709    FIELD(L1_TX_ANA_TM_10, MPHY_HS_POWERUP_TIME, 4, 4)
2710    FIELD(L1_TX_ANA_TM_10, MPHY_TX_HS_EQUALIZER_SETTING, 1, 3)
2711    FIELD(L1_TX_ANA_TM_10, FORCE_MPHY_TX_HS_EQUALIZER_SETTING, 0, 1)
2712REG32(L1_TX_ANA_TM_13, 0x4034)
2713    FIELD(L1_TX_ANA_TM_13, TX_ANA_TM_13_31_8_RSVD, 24, 8)
2714    FIELD(L1_TX_ANA_TM_13, ANA_BYP13_7_4_RSVD, 4, 4)
2715    FIELD(L1_TX_ANA_TM_13, TX_SWAP_POLARITY, 3, 1)
2716    FIELD(L1_TX_ANA_TM_13, FORCE_TX_SWAP_POLARITY, 2, 1)
2717    FIELD(L1_TX_ANA_TM_13, MPHY_TX_TRISTATE, 1, 1)
2718    FIELD(L1_TX_ANA_TM_13, FORCE_MPHY_TX_TRISTATE, 0, 1)
2719REG32(L1_TX_ANA_TM_14, 0x4038)
2720    FIELD(L1_TX_ANA_TM_14, TX_ANA_TM_14_31_8_RSVD, 24, 8)
2721    FIELD(L1_TX_ANA_TM_14, ANA_BYP14_7_6_RSVD, 6, 2)
2722    FIELD(L1_TX_ANA_TM_14, PIPE_TX_FAST_EST_COMMON_MODE, 5, 1)
2723    FIELD(L1_TX_ANA_TM_14, FORCE_PIPE_TX_FAST_EST_COMMON_MODE, 4, 1)
2724    FIELD(L1_TX_ANA_TM_14, ANA_BYP14_3_0_RSVD, 0, 4)
2725REG32(L1_TX_ANA_TM_15, 0x403c)
2726    FIELD(L1_TX_ANA_TM_15, TX_ANA_TM_15_31_8_RSVD, 24, 8)
2727    FIELD(L1_TX_ANA_TM_15, PIPE_TX_SWING, 7, 1)
2728    FIELD(L1_TX_ANA_TM_15, FORCE_PIPE_TX_SWING, 6, 1)
2729    FIELD(L1_TX_ANA_TM_15, PIPE_TX_RXDET_DISCHARGE, 5, 1)
2730    FIELD(L1_TX_ANA_TM_15, FORCE_PIPE_TX_RXDET_DISCHARGE, 4, 1)
2731    FIELD(L1_TX_ANA_TM_15, PIPE_TX_RXDET_CHARGE, 3, 1)
2732    FIELD(L1_TX_ANA_TM_15, FORCE_PIPE_TX_RXDET_CHARGE, 2, 1)
2733    FIELD(L1_TX_ANA_TM_15, PIPE_TX_ENABLE_RXDET, 1, 1)
2734    FIELD(L1_TX_ANA_TM_15, FORCE_PIPE_TX_ENABLE_RXDET, 0, 1)
2735REG32(L1_TX_ANA_TM_16, 0x4040)
2736    FIELD(L1_TX_ANA_TM_16, TX_ANA_TM_16_31_8_RSVD, 24, 8)
2737    FIELD(L1_TX_ANA_TM_16, ANA_BYP16_7_4_RSVD, 4, 4)
2738    FIELD(L1_TX_ANA_TM_16, PIPE_TX_MARGIN, 1, 3)
2739    FIELD(L1_TX_ANA_TM_16, FORCE_PIPE_TX_MARGIN, 0, 1)
2740REG32(L1_TX_ANA_TM_18, 0x4048)
2741    FIELD(L1_TX_ANA_TM_18, TX_ANA_TM_18_31_8_RSVD, 24, 8)
2742    FIELD(L1_TX_ANA_TM_18, PIPE_TX_DEEMPH_7_0, 0, 8)
2743REG32(L1_TX_ANA_TM_19, 0x404c)
2744    FIELD(L1_TX_ANA_TM_19, TX_ANA_TM_19_31_8_RSVD, 24, 8)
2745    FIELD(L1_TX_ANA_TM_19, PIPE_TX_DEEMPH_15_8, 0, 8)
2746REG32(L1_TX_ANA_TM_20, 0x4050)
2747    FIELD(L1_TX_ANA_TM_20, TX_ANA_TM_20_31_8_RSVD, 24, 8)
2748    FIELD(L1_TX_ANA_TM_20, ANA_BYP20_7_5_RSVD, 5, 3)
2749    FIELD(L1_TX_ANA_TM_20, TX_SERIALIZER_RST_REL, 4, 1)
2750    FIELD(L1_TX_ANA_TM_20, FORCE_TX_SERIALIZER_RST_REL, 3, 1)
2751    FIELD(L1_TX_ANA_TM_20, FORCE_MPHY_TX_HS_SLEWRATE, 2, 1)
2752    FIELD(L1_TX_ANA_TM_20, PIPE_TX_DEEMPH_17_16, 0, 2)
2753REG32(L1_TX_ANA_TM_21, 0x4054)
2754    FIELD(L1_TX_ANA_TM_21, TX_ANA_TM_21_31_8_RSVD, 24, 8)
2755    FIELD(L1_TX_ANA_TM_21, ANA_BYP21_7_6_RSVD, 6, 2)
2756    FIELD(L1_TX_ANA_TM_21, PIPE_TX_COEF_CALC_CLK, 5, 1)
2757    FIELD(L1_TX_ANA_TM_21, FORCE_PIPE_TX_COEF_CALC_CLK, 4, 1)
2758    FIELD(L1_TX_ANA_TM_21, PIPE_TX_COEF_CALC_FSM_RESET_B, 3, 1)
2759    FIELD(L1_TX_ANA_TM_21, FORCE_PIPE_TX_COEF_CALC_FSM_RESET_B, 2, 1)
2760    FIELD(L1_TX_ANA_TM_21, PIPE_TX_DEEMPH_CTRL_SEL, 1, 1)
2761    FIELD(L1_TX_ANA_TM_21, FORCE_PIPE_TX_DEEMPH_CTRL_SEL, 0, 1)
2762REG32(L1_TX_DIG_TM_61, 0x40f4)
2763    FIELD(L1_TX_DIG_TM_61, TX_DIG_TM_61_31_8_RSVD, 24, 8)
2764    FIELD(L1_TX_DIG_TM_61, MPHY_PLL_GEAR, 6, 2)
2765    FIELD(L1_TX_DIG_TM_61, DIG_BYP1_5_4_RSVD, 4, 2)
2766    FIELD(L1_TX_DIG_TM_61, BYPASS_ENC, 3, 1)
2767    FIELD(L1_TX_DIG_TM_61, DIG_BYP1_2_RSVD, 2, 1)
2768    FIELD(L1_TX_DIG_TM_61, BYPASS_SCRAM, 1, 1)
2769    FIELD(L1_TX_DIG_TM_61, FORCE_BYPASS_SCRAM, 0, 1)
2770REG32(L1_TX_DIG_TM_62, 0x40f8)
2771    FIELD(L1_TX_DIG_TM_62, TX_DIG_TM_62_31_8_RSVD, 24, 8)
2772    FIELD(L1_TX_DIG_TM_62, G0_BIT_PER_CNT, 0, 8)
2773REG32(L1_TX_DIG_TM_65, 0x4104)
2774    FIELD(L1_TX_DIG_TM_65, TX_DIG_TM_65_31_8_RSVD, 24, 8)
2775    FIELD(L1_TX_DIG_TM_65, FORCE_TX_RXDET_PROBE_THRESHOLD, 7, 1)
2776    FIELD(L1_TX_DIG_TM_65, FORCE_TX_RXDET_END_CH_THRESHOLD, 6, 1)
2777    FIELD(L1_TX_DIG_TM_65, FORCE_TX_RXDET_START_CH_THRESHOLD, 5, 1)
2778    FIELD(L1_TX_DIG_TM_65, FORCE_TX_RXDET_END_DCH_THRESHOLD, 4, 1)
2779    FIELD(L1_TX_DIG_TM_65, FORCE_TX_RXDET_START_DCH_THRESHOLD, 3, 1)
2780    FIELD(L1_TX_DIG_TM_65, TX_EN_FULL_CALIB, 2, 1)
2781    FIELD(L1_TX_DIG_TM_65, FORCE_TX_EN_FULL_CALIB, 1, 1)
2782    FIELD(L1_TX_DIG_TM_65, DIG_BYP5_0_RSVD, 0, 1)
2783REG32(L1_TX_DIG_TM_67, 0x410c)
2784    FIELD(L1_TX_DIG_TM_67, TX_DIG_TM_67_31_8_RSVD, 24, 8)
2785    FIELD(L1_TX_DIG_TM_67, TX_MPHY_SER_THRESHOLD, 0, 8)
2786REG32(L1_TX_DIG_TM_68, 0x4110)
2787    FIELD(L1_TX_DIG_TM_68, TX_DIG_TM_68_31_8_RSVD, 24, 8)
2788    FIELD(L1_TX_DIG_TM_68, TX_SER_SUP_THRESHOLD, 0, 8)
2789REG32(L1_TX_DIG_TM_69, 0x4114)
2790    FIELD(L1_TX_DIG_TM_69, TX_DIG_TM_69_31_8_RSVD, 24, 8)
2791    FIELD(L1_TX_DIG_TM_69, TX_MPHY_SUP_THRESHOLD, 0, 8)
2792REG32(L1_TX_DIG_TM_76, 0x4130)
2793    FIELD(L1_TX_DIG_TM_76, TX_DIG_TM_76_31_8_RSVD, 24, 8)
2794    FIELD(L1_TX_DIG_TM_76, TX_RXDET_START_DCH_THRESHOLD_7_0, 0, 8)
2795REG32(L1_TX_DIG_TM_77, 0x4134)
2796    FIELD(L1_TX_DIG_TM_77, TX_DIG_TM_77_31_8_RSVD, 24, 8)
2797    FIELD(L1_TX_DIG_TM_77, TX_RXDET_END_DCH_THRESHOLD_11_8, 4, 4)
2798    FIELD(L1_TX_DIG_TM_77, TX_RXDET_START_DCH_THRESHOLD_11_8, 0, 4)
2799REG32(L1_TX_DIG_TM_78, 0x4138)
2800    FIELD(L1_TX_DIG_TM_78, TX_DIG_TM_78_31_8_RSVD, 24, 8)
2801    FIELD(L1_TX_DIG_TM_78, TX_RXDET_END_DCH_THRESHOLD_7_0, 0, 8)
2802REG32(L1_TX_DIG_TM_79, 0x413c)
2803    FIELD(L1_TX_DIG_TM_79, TX_DIG_TM_79_31_8_RSVD, 24, 8)
2804    FIELD(L1_TX_DIG_TM_79, TX_RXDET_START_CH_THRESHOLD_7_0, 0, 8)
2805REG32(L1_TX_DIG_TM_80, 0x4140)
2806    FIELD(L1_TX_DIG_TM_80, TX_DIG_TM_80_31_8_RSVD, 24, 8)
2807    FIELD(L1_TX_DIG_TM_80, TX_RXDET_END_CH_THRESHOLD_11_8, 4, 4)
2808    FIELD(L1_TX_DIG_TM_80, TX_RXDET_START_CH_THRESHOLD_11_8, 0, 4)
2809REG32(L1_TX_DIG_TM_81, 0x4144)
2810    FIELD(L1_TX_DIG_TM_81, TX_DIG_TM_81_31_8_RSVD, 24, 8)
2811    FIELD(L1_TX_DIG_TM_81, TX_RXDET_END_CH_THRESHOLD_7_0, 0, 8)
2812REG32(L1_TX_DIG_TM_82, 0x4148)
2813    FIELD(L1_TX_DIG_TM_82, TX_DIG_TM_82_31_8_RSVD, 24, 8)
2814    FIELD(L1_TX_DIG_TM_82, TX_RXDET_PROBE_THRESHOLD_7_0, 0, 8)
2815REG32(L1_TX_DIG_TM_83, 0x414c)
2816    FIELD(L1_TX_DIG_TM_83, TX_DIG_TM_83_31_8_RSVD, 24, 8)
2817    FIELD(L1_TX_DIG_TM_83, DIG_BYP23_7_4_RSVD, 4, 4)
2818    FIELD(L1_TX_DIG_TM_83, TX_RXDET_PROBE_THRESHOLD_11_8, 0, 4)
2819REG32(L1_TX_DIG_TM_84, 0x4150)
2820    FIELD(L1_TX_DIG_TM_84, TX_DIG_TM_84_31_8_RSVD, 24, 8)
2821    FIELD(L1_TX_DIG_TM_84, TX_DIF_P, 7, 1)
2822    FIELD(L1_TX_DIG_TM_84, TX_DITHER_1P, 6, 1)
2823    FIELD(L1_TX_DIG_TM_84, TX_DITHER_1N, 5, 1)
2824    FIELD(L1_TX_DIG_TM_84, TX_DITHER_EN, 4, 1)
2825    FIELD(L1_TX_DIG_TM_84, DIG_BYP24_3_RSVD, 3, 1)
2826    FIELD(L1_TX_DIG_TM_84, TX_PHYDIRDY_SOC_MODE, 2, 1)
2827    FIELD(L1_TX_DIG_TM_84, DIG_BYP24_1_RSVD, 1, 1)
2828    FIELD(L1_TX_DIG_TM_84, TX_READ_SHADOW, 0, 1)
2829REG32(L1_TX_ANA_TM_85, 0x4154)
2830    FIELD(L1_TX_ANA_TM_85, TX_ANA_TM_85_31_8_RSVD, 24, 8)
2831    FIELD(L1_TX_ANA_TM_85, DIG_BYP25_7_6_RSVD, 6, 2)
2832    FIELD(L1_TX_ANA_TM_85, TX_HIBERN8_CTRL, 5, 1)
2833    FIELD(L1_TX_ANA_TM_85, TX_ALLOW_INLNCFG_FROM_TOP, 4, 1)
2834    FIELD(L1_TX_ANA_TM_85, DIG_BYP25_3_RSVD, 3, 1)
2835    FIELD(L1_TX_ANA_TM_85, TX_SEND_MSB_FIRST, 2, 1)
2836    FIELD(L1_TX_ANA_TM_85, DIG_BYP25_1_RSVD, 1, 1)
2837    FIELD(L1_TX_ANA_TM_85, TX_DIF_N, 0, 1)
2838REG32(L1_TX_ANA_TM_87, 0x415c)
2839    FIELD(L1_TX_ANA_TM_87, TX_ANA_TM_87_31_8_RSVD, 24, 8)
2840    FIELD(L1_TX_ANA_TM_87, DIG_BYP27_7_4_RSVD, 4, 4)
2841    FIELD(L1_TX_ANA_TM_87, TX_SM_STATUS, 0, 4)
2842REG32(L1_TX_ANA_TM_88, 0x4160)
2843    FIELD(L1_TX_ANA_TM_88, TX_ANA_TM_88_31_8_RSVD, 24, 8)
2844    FIELD(L1_TX_ANA_TM_88, TX_COMP_PAT_HIGH_TIME_REGS, 0, 8)
2845REG32(L1_TX_ANA_TM_89, 0x4164)
2846    FIELD(L1_TX_ANA_TM_89, TX_ANA_TM_89_31_8_RSVD, 24, 8)
2847    FIELD(L1_TX_ANA_TM_89, DIG_BYP29_7_6_RSVD, 6, 2)
2848    FIELD(L1_TX_ANA_TM_89, TX_DATAPATH_CTRL_1_REGS, 5, 1)
2849    FIELD(L1_TX_ANA_TM_89, DIG_BYP29_4_3_RSVD, 3, 2)
2850    FIELD(L1_TX_ANA_TM_89, INITIAL_DISPARITY, 2, 1)
2851    FIELD(L1_TX_ANA_TM_89, SCRAMBLER_ENABLE, 1, 1)
2852    FIELD(L1_TX_ANA_TM_89, DIG_BYP29_0_RSVD, 0, 1)
2853REG32(L1_TX_ANA_TM_90, 0x4168)
2854    FIELD(L1_TX_ANA_TM_90, TX_ANA_TM_90_31_8_RSVD, 24, 8)
2855    FIELD(L1_TX_ANA_TM_90, DIG_BYP30_7_6_RSVD, 6, 2)
2856    FIELD(L1_TX_ANA_TM_90, TX_BYPASS_BCNT_LPBACK_REGS, 5, 1)
2857    FIELD(L1_TX_ANA_TM_90, DIG_BYP30_4_0_RSVD, 0, 5)
2858REG32(L1_TX_DIG_TM_91, 0x416c)
2859    FIELD(L1_TX_DIG_TM_91, TX_DIG_TM_91_31_8_RSVD, 24, 8)
2860    FIELD(L1_TX_DIG_TM_91, TX_CFGCLK_FREQ, 0, 8)
2861REG32(L1_TX_DIG_TM_92, 0x4170)
2862    FIELD(L1_TX_DIG_TM_92, TX_DIG_TM_92_31_8_RSVD, 24, 8)
2863    FIELD(L1_TX_DIG_TM_92, TX_PHYDIRDY_PULL_UP_LATENCY, 0, 8)
2864REG32(L1_TX_ANA_TM_95, 0x417c)
2865    FIELD(L1_TX_ANA_TM_95, TX_ANA_TM_95_31_8_RSVD, 24, 8)
2866    FIELD(L1_TX_ANA_TM_95, ANA_BYP63_7_6_RSVD, 6, 2)
2867    FIELD(L1_TX_ANA_TM_95, TX_TM_EN_PROG_SYNC_PATTERN, 5, 1)
2868    FIELD(L1_TX_ANA_TM_95, TX_EXTRA_HS_BURST_IN_LCC, 2, 3)
2869    FIELD(L1_TX_ANA_TM_95, ANA_BYP22_1_0_RSVD, 0, 2)
2870REG32(L1_TX_ANA_TM_96, 0x4180)
2871    FIELD(L1_TX_ANA_TM_96, TX_ANA_TM_96_31_8_RSVD, 24, 8)
2872    FIELD(L1_TX_ANA_TM_96, TX_TM_PROG_SYNC_PATTERN1, 0, 8)
2873REG32(L1_TX_ANA_TM_97, 0x4184)
2874    FIELD(L1_TX_ANA_TM_97, TX_ANA_TM_97_31_8_RSVD, 24, 8)
2875    FIELD(L1_TX_ANA_TM_97, TX_TM_PROG_SYNC_PATTERN2, 0, 8)
2876REG32(L1_TX_DIG_TM_98, 0x4188)
2877    FIELD(L1_TX_DIG_TM_98, TX_DIG_TM_98_31_8_RSVD, 24, 8)
2878    FIELD(L1_TX_DIG_TM_98, DIG_BYP33_7_6_RSVD, 6, 2)
2879    FIELD(L1_TX_DIG_TM_98, FORCE_RD_VALUE, 5, 1)
2880    FIELD(L1_TX_DIG_TM_98, FORCE_RD, 4, 1)
2881    FIELD(L1_TX_DIG_TM_98, TX_SER_ISO_CTRL_BAR, 3, 1)
2882    FIELD(L1_TX_DIG_TM_98, FORCE_TX_SER_ISO_CTRL_BAR, 2, 1)
2883    FIELD(L1_TX_DIG_TM_98, TX_ISO_CTRL_BAR, 1, 1)
2884    FIELD(L1_TX_DIG_TM_98, FORCE_TX_ISO_CTRL_BAR, 0, 1)
2885REG32(L1_TX_DIG_TM_99, 0x418c)
2886    FIELD(L1_TX_DIG_TM_99, TX_DIG_TM_99_31_8_RSVD, 24, 8)
2887    FIELD(L1_TX_DIG_TM_99, TX_PIPE_SUPPLY_ENABLE_THRESHOLD, 0, 8)
2888REG32(L1_TX_DIG_TM_100, 0x4190)
2889    FIELD(L1_TX_DIG_TM_100, TX_DIG_TM_100_31_8_RSVD, 24, 8)
2890    FIELD(L1_TX_DIG_TM_100, TX_SERIALISER_SUPPLY_ENABLE_THRESHOLD, 0, 8)
2891REG32(L1_TX_DIG_TM_101, 0x4194)
2892    FIELD(L1_TX_DIG_TM_101, TX_DIG_TM_101_31_8_RSVD, 24, 8)
2893    FIELD(L1_TX_DIG_TM_101, TX_SERIALISER_ENABLE_THRESHOLD, 0, 8)
2894REG32(L1_TX_DIG_TM_102, 0x4198)
2895    FIELD(L1_TX_DIG_TM_102, TX_DIG_TM_102_31_8_RSVD, 24, 8)
2896    FIELD(L1_TX_DIG_TM_102, FORCE_TX_ANA_LL_EN, 7, 1)
2897    FIELD(L1_TX_DIG_TM_102, TX_ANA_LL_EN, 6, 1)
2898    FIELD(L1_TX_DIG_TM_102, FORCE_DELAY_CNT_THRESHOLD, 5, 1)
2899    FIELD(L1_TX_DIG_TM_102, FORCE_TX_MPHY_TRST_THRESHOLD, 4, 1)
2900    FIELD(L1_TX_DIG_TM_102, FORCE_TX_LDO_THRESHOLD, 3, 1)
2901    FIELD(L1_TX_DIG_TM_102, FORCE_TX_SERIALISER_ENABLE_THRESHOLD, 2, 1)
2902    FIELD(L1_TX_DIG_TM_102, FORCE_TX_SERIALISER_SUPPLY_ENABLE_THRESHOLD, 1, 1)
2903    FIELD(L1_TX_DIG_TM_102, FORCE_TX_PIPE_SUPPLY_ENABLE_THRESHOLD, 0, 1)
2904REG32(L1_TX_DIG_TM_103, 0x419c)
2905    FIELD(L1_TX_DIG_TM_103, TX_DIG_TM_103_31_8_RSVD, 24, 8)
2906    FIELD(L1_TX_DIG_TM_103, FORCE_BG_EN, 7, 1)
2907    FIELD(L1_TX_DIG_TM_103, FORCE_CALIB_EN, 6, 1)
2908    FIELD(L1_TX_DIG_TM_103, FORCE_PLL_EN, 5, 1)
2909    FIELD(L1_TX_DIG_TM_103, FORCE_PSO, 4, 1)
2910    FIELD(L1_TX_DIG_TM_103, BG_EN, 3, 1)
2911    FIELD(L1_TX_DIG_TM_103, CALIB_EN, 2, 1)
2912    FIELD(L1_TX_DIG_TM_103, PLL_EN, 1, 1)
2913    FIELD(L1_TX_DIG_TM_103, PSO, 0, 1)
2914REG32(L1_TX_DIG_TM_104, 0x41a0)
2915    FIELD(L1_TX_DIG_TM_104, TX_DIG_TM_104_31_8_RSVD, 24, 8)
2916    FIELD(L1_TX_DIG_TM_104, TX_LDO_THRESHOLD, 0, 8)
2917REG32(L1_TX_DIG_TM_105, 0x41a4)
2918    FIELD(L1_TX_DIG_TM_105, TX_DIG_TM_105_31_8_RSVD, 24, 8)
2919    FIELD(L1_TX_DIG_TM_105, TX_MPHY_TRST_THRESHOLD, 0, 8)
2920REG32(L1_TX_DIG_TM_106, 0x41a8)
2921    FIELD(L1_TX_DIG_TM_106, TX_DIG_TM_106_31_8_RSVD, 24, 8)
2922    FIELD(L1_TX_DIG_TM_106, DELAY_CNT_THRESHOLD, 0, 8)
2923REG32(L1_TX_DIG_TM_107, 0x41ac)
2924    FIELD(L1_TX_DIG_TM_107, TX_DIG_TM_107_31_8_RSVD, 24, 8)
2925    FIELD(L1_TX_DIG_TM_107, DIG_BYP42_7_RSVD, 7, 1)
2926    FIELD(L1_TX_DIG_TM_107, FORCE_P3TOP0_PHYSTATUS_PULSE, 6, 1)
2927    FIELD(L1_TX_DIG_TM_107, ENABLE_HS_CLK_DIVISION, 5, 1)
2928    FIELD(L1_TX_DIG_TM_107, TESTDIGOUT_SEL, 1, 4)
2929    FIELD(L1_TX_DIG_TM_107, FORCE_TESTDIGOUT_SEL, 0, 1)
2930REG32(L1_TX_DIG_TM_108, 0x41b0)
2931    FIELD(L1_TX_DIG_TM_108, TX_DIG_TM_108_31_8_RSVD, 24, 8)
2932    FIELD(L1_TX_DIG_TM_108, ANA_BYP43_7_RSVD, 7, 1)
2933    FIELD(L1_TX_DIG_TM_108, TX_EXT_DATA_DELAY, 3, 4)
2934    FIELD(L1_TX_DIG_TM_108, FORCE_TX_EXT_DATA_DELAY, 2, 1)
2935    FIELD(L1_TX_DIG_TM_108, FORCE_TX_DATA_DELAY, 1, 1)
2936    FIELD(L1_TX_DIG_TM_108, FORCE_UPHY_TXPMA_OPMODE, 0, 1)
2937REG32(L1_TX_DIG_TM_109, 0x41b4)
2938    FIELD(L1_TX_DIG_TM_109, TX_DIG_TM_109_31_8_RSVD, 24, 8)
2939    FIELD(L1_TX_DIG_TM_109, UPHY_TXPMA_OPMODE, 0, 8)
2940REG32(L1_TX_DIG_TM_110, 0x41b8)
2941    FIELD(L1_TX_DIG_TM_110, TX_DIG_TM_110_31_8_RSVD, 24, 8)
2942    FIELD(L1_TX_DIG_TM_110, TX_DATA_DELAY, 0, 8)
2943REG32(L1_TX_DIG_TM_111, 0x41bc)
2944    FIELD(L1_TX_DIG_TM_111, TX_DIG_TM_111_31_8_RSVD, 24, 8)
2945    FIELD(L1_TX_DIG_TM_111, TX_DA_SPARE, 0, 8)
2946REG32(L1_TX_ANA_TM_112, 0x41c0)
2947    FIELD(L1_TX_ANA_TM_112, TX_ANA_TM_112_31_8_RSVD, 24, 8)
2948    FIELD(L1_TX_ANA_TM_112, ANA_BYP25_7_6_RSVD, 6, 2)
2949    FIELD(L1_TX_ANA_TM_112, PIPE_TX_ENABLE_LFPS, 4, 2)
2950    FIELD(L1_TX_ANA_TM_112, FORCE_PIPE_TX_ENABLE_LFPS, 3, 1)
2951    FIELD(L1_TX_ANA_TM_112, PIPE_TX_ENABLE_IDLE_MODE, 1, 2)
2952    FIELD(L1_TX_ANA_TM_112, FORCE_PIPE_TX_ENABLE_IDLE_MODE, 0, 1)
2953REG32(L1_TX_ANA_TM_113, 0x41c4)
2954    FIELD(L1_TX_ANA_TM_113, TX_ANA_TM_113_31_8_RSVD, 24, 8)
2955    FIELD(L1_TX_ANA_TM_113, MPHY_TX_DRIVERLDO_PROG, 0, 8)
2956REG32(L1_TX_ANA_TM_114, 0x41c8)
2957    FIELD(L1_TX_ANA_TM_114, TX_ANA_TM_114_31_8_RSVD, 24, 8)
2958    FIELD(L1_TX_ANA_TM_114, ANA_BYP27_7_5_RSVD, 5, 3)
2959    FIELD(L1_TX_ANA_TM_114, FORCE_MPHY_TX_DRIVERLDO_PROG, 4, 1)
2960    FIELD(L1_TX_ANA_TM_114, MPHY_TX_DRIVERLDO_PROG, 0, 4)
2961REG32(L1_TX_ANA_TM_115, 0x41cc)
2962    FIELD(L1_TX_ANA_TM_115, TX_ANA_TM_115_31_8_RSVD, 24, 8)
2963    FIELD(L1_TX_ANA_TM_115, ANA_BYP28_7_RSVD, 7, 1)
2964    FIELD(L1_TX_ANA_TM_115, PIPE_TX_GETLOCALPRESETCOEFFICIENTS, 6, 1)
2965    FIELD(L1_TX_ANA_TM_115, FORCE_PIPE_TX_GETLOCALPRESETCOEFFICIENTS, 5, 1)
2966    FIELD(L1_TX_ANA_TM_115, TX_PMADIG_DIGITAL_RESET_N, 4, 1)
2967    FIELD(L1_TX_ANA_TM_115, FORCE_TX_PMADIG_DIGITAL_RESET_N, 3, 1)
2968    FIELD(L1_TX_ANA_TM_115, TX_ANA_IF_RATE, 1, 2)
2969    FIELD(L1_TX_ANA_TM_115, FORCE_TX_ANA_IF_RATE, 0, 1)
2970REG32(L1_TX_ANA_TM_116, 0x41d0)
2971    FIELD(L1_TX_ANA_TM_116, TX_ANA_TM_116_31_8_RSVD, 24, 8)
2972    FIELD(L1_TX_ANA_TM_116, ANA_BYP29_7_RSVD, 7, 1)
2973    FIELD(L1_TX_ANA_TM_116, PIPE_TX_LOCALPRESETINDEX, 3, 4)
2974    FIELD(L1_TX_ANA_TM_116, FORCE_PIPE_TX_LOCALPRESETINDEX, 2, 1)
2975    FIELD(L1_TX_ANA_TM_116, MPHY_TX_EN_LANE_LS_CLK, 1, 1)
2976    FIELD(L1_TX_ANA_TM_116, FORCE_MPHY_TX_EN_LANE_LS_CLK, 0, 1)
2977REG32(L1_TX_ANA_TM_117, 0x41d4)
2978    FIELD(L1_TX_ANA_TM_117, TX_ANA_TM_117_31_8_RSVD, 24, 8)
2979    FIELD(L1_TX_ANA_TM_117, MULTILANE_BYP1_7_6_RSVD, 6, 2)
2980    FIELD(L1_TX_ANA_TM_117, TX_PCIE_4X_CFG_EN, 5, 1)
2981    FIELD(L1_TX_ANA_TM_117, FORCE_TX_PCIE_4X_CFG_EN, 4, 1)
2982    FIELD(L1_TX_ANA_TM_117, TX_PCIE_2X_CFG_EN, 3, 1)
2983    FIELD(L1_TX_ANA_TM_117, FORCE_TX_PCIE_2X_CFG_EN, 2, 1)
2984    FIELD(L1_TX_ANA_TM_117, TX_DP_MULTILANE_CFG_EN, 1, 1)
2985    FIELD(L1_TX_ANA_TM_117, FORCE_TX_DP_MULTILANE_CFG_EN, 0, 1)
2986REG32(L1_TX_ANA_TM_118, 0x41d8)
2987    FIELD(L1_TX_ANA_TM_118, TX_ANA_TM_118_31_8_RSVD, 24, 8)
2988    FIELD(L1_TX_ANA_TM_118, ANA_BYP30_7_4_RSVD, 4, 4)
2989    FIELD(L1_TX_ANA_TM_118, FORCE_TX_DEEMPH_17_12, 3, 1)
2990    FIELD(L1_TX_ANA_TM_118, FORCE_TX_DEEMPH_11_6, 2, 1)
2991    FIELD(L1_TX_ANA_TM_118, FORCE_TX_DEEMPH_5_0, 1, 1)
2992    FIELD(L1_TX_ANA_TM_118, FORCE_TX_DEEMPH_17_0, 0, 1)
2993REG32(L1_TXPMA_TM_0, 0x4800)
2994    FIELD(L1_TXPMA_TM_0, TXPMA_TM_0_31_8_RSVD, 24, 8)
2995    FIELD(L1_TXPMA_TM_0, TM_TX_ENABLE_SUPPLY_MPHY, 7, 1)
2996    FIELD(L1_TXPMA_TM_0, TM_FORCE_TX_ENABLE_SUPPLY_MPHY, 6, 1)
2997    FIELD(L1_TXPMA_TM_0, TM_MPHY_TX_ENABLE_SUPPLY_LS_CLOCK, 5, 1)
2998    FIELD(L1_TXPMA_TM_0, TM_FORCE_MPHY_TX_ENABLE_SUPPLY_LS_CLOCK, 4, 1)
2999    FIELD(L1_TXPMA_TM_0, TM_MPHY_TX_ENABLE_SA_MODE, 3, 1)
3000    FIELD(L1_TXPMA_TM_0, TM_FORCE_MPHY_TX_ENABLE_SA_MODE, 2, 1)

3001    FIELD(L1_TXPMA_TM_0, TM_MPHY_TX_ENABLE_HS_NT, 1, 1)
3002    FIELD(L1_TXPMA_TM_0, TM_FORCE_MPHY_TX_ENABLE_HS_NT, 0, 1)
3003REG32(L1_TXPMA_TM_1, 0x4804)
3004    FIELD(L1_TXPMA_TM_1, TXPMA_TM_1_31_8_RSVD, 24, 8)
3005    FIELD(L1_TXPMA_TM_1, ANA_MPHY_BYP1_7_4_RSVD, 4, 4)
3006    FIELD(L1_TXPMA_TM_1, TM_MPHY_TX_HS_DITHER_VAL, 1, 3)
3007    FIELD(L1_TXPMA_TM_1, TM_FORCE_MPHY_TX_HS_DITHER_VAL, 0, 1)
3008REG32(L1_TXPMA_TM_2, 0x4808)
3009    FIELD(L1_TXPMA_TM_2, TXPMA_TM_2_31_8_RSVD, 24, 8)
3010    FIELD(L1_TXPMA_TM_2, TM_MPHY_TX_DRIVERLDO_PROG_6_0, 1, 7)
3011    FIELD(L1_TXPMA_TM_2, TM_FORCE_MPHY_TX_DRIVERLDO_PROG, 0, 1)
3012REG32(L1_TXPMA_TM_3, 0x480c)
3013    FIELD(L1_TXPMA_TM_3, TXPMA_TM_3_31_8_RSVD, 24, 8)
3014    FIELD(L1_TXPMA_TM_3, ANA_MPHY_BYP3_7_5_RSVD, 5, 3)
3015    FIELD(L1_TXPMA_TM_3, TM_MPHY_TX_DRIVERLDO_PROG_11_7, 0, 5)
3016REG32(L1_TXPMA_TM_4, 0x4810)
3017    FIELD(L1_TXPMA_TM_4, TXPMA_TM_4_31_8_RSVD, 24, 8)
3018    FIELD(L1_TXPMA_TM_4, TM_PIPE_TX_TX_DATA_WIDTH, 5, 3)
3019    FIELD(L1_TXPMA_TM_4, TM_FORCE_PIPE_TX_TX_DATA_WIDTH, 4, 1)
3020    FIELD(L1_TXPMA_TM_4, TM_PIPE_TX_POWERDOWN_VCM_HOLD, 3, 1)
3021    FIELD(L1_TXPMA_TM_4, TM_FORCE_PIPE_TX_POWERDOWN_VCM_HOLD, 2, 1)
3022    FIELD(L1_TXPMA_TM_4, TM_PIPE_TX_ANABOOST_POWERDOWN, 1, 1)
3023    FIELD(L1_TXPMA_TM_4, ANA_PIPE_BYP0_0_RSVD, 0, 1)
3024REG32(L1_TXPMA_TM_5, 0x4814)
3025    FIELD(L1_TXPMA_TM_5, TXPMA_TM_5_31_8_RSVD, 24, 8)
3026    FIELD(L1_TXPMA_TM_5, ANA_BSCAN_BYP0_7_4_RSVD, 4, 4)
3027    FIELD(L1_TXPMA_TM_5, TM_TX_BSCAN_SEL, 3, 1)
3028    FIELD(L1_TXPMA_TM_5, TM_FORCE_TX_BSCAN_SEL, 2, 1)
3029    FIELD(L1_TXPMA_TM_5, TM_TX_BSCAN_DATA, 1, 1)
3030    FIELD(L1_TXPMA_TM_5, TM_FORCE_TX_BSCAN_DATA, 0, 1)
3031REG32(L1_TXPMA_TM_6, 0x4818)
3032    FIELD(L1_TXPMA_TM_6, TXPMA_TM_6_31_8_RSVD, 24, 8)
3033    FIELD(L1_TXPMA_TM_6, TM_TX_ENABLE_ISI_LPBK, 7, 1)
3034    FIELD(L1_TXPMA_TM_6, TM_FORCE_TX_ENABLE_ISI_LPBK, 6, 1)
3035    FIELD(L1_TXPMA_TM_6, TM_TX_ENABLE_SER_LPBK, 5, 1)
3036    FIELD(L1_TXPMA_TM_6, TM_FORCE_TX_ENABLE_SER_LPBK, 4, 1)
3037    FIELD(L1_TXPMA_TM_6, TM_TX_ENABLE_RX_LIN_LPBK, 3, 1)
3038    FIELD(L1_TXPMA_TM_6, TM_FORCE_TX_ENABLE_RX_LIN_LPBK, 2, 1)
3039    FIELD(L1_TXPMA_TM_6, TM_TX_ENABLE_RCRVD_DATA_LPBK, 1, 1)
3040    FIELD(L1_TXPMA_TM_6, TM_FORCE_TX_ENABLE_RCRVD_DATA_LPBK, 0, 1)
3041REG32(L1_TXPMA_TM_7, 0x481c)
3042    FIELD(L1_TXPMA_TM_7, TXPMA_TM_7_31_8_RSVD, 24, 8)
3043    FIELD(L1_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_UPHY, 7, 1)
3044    FIELD(L1_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_UPHY, 6, 1)
3045    FIELD(L1_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_SERIALIZER, 5, 1)
3046    FIELD(L1_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_SERIALIZER, 4, 1)
3047    FIELD(L1_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_PIPE, 3, 1)
3048    FIELD(L1_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_PIPE, 2, 1)
3049    FIELD(L1_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_HSCLK, 1, 1)
3050    FIELD(L1_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_HSCLK, 0, 1)
3051REG32(L1_TXPMA_TM_8, 0x4820)
3052    FIELD(L1_TXPMA_TM_8, TXPMA_TM_8_31_8_RSVD, 24, 8)
3053    FIELD(L1_TXPMA_TM_8, ANA_LS_LFPS_BYP0_7_2_RSVD, 2, 6)
3054    FIELD(L1_TXPMA_TM_8, TM_TX_LS_LFPS_DATA, 1, 1)
3055    FIELD(L1_TXPMA_TM_8, TM_FORCE_TX_LS_LFPS_DATA, 0, 1)
3056REG32(L1_TXPMA_TM_9, 0x4824)
3057    FIELD(L1_TXPMA_TM_9, TXPMA_TM_9_31_8_RSVD, 24, 8)
3058    FIELD(L1_TXPMA_TM_9, ANA_MISC0_7_RSVD, 7, 1)
3059    FIELD(L1_TXPMA_TM_9, TM_TX_SERIALIZER_MODE, 6, 1)
3060    FIELD(L1_TXPMA_TM_9, TM_FORCE_TX_SERIALIZER_MODE, 5, 1)
3061    FIELD(L1_TXPMA_TM_9, TM_TX_ENABLE_HSCLK_DIVISION, 3, 2)
3062    FIELD(L1_TXPMA_TM_9, TM_FORCE_TX_ENABLE_HSCLK_DIVISION, 2, 1)
3063    FIELD(L1_TXPMA_TM_9, TM_TX_DRIVER_POLARITY, 1, 1)
3064    FIELD(L1_TXPMA_TM_9, TM_FORCE_TX_DRIVER_POLARITY, 0, 1)
3065REG32(L1_TXPMA_TM_10, 0x4828)
3066    FIELD(L1_TXPMA_TM_10, TXPMA_TM_10_31_8_RSVD, 24, 8)
3067    FIELD(L1_TXPMA_TM_10, ANA_MISC1_7_6_RSVD, 6, 2)
3068    FIELD(L1_TXPMA_TM_10, TM_TX_ENABLE_LOWLEAKAGE, 5, 1)
3069    FIELD(L1_TXPMA_TM_10, TM_FORCE_TX_ENABLE_LOWLEAKAGE, 4, 1)
3070    FIELD(L1_TXPMA_TM_10, TM_TX_ENABLE_REF, 3, 1)
3071    FIELD(L1_TXPMA_TM_10, TM_FORCE_TX_ENABLE_REF, 2, 1)
3072    FIELD(L1_TXPMA_TM_10, TM_TX_ENABLE_LDO, 1, 1)
3073    FIELD(L1_TXPMA_TM_10, TM_FORCE_TX_ENABLE_LDO, 0, 1)
3074REG32(L1_TXPMA_TM_11, 0x482c)
3075    FIELD(L1_TXPMA_TM_11, TXPMA_TM_11_31_8_RSVD, 24, 8)
3076    FIELD(L1_TXPMA_TM_11, ANA_VCM_BYP0_7_5_RSVD, 5, 3)
3077    FIELD(L1_TXPMA_TM_11, TM_TX_VCMHOLD_PROG, 1, 4)
3078    FIELD(L1_TXPMA_TM_11, TM_TX_VCMHOLD_OBSRV, 0, 1)
3079REG32(L1_TXPMA_TM_12, 0x4830)
3080    FIELD(L1_TXPMA_TM_12, TXPMA_TM_12_31_8_RSVD, 24, 8)
3081    FIELD(L1_TXPMA_TM_12, TM_TX_SER_POWERISLAND_OBSRV, 5, 3)
3082    FIELD(L1_TXPMA_TM_12, TM_TX_CLK_POWERISLAND_OBSRV, 1, 4)
3083    FIELD(L1_TXPMA_TM_12, ANA_PWR_ISLAND_BYP0_0_RSVD, 0, 1)
3084REG32(L1_TXPMA_TM_13, 0x4834)
3085    FIELD(L1_TXPMA_TM_13, TXPMA_TM_13_31_8_RSVD, 24, 8)
3086    FIELD(L1_TXPMA_TM_13, TM_TX_POWERISLAND_OBSRV, 0, 8)
3087REG32(L1_TXPMA_TM_14, 0x4838)
3088    FIELD(L1_TXPMA_TM_14, TXPMA_TM_14_31_8_RSVD, 24, 8)
3089    FIELD(L1_TXPMA_TM_14, ANA_MISC2_7_5_RSVD, 5, 3)
3090    FIELD(L1_TXPMA_TM_14, TM_TX_POWERISLAND_OBSRV, 3, 2)
3091    FIELD(L1_TXPMA_TM_14, PIPE_TM_TX_ANABOOST_POWER_OBSRV, 2, 1)
3092    FIELD(L1_TXPMA_TM_14, MPHY_TM_TX_ENABLE_DRIVERLDO_OBSRV, 1, 1)
3093    FIELD(L1_TXPMA_TM_14, MPHY_TM_TX_DRIVERLDO_REDC_SINKIQ, 0, 1)
3094REG32(L1_TXPMA_TM_15, 0x483c)
3095    FIELD(L1_TXPMA_TM_15, TXPMA_TM_15_31_8_RSVD, 24, 8)
3096    FIELD(L1_TXPMA_TM_15, PIPE_TM_TX_ANABOOST_PROG_7_0, 0, 8)
3097REG32(L1_TXPMA_TM_16, 0x4840)
3098    FIELD(L1_TXPMA_TM_16, TXPMA_TM_16_31_8_RSVD, 24, 8)
3099    FIELD(L1_TXPMA_TM_16, PIPE_TM_TX_ANABOOST_PROG_15_8, 0, 8)
3100REG32(L1_TXPMA_TM_17, 0x4844)
3101    FIELD(L1_TXPMA_TM_17, TXPMA_TM_17_31_8_RSVD, 24, 8)
3102    FIELD(L1_TXPMA_TM_17, TM_TX_RSVD2, 0, 8)
3103REG32(L1_TXPMA_TM_18, 0x4848)
3104    FIELD(L1_TXPMA_TM_18, TXPMA_TM_18_31_8_RSVD, 24, 8)
3105    FIELD(L1_TXPMA_TM_18, TM_TX_ENABLE_VDDREF_CORE, 7, 1)
3106    FIELD(L1_TXPMA_TM_18, TM_FORCE_TX_ENABLE_VDDREF_CORE, 6, 1)
3107    FIELD(L1_TXPMA_TM_18, TM_TX_ENABLE_RBYRFB_CORE, 5, 1)
3108    FIELD(L1_TXPMA_TM_18, TM_FORCE_TX_ENABLE_RBYRFB_CORE, 4, 1)
3109    FIELD(L1_TXPMA_TM_18, TM_TX_ENABLE_BGREF_CORE, 3, 1)
3110    FIELD(L1_TXPMA_TM_18, TM_FORCE_TX_ENABLE_BGREF_CORE, 2, 1)
3111    FIELD(L1_TXPMA_TM_18, TM_TX_ENABLE_BGFB_CORE, 1, 1)
3112    FIELD(L1_TXPMA_TM_18, TM_FORCE_TX_ENABLE_BGFB_CORE, 0, 1)
3113REG32(L1_TXPMA_TM_19, 0x484c)
3114    FIELD(L1_TXPMA_TM_19, TXPMA_TM_19_31_8_RSVD, 24, 8)
3115    FIELD(L1_TXPMA_TM_19, ANA_SATA_BYP0_RSVD, 6, 2)
3116    FIELD(L1_TXPMA_TM_19, TM_ZDIF_TX_SATA_OFFSET, 0, 6)
3117REG32(L1_TXPMA_TM_20, 0x4850)
3118    FIELD(L1_TXPMA_TM_20, TXPMA_TM_20_31_8_RSVD, 24, 8)
3119    FIELD(L1_TXPMA_TM_20, TM_TX_ELEC_IDLE_DELAY_ENTRY, 0, 8)
3120REG32(L1_TXPMA_TM_21, 0x4854)
3121    FIELD(L1_TXPMA_TM_21, TXPMA_TM_21_31_8_RSVD, 24, 8)
3122    FIELD(L1_TXPMA_TM_21, TM_TX_ELEC_IDLE_DELAY_EXIT, 0, 8)
3123REG32(L1_TXPMA_TM_22, 0x4858)
3124    FIELD(L1_TXPMA_TM_22, TXPMA_TM_22_31_8_RSVD, 24, 8)
3125    FIELD(L1_TXPMA_TM_22, TM_TX_ENABLE_LFPS_DELAY_ENTRY, 0, 8)
3126REG32(L1_TXPMA_TM_23, 0x485c)
3127    FIELD(L1_TXPMA_TM_23, TXPMA_TM_23_31_8_RSVD, 24, 8)
3128    FIELD(L1_TXPMA_TM_23, TM_TX_ENABLE_LFPS_DELAY_EXIT, 0, 8)
3129REG32(L1_TXPMA_TM_24, 0x4860)
3130    FIELD(L1_TXPMA_TM_24, TXPMA_TM_24_31_8_RSVD, 24, 8)
3131    FIELD(L1_TXPMA_TM_24, ANA_MISC6_7_RSVD, 7, 1)
3132    FIELD(L1_TXPMA_TM_24, TM_TX_EN_ANA_SUBLP_MODE, 6, 1)
3133    FIELD(L1_TXPMA_TM_24, TM_FORCE_TX_EN_ANA_SUBLP_MODE, 5, 1)
3134    FIELD(L1_TXPMA_TM_24, TM_TX_EN_DIG_SUBLP_MODE, 4, 1)
3135    FIELD(L1_TXPMA_TM_24, TM_FORCE_TX_EN_DIG_SUBLP_MODE, 3, 1)
3136    FIELD(L1_TXPMA_TM_24, TM_TX_DP_LVLDB0_OVRRD, 2, 1)
3137    FIELD(L1_TXPMA_TM_24, TM_FORCE_TX_DP_LVLDB0_OVRRD, 1, 1)
3138    FIELD(L1_TXPMA_TM_24, TM_TX_CLOCK_STOP_REQ, 0, 1)
3139REG32(L1_TXPMA_TM_25, 0x4864)
3140    FIELD(L1_TXPMA_TM_25, TXPMA_TM_25_31_8_RSVD, 24, 8)
3141    FIELD(L1_TXPMA_TM_25, ANA_MISC6_7_6_RSVD, 6, 2)
3142    FIELD(L1_TXPMA_TM_25, TM_TX_WRRD_SYNC_SUP_OBSRV_PLL, 5, 1)
3143    FIELD(L1_TXPMA_TM_25, TM_TX_WRRD_SYNC_SUP_OBSRV_RX, 4, 1)
3144    FIELD(L1_TXPMA_TM_25, TM_TX_LANE_LNG, 3, 1)
3145    FIELD(L1_TXPMA_TM_25, TM_FORCE_TX_LANE_LNG, 2, 1)
3146    FIELD(L1_TXPMA_TM_25, TM_TX_LANE_MASTER, 1, 1)
3147    FIELD(L1_TXPMA_TM_25, TM_FORCE_TX_LANE_MASTER, 0, 1)
3148REG32(L1_TXPMA_TM_26, 0x4868)
3149    FIELD(L1_TXPMA_TM_26, TXPMA_TM_26_31_8_RSVD, 24, 8)
3150    FIELD(L1_TXPMA_TM_26, TM_TXPMD_APB_RESET_DELAY, 0, 8)
3151REG32(L1_TXPMA_TM_27, 0x486c)
3152    FIELD(L1_TXPMA_TM_27, TXPMA_TM_27_31_8_RSVD, 24, 8)
3153    FIELD(L1_TXPMA_TM_27, TM_BSCAN_MODE_EN, 7, 1)
3154    FIELD(L1_TXPMA_TM_27, TM_FORCE_BSCAN_MODE_EN, 6, 1)
3155    FIELD(L1_TXPMA_TM_27, TM_PIPE_TX_FAST_EST_COMMON_MODE, 5, 1)
3156    FIELD(L1_TXPMA_TM_27, TM_FORCE_PIPE_TX_FAST_EST_COMMON_MODE, 4, 1)
3157    FIELD(L1_TXPMA_TM_27, TM_TX_PIPE_TX_ENABLE_LFPS, 3, 1)
3158    FIELD(L1_TXPMA_TM_27, TM_FORCE_TX_PIPE_TX_ENABLE_LFPS, 2, 1)
3159    FIELD(L1_TXPMA_TM_27, TM_TX_PIPE_TX_ENABLE_IDLE_MODE, 1, 1)
3160    FIELD(L1_TXPMA_TM_27, TM_FORCE_TX_PIPE_TX_ENABLE_IDLE_MODE, 0, 1)
3161REG32(L1_TXPMA_ST_0, 0x4b00)
3162    FIELD(L1_TXPMA_ST_0, TXPMA_ST_0_31_8_RSVD, 24, 8)
3163    FIELD(L1_TXPMA_ST_0, TX_PHY_MODE, 4, 4)
3164    FIELD(L1_TXPMA_ST_0, TX_PHY_GEAR, 0, 4)
3165REG32(L1_TXPMA_ST_1, 0x4b04)
3166    FIELD(L1_TXPMA_ST_1, TXPMA_ST_1_31_8_RSVD, 24, 8)
3167    FIELD(L1_TXPMA_ST_1, TX_ENABLE_HSCLK_DIVISION, 6, 2)
3168    FIELD(L1_TXPMA_ST_1, PIPE_TX_TRISTATE, 5, 1)
3169    FIELD(L1_TXPMA_ST_1, TX_ENABLE_SUPPLY_SERIALIZER, 4, 1)
3170    FIELD(L1_TXPMA_ST_1, TX_ENABLE_SUPPLY_HSCLK, 3, 1)
3171    FIELD(L1_TXPMA_ST_1, TX_ENABLE_SUPPLY_MPHY, 2, 1)
3172    FIELD(L1_TXPMA_ST_1, TX_ENABLE_SUPPLY_PIPE, 1, 1)
3173    FIELD(L1_TXPMA_ST_1, TX_ENABLE_SUPPLY_UPHY, 0, 1)
3174REG32(L1_TXPMA_ST_2, 0x4b08)
3175    FIELD(L1_TXPMA_ST_2, TXPMA_ST_2_31_8_RSVD, 24, 8)
3176    FIELD(L1_TXPMA_ST_2, ANA_ST2_7_5_SPARE, 5, 3)
3177    FIELD(L1_TXPMA_ST_2, PIPE_TX_ENABLE_RXDET, 4, 1)
3178    FIELD(L1_TXPMA_ST_2, PIPE_TX_ENABLE_IDLE_MODE, 2, 2)
3179    FIELD(L1_TXPMA_ST_2, PIPE_TX_ENABLE_LFPS, 0, 2)
3180REG32(L1_TXPMA_ST_3, 0x4b0c)
3181    FIELD(L1_TXPMA_ST_3, TXPMA_ST_3_31_8_RSVD, 24, 8)
3182    FIELD(L1_TXPMA_ST_3, ANA_ST3_7_6_SPARE, 6, 2)
3183    FIELD(L1_TXPMA_ST_3, TX_LSEG_DN_RESCAL_CODE, 0, 6)
3184REG32(L1_TXPMA_ST_4, 0x4b10)
3185    FIELD(L1_TXPMA_ST_4, TXPMA_ST_4_31_8_RSVD, 24, 8)
3186    FIELD(L1_TXPMA_ST_4, ANA_ST4_7_6_SPARE, 6, 2)
3187    FIELD(L1_TXPMA_ST_4, TX_USEG_DP_RESCAL_CODE, 0, 6)
3188REG32(L1_TXPMA_ST_5, 0x4b14)
3189    FIELD(L1_TXPMA_ST_5, TXPMA_ST_5_31_8_RSVD, 24, 8)
3190    FIELD(L1_TXPMA_ST_5, ANA_ST5_7_6_SPARE, 6, 2)
3191    FIELD(L1_TXPMA_ST_5, PIPE_TX_LOCALFS, 0, 6)
3192REG32(L1_TXPMA_ST_6, 0x4b18)
3193    FIELD(L1_TXPMA_ST_6, TXPMA_ST_6_31_8_RSVD, 24, 8)
3194    FIELD(L1_TXPMA_ST_6, ANA_ST6_7_SPARE, 7, 1)
3195    FIELD(L1_TXPMA_ST_6, PIPE_TX_LOCALTXCOEFFICIENTSVALID, 6, 1)
3196    FIELD(L1_TXPMA_ST_6, PIPE_TX_LOCALLF, 0, 6)
3197REG32(L1_TXPMA_ST_7, 0x4b1c)
3198    FIELD(L1_TXPMA_ST_7, TXPMA_ST_7_31_8_RSVD, 24, 8)
3199    FIELD(L1_TXPMA_ST_7, PIPE_TX_LOCALTXPRESETCOEFFICIENTS_7_0, 0, 8)
3200REG32(L1_TXPMA_ST_8, 0x4b20)
3201    FIELD(L1_TXPMA_ST_8, TXPMA_ST_8_31_8_RSVD, 24, 8)
3202    FIELD(L1_TXPMA_ST_8, PIPE_TX_LOCALTXPRESETCOEFFICIENTS_15_8, 0, 8)
3203REG32(L1_TXPMA_ST_9, 0x4b24)
3204    FIELD(L1_TXPMA_ST_9, TXPMA_ST_9_31_8_RSVD, 24, 8)
3205    FIELD(L1_TXPMA_ST_9, ANA_ST9_7_2_SPARE, 2, 6)
3206    FIELD(L1_TXPMA_ST_9, PIPE_TX_LOCALTXPRESETCOEFFICIENTS_17_16, 0, 2)
3207REG32(L1_TXPMD_TM_0, 0x4c00)
3208    FIELD(L1_TXPMD_TM_0, TXPMD_TM_0_31_8_RSVD, 24, 8)
3209    FIELD(L1_TXPMD_TM_0, PIPE_TM_TX_USEG_POST_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
3210    FIELD(L1_TXPMD_TM_0, PIPE_TM_TX_USEG_POST_DISABLE_ENDPOS, 0, 5)
3211REG32(L1_TXPMD_TM_1, 0x4c04)
3212    FIELD(L1_TXPMD_TM_1, TXPMD_TM_1_31_8_RSVD, 24, 8)
3213    FIELD(L1_TXPMD_TM_1, PIPE_TM_TX_USEG_POST_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
3214    FIELD(L1_TXPMD_TM_1, PIPE_TM_TX_USEG_POST_DISABLE_STARTPOS, 0, 5)
3215REG32(L1_TXPMD_TM_2, 0x4c08)
3216    FIELD(L1_TXPMD_TM_2, TXPMD_TM_2_31_8_RSVD, 24, 8)
3217    FIELD(L1_TXPMD_TM_2, PIPE_TM_TX_USEG_POST_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
3218    FIELD(L1_TXPMD_TM_2, PIPE_TM_TX_USEG_POST_EMPHASIS_ENDPOS, 0, 5)
3219REG32(L1_TXPMD_TM_3, 0x4c0c)
3220    FIELD(L1_TXPMD_TM_3, TXPMD_TM_3_31_8_RSVD, 24, 8)
3221    FIELD(L1_TXPMD_TM_3, PIPE_TM_TX_USEG_POST_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
3222    FIELD(L1_TXPMD_TM_3, PIPE_TM_TX_USEG_POST_EMPHASIS_STARTPOS, 0, 5)
3223REG32(L1_TXPMD_TM_4, 0x4c10)
3224    FIELD(L1_TXPMD_TM_4, TXPMD_TM_4_31_8_RSVD, 24, 8)
3225    FIELD(L1_TXPMD_TM_4, PIPE_TM_TX_USEG_POST_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
3226    FIELD(L1_TXPMD_TM_4, PIPE_TM_TX_USEG_POST_MAINSEL_ENDPOS, 0, 5)
3227REG32(L1_TXPMD_TM_5, 0x4c14)
3228    FIELD(L1_TXPMD_TM_5, TXPMD_TM_5_31_8_RSVD, 24, 8)
3229    FIELD(L1_TXPMD_TM_5, PIPE_TM_TX_USEG_POST_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
3230    FIELD(L1_TXPMD_TM_5, PIPE_TM_TX_USEG_POST_MAINSEL_STARTPOS, 0, 5)
3231REG32(L1_TXPMD_TM_6, 0x4c18)
3232    FIELD(L1_TXPMD_TM_6, TXPMD_TM_6_31_8_RSVD, 24, 8)
3233    FIELD(L1_TXPMD_TM_6, PIPE_TM_TX_USEG_POST_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
3234    FIELD(L1_TXPMD_TM_6, PIPE_TM_TX_USEG_POST_MARGIN_ENDPOS, 0, 5)
3235REG32(L1_TXPMD_TM_7, 0x4c1c)
3236    FIELD(L1_TXPMD_TM_7, TXPMD_TM_7_31_8_RSVD, 24, 8)
3237    FIELD(L1_TXPMD_TM_7, PIPE_TM_TX_USEG_POST_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
3238    FIELD(L1_TXPMD_TM_7, PIPE_TM_TX_USEG_POST_MARGIN_STARTPOS, 0, 5)
3239REG32(L1_TXPMD_TM_8, 0x4c20)
3240    FIELD(L1_TXPMD_TM_8, TXPMD_TM_8_31_8_RSVD, 24, 8)
3241    FIELD(L1_TXPMD_TM_8, PIPE_TM_TX_USEG_PRE_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
3242    FIELD(L1_TXPMD_TM_8, PIPE_TM_TX_USEG_PRE_DISABLE_ENDPOS, 0, 5)
3243REG32(L1_TXPMD_TM_9, 0x4c24)
3244    FIELD(L1_TXPMD_TM_9, TXPMD_TM_9_31_8_RSVD, 24, 8)
3245    FIELD(L1_TXPMD_TM_9, PIPE_TM_TX_USEG_PRE_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
3246    FIELD(L1_TXPMD_TM_9, PIPE_TM_TX_USEG_PRE_DISABLE_STARTPOS, 0, 5)
3247REG32(L1_TXPMD_TM_10, 0x4c28)
3248    FIELD(L1_TXPMD_TM_10, TXPMD_TM_10_31_8_RSVD, 24, 8)
3249    FIELD(L1_TXPMD_TM_10, PIPE_TM_TX_USEG_PRE_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
3250    FIELD(L1_TXPMD_TM_10, PIPE_TM_TX_USEG_PRE_EMPHASIS_ENDPOS, 0, 5)
3251REG32(L1_TXPMD_TM_11, 0x4c2c)
3252    FIELD(L1_TXPMD_TM_11, TXPMD_TM_11_31_8_RSVD, 24, 8)
3253    FIELD(L1_TXPMD_TM_11, PIPE_TM_TX_USEG_PRE_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
3254    FIELD(L1_TXPMD_TM_11, PIPE_TM_TX_USEG_PRE_EMPHASIS_STARTPOS, 0, 5)
3255REG32(L1_TXPMD_TM_12, 0x4c30)
3256    FIELD(L1_TXPMD_TM_12, TXPMD_TM_12_31_8_RSVD, 24, 8)
3257    FIELD(L1_TXPMD_TM_12, PIPE_TM_TX_USEG_PRE_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
3258    FIELD(L1_TXPMD_TM_12, PIPE_TM_TX_USEG_PRE_MAINSEL_ENDPOS, 0, 5)
3259REG32(L1_TXPMD_TM_13, 0x4c34)
3260    FIELD(L1_TXPMD_TM_13, TXPMD_TM_13_31_8_RSVD, 24, 8)
3261    FIELD(L1_TXPMD_TM_13, PIPE_TM_TX_USEG_PRE_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
3262    FIELD(L1_TXPMD_TM_13, PIPE_TM_TX_USEG_PRE_MAINSEL_STARTPOS, 0, 5)
3263REG32(L1_TXPMD_TM_14, 0x4c38)
3264    FIELD(L1_TXPMD_TM_14, TXPMD_TM_14_31_8_RSVD, 24, 8)
3265    FIELD(L1_TXPMD_TM_14, PIPE_TM_TX_USEG_PRE_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
3266    FIELD(L1_TXPMD_TM_14, PIPE_TM_TX_USEG_PRE_MARGIN_ENDPOS, 0, 5)
3267REG32(L1_TXPMD_TM_15, 0x4c3c)
3268    FIELD(L1_TXPMD_TM_15, TXPMD_TM_15_31_8_RSVD, 24, 8)
3269    FIELD(L1_TXPMD_TM_15, PIPE_TM_TX_USEG_PRE_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
3270    FIELD(L1_TXPMD_TM_15, PIPE_TM_TX_USEG_PRE_MARGIN_STARTPOS, 0, 5)
3271REG32(L1_TXPMD_TM_16, 0x4c40)
3272    FIELD(L1_TXPMD_TM_16, TXPMD_TM_16_31_8_RSVD, 24, 8)
3273    FIELD(L1_TXPMD_TM_16, PIPE_TM_TX_LSEG_POST_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
3274    FIELD(L1_TXPMD_TM_16, PIPE_TM_TX_LSEG_POST_DISABLE_ENDPOS, 0, 5)
3275REG32(L1_TXPMD_TM_17, 0x4c44)
3276    FIELD(L1_TXPMD_TM_17, TXPMD_TM_17_31_8_RSVD, 24, 8)
3277    FIELD(L1_TXPMD_TM_17, PIPE_TM_TX_LSEG_POST_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
3278    FIELD(L1_TXPMD_TM_17, PIPE_TM_TX_LSEG_POST_DISABLE_STARTPOS, 0, 5)
3279REG32(L1_TXPMD_TM_18, 0x4c48)
3280    FIELD(L1_TXPMD_TM_18, TXPMD_TM_18_31_8_RSVD, 24, 8)
3281    FIELD(L1_TXPMD_TM_18, PIPE_TM_TX_LSEG_POST_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
3282    FIELD(L1_TXPMD_TM_18, PIPE_TM_TX_LSEG_POST_EMPHASIS_ENDPOS, 0, 5)
3283REG32(L1_TXPMD_TM_19, 0x4c4c)
3284    FIELD(L1_TXPMD_TM_19, TXPMD_TM_19_31_8_RSVD, 24, 8)
3285    FIELD(L1_TXPMD_TM_19, PIPE_TM_TX_LSEG_POST_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
3286    FIELD(L1_TXPMD_TM_19, PIPE_TM_TX_LSEG_POST_EMPHASIS_STARTPOS, 0, 5)
3287REG32(L1_TXPMD_TM_20, 0x4c50)
3288    FIELD(L1_TXPMD_TM_20, TXPMD_TM_20_31_8_RSVD, 24, 8)
3289    FIELD(L1_TXPMD_TM_20, PIPE_TM_TX_LSEG_POST_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
3290    FIELD(L1_TXPMD_TM_20, PIPE_TM_TX_LSEG_POST_MAINSEL_ENDPOS, 0, 5)
3291REG32(L1_TXPMD_TM_21, 0x4c54)
3292    FIELD(L1_TXPMD_TM_21, TXPMD_TM_21_31_8_RSVD, 24, 8)
3293    FIELD(L1_TXPMD_TM_21, PIPE_TM_TX_LSEG_POST_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
3294    FIELD(L1_TXPMD_TM_21, PIPE_TM_TX_LSEG_POST_MAINSEL_STARTPOS, 0, 5)
3295REG32(L1_TXPMD_TM_22, 0x4c58)
3296    FIELD(L1_TXPMD_TM_22, TXPMD_TM_22_31_8_RSVD, 24, 8)
3297    FIELD(L1_TXPMD_TM_22, PIPE_TM_TX_LSEG_POST_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
3298    FIELD(L1_TXPMD_TM_22, PIPE_TM_TX_LSEG_POST_MARGIN_ENDPOS, 0, 5)
3299REG32(L1_TXPMD_TM_23, 0x4c5c)
3300    FIELD(L1_TXPMD_TM_23, TXPMD_TM_23_31_8_RSVD, 24, 8)
3301    FIELD(L1_TXPMD_TM_23, PIPE_TM_TX_LSEG_POST_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
3302    FIELD(L1_TXPMD_TM_23, PIPE_TM_TX_LSEG_POST_MARGIN_STARTPOS, 0, 5)
3303REG32(L1_TXPMD_TM_24, 0x4c60)
3304    FIELD(L1_TXPMD_TM_24, TXPMD_TM_24_31_8_RSVD, 24, 8)
3305    FIELD(L1_TXPMD_TM_24, PIPE_TM_TX_LSEG_PRE_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
3306    FIELD(L1_TXPMD_TM_24, PIPE_TM_TX_LSEG_PRE_DISABLE_ENDPOS, 0, 5)
3307REG32(L1_TXPMD_TM_25, 0x4c64)
3308    FIELD(L1_TXPMD_TM_25, TXPMD_TM_25_31_8_RSVD, 24, 8)
3309    FIELD(L1_TXPMD_TM_25, PIPE_TM_TX_LSEG_PRE_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
3310    FIELD(L1_TXPMD_TM_25, PIPE_TM_TX_LSEG_PRE_DISABLE_STARTPOS, 0, 5)
3311REG32(L1_TXPMD_TM_26, 0x4c68)
3312    FIELD(L1_TXPMD_TM_26, TXPMD_TM_26_31_8_RSVD, 24, 8)
3313    FIELD(L1_TXPMD_TM_26, PIPE_TM_TX_LSEG_PRE_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
3314    FIELD(L1_TXPMD_TM_26, PIPE_TM_TX_LSEG_PRE_EMPHASIS_ENDPOS, 0, 5)
3315REG32(L1_TXPMD_TM_27, 0x4c6c)
3316    FIELD(L1_TXPMD_TM_27, TXPMD_TM_27_31_8_RSVD, 24, 8)
3317    FIELD(L1_TXPMD_TM_27, PIPE_TM_TX_LSEG_PRE_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
3318    FIELD(L1_TXPMD_TM_27, PIPE_TM_TX_LSEG_PRE_EMPHASIS_STARTPOS, 0, 5)
3319REG32(L1_TXPMD_TM_28, 0x4c70)
3320    FIELD(L1_TXPMD_TM_28, TXPMD_TM_28_31_8_RSVD, 24, 8)
3321    FIELD(L1_TXPMD_TM_28, PIPE_TM_TX_LSEG_PRE_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
3322    FIELD(L1_TXPMD_TM_28, PIPE_TM_TX_LSEG_PRE_MAINSEL_ENDPOS, 0, 5)
3323REG32(L1_TXPMD_TM_29, 0x4c74)
3324    FIELD(L1_TXPMD_TM_29, TXPMD_TM_29_31_8_RSVD, 24, 8)
3325    FIELD(L1_TXPMD_TM_29, PIPE_TM_TX_LSEG_PRE_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
3326    FIELD(L1_TXPMD_TM_29, PIPE_TM_TX_LSEG_PRE_MAINSEL_STARTPOS, 0, 5)
3327REG32(L1_TXPMD_TM_30, 0x4c78)
3328    FIELD(L1_TXPMD_TM_30, TXPMD_TM_30_31_8_RSVD, 24, 8)
3329    FIELD(L1_TXPMD_TM_30, PIPE_TM_TX_LSEG_PRE_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
3330    FIELD(L1_TXPMD_TM_30, PIPE_TM_TX_LSEG_PRE_MARGIN_ENDPOS, 0, 5)
3331REG32(L1_TXPMD_TM_31, 0x4c7c)
3332    FIELD(L1_TXPMD_TM_31, TXPMD_TM_31_31_8_RSVD, 24, 8)
3333    FIELD(L1_TXPMD_TM_31, PIPE_TM_TX_LSEG_PRE_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
3334    FIELD(L1_TXPMD_TM_31, PIPE_TM_TX_LSEG_PRE_MARGIN_STARTPOS, 0, 5)
3335REG32(L1_TXPMD_TM_32, 0x4c80)
3336    FIELD(L1_TXPMD_TM_32, TXPMD_TM_32_31_8_RSVD, 24, 8)
3337    FIELD(L1_TXPMD_TM_32, PIPE_TM_TX_PRE_FS_DIVISION_COEF_7_0, 0, 8)
3338REG32(L1_TXPMD_TM_33, 0x4c84)
3339    FIELD(L1_TXPMD_TM_33, TXPMD_TM_33_31_8_RSVD, 24, 8)
3340    FIELD(L1_TXPMD_TM_33, PIPE_TM_TX_PRE_FS_DIVISION_COEF_15_8, 0, 8)
3341REG32(L1_TXPMD_TM_34, 0x4c88)
3342    FIELD(L1_TXPMD_TM_34, TXPMD_TM_34_31_8_RSVD, 24, 8)
3343    FIELD(L1_TXPMD_TM_34, PIPE_TM_TX_MAIN_FS_DIVISION_COEF_7_0, 0, 8)
3344REG32(L1_TXPMD_TM_35, 0x4c8c)
3345    FIELD(L1_TXPMD_TM_35, TXPMD_TM_35_31_8_RSVD, 24, 8)
3346    FIELD(L1_TXPMD_TM_35, PIPE_TM_TX_MAIN_FS_DIVISION_COEF_15_8, 0, 8)
3347REG32(L1_TXPMD_TM_36, 0x4c90)
3348    FIELD(L1_TXPMD_TM_36, TXPMD_TM_36_31_8_RSVD, 24, 8)
3349    FIELD(L1_TXPMD_TM_36, PIPE_TM_TX_POST_FS_DIVISION_COEF_7_0, 0, 8)
3350REG32(L1_TXPMD_TM_37, 0x4c94)
3351    FIELD(L1_TXPMD_TM_37, TXPMD_TM_37_31_8_RSVD, 24, 8)
3352    FIELD(L1_TXPMD_TM_37, PIPE_TM_TX_POST_FS_DIVISION_COEF_15_8, 0, 8)
3353REG32(L1_TXPMD_TM_38, 0x4c98)
3354    FIELD(L1_TXPMD_TM_38, TXPMD_TM_38_31_8_RSVD, 24, 8)
3355    FIELD(L1_TXPMD_TM_38, ANA_MISC0_7_RSVD, 7, 1)
3356    FIELD(L1_TXPMD_TM_38, PIPE_TM_TX_ENABLE_SWNW_CNTRL_BYP, 6, 1)
3357    FIELD(L1_TXPMD_TM_38, PIPE_TM_TX_ENABLE_TRISTATE_BYP, 5, 1)
3358    FIELD(L1_TXPMD_TM_38, PIPE_TM_TX_TRISTATE, 4, 1)
3359    FIELD(L1_TXPMD_TM_38, TM_TX_DRIVERLDO_RXDET_BYP, 3, 1)
3360    FIELD(L1_TXPMD_TM_38, TM_TX_DRIVERLDO_IDLE_BYP, 2, 1)
3361    FIELD(L1_TXPMD_TM_38, TM_TX_DRIVERLDO_EN_RXDET_BYP, 1, 1)
3362    FIELD(L1_TXPMD_TM_38, TM_TX_DRIVERLDO_EN_IDLE_BYP, 0, 1)
3363REG32(L1_TXPMD_TM_39, 0x4c9c)
3364    FIELD(L1_TXPMD_TM_39, TXPMD_TM_39_31_8_RSVD, 24, 8)
3365    FIELD(L1_TXPMD_TM_39, ANA_MPHY_BYP0_7_3_RSVD, 3, 5)
3366    FIELD(L1_TXPMD_TM_39, MPHY_TM_TX_OVRD_DEEMPH_TRIM, 2, 1)
3367    FIELD(L1_TXPMD_TM_39, MPHY_TM_TX_ENABLE_DEEMPH, 1, 1)
3368    FIELD(L1_TXPMD_TM_39, MPHY_TM_TX_OVRD_ENABLE_DEEMPH, 0, 1)
3369REG32(L1_TXPMD_TM_40, 0x4ca0)
3370    FIELD(L1_TXPMD_TM_40, TXPMD_TM_40_31_8_RSVD, 24, 8)
3371    FIELD(L1_TXPMD_TM_40, MPHY_TM_TX_DEEMPH_TRIM_7_0, 0, 8)
3372REG32(L1_TXPMD_TM_41, 0x4ca4)
3373    FIELD(L1_TXPMD_TM_41, TXPMD_TM_41_31_8_RSVD, 24, 8)
3374    FIELD(L1_TXPMD_TM_41, MPHY_TM_TX_DEEMPH_TRIM_15_8, 0, 8)
3375REG32(L1_TXPMD_TM_42, 0x4ca8)
3376    FIELD(L1_TXPMD_TM_42, TXPMD_TM_42_31_8_RSVD, 24, 8)
3377    FIELD(L1_TXPMD_TM_42, ANA_MPHY_BYP3_7_5_RSVD, 5, 3)
3378    FIELD(L1_TXPMD_TM_42, MPHY_TM_TX_OVRD_LS_DATA, 1, 4)
3379    FIELD(L1_TXPMD_TM_42, MPHY_TM_TX_ENABLE_OVRD_LS_DATA, 0, 1)
3380REG32(L1_TXPMD_TM_43, 0x4cac)
3381    FIELD(L1_TXPMD_TM_43, TXPMD_TM_43_31_8_RSVD, 24, 8)
3382    FIELD(L1_TXPMD_TM_43, ANA_MPHY_BYP4_7_4_RSVD, 4, 4)
3383    FIELD(L1_TXPMD_TM_43, MPHY_TM_TX_OVRD_LS_DATA_BAR, 0, 4)
3384REG32(L1_TXPMD_TM_44, 0x4cb0)
3385    FIELD(L1_TXPMD_TM_44, TXPMD_TM_44_31_8_RSVD, 24, 8)
3386    FIELD(L1_TXPMD_TM_44, ANA_PIPE_BYP38_7_6_RSVD, 6, 2)
3387    FIELD(L1_TXPMD_TM_44, PIPE_TM_TX_EN_PRE_LFPS_PATH, 5, 1)
3388    FIELD(L1_TXPMD_TM_44, PIPE_TM_TX_OVRD_EN_PRE_LFPS_PATH, 4, 1)
3389    FIELD(L1_TXPMD_TM_44, PIPE_TM_TX_EN_POST_LFPS_PATH, 3, 1)
3390    FIELD(L1_TXPMD_TM_44, PIPE_TM_TX_OVRD_EN_POST_LFPS_PATH, 2, 1)
3391    FIELD(L1_TXPMD_TM_44, PIPE_TM_TX_EN_MAIN_LFPS_PATH, 1, 1)
3392    FIELD(L1_TXPMD_TM_44, PIPE_TM_TX_OVRD_EN_MAIN_LFPS_PATH, 0, 1)
3393REG32(L1_TXPMD_TM_45, 0x4cb4)
3394    FIELD(L1_TXPMD_TM_45, TXPMD_TM_45_31_8_RSVD, 24, 8)
3395    FIELD(L1_TXPMD_TM_45, ANA_DP_BYP0_7_6_RSVD, 6, 2)
3396    FIELD(L1_TXPMD_TM_45, DP_TM_TX_DP_ENABLE_POST2_PATH, 5, 1)
3397    FIELD(L1_TXPMD_TM_45, DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH, 4, 1)
3398    FIELD(L1_TXPMD_TM_45, DP_TM_TX_DP_ENABLE_POST1_PATH, 3, 1)
3399    FIELD(L1_TXPMD_TM_45, DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH, 2, 1)
3400    FIELD(L1_TXPMD_TM_45, DP_TM_TX_DP_ENABLE_MAIN_PATH, 1, 1)
3401    FIELD(L1_TXPMD_TM_45, DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH, 0, 1)
3402REG32(L1_TXPMD_TM_46, 0x4cb8)
3403    FIELD(L1_TXPMD_TM_46, TXPMD_TM_46_31_8_RSVD, 24, 8)
3404    FIELD(L1_TXPMD_TM_46, ANA_PIPE_BYP39_7_6_RSVD, 6, 2)
3405    FIELD(L1_TXPMD_TM_46, PIPE_TM_TX_PIPE_ENABLE_PRE_PATH, 5, 1)
3406    FIELD(L1_TXPMD_TM_46, PIPE_TM_TX_OVRD_PIPE_ENABLE_PRE_PATH, 4, 1)
3407    FIELD(L1_TXPMD_TM_46, PIPE_TM_TX_PIPE_ENABLE_POST_PATH, 3, 1)
3408    FIELD(L1_TXPMD_TM_46, PIPE_TM_TX_OVRD_PIPE_ENABLE_POST_PATH, 2, 1)
3409    FIELD(L1_TXPMD_TM_46, PIPE_TM_TX_PIPE_ENABLE_MAIN_PATH, 1, 1)
3410    FIELD(L1_TXPMD_TM_46, PIPE_TM_TX_OVRD_PIPE_ENABLE_MAIN_PATH, 0, 1)
3411REG32(L1_TXPMD_TM_47, 0x4cbc)
3412    FIELD(L1_TXPMD_TM_47, TXPMD_TM_47_31_8_RSVD, 24, 8)
3413    FIELD(L1_TXPMD_TM_47, TM_TX_RSVD1, 0, 8)
3414REG32(L1_TXPMD_TM_48, 0x4cc0)
3415    FIELD(L1_TXPMD_TM_48, TXPMD_TM_48_31_8_RSVD, 24, 8)
3416    FIELD(L1_TXPMD_TM_48, ANA_MISC2_7_6_RSVD, 6, 2)
3417    FIELD(L1_TXPMD_TM_48, TM_FORCE_RESULTANT_MARGINING_FACTOR, 5, 1)
3418    FIELD(L1_TXPMD_TM_48, TM_RESULTANT_MARGINING_FACTOR, 0, 5)
3419REG32(L1_TM_ANA_BYP_1, 0x5004)
3420    FIELD(L1_TM_ANA_BYP_1, TM_ANA_BYP_1_31_8_RSVD, 24, 8)
3421    FIELD(L1_TM_ANA_BYP_1, MPHY_PWM_DES_PDZ, 7, 1)
3422    FIELD(L1_TM_ANA_BYP_1, FORCE_MPHY_PWM_DES_PDZ, 6, 1)
3423    FIELD(L1_TM_ANA_BYP_1, MPHY_PWMB_SYS_ENABLE, 5, 1)
3424    FIELD(L1_TM_ANA_BYP_1, FORCE_MPHY_PWMB_SYS_ENABLE, 4, 1)
3425    FIELD(L1_TM_ANA_BYP_1, MPHY_PSO_SQUELCH, 3, 1)
3426    FIELD(L1_TM_ANA_BYP_1, FORCE_MPHY_PSO_SQUELCH, 2, 1)
3427    FIELD(L1_TM_ANA_BYP_1, MPHY_PSO_LSRX, 1, 1)
3428    FIELD(L1_TM_ANA_BYP_1, FORCE_MPHY_PSO_LSRX, 0, 1)
3429REG32(L1_TM_ANA_BYP_2, 0x5008)
3430    FIELD(L1_TM_ANA_BYP_2, TM_ANA_BYP_2_31_8_RSVD, 24, 8)
3431    FIELD(L1_TM_ANA_BYP_2, MPHY_PWM_LSPREAMP_PD, 7, 1)
3432    FIELD(L1_TM_ANA_BYP_2, FORCE_MPHY_PWM_LSPREAMP_PD, 6, 1)
3433    FIELD(L1_TM_ANA_BYP_2, MPHY_PWM_GEAR_SEL, 3, 3)
3434    FIELD(L1_TM_ANA_BYP_2, FORCE_MPHY_PWM_GEAR_SEL, 2, 1)
3435    FIELD(L1_TM_ANA_BYP_2, MPHY_PWM_DET_PD, 1, 1)
3436    FIELD(L1_TM_ANA_BYP_2, FORCE_MPHY_PWM_DET_PD, 0, 1)
3437REG32(L1_TM_ANA_BYP_3, 0x500c)
3438    FIELD(L1_TM_ANA_BYP_3, TM_ANA_BYP_3_31_8_RSVD, 24, 8)
3439    FIELD(L1_TM_ANA_BYP_3, MPHY_RX_MASK_BURST_START, 7, 1)
3440    FIELD(L1_TM_ANA_BYP_3, FORCE_MPHY_RX_MASK_BURST_START, 6, 1)
3441    FIELD(L1_TM_ANA_BYP_3, MPHY_RX_GATE_SYMBOL_CLK, 5, 1)
3442    FIELD(L1_TM_ANA_BYP_3, FORCE_MPHY_RX_GATE_SYMBOL_CLK, 4, 1)
3443    FIELD(L1_TM_ANA_BYP_3, MPHY_PWM_PREAMP_BIAS_PD, 3, 1)
3444    FIELD(L1_TM_ANA_BYP_3, FORCE_MPHY_PWM_PREAMP_BIAS_PD, 2, 1)
3445    FIELD(L1_TM_ANA_BYP_3, MPHY_PWM_LSPREAMP_STANDBYSLEEPSTALL, 1, 1)
3446    FIELD(L1_TM_ANA_BYP_3, FORCE_MPHY_PWM_LSPREAMP_STANDBYSLEEPSTAL, 0, 1)
3447REG32(L1_TM_ANA_BYP_4, 0x5010)
3448    FIELD(L1_TM_ANA_BYP_4, TM_ANA_BYP_4_31_8_RSVD, 24, 8)
3449    FIELD(L1_TM_ANA_BYP_4, HSRX_RSTB, 7, 1)
3450    FIELD(L1_TM_ANA_BYP_4, FORCE_HSRX_RSTB, 6, 1)
3451    FIELD(L1_TM_ANA_BYP_4, MPHY_RX_TERM_ENABLE, 5, 1)
3452    FIELD(L1_TM_ANA_BYP_4, FORCE_MPHY_RX_TERM_ENABLE, 4, 1)
3453    FIELD(L1_TM_ANA_BYP_4, MPHY_RX_MUX_TYP1B_TYP2, 3, 1)
3454    FIELD(L1_TM_ANA_BYP_4, FORCE_MPHY_RX_MUX_TYP1B_TYP2, 2, 1)
3455    FIELD(L1_TM_ANA_BYP_4, MPHY_RX_MUX_HSB_LS, 1, 1)
3456    FIELD(L1_TM_ANA_BYP_4, FORCE_MPHY_RX_MUX_HSB_LS, 0, 1)
3457REG32(L1_TM_ANA_BYP_5, 0x5014)
3458    FIELD(L1_TM_ANA_BYP_5, TM_ANA_BYP_5_31_8_RSVD, 24, 8)
3459    FIELD(L1_TM_ANA_BYP_5, MPHY_SQ_SWAP_POLARITY, 5, 1)
3460    FIELD(L1_TM_ANA_BYP_5, FORCE_MPHY_SQ_SWAP_POLARITY, 4, 1)
3461    FIELD(L1_TM_ANA_BYP_5, MPHY_SQ_PD, 3, 1)
3462    FIELD(L1_TM_ANA_BYP_5, FORCE_MPHY_SQ_PD, 2, 1)
3463    FIELD(L1_TM_ANA_BYP_5, MPHY_SQ_DETECTOR_PD, 1, 1)
3464    FIELD(L1_TM_ANA_BYP_5, FORCE_MPHY_SQ_DETECTOR_PD, 0, 1)
3465REG32(L1_TM_ANA_BYP_7, 0x5018)
3466    FIELD(L1_TM_ANA_BYP_7, TM_ANA_BYP_7_31_8_RSVD, 24, 8)
3467    FIELD(L1_TM_ANA_BYP_7, PIPE_RXEQTRAINING, 7, 1)
3468    FIELD(L1_TM_ANA_BYP_7, FORCE_PIPE_RXEQTRAINING, 6, 1)
3469    FIELD(L1_TM_ANA_BYP_7, PIPE_RX_TERM_ENABLE, 5, 1)
3470    FIELD(L1_TM_ANA_BYP_7, FORCE_PIPE_RX_TERM_ENABLE, 4, 1)
3471REG32(L1_TM_ANA_BYP_8, 0x501c)
3472    FIELD(L1_TM_ANA_BYP_8, TM_ANA_BYP_8_31_8_RSVD, 24, 8)
3473    FIELD(L1_TM_ANA_BYP_8, UPHY_BIASGEN_IRCONST_IO_MIRROR_ENABLE, 7, 1)
3474    FIELD(L1_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_IRCONST_IO_MIRROR_ENABLE, 6, 1)
3475    FIELD(L1_TM_ANA_BYP_8, UPHY_BIASGEN_IRCONST_CORE_MIRROR_ENABLE, 5, 1)
3476    FIELD(L1_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_IRCONST_CORE_MIRROR_ENABLE, 4, 1)
3477    FIELD(L1_TM_ANA_BYP_8, UPHY_BIASGEN_ICONST_IO_MIRROR_ENABLE, 3, 1)
3478    FIELD(L1_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_ICONST_IO_MIRROR_ENABLE, 2, 1)
3479    FIELD(L1_TM_ANA_BYP_8, UPHY_BIASGEN_ICONST_CORE_MIRROR_ENABLE, 1, 1)
3480    FIELD(L1_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_ICONST_CORE_MIRROR_ENABLE, 0, 1)
3481REG32(L1_TM_ANA_BYP_9, 0x5020)
3482    FIELD(L1_TM_ANA_BYP_9, TM_ANA_BYP_9_31_8_RSVD, 24, 8)
3483    FIELD(L1_TM_ANA_BYP_9, UPHY_RECLPBK_CLK_DATAZ_ENABLE_CORE, 7, 1)
3484    FIELD(L1_TM_ANA_BYP_9, FORCE_UPHY_RECLPBK_CLK_DATAZ_ENABLE_CORE, 6, 1)
3485    FIELD(L1_TM_ANA_BYP_9, UPHY_PSO_SAMP_LPBK, 5, 1)
3486    FIELD(L1_TM_ANA_BYP_9, FORCE_UPHY_PSO_SAMP_LPBK, 4, 1)
3487    FIELD(L1_TM_ANA_BYP_9, UPHY_EQ_LPBK_ENABLE_CORE, 3, 1)
3488    FIELD(L1_TM_ANA_BYP_9, FORCE_UPHY_EQ_LPBK_ENABLE_CORE, 2, 1)
3489    FIELD(L1_TM_ANA_BYP_9, UPHY_EQ_AC_DCZ_COUPLED_CORE, 1, 1)
3490    FIELD(L1_TM_ANA_BYP_9, FORCE_UPHY_EQ_AC_DCZ_COUPLED_CORE, 0, 1)
3491REG32(L1_TM_ANA_BYP_10, 0x5024)
3492    FIELD(L1_TM_ANA_BYP_10, TM_ANA_BYP_10_31_8_RSVD, 24, 8)
3493    FIELD(L1_TM_ANA_BYP_10, UPHY_LPBK_CLK_DATA_SEL, 5, 1)
3494    FIELD(L1_TM_ANA_BYP_10, UPHY_LPBK_CENTRE_EDGEZ_ENABLE_CORE, 4, 1)
3495    FIELD(L1_TM_ANA_BYP_10, UPHY_HSRX_LPBK_SEL, 1, 3)
3496    FIELD(L1_TM_ANA_BYP_10, FORCE_UPHY_HSRX_LPBK_SEL, 0, 1)
3497REG32(L1_TM_ANA_BYP_11, 0x5028)
3498    FIELD(L1_TM_ANA_BYP_11, TM_ANA_BYP_11_31_8_RSVD, 24, 8)
3499    FIELD(L1_TM_ANA_BYP_11, UPHY_PD_PI_DIV_PATH, 5, 1)
3500    FIELD(L1_TM_ANA_BYP_11, UPHY_PSO_CLK_LANE, 4, 1)
3501    FIELD(L1_TM_ANA_BYP_11, FORCE_UPHY_PSO_CLK_LANE, 3, 1)
3502    FIELD(L1_TM_ANA_BYP_11, UPHY_HSCLK_DIVISION_FACTOR, 1, 2)
3503    FIELD(L1_TM_ANA_BYP_11, FORCE_UPHY_HSCLK_DIVISION_FACTOR, 0, 1)
3504REG32(L1_TM_ANA_BYP_12, 0x502c)
3505    FIELD(L1_TM_ANA_BYP_12, TM_ANA_BYP_12_31_8_RSVD, 24, 8)
3506    FIELD(L1_TM_ANA_BYP_12, UPHY_PSO_HSRXDIG, 7, 1)
3507    FIELD(L1_TM_ANA_BYP_12, FORCE_UPHY_PSO_HSRXDIG, 6, 1)
3508    FIELD(L1_TM_ANA_BYP_12, UPHY_PDN_HS_DES, 5, 1)
3509    FIELD(L1_TM_ANA_BYP_12, FORCE_UPHY_PDN_HS_DES, 4, 1)
3510    FIELD(L1_TM_ANA_BYP_12, UPHY_RST_GF_MUX, 3, 1)
3511    FIELD(L1_TM_ANA_BYP_12, FORCE_UPHY_RST_GF_MUX, 2, 1)
3512    FIELD(L1_TM_ANA_BYP_12, UPHY_ENABLE_CDR, 1, 1)
3513    FIELD(L1_TM_ANA_BYP_12, FORCE_UPHY_ENABLE_CDR, 0, 1)
3514REG32(L1_TM_ANA_BYP_13, 0x5030)
3515    FIELD(L1_TM_ANA_BYP_13, TM_ANA_BYP_13_31_8_RSVD, 24, 8)
3516    FIELD(L1_TM_ANA_BYP_13, UPHY_PSO_SAMP_FLOPS, 1, 1)
3517    FIELD(L1_TM_ANA_BYP_13, FORCE_UPHY_PSO_SAMP_FLOPS, 0, 1)
3518REG32(L1_TM_ANA_BYP_14, 0x5034)
3519    FIELD(L1_TM_ANA_BYP_14, TM_ANA_BYP_14_31_8_RSVD, 24, 8)
3520    FIELD(L1_TM_ANA_BYP_14, UPHY_PSO_EPI, 7, 1)
3521    FIELD(L1_TM_ANA_BYP_14, FORCE_UPHY_PSO_EPI, 6, 1)
3522    FIELD(L1_TM_ANA_BYP_14, UPHY_PD_SAMP_C2C_ECLK, 5, 1)
3523    FIELD(L1_TM_ANA_BYP_14, FORCE_UPHY_PD_SAMP_C2C_ECLK, 4, 1)
3524    FIELD(L1_TM_ANA_BYP_14, UPHY_PSO_IQPI, 1, 1)
3525    FIELD(L1_TM_ANA_BYP_14, FORCE_UPHY_PSO_IQPI, 0, 1)
3526REG32(L1_TM_ANA_BYP_15, 0x5038)
3527    FIELD(L1_TM_ANA_BYP_15, TM_ANA_BYP_15_31_8_RSVD, 24, 8)
3528    FIELD(L1_TM_ANA_BYP_15, UPHY_ENABLE_LOW_LEAKAGE, 7, 1)
3529    FIELD(L1_TM_ANA_BYP_15, FORCE_UPHY_ENABLE_LOW_LEAKAGE, 6, 1)
3530    FIELD(L1_TM_ANA_BYP_15, UPHY_PD_SAMP_C2C, 5, 1)
3531    FIELD(L1_TM_ANA_BYP_15, FORCE_UPHY_PD_SAMP_C2C, 4, 1)
3532    FIELD(L1_TM_ANA_BYP_15, UPHY_PSO_CORE_EQ, 3, 1)
3533    FIELD(L1_TM_ANA_BYP_15, FORCE_UPHY_PSO_CORE_EQ, 2, 1)
3534    FIELD(L1_TM_ANA_BYP_15, UPHY_PSO_IO_EQ, 1, 1)
3535    FIELD(L1_TM_ANA_BYP_15, FORCE_UPHY_PSO_IO_EQ, 0, 1)
3536REG32(L1_TM_ANA_BYP_16, 0x503c)
3537    FIELD(L1_TM_ANA_BYP_16, TM_ANA_BYP_16_31_8_RSVD, 24, 8)
3538    FIELD(L1_TM_ANA_BYP_16, UPHY_PSO_SIGDET, 7, 1)
3539    FIELD(L1_TM_ANA_BYP_16, FORCE_UPHY_PSO_SIGDET, 6, 1)
3540    FIELD(L1_TM_ANA_BYP_16, UPHY_RX_LANE_POLARITY_SWAP, 5, 1)
3541    FIELD(L1_TM_ANA_BYP_16, FORCE_UPHY_RX_LANE_POLARITY_SWAP, 4, 1)
3542    FIELD(L1_TM_ANA_BYP_16, UPHY_RUN_CALIB, 3, 1)
3543    FIELD(L1_TM_ANA_BYP_16, FORCE_UPHY_RUN_CALIB, 2, 1)
3544    FIELD(L1_TM_ANA_BYP_16, UPHY_RESTORE_CALCODE, 1, 1)
3545    FIELD(L1_TM_ANA_BYP_16, FORCE_UPHY_RESTORE_CALCODE, 0, 1)
3546REG32(L1_TM_ANA_BYP_17, 0x5040)
3547    FIELD(L1_TM_ANA_BYP_17, TM_ANA_BYP_17_31_8_RSVD, 24, 8)
3548    FIELD(L1_TM_ANA_BYP_17, UPHY_STARTLOOP_PLL, 6, 1)
3549    FIELD(L1_TM_ANA_BYP_17, FORCE_UPHY_STARTLOOP_PLL, 5, 1)
3550    FIELD(L1_TM_ANA_BYP_17, UPHY_RX_RESCALIB_CODE, 1, 4)
3551    FIELD(L1_TM_ANA_BYP_17, FORCE_UPHY_RX_RESCALIB_CODE, 0, 1)
3552REG32(L1_TM_ANA_BYP_18, 0x5044)
3553    FIELD(L1_TM_ANA_BYP_18, TM_ANA_BYP_18_31_8_RSVD, 24, 8)
3554    FIELD(L1_TM_ANA_BYP_18, FORCE_UPHY_RESTORE_CALCODE_DATA, 3, 1)
3555    FIELD(L1_TM_ANA_BYP_18, FORCE_UPHY_RX_PMA_OPMODE, 2, 1)
3556    FIELD(L1_TM_ANA_BYP_18, UPHY_PSO_LFPSBCN, 1, 1)
3557    FIELD(L1_TM_ANA_BYP_18, FORCE_UPHY_PSO_LFPSBCN, 0, 1)
3558REG32(L1_TM_ANA_BYP_20, 0x5048)
3559    FIELD(L1_TM_ANA_BYP_20, TM_ANA_BYP_20_31_8_RSVD, 24, 8)
3560    FIELD(L1_TM_ANA_BYP_20, UPHY_RX_PMA_OPMODE, 0, 8)
3561REG32(L1_TM_ANA_BYP_21, 0x504c)
3562    FIELD(L1_TM_ANA_BYP_21, TM_ANA_BYP_21_31_8_RSVD, 24, 8)
3563    FIELD(L1_TM_ANA_BYP_21, UPHY_RESTORE_CALCODE_DATA, 0, 8)
3564REG32(L1_TM_ANA_BYP_22, 0x5050)
3565    FIELD(L1_TM_ANA_BYP_22, TM_ANA_BYP_22_31_8_RSVD, 24, 8)
3566    FIELD(L1_TM_ANA_BYP_22, ISO_HSRX_CTRL_BAR, 7, 1)
3567    FIELD(L1_TM_ANA_BYP_22, FORCE_ISO_HSRX_CTRL_BAR, 6, 1)
3568    FIELD(L1_TM_ANA_BYP_22, HSRX_CLOCK_STOP_REQ, 5, 1)
3569    FIELD(L1_TM_ANA_BYP_22, FORCE_HSRX_CLOCK_STOP_REQ, 4, 1)
3570    FIELD(L1_TM_ANA_BYP_22, UPHY_SBRX_RUN_CALIB, 3, 1)
3571    FIELD(L1_TM_ANA_BYP_22, FORCE_UPHY_SBRX_RUN_CALIB, 2, 1)
3572    FIELD(L1_TM_ANA_BYP_22, RXPMA_RSTB, 1, 1)
3573    FIELD(L1_TM_ANA_BYP_22, FORCE_RXPMA_RSTB, 0, 1)
3574REG32(L1_TM_ANA_BYP_23, 0x5054)
3575    FIELD(L1_TM_ANA_BYP_23, TM_ANA_BYP_23_31_8_RSVD, 24, 8)
3576    FIELD(L1_TM_ANA_BYP_23, ISO_SIGDET_CTRL_BAR, 7, 1)
3577    FIELD(L1_TM_ANA_BYP_23, FORCE_ISO_SIGDET_CTRL_BAR, 6, 1)
3578    FIELD(L1_TM_ANA_BYP_23, ISO_LFPS_CTRL_BAR, 5, 1)
3579    FIELD(L1_TM_ANA_BYP_23, FORCE_ISO_LFPS_CTRL_BAR, 4, 1)
3580    FIELD(L1_TM_ANA_BYP_23, ISO_MPHY_LSRX_CTRL_BAR, 3, 1)
3581    FIELD(L1_TM_ANA_BYP_23, FORCE_ISO_MPHY_LSRX_CTRL_BAR, 2, 1)
3582    FIELD(L1_TM_ANA_BYP_23, ISO_MPHY_SQUELCH_CTRL_BAR, 1, 1)
3583    FIELD(L1_TM_ANA_BYP_23, FORCE_ISO_MPHY_SQUELCH_CTRL_BAR, 0, 1)
3584REG32(L1_TM_DIG_1, 0x5058)
3585    FIELD(L1_TM_DIG_1, TM_DIG_1_31_8_RSVD, 24, 8)
3586    FIELD(L1_TM_DIG_1, EN_TXRX_DIFGEAR, 7, 1)
3587    FIELD(L1_TM_DIG_1, MPHY_HS_TERM_PT_SEL, 6, 1)
3588    FIELD(L1_TM_DIG_1, TX_ALLOW_INLNCFG_FROM_TOP, 5, 1)
3589    FIELD(L1_TM_DIG_1, BYPASS_MARKER_DETECTOR, 4, 1)
3590    FIELD(L1_TM_DIG_1, BYPASS_EXIT_VAL, 0, 4)
3591REG32(L1_TM_DIG_2, 0x505c)
3592    FIELD(L1_TM_DIG_2, TM_DIG_2_31_8_RSVD, 24, 8)
3593    FIELD(L1_TM_DIG_2, MPHY_SYM_STATE, 1, 5)
3594    FIELD(L1_TM_DIG_2, FORCE_MPHY_SYM_STATE, 0, 1)
3595REG32(L1_TM_DIG_3, 0x5060)
3596    FIELD(L1_TM_DIG_3, TM_DIG_3_31_8_RSVD, 24, 8)
3597    FIELD(L1_TM_DIG_3, MPHY_SQUELCH_DETECT, 7, 1)
3598    FIELD(L1_TM_DIG_3, FORCE_MPHY_SQUELCH_DETECT, 6, 1)
3599    FIELD(L1_TM_DIG_3, MPHY_CFG_STATE, 1, 5)
3600    FIELD(L1_TM_DIG_3, FORCE_MPHY_CFG_STATE, 0, 1)
3601REG32(L1_TM_DIG_4, 0x5064)
3602    FIELD(L1_TM_DIG_4, TM_DIG_4_31_8_RSVD, 24, 8)
3603    FIELD(L1_TM_DIG_4, STATUS_REG_VAL, 4, 4)
3604    FIELD(L1_TM_DIG_4, READ_SHADOW, 3, 1)
3605REG32(L1_TM_DIG_5, 0x5068)
3606    FIELD(L1_TM_DIG_5, TM_DIG_5_31_8_RSVD, 24, 8)
3607    FIELD(L1_TM_DIG_5, SYMBOL_CLK_ALWAYS_ON_N, 2, 1)
3608    FIELD(L1_TM_DIG_5, BYPASS_DIFN_DETECT, 1, 1)
3609    FIELD(L1_TM_DIG_5, HIBERN8_CTRL, 0, 1)
3610REG32(L1_TM_DIG_6, 0x506c)
3611    FIELD(L1_TM_DIG_6, TM_DIG_6_31_8_RSVD, 24, 8)
3612    FIELD(L1_TM_DIG_6, FORCE_BYPASS_ON_ERR, 6, 1)
3613    FIELD(L1_TM_DIG_6, SUPPRESS_ERR, 5, 1)
3614    FIELD(L1_TM_DIG_6, BYPASS_OHC, 4, 1)
3615    FIELD(L1_TM_DIG_6, BYPASS_DECODER, 3, 1)
3616    FIELD(L1_TM_DIG_6, FORCE_BYPASS_DEC, 2, 1)
3617    FIELD(L1_TM_DIG_6, BYPASS_DESCRAM, 1, 1)
3618    FIELD(L1_TM_DIG_6, FORCE_BYPASS_DESCRAM, 0, 1)
3619REG32(L1_TM_DIG_7, 0x5070)
3620    FIELD(L1_TM_DIG_7, TM_DIG_7_31_8_RSVD, 24, 8)
3621    FIELD(L1_TM_DIG_7, BYPASS_ON_ERR_CHAR, 0, 8)
3622REG32(L1_TM_DIG_8, 0x5074)
3623    FIELD(L1_TM_DIG_8, TM_DIG_8_31_8_RSVD, 24, 8)
3624    FIELD(L1_TM_DIG_8, EYESURF_ENABLE, 4, 1)
3625    FIELD(L1_TM_DIG_8, USE_EB_IN_MPHY, 3, 1)
3626    FIELD(L1_TM_DIG_8, BYPASS_EB, 2, 1)
3627    FIELD(L1_TM_DIG_8, EB_MODE, 1, 1)
3628    FIELD(L1_TM_DIG_8, FORCE_EB_MODE, 0, 1)
3629REG32(L1_TM_DIG_9, 0x5078)
3630    FIELD(L1_TM_DIG_9, TM_DIG_9_31_8_RSVD, 24, 8)
3631    FIELD(L1_TM_DIG_9, FLIP_ENDIAN, 3, 1)
3632    FIELD(L1_TM_DIG_9, DEC_ERR_CNT_THRESHOLD, 0, 3)
3633REG32(L1_TM_DIG_10, 0x507c)
3634    FIELD(L1_TM_DIG_10, TM_DIG_10_31_8_RSVD, 24, 8)
3635    FIELD(L1_TM_DIG_10, CDR_BIT_LOCK_TIME, 0, 4)
3636REG32(L1_TM_DIG_11, 0x5080)
3637    FIELD(L1_TM_DIG_11, TM_DIG_11_31_8_RSVD, 24, 8)
3638    FIELD(L1_TM_DIG_11, BYPASS_CDR_ERR_MASK, 7, 1)
3639    FIELD(L1_TM_DIG_11, SYMB_ERR_SEL, 5, 2)
3640    FIELD(L1_TM_DIG_11, SYMB_ERR, 4, 1)
3641REG32(L1_TM_DIG_12, 0x5084)
3642    FIELD(L1_TM_DIG_12, TM_DIG_12_31_8_RSVD, 24, 8)
3643    FIELD(L1_TM_DIG_12, FLIP_ENDIAN_EB_DATA_OUT, 5, 1)
3644    FIELD(L1_TM_DIG_12, FLIP_ENDIAN_EB_DATA_IN, 4, 1)
3645    FIELD(L1_TM_DIG_12, OVERFLOW_BYP, 3, 1)
3646    FIELD(L1_TM_DIG_12, UNDERFLOW_BYP, 2, 1)
3647    FIELD(L1_TM_DIG_12, OVERFLOW_BYP_VAL, 1, 1)
3648    FIELD(L1_TM_DIG_12, UNDERFLOW_BYP_VAL, 0, 1)
3649REG32(L1_TM_DIG_13, 0x5088)
3650    FIELD(L1_TM_DIG_13, TM_DIG_13_31_8_RSVD, 24, 8)
3651    FIELD(L1_TM_DIG_13, OMC_PRESENTN, 6, 1)
3652    FIELD(L1_TM_DIG_13, CFG_CLK_FREQ, 0, 6)
3653REG32(L1_TM_DIG_14, 0x508c)
3654    FIELD(L1_TM_DIG_14, TM_DIG_14_31_8_RSVD, 24, 8)
3655    FIELD(L1_TM_DIG_14, LFPS_OUTPUT_SEL, 6, 2)
3656    FIELD(L1_TM_DIG_14, LFPS_STRETCH, 4, 2)
3657REG32(L1_TM_DIG_15, 0x5090)
3658    FIELD(L1_TM_DIG_15, TM_DIG_15_31_8_RSVD, 24, 8)
3659    FIELD(L1_TM_DIG_15, FORCE_LFPS_FILTER_THRESH, 5, 1)
3660    FIELD(L1_TM_DIG_15, LFPS_FILTER_THRESH, 0, 5)
3661REG32(L1_TM_DIG_16, 0x5094)
3662    FIELD(L1_TM_DIG_16, TM_DIG_16_31_8_RSVD, 24, 8)
3663    FIELD(L1_TM_DIG_16, TESTDIGOUT_SEL, 1, 4)
3664    FIELD(L1_TM_DIG_16, FORCE_TESTDIGOUT_SEL, 0, 1)
3665REG32(L1_TM_DIG_17, 0x5098)
3666    FIELD(L1_TM_DIG_17, TM_DIG_17_31_8_RSVD, 24, 8)
3667    FIELD(L1_TM_DIG_17, FORCE_SATA_RX_VALID_CNT, 4, 1)
3668    FIELD(L1_TM_DIG_17, SATA_RX_VALID_CNT, 0, 4)
3669REG32(L1_TM_DIG_18, 0x509c)
3670    FIELD(L1_TM_DIG_18, TM_DIG_18_31_8_RSVD, 24, 8)
3671    FIELD(L1_TM_DIG_18, CLK_DIST_SETTLE_TIME, 4, 4)
3672    FIELD(L1_TM_DIG_18, BIASGEN_SETTLE_TIME, 0, 4)
3673REG32(L1_TM_DIG_19, 0x50a0)
3674    FIELD(L1_TM_DIG_19, TM_DIG_19_31_8_RSVD, 24, 8)
3675    FIELD(L1_TM_DIG_19, HSRX_ANA_SETTLE_TIME, 4, 4)
3676    FIELD(L1_TM_DIG_19, SBRX_ANA_SETTLE_TIME, 0, 4)
3677REG32(L1_TM_DIG_20, 0x50a4)
3678    FIELD(L1_TM_DIG_20, TM_DIG_20_31_8_RSVD, 24, 8)
3679    FIELD(L1_TM_DIG_20, HSRX_COOLING_TIME, 3, 4)
3680    FIELD(L1_TM_DIG_20, FORCE_RX_CAL, 2, 1)
3681    FIELD(L1_TM_DIG_20, BYPASS_HSRX_CAL, 1, 1)
3682    FIELD(L1_TM_DIG_20, BYPASS_SBRX_CAL, 0, 1)
3683REG32(L1_TM_DIG_21, 0x50a8)
3684    FIELD(L1_TM_DIG_21, TM_DIG_21_31_8_RSVD, 24, 8)
3685    FIELD(L1_TM_DIG_21, COMMA_LOCATION_RST, 4, 1)
3686    FIELD(L1_TM_DIG_21, SSC_WAIT_CNT, 2, 2)
3687    FIELD(L1_TM_DIG_21, COMMA_PRE_LOCK_THRESH, 0, 2)
3688REG32(L1_TM_DIG_22, 0x50ac)
3689    FIELD(L1_TM_DIG_22, TM_DIG_22_31_8_RSVD, 24, 8)
3690    FIELD(L1_TM_DIG_22, DIS_DEFAULT_CDR_GATE_LOGIC, 5, 1)
3691    FIELD(L1_TM_DIG_22, INV_POL_SIGDET_HIGH, 4, 1)
3692    FIELD(L1_TM_DIG_22, INV_POL_SIGDET_LOW, 3, 1)
3693    FIELD(L1_TM_DIG_22, SIGDET_LFPS_BAR_EN, 2, 1)
3694    FIELD(L1_TM_DIG_22, OBSRV_SIGDET_OUTPUT, 1, 1)
3695    FIELD(L1_TM_DIG_22, RX_SIGDET_EN, 0, 1)
3696REG32(L1_TM_DIG_23, 0x50b0)
3697    FIELD(L1_TM_DIG_23, TM_DIG_23_31_8_RSVD, 24, 8)
3698    FIELD(L1_TM_DIG_23, DELAY_TIMER_LOAD_VAL_HIGH_1, 6, 2)
3699    FIELD(L1_TM_DIG_23, FORCE_RX_SIGDET_SEL, 5, 1)
3700    FIELD(L1_TM_DIG_23, RX_SIGDET_SEL_VAL, 4, 1)
3701    FIELD(L1_TM_DIG_23, FORCE_RX_SIG_DET_FILT_FUNC_SEL, 3, 1)
3702    FIELD(L1_TM_DIG_23, RX_SIG_DET_FILT_FUNC_SEL, 0, 3)
3703REG32(L1_TM_DIG_24, 0x50b4)
3704    FIELD(L1_TM_DIG_24, TM_DIG_24_31_8_RSVD, 24, 8)
3705    FIELD(L1_TM_DIG_24, FILTER_TIMER_LOAD_VAL_HIGH_1, 6, 2)
3706    FIELD(L1_TM_DIG_24, MIN_TIMER_LOAD_VAL_HIGH_1, 4, 2)
3707    FIELD(L1_TM_DIG_24, FILTER_TIMER_LOAD_VAL_LOW_1, 2, 2)
3708    FIELD(L1_TM_DIG_24, MIN_TIMER_LOAD_VAL_LOW_1, 0, 2)
3709REG32(L1_TM_DIG_25, 0x50b8)
3710    FIELD(L1_TM_DIG_25, TM_DIG_25_31_8_RSVD, 24, 8)
3711    FIELD(L1_TM_DIG_25, FILTER_TIMER_LOAD_VAL_HIGH_0, 0, 8)
3712REG32(L1_TM_DIG_26, 0x50bc)
3713    FIELD(L1_TM_DIG_26, TM_DIG_26_31_8_RSVD, 24, 8)
3714    FIELD(L1_TM_DIG_26, DELAY_TIMER_LOAD_VAL_HIGH_0, 0, 8)
3715REG32(L1_TM_DIG_27, 0x50c0)
3716    FIELD(L1_TM_DIG_27, TM_DIG_27_31_8_RSVD, 24, 8)
3717    FIELD(L1_TM_DIG_27, MIN_TIMER_LOAD_VAL_HIGH_0, 0, 8)
3718REG32(L1_TM_DIG_28, 0x50c4)
3719    FIELD(L1_TM_DIG_28, TM_DIG_28_31_8_RSVD, 24, 8)
3720    FIELD(L1_TM_DIG_28, FILTER_TIMER_LOAD_VAL_LOW_0, 0, 8)
3721REG32(L1_TM_DIG_29, 0x50c8)
3722    FIELD(L1_TM_DIG_29, TM_DIG_29_31_8_RSVD, 24, 8)
3723    FIELD(L1_TM_DIG_29, MIN_TIMER_LOAD_VAL_LOW_0, 0, 8)
3724REG32(L1_TM_AUX_0, 0x50cc)
3725    FIELD(L1_TM_AUX_0, TM_AUX_0_31_8_RSVD, 24, 8)
3726    FIELD(L1_TM_AUX_0, BIT_0, 7, 1)
3727    FIELD(L1_TM_AUX_0, BIT_1, 6, 1)
3728    FIELD(L1_TM_AUX_0, BIT_2, 5, 1)
3729    FIELD(L1_TM_AUX_0, BIT_3, 4, 1)
3730    FIELD(L1_TM_AUX_0, BIT_4, 3, 1)
3731    FIELD(L1_TM_AUX_0, BIT_5, 2, 1)
3732    FIELD(L1_TM_AUX_0, BIT_6, 1, 1)
3733    FIELD(L1_TM_AUX_0, BIT_7, 0, 1)
3734REG32(L1_TM_AUX_1, 0x50d0)
3735    FIELD(L1_TM_AUX_1, TM_AUX_1_31_8_RSVD, 24, 8)
3736    FIELD(L1_TM_AUX_1, BIT_0, 7, 1)
3737    FIELD(L1_TM_AUX_1, BIT_1, 6, 1)
3738    FIELD(L1_TM_AUX_1, BIT_2, 5, 1)
3739    FIELD(L1_TM_AUX_1, BIT_3, 4, 1)
3740    FIELD(L1_TM_AUX_1, BIT_4, 3, 1)
3741    FIELD(L1_TM_AUX_1, BIT_5, 2, 1)
3742    FIELD(L1_TM_AUX_1, BIT_6, 1, 1)
3743    FIELD(L1_TM_AUX_1, BIT_7, 0, 1)
3744REG32(L1_TM_AUX_2, 0x50d4)
3745    FIELD(L1_TM_AUX_2, TM_AUX_2_31_8_RSVD, 24, 8)
3746    FIELD(L1_TM_AUX_2, BIT_0, 7, 1)
3747    FIELD(L1_TM_AUX_2, BIT_1, 6, 1)
3748    FIELD(L1_TM_AUX_2, BIT_2, 5, 1)
3749    FIELD(L1_TM_AUX_2, BIT_3, 4, 1)
3750    FIELD(L1_TM_AUX_2, BIT_4, 3, 1)
3751    FIELD(L1_TM_AUX_2, BIT_5, 2, 1)
3752    FIELD(L1_TM_AUX_2, BIT_6, 1, 1)
3753    FIELD(L1_TM_AUX_2, BIT_7, 0, 1)
3754REG32(L1_TM_AUX_3, 0x50d8)
3755    FIELD(L1_TM_AUX_3, TM_AUX_3_31_8_RSVD, 24, 8)
3756    FIELD(L1_TM_AUX_3, BIT_0, 7, 1)
3757    FIELD(L1_TM_AUX_3, BIT_1, 6, 1)
3758    FIELD(L1_TM_AUX_3, BIT_2, 5, 1)
3759    FIELD(L1_TM_AUX_3, BIT_3, 4, 1)
3760    FIELD(L1_TM_AUX_3, BIT_4, 3, 1)
3761    FIELD(L1_TM_AUX_3, BIT_5, 2, 1)
3762    FIELD(L1_TM_AUX_3, BIT_6, 1, 1)
3763    FIELD(L1_TM_AUX_3, BIT_7, 0, 1)
3764REG32(L1_TM_AUX_4, 0x50dc)
3765    FIELD(L1_TM_AUX_4, TM_AUX_4_31_8_RSVD, 24, 8)
3766    FIELD(L1_TM_AUX_4, BIT_0, 7, 1)
3767    FIELD(L1_TM_AUX_4, BIT_1, 6, 1)
3768    FIELD(L1_TM_AUX_4, BIT_2, 5, 1)
3769    FIELD(L1_TM_AUX_4, BIT_3, 4, 1)
3770    FIELD(L1_TM_AUX_4, BIT_4, 3, 1)
3771    FIELD(L1_TM_AUX_4, BIT_5, 2, 1)
3772    FIELD(L1_TM_AUX_4, BIT_6, 1, 1)
3773    FIELD(L1_TM_AUX_4, BIT_7, 0, 1)
3774REG32(L1_TM_DIG_30, 0x50e0)
3775    FIELD(L1_TM_DIG_30, TM_DIG_30_31_8_RSVD, 24, 8)
3776    FIELD(L1_TM_DIG_30, SD_LD_BAR_FILTER_TIME_VAL_1, 4, 2)
3777    FIELD(L1_TM_DIG_30, SD_LD_BAR_DLY_TIME_VAL_1, 2, 2)
3778    FIELD(L1_TM_DIG_30, SD_LD_BAR_MIN_TIMER_VAL_1, 0, 2)
3779REG32(L1_TM_DIG_31, 0x50e4)
3780    FIELD(L1_TM_DIG_31, TM_DIG_31_31_8_RSVD, 24, 8)
3781    FIELD(L1_TM_DIG_31, SD_LD_BAR_FILTER_TIME_VAL_0, 0, 8)
3782REG32(L1_TM_DIG_32, 0x50e8)
3783    FIELD(L1_TM_DIG_32, TM_DIG_32_31_8_RSVD, 24, 8)
3784    FIELD(L1_TM_DIG_32, SD_LD_BAR_DLY_TIME_VAL_0, 0, 8)
3785REG32(L1_TM_DIG_33, 0x50ec)
3786    FIELD(L1_TM_DIG_33, TM_DIG_33_31_8_RSVD, 24, 8)
3787    FIELD(L1_TM_DIG_33, SD_LD_BAR_MIN_TIMER_VAL_0, 0, 8)
3788REG32(L1_TM_DIG_34, 0x50f0)
3789    FIELD(L1_TM_DIG_34, TM_DIG_34_31_8_RSVD, 24, 8)
3790    FIELD(L1_TM_DIG_34, SATA_JUNK_DATA_TIMEOUT_VAL, 0, 6)
3791REG32(L1_TM_DIG_35, 0x50f4)
3792    FIELD(L1_TM_DIG_35, TM_DIG_35_31_8_RSVD, 24, 8)
3793    FIELD(L1_TM_DIG_35, SATA_CDR_LOCK_WAIT_TIMEOUT_VAL, 0, 6)
3794REG32(L1_TM_DIG_36, 0x50f8)
3795    FIELD(L1_TM_DIG_36, TM_DIG_36_31_8_RSVD, 24, 8)
3796    FIELD(L1_TM_DIG_36, COM_DET_THRESH_VAL_0, 0, 8)
3797REG32(L1_TM_DIG_37, 0x50fc)
3798    FIELD(L1_TM_DIG_37, TM_DIG_37_31_8_RSVD, 24, 8)
3799    FIELD(L1_TM_DIG_37, FORCE_COM_DETECT_THRESH, 4, 1)
3800    FIELD(L1_TM_DIG_37, COM_DET_THRESH_VAL_1, 0, 4)
3801REG32(L1_TM_LFPS_1, 0x5800)
3802    FIELD(L1_TM_LFPS_1, TM_LFPS_1_31_8_RSVD, 24, 8)
3803    FIELD(L1_TM_LFPS_1, PROG_REFP, 4, 4)
3804    FIELD(L1_TM_LFPS_1, PROG_REFM, 0, 4)
3805REG32(L1_TM_LFPS_2, 0x5804)
3806    FIELD(L1_TM_LFPS_2, TM_LFPS_2_31_8_RSVD, 24, 8)
3807    FIELD(L1_TM_LFPS_2, PROG_VCM, 4, 3)
3808    FIELD(L1_TM_LFPS_2, PROG_FILTER_CAP, 0, 4)
3809REG32(L1_TM_LFPS_3, 0x5808)
3810    FIELD(L1_TM_LFPS_3, TM_LFPS_3_31_8_RSVD, 24, 8)
3811    FIELD(L1_TM_LFPS_3, PROG_C2, 5, 3)
3812    FIELD(L1_TM_LFPS_3, PROG_C1, 2, 3)
3813    FIELD(L1_TM_LFPS_3, PROG_PADINTF, 0, 2)
3814REG32(L1_TM_LFPS_4, 0x580c)
3815    FIELD(L1_TM_LFPS_4, TM_LFPS_4_31_8_RSVD, 24, 8)
3816    FIELD(L1_TM_LFPS_4, TESTBIT, 0, 6)
3817REG32(L1_TM_RXPMA_1, 0x5810)
3818    FIELD(L1_TM_RXPMA_1, TM_RXPMA_1_31_8_RSVD, 24, 8)
3819    FIELD(L1_TM_RXPMA_1, UPHY_TESTBIT, 0, 8)
3820REG32(L1_TM_BSCAN_1, 0x5814)
3821    FIELD(L1_TM_BSCAN_1, TM_BSCAN_1_31_8_RSVD, 24, 8)
3822    FIELD(L1_TM_BSCAN_1, BSCAN_LPF_RES, 0, 3)
3823REG32(L1_TM_MPHY_SQ_1, 0x5818)
3824    FIELD(L1_TM_MPHY_SQ_1, TM_MPHY_SQ_1_31_8_RSVD, 24, 8)
3825    FIELD(L1_TM_MPHY_SQ_1, TB_REDUCE_OFFSET, 4, 1)
3826    FIELD(L1_TM_MPHY_SQ_1, TB_INCREASE_OFFSET, 3, 1)
3827    FIELD(L1_TM_MPHY_SQ_1, TB_DRIVE_RES_SEL, 1, 2)
3828    FIELD(L1_TM_MPHY_SQ_1, TB_BYPASS_HYST, 0, 1)
3829REG32(L1_TM_LSRX_1, 0x581c)
3830    FIELD(L1_TM_LSRX_1, TM_LSRX_1_31_8_RSVD, 24, 8)
3831    FIELD(L1_TM_LSRX_1, LSRX_TESTBITS_0, 0, 8)
3832REG32(L1_TM_LSRX_2, 0x5820)
3833    FIELD(L1_TM_LSRX_2, TM_LSRX_2_31_8_RSVD, 24, 8)
3834    FIELD(L1_TM_LSRX_2, LSRX_TESTBITS_1, 0, 6)
3835REG32(L1_TM_SIGDET_1, 0x5824)
3836    FIELD(L1_TM_SIGDET_1, TM_SIGDET_1_31_8_RSVD, 24, 8)
3837    FIELD(L1_TM_SIGDET_1, BIASTRIM, 4, 3)
3838    FIELD(L1_TM_SIGDET_1, RELIABPROT, 2, 2)
3839    FIELD(L1_TM_SIGDET_1, STRESSPORT, 0, 2)
3840REG32(L1_TM_SIGDET_2, 0x5828)
3841    FIELD(L1_TM_SIGDET_2, TM_SIGDET_2_31_8_RSVD, 24, 8)
3842    FIELD(L1_TM_SIGDET_2, VSENSETRIM, 0, 8)
3843REG32(L1_TM_DFT_1, 0x582c)
3844    FIELD(L1_TM_DFT_1, TM_DFT_1_31_8_RSVD, 24, 8)
3845    FIELD(L1_TM_DFT_1, LFPS_DFT_SEL_P, 4, 4)
3846    FIELD(L1_TM_DFT_1, LFPS_DFT_ENABLE, 3, 1)
3847REG32(L1_TM_DFT_2, 0x5830)
3848    FIELD(L1_TM_DFT_2, TM_DFT_2_31_8_RSVD, 24, 8)
3849    FIELD(L1_TM_DFT_2, SIGDET_DFT_SEL_P, 0, 3)
3850REG32(L1_TM_DFT_3, 0x5834)
3851    FIELD(L1_TM_DFT_3, TM_DFT_3_31_8_RSVD, 24, 8)
3852    FIELD(L1_TM_DFT_3, BSCAN_DFT_ENABLE, 4, 1)
3853    FIELD(L1_TM_DFT_3, BSCAN_DFT_SEL_P, 0, 4)
3854REG32(L1_TM_DFT_4, 0x5838)
3855    FIELD(L1_TM_DFT_4, TM_DFT_4_31_8_RSVD, 24, 8)
3856    FIELD(L1_TM_DFT_4, IQPI_DFT_ENABLE, 1, 1)
3857    FIELD(L1_TM_DFT_4, EPI_DFT_ENABLE, 0, 1)
3858REG32(L1_TM_DFT_5, 0x583c)
3859    FIELD(L1_TM_DFT_5, TM_DFT_5_31_8_RSVD, 24, 8)
3860    FIELD(L1_TM_DFT_5, IQPI_DFT_SEL, 0, 8)
3861REG32(L1_TM_DFT_6, 0x5840)
3862    FIELD(L1_TM_DFT_6, TM_DFT_6_31_8_RSVD, 24, 8)
3863    FIELD(L1_TM_DFT_6, EPI_DFT_SEL, 0, 8)
3864REG32(L1_TM_DFT_7, 0x5844)
3865    FIELD(L1_TM_DFT_7, TM_DFT_7_31_8_RSVD, 24, 8)
3866    FIELD(L1_TM_DFT_7, EQ_DFT_ENABLE, 4, 1)
3867    FIELD(L1_TM_DFT_7, EQ_DFT_SEL_P, 0, 4)
3868REG32(L1_TM_DFT_8, 0x5848)
3869    FIELD(L1_TM_DFT_8, TM_DFT_8_31_8_RSVD, 24, 8)
3870    FIELD(L1_TM_DFT_8, LSRX_DFT_ENABLE, 4, 1)
3871    FIELD(L1_TM_DFT_8, LSRX_DFT_SEL_P, 0, 4)
3872REG32(L1_TM_DFT_9, 0x584c)
3873    FIELD(L1_TM_DFT_9, TM_DFT_9_31_8_RSVD, 24, 8)
3874    FIELD(L1_TM_DFT_9, SAMP_DFT_SEL_P_0, 0, 8)
3875REG32(L1_TM_DFT_10, 0x5850)
3876    FIELD(L1_TM_DFT_10, TM_DFT_10_31_8_RSVD, 24, 8)
3877    FIELD(L1_TM_DFT_10, CLKLANE_DFT_SEL, 2, 2)
3878    FIELD(L1_TM_DFT_10, SAMP_DFT_SEL_P_1, 0, 2)
3879REG32(L1_TM_BG_1, 0x5854)
3880    FIELD(L1_TM_BG_1, TM_BG_1_31_8_RSVD, 24, 8)
3881    FIELD(L1_TM_BG_1, BIASGEN_CURRENT_PROG_0, 0, 8)
3882REG32(L1_TM_BG_2, 0x5858)
3883    FIELD(L1_TM_BG_2, TM_BG_2_31_8_RSVD, 24, 8)
3884    FIELD(L1_TM_BG_2, BIASGEN_CURRENT_PROG_1, 0, 8)
3885REG32(L1_TM_BG_3, 0x585c)
3886    FIELD(L1_TM_BG_3, TM_BG_3_31_8_RSVD, 24, 8)
3887    FIELD(L1_TM_BG_3, BIASGEN_CURRENT_PROG_2, 0, 8)
3888REG32(L1_TM_BG_4, 0x5860)
3889    FIELD(L1_TM_BG_4, TM_BG_4_31_8_RSVD, 24, 8)
3890    FIELD(L1_TM_BG_4, BIASGEN_CURRENT_PROG_3, 0, 8)
3891REG32(L1_TM_BG_5, 0x5864)
3892    FIELD(L1_TM_BG_5, TM_BG_5_31_8_RSVD, 24, 8)
3893    FIELD(L1_TM_BG_5, BIASGEN_CURRENT_PROG_4, 0, 8)
3894REG32(L1_TM_BG_6, 0x5868)
3895    FIELD(L1_TM_BG_6, TM_BG_6_31_8_RSVD, 24, 8)
3896    FIELD(L1_TM_BG_6, BIASGEN_CURRENT_PROG_5, 0, 8)
3897REG32(L1_TM_BG_7, 0x586c)
3898    FIELD(L1_TM_BG_7, TM_BG_7_31_8_RSVD, 24, 8)
3899    FIELD(L1_TM_BG_7, BIASGEN_CURRENT_PROG_6, 0, 8)
3900REG32(L1_TM_BG_8, 0x5870)
3901    FIELD(L1_TM_BG_8, TM_BG_8_31_8_RSVD, 24, 8)
3902    FIELD(L1_TM_BG_8, BIASGEN_CURRENT_PROG_7, 0, 8)
3903REG32(L1_TM_BG_9, 0x5874)
3904    FIELD(L1_TM_BG_9, TM_BG_9_31_8_RSVD, 24, 8)
3905    FIELD(L1_TM_BG_9, BIASGEN_CURRENT_PROG_8, 0, 8)
3906REG32(L1_TM_BG_10, 0x5878)
3907    FIELD(L1_TM_BG_10, TM_BG_10_31_8_RSVD, 24, 8)
3908    FIELD(L1_TM_BG_10, BIASGEN_CURRENT_PROG_9, 0, 8)
3909REG32(L1_TM_SD0, 0x587c)
3910    FIELD(L1_TM_SD0, TM_SD0_31_8_RSVD, 24, 8)
3911    FIELD(L1_TM_SD0, SD_CAL_OVERRIDE_CODE, 2, 6)
3912    FIELD(L1_TM_SD0, SD_CAL_OVERRIDE_EN, 1, 1)
3913    FIELD(L1_TM_SD0, SD_CAL_DIR, 0, 1)
3914REG32(L1_TM_SD1, 0x5880)
3915    FIELD(L1_TM_SD1, TM_SD1_31_8_RSVD, 24, 8)
3916    FIELD(L1_TM_SD1, SD_BYPASS_ANA_CAL_EN_VAL, 7, 1)
3917    FIELD(L1_TM_SD1, SD_BYPASS_ANA_CAL_EN, 6, 1)
3918    FIELD(L1_TM_SD1, SD_CAL_CODE_START, 0, 6)
3919REG32(L1_TM_SD2, 0x5884)
3920    FIELD(L1_TM_SD2, TM_SD2_31_8_RSVD, 24, 8)
3921    FIELD(L1_TM_SD2, SD_CAL_FORCE_CAL, 7, 1)
3922    FIELD(L1_TM_SD2, SD_CAL_CODE_TUNE_BYP, 6, 1)
3923    FIELD(L1_TM_SD2, SD_CAL_CODE_TUNE, 0, 6)
3924REG32(L1_TM_SD3, 0x5888)
3925    FIELD(L1_TM_SD3, TM_SD3_31_8_RSVD, 24, 8)
3926    FIELD(L1_TM_SD3, SD_CAL_ITER_WAIT_0, 0, 8)
3927REG32(L1_TM_SD4, 0x588c)
3928    FIELD(L1_TM_SD4, TM_SD4_31_8_RSVD, 24, 8)
3929    FIELD(L1_TM_SD4, SD_CAL_ITER_WAIT_BYPASS, 4, 1)
3930    FIELD(L1_TM_SD4, SD_CAL_ITER_WAIT_1, 0, 4)
3931REG32(L1_TM_SD5, 0x5890)
3932    FIELD(L1_TM_SD5, TM_SD5_31_8_RSVD, 24, 8)
3933    FIELD(L1_TM_SD5, SD_CAL_INIT_WAIT_0, 0, 8)
3934REG32(L1_TM_SD6, 0x5894)
3935    FIELD(L1_TM_SD6, TM_SD6_31_8_RSVD, 24, 8)
3936    FIELD(L1_TM_SD6, SD_CAL_INIT_WAIT_BYPASS, 4, 1)
3937    FIELD(L1_TM_SD6, SD_CAL_INIT_WAIT_1, 0, 4)
3938REG32(L1_TM_MISC1, 0x5898)
3939    FIELD(L1_TM_MISC1, TM_MISC1_31_8_RSVD, 24, 8)
3940    FIELD(L1_TM_MISC1, HSRX_POLARITY_FLIP, 7, 1)
3941    FIELD(L1_TM_MISC1, RXTERM_BIAS_PROG, 3, 4)
3942    FIELD(L1_TM_MISC1, LSRX_OR_SYS_POLARITY_FLIP, 2, 1)
3943    FIELD(L1_TM_MISC1, FORCE_SATAG1_DCC_MODE, 1, 1)
3944    FIELD(L1_TM_MISC1, SATAG1_DCC_MODE_VAL, 0, 1)
3945REG32(L1_TM_MISC2, 0x589c)
3946    FIELD(L1_TM_MISC2, TM_MISC2_31_8_RSVD, 24, 8)
3947    FIELD(L1_TM_MISC2, ILL_CAL_BYPASS_COUNTS, 7, 1)
3948    FIELD(L1_TM_MISC2, PWR_SEQ_SAMP_CAL_ALWAYS, 6, 1)
3949    FIELD(L1_TM_MISC2, PWR_SEQ_BYP_CAL_DONE, 5, 1)
3950    FIELD(L1_TM_MISC2, PWR_SEQ_BYP_CAL_DONE_VAL, 4, 1)
3951    FIELD(L1_TM_MISC2, SAMP_BYPASS_CAL_TO_EQ, 3, 1)
3952    FIELD(L1_TM_MISC2, SAMP_BYPASS_CAL_TO_EQ_VAL, 2, 1)
3953    FIELD(L1_TM_MISC2, UNUSED, 0, 2)
3954REG32(L1_TM_EYE_SURF0, 0x58a0)
3955    FIELD(L1_TM_EYE_SURF0, TM_EYE_SURF0_31_8_RSVD, 24, 8)
3956    FIELD(L1_TM_EYE_SURF0, UNUSED, 7, 1)
3957    FIELD(L1_TM_EYE_SURF0, EYE_SURF_RUN, 6, 1)
3958    FIELD(L1_TM_EYE_SURF0, COORD_EW_DIR, 5, 1)
3959    FIELD(L1_TM_EYE_SURF0, COORD_EW_OFFSET, 0, 5)
3960REG32(L1_TM_EYE_SURF1, 0x58a4)
3961    FIELD(L1_TM_EYE_SURF1, TM_EYE_SURF1_31_8_RSVD, 24, 8)
3962    FIELD(L1_TM_EYE_SURF1, COORD_NS_DIR, 7, 1)
3963    FIELD(L1_TM_EYE_SURF1, COORD_NS_OFFSET, 0, 7)
3964REG32(L1_TM_EYE_SURF2, 0x58a8)
3965    FIELD(L1_TM_EYE_SURF2, TM_EYE_SURF2_31_8_RSVD, 24, 8)
3966    FIELD(L1_TM_EYE_SURF2, TIMER_DELAY_TIME0, 0, 8)
3967REG32(L1_TM_EYE_SURF3, 0x58ac)
3968    FIELD(L1_TM_EYE_SURF3, TM_EYE_SURF3_31_8_RSVD, 24, 8)
3969    FIELD(L1_TM_EYE_SURF3, TIMER_DELAY_TIME1, 0, 8)
3970REG32(L1_TM_EYE_SURF4, 0x58b0)
3971    FIELD(L1_TM_EYE_SURF4, TM_EYE_SURF4_31_8_RSVD, 24, 8)
3972    FIELD(L1_TM_EYE_SURF4, TIMER_DELAY_TIME2, 0, 8)
3973REG32(L1_TM_EYE_SURF5, 0x58b4)
3974    FIELD(L1_TM_EYE_SURF5, TM_EYE_SURF5_31_8_RSVD, 24, 8)
3975    FIELD(L1_TM_EYE_SURF5, TIMER_DELAY_TIME3, 0, 8)
3976REG32(L1_TM_EYE_SURF6, 0x58b8)
3977    FIELD(L1_TM_EYE_SURF6, TM_EYE_SURF6_31_8_RSVD, 24, 8)
3978    FIELD(L1_TM_EYE_SURF6, TIMER_TEST_TIME0, 0, 8)
3979REG32(L1_TM_EYE_SURF7, 0x58bc)
3980    FIELD(L1_TM_EYE_SURF7, TM_EYE_SURF7_31_8_RSVD, 24, 8)
3981    FIELD(L1_TM_EYE_SURF7, TIMER_TEST_TIME1, 0, 8)
3982REG32(L1_TM_EYE_SURF8, 0x58c0)
3983    FIELD(L1_TM_EYE_SURF8, TM_EYE_SURF8_31_8_RSVD, 24, 8)
3984    FIELD(L1_TM_EYE_SURF8, TIMER_TEST_TIME2, 0, 8)
3985REG32(L1_TM_EYE_SURF9, 0x58c4)
3986    FIELD(L1_TM_EYE_SURF9, TM_EYE_SURF9_31_8_RSVD, 24, 8)
3987    FIELD(L1_TM_EYE_SURF9, TIMER_TEST_TIME3, 0, 8)
3988REG32(L1_TM_SPARE, 0x58c8)
3989    FIELD(L1_TM_SPARE, TM_SPARE_31_8_RSVD, 24, 8)
3990    FIELD(L1_TM_SPARE, RXDA_SPARE_PORT, 0, 8)
3991REG32(L1_TM_ANA_EQ1, 0x58cc)
3992    FIELD(L1_TM_ANA_EQ1, TM_ANA_EQ1_31_8_RSVD, 24, 8)
3993    FIELD(L1_TM_ANA_EQ1, UNUSED, 5, 3)
3994    FIELD(L1_TM_ANA_EQ1, EQ_INPUT_CM_PROG, 2, 3)
3995    FIELD(L1_TM_ANA_EQ1, EQ_PADINTF_HQ_PROG, 0, 2)
3996REG32(L1_TM_ANA_E_PI0, 0x58d0)
3997    FIELD(L1_TM_ANA_E_PI0, TM_ANA_E_PI0_31_8_RSVD, 24, 8)
3998    FIELD(L1_TM_ANA_E_PI0, EPI_BIASTRIM, 5, 3)
3999    FIELD(L1_TM_ANA_E_PI0, UNUSED, 0, 5)
4000REG32(L1_TM_ANA_IQ_PI0, 0x58d4)

4001    FIELD(L1_TM_ANA_IQ_PI0, TM_ANA_IQ_PI0_31_8_RSVD, 24, 8)
4002    FIELD(L1_TM_ANA_IQ_PI0, IQPI_BIASTRIM, 5, 3)
4003    FIELD(L1_TM_ANA_IQ_PI0, UNUSED, 0, 5)
4004REG32(L1_TM_ANA_MISC0, 0x58d8)
4005    FIELD(L1_TM_ANA_MISC0, TM_ANA_MISC0_31_8_RSVD, 24, 8)
4006    FIELD(L1_TM_ANA_MISC0, EPI_CALIB_EN, 7, 1)
4007    FIELD(L1_TM_ANA_MISC0, IQPI_CALIB_EN, 6, 1)
4008    FIELD(L1_TM_ANA_MISC0, UNUSED, 0, 6)
4009REG32(L1_TM_SAMP_CODE_IQ_PH0, 0x58dc)
4010    FIELD(L1_TM_SAMP_CODE_IQ_PH0, TM_SAMP_CODE_IQ_PH0_31_8_RSVD, 24, 8)
4011    FIELD(L1_TM_SAMP_CODE_IQ_PH0, UNUSED, 7, 1)
4012    FIELD(L1_TM_SAMP_CODE_IQ_PH0, SAMP_CALIB_BYP, 6, 1)
4013    FIELD(L1_TM_SAMP_CODE_IQ_PH0, IQ_PH0_SAMP_CODE, 0, 6)
4014REG32(L1_TM_SAMP_CODE_IQ_PH90, 0x58e0)
4015    FIELD(L1_TM_SAMP_CODE_IQ_PH90, TM_SAMP_CODE_IQ_PH90_31_8_RSVD, 24, 8)
4016    FIELD(L1_TM_SAMP_CODE_IQ_PH90, CALIB_SWEEP_DIR, 6, 2)
4017    FIELD(L1_TM_SAMP_CODE_IQ_PH90, IQ_PH90_SAMP_CODE, 0, 6)
4018REG32(L1_TM_SAMP_CODE_IQ_PH180, 0x58e4)
4019    FIELD(L1_TM_SAMP_CODE_IQ_PH180, TM_SAMP_CODE_IQ_PH180_31_8_RSVD, 24, 8)
4020    FIELD(L1_TM_SAMP_CODE_IQ_PH180, UNUSED, 6, 2)
4021    FIELD(L1_TM_SAMP_CODE_IQ_PH180, IQ_PH180_SAMP_CODE, 0, 6)
4022REG32(L1_TM_SAMP_CODE_IQ_PH270, 0x58e8)
4023    FIELD(L1_TM_SAMP_CODE_IQ_PH270, TM_SAMP_CODE_IQ_PH270_31_8_RSVD, 24, 8)
4024    FIELD(L1_TM_SAMP_CODE_IQ_PH270, HSRX_DBG_BUS_SEL, 6, 2)
4025    FIELD(L1_TM_SAMP_CODE_IQ_PH270, IQ_PH270_SAMP_CODE, 0, 6)
4026REG32(L1_TM_SAMP_CODE_E_PH0, 0x58ec)
4027    FIELD(L1_TM_SAMP_CODE_E_PH0, TM_SAMP_CODE_E_PH0_31_8_RSVD, 24, 8)
4028    FIELD(L1_TM_SAMP_CODE_E_PH0, UNUSED, 6, 2)
4029    FIELD(L1_TM_SAMP_CODE_E_PH0, E_PH90_SAMP_CODE, 0, 6)
4030REG32(L1_TM_SAMP_CODE_E_PH180, 0x58f0)
4031    FIELD(L1_TM_SAMP_CODE_E_PH180, TM_SAMP_CODE_E_PH180_31_8_RSVD, 24, 8)
4032    FIELD(L1_TM_SAMP_CODE_E_PH180, UNUSED, 6, 2)
4033    FIELD(L1_TM_SAMP_CODE_E_PH180, E_PH270_SAMP_CODE, 0, 6)
4034REG32(L1_TM_IQ_ILL0, 0x58f4)
4035    FIELD(L1_TM_IQ_ILL0, TM_IQ_ILL0_31_8_RSVD, 24, 8)
4036    FIELD(L1_TM_IQ_ILL0, ILL_BYPASS_IQ_CAL_EN, 7, 1)
4037    FIELD(L1_TM_IQ_ILL0, IQ_ILL_PLOADTRIM_BYP_VAL, 2, 5)
4038    FIELD(L1_TM_IQ_ILL0, IQ_ILL_PLOADTRIM_BYP, 1, 1)
4039    FIELD(L1_TM_IQ_ILL0, ILL_BYPASS_IQ_CODES, 0, 1)
4040REG32(L1_TM_IQ_ILL1, 0x58f8)
4041    FIELD(L1_TM_IQ_ILL1, TM_IQ_ILL1_31_8_RSVD, 24, 8)
4042    FIELD(L1_TM_IQ_ILL1, ILL_BYPASS_IQ_CALCODE_F0, 0, 8)
4043REG32(L1_TM_IQ_ILL2, 0x58fc)
4044    FIELD(L1_TM_IQ_ILL2, TM_IQ_ILL2_31_8_RSVD, 24, 8)
4045    FIELD(L1_TM_IQ_ILL2, ILL_BYPASS_IQ_CALCODE_F1, 0, 8)
4046REG32(L1_TM_IQ_ILL3, 0x5900)
4047    FIELD(L1_TM_IQ_ILL3, TM_IQ_ILL3_31_8_RSVD, 24, 8)
4048    FIELD(L1_TM_IQ_ILL3, ILL_BYPASS_IQ_CALCODE_F2, 0, 8)
4049REG32(L1_TM_IQ_ILL4, 0x5904)
4050    FIELD(L1_TM_IQ_ILL4, TM_IQ_ILL4_31_8_RSVD, 24, 8)
4051    FIELD(L1_TM_IQ_ILL4, ILL_BYPASS_IQ_CALCODE_F3, 0, 8)
4052REG32(L1_TM_IQ_ILL5, 0x5908)
4053    FIELD(L1_TM_IQ_ILL5, TM_IQ_ILL5_31_8_RSVD, 24, 8)
4054    FIELD(L1_TM_IQ_ILL5, ILL_BYPASS_IQ_CALCODE_F4, 0, 8)
4055REG32(L1_TM_IQ_ILL6, 0x590c)
4056    FIELD(L1_TM_IQ_ILL6, TM_IQ_ILL6_31_8_RSVD, 24, 8)
4057    FIELD(L1_TM_IQ_ILL6, ILL_BYPASS_IQ_CALCODE_F5, 0, 8)
4058REG32(L1_TM_IQ_ILL7, 0x5910)
4059    FIELD(L1_TM_IQ_ILL7, TM_IQ_ILL7_31_8_RSVD, 24, 8)
4060    FIELD(L1_TM_IQ_ILL7, ILL_BYPASS_IQ_CNSTGMTRIM_VAL, 0, 8)
4061REG32(L1_TM_IQ_ILL8, 0x5914)
4062    FIELD(L1_TM_IQ_ILL8, TM_IQ_ILL8_31_8_RSVD, 24, 8)
4063    FIELD(L1_TM_IQ_ILL8, ILL_BYPASS_IQ_POLYTRIM_VAL, 0, 8)
4064REG32(L1_TM_IQ_ILL9, 0x5918)
4065    FIELD(L1_TM_IQ_ILL9, TM_IQ_ILL9_31_8_RSVD, 24, 8)
4066    FIELD(L1_TM_IQ_ILL9, UNUSED, 4, 4)
4067    FIELD(L1_TM_IQ_ILL9, ILL_BYPASS_IQ_LFEN, 3, 1)
4068    FIELD(L1_TM_IQ_ILL9, ILL_BYPASS_IQ_LFEN_VAL, 2, 1)
4069    FIELD(L1_TM_IQ_ILL9, ILL_BYPASS_IQ_CNSTGMTRIM, 1, 1)
4070    FIELD(L1_TM_IQ_ILL9, ILL_BYPASS_IQ_POLYTIM, 0, 1)
4071REG32(L1_TM_IQ_ILL10, 0x591c)
4072    FIELD(L1_TM_IQ_ILL10, TM_IQ_ILL10_31_8_RSVD, 24, 8)
4073    FIELD(L1_TM_IQ_ILL10, UNUSED, 6, 2)
4074    FIELD(L1_TM_IQ_ILL10, IQPI_CALCTRIM, 4, 2)
4075    FIELD(L1_TM_IQ_ILL10, IQPI_REPLICATRIM, 0, 4)
4076REG32(L1_TM_E_ILL0, 0x5920)
4077    FIELD(L1_TM_E_ILL0, TM_E_ILL0_31_8_RSVD, 24, 8)
4078    FIELD(L1_TM_E_ILL0, E_ILL_CALIB_CTRL, 7, 1)
4079    FIELD(L1_TM_E_ILL0, E_ILL_PLOADTRIM_BYP_VAL, 2, 5)
4080    FIELD(L1_TM_E_ILL0, E_ILL_PLOADTRIM_BYP, 1, 1)
4081    FIELD(L1_TM_E_ILL0, E_ILL_CALIB_BYP, 0, 1)
4082REG32(L1_TM_E_ILL1, 0x5924)
4083    FIELD(L1_TM_E_ILL1, TM_E_ILL1_31_8_RSVD, 24, 8)
4084    FIELD(L1_TM_E_ILL1, ILL_BYPASS_E_CALCODE_F0, 0, 8)
4085REG32(L1_TM_E_ILL2, 0x5928)
4086    FIELD(L1_TM_E_ILL2, TM_E_ILL2_31_8_RSVD, 24, 8)
4087    FIELD(L1_TM_E_ILL2, ILL_BYPASS_E_CALCODE_F1, 0, 8)
4088REG32(L1_TM_E_ILL3, 0x592c)
4089    FIELD(L1_TM_E_ILL3, TM_E_ILL3_31_8_RSVD, 24, 8)
4090    FIELD(L1_TM_E_ILL3, ILL_BYPASS_E_CALCODE_F2, 0, 8)
4091REG32(L1_TM_E_ILL4, 0x5930)
4092    FIELD(L1_TM_E_ILL4, TM_E_ILL4_31_8_RSVD, 24, 8)
4093    FIELD(L1_TM_E_ILL4, ILL_BYPASS_E_CALCODE_F3, 0, 8)
4094REG32(L1_TM_E_ILL5, 0x5934)
4095    FIELD(L1_TM_E_ILL5, TM_E_ILL5_31_8_RSVD, 24, 8)
4096    FIELD(L1_TM_E_ILL5, ILL_BYPASS_E_CALCODE_F4, 0, 8)
4097REG32(L1_TM_E_ILL6, 0x5938)
4098    FIELD(L1_TM_E_ILL6, TM_E_ILL6_31_8_RSVD, 24, 8)
4099    FIELD(L1_TM_E_ILL6, ILL_BYPASS_E_CALCODE_F5, 0, 8)
4100REG32(L1_TM_E_ILL7, 0x593c)
4101    FIELD(L1_TM_E_ILL7, TM_E_ILL7_31_8_RSVD, 24, 8)
4102    FIELD(L1_TM_E_ILL7, ILL_BYPASS_E_CNSTGMTRIM_VAL, 0, 8)
4103REG32(L1_TM_E_ILL8, 0x5940)
4104    FIELD(L1_TM_E_ILL8, TM_E_ILL8_31_8_RSVD, 24, 8)
4105    FIELD(L1_TM_E_ILL8, ILL_BYPASS_E_POLYTRIM_VAL, 0, 8)
4106REG32(L1_TM_E_ILL9, 0x5944)
4107    FIELD(L1_TM_E_ILL9, TM_E_ILL9_31_8_RSVD, 24, 8)
4108    FIELD(L1_TM_E_ILL9, UNUSED, 4, 4)
4109    FIELD(L1_TM_E_ILL9, ILL_BYPASS_E_LFEN, 3, 1)
4110    FIELD(L1_TM_E_ILL9, ILL_BYPASS_E_LFEN_VAL, 2, 1)
4111    FIELD(L1_TM_E_ILL9, ILL_BYPASS_E_CNSTGMTRIM, 1, 1)
4112    FIELD(L1_TM_E_ILL9, ILL_BYPASS_E_POLYTIM, 0, 1)
4113REG32(L1_TM_E_ILL10, 0x5948)
4114    FIELD(L1_TM_E_ILL10, TM_E_ILL10_31_8_RSVD, 24, 8)
4115    FIELD(L1_TM_E_ILL10, UNUSED, 6, 2)
4116    FIELD(L1_TM_E_ILL10, EPI_CALCTRIM, 4, 2)
4117    FIELD(L1_TM_E_ILL10, EPI_REPLICATRIM, 0, 4)
4118REG32(L1_TM_EQ0, 0x594c)
4119    FIELD(L1_TM_EQ0, TM_EQ0_31_8_RSVD, 24, 8)
4120    FIELD(L1_TM_EQ0, EQ_STG1_RL_PROG_MSB, 7, 1)
4121    FIELD(L1_TM_EQ0, EQ_STG1_CTRL_BYP, 6, 1)
4122    FIELD(L1_TM_EQ0, EQ_STG2_CTRL_BYP, 5, 1)
4123    FIELD(L1_TM_EQ0, EQ_ADAPTATION_FORCE, 4, 1)
4124    FIELD(L1_TM_EQ0, EQ_ADAPTATION_FORCE_VAL, 3, 1)
4125    FIELD(L1_TM_EQ0, EQ_ISOURCE_EN_VAL, 0, 3)
4126REG32(L1_TM_EQ1, 0x5950)
4127    FIELD(L1_TM_EQ1, TM_EQ1_31_8_RSVD, 24, 8)
4128    FIELD(L1_TM_EQ1, EQ_STG1_PREAMP_MODE_VAL, 7, 1)
4129    FIELD(L1_TM_EQ1, EQ_STG1_RL_PROG, 5, 2)
4130    FIELD(L1_TM_EQ1, EQ_STG2_CM_PROG, 3, 2)
4131    FIELD(L1_TM_EQ1, EQ_STG2_PREAMP_MODE_VAL, 2, 1)
4132    FIELD(L1_TM_EQ1, EQ_STG2_RL_PROG, 0, 2)
4133REG32(L1_TM_EQ2, 0x5954)
4134    FIELD(L1_TM_EQ2, TM_EQ2_31_8_RSVD, 24, 8)
4135    FIELD(L1_TM_EQ2, UNUSED, 7, 1)
4136    FIELD(L1_TM_EQ2, EQ_EN_BACKGND_ADAPT, 6, 1)
4137    FIELD(L1_TM_EQ2, EQ_COUNT_STRAYS, 5, 1)
4138    FIELD(L1_TM_EQ2, EQ_WINDOW_SIZE, 3, 2)
4139    FIELD(L1_TM_EQ2, EQ_MAJ_THRESH, 1, 2)
4140    FIELD(L1_TM_EQ2, EQ_BIAS_CTRL_BYP, 0, 1)
4141REG32(L1_TM_EQ3, 0x5958)
4142    FIELD(L1_TM_EQ3, TM_EQ3_31_8_RSVD, 24, 8)
4143    FIELD(L1_TM_EQ3, UNUSED, 5, 3)
4144    FIELD(L1_TM_EQ3, EQ_BYPASS_ISINK_ENZ_VAL, 0, 5)
4145REG32(L1_TM_EQ4, 0x595c)
4146    FIELD(L1_TM_EQ4, TM_EQ4_31_8_RSVD, 24, 8)
4147    FIELD(L1_TM_EQ4, UNUSED, 5, 3)
4148    FIELD(L1_TM_EQ4, BYPASS_EQ_C_STG1, 4, 1)
4149    FIELD(L1_TM_EQ4, BYPASS_EQ_C_VAL_STG1, 0, 4)
4150REG32(L1_TM_EQ5, 0x5960)
4151    FIELD(L1_TM_EQ5, TM_EQ5_31_8_RSVD, 24, 8)
4152    FIELD(L1_TM_EQ5, UNUSED, 6, 2)
4153    FIELD(L1_TM_EQ5, BYPASS_EQ_R_STG1, 5, 1)
4154    FIELD(L1_TM_EQ5, BYPASS_EQ_R_VAL_STG1, 0, 5)
4155REG32(L1_TM_EQ6, 0x5964)
4156    FIELD(L1_TM_EQ6, TM_EQ6_31_8_RSVD, 24, 8)
4157    FIELD(L1_TM_EQ6, UNUSED, 5, 3)
4158    FIELD(L1_TM_EQ6, BYPASS_EQ_C_STG2, 4, 1)
4159    FIELD(L1_TM_EQ6, BYPASS_EQ_C_VAL_STG2, 0, 4)
4160REG32(L1_TM_EQ7, 0x5968)
4161    FIELD(L1_TM_EQ7, TM_EQ7_31_8_RSVD, 24, 8)
4162    FIELD(L1_TM_EQ7, UNUSED, 6, 2)
4163    FIELD(L1_TM_EQ7, BYPASS_EQ_R_STG2, 5, 1)
4164    FIELD(L1_TM_EQ7, BYPASS_EQ_R_VAL_STG2, 0, 5)
4165REG32(L1_TM_EQ8, 0x596c)
4166    FIELD(L1_TM_EQ8, TM_EQ8_31_8_RSVD, 24, 8)
4167    FIELD(L1_TM_EQ8, EQ_BYPASS_CALIB, 7, 1)
4168    FIELD(L1_TM_EQ8, EQ_SWEEP, 5, 2)
4169    FIELD(L1_TM_EQ8, SEL_SAMP, 2, 3)
4170    FIELD(L1_TM_EQ8, BYPASS_EQ_CAL, 1, 1)
4171    FIELD(L1_TM_EQ8, BYPASS_EQ_CAL_VAL, 0, 1)
4172REG32(L1_TM_EQ9, 0x5970)
4173    FIELD(L1_TM_EQ9, TM_EQ9_31_8_RSVD, 24, 8)
4174    FIELD(L1_TM_EQ9, UNUSED, 7, 1)
4175    FIELD(L1_TM_EQ9, EQ_BYPASS_CALIB_CODE, 0, 7)
4176REG32(L1_TM_EQ10, 0x5974)
4177    FIELD(L1_TM_EQ10, TM_EQ10_31_8_RSVD, 24, 8)
4178    FIELD(L1_TM_EQ10, UNUSED, 7, 1)
4179    FIELD(L1_TM_EQ10, OFFSET_COEF_SCALER, 4, 3)
4180    FIELD(L1_TM_EQ10, DIAG_OUTPUT_SEL, 0, 4)
4181REG32(L1_TM_EQ11, 0x5978)
4182    FIELD(L1_TM_EQ11, TM_EQ11_31_8_RSVD, 24, 8)
4183    FIELD(L1_TM_EQ11, EQ_CALIB_CLK_DIV_FORCE, 7, 1)
4184    FIELD(L1_TM_EQ11, EDGE_IS_FIRST, 6, 1)
4185    FIELD(L1_TM_EQ11, FORCE_EQ_OFFS_ON, 5, 1)
4186    FIELD(L1_TM_EQ11, FORCE_EQ_OFFS_OFF, 4, 1)
4187    FIELD(L1_TM_EQ11, EQ_OFFS_WITH_ADAPT, 3, 1)
4188    FIELD(L1_TM_EQ11, OFFSET_VOTER_OVERRIDE_EN, 2, 1)
4189    FIELD(L1_TM_EQ11, OFFSET_VOTER_OVERRIDE_NEG, 1, 1)
4190    FIELD(L1_TM_EQ11, OFFSET_VOTER_OVERRIDE_POS, 0, 1)
4191REG32(L1_TM_ILL7, 0x597c)
4192    FIELD(L1_TM_ILL7, TM_ILL7_31_8_RSVD, 24, 8)
4193    FIELD(L1_TM_ILL7, ILL_CAL_INIT_WAIT, 0, 8)
4194REG32(L1_TM_ILL8, 0x5980)
4195    FIELD(L1_TM_ILL8, TM_ILL8_31_8_RSVD, 24, 8)
4196    FIELD(L1_TM_ILL8, ILL_CAL_ITER_WAIT, 0, 8)
4197REG32(L1_TM_ILL9, 0x5984)
4198    FIELD(L1_TM_ILL9, TM_ILL9_31_8_RSVD, 24, 8)
4199    FIELD(L1_TM_ILL9, ILL_CAL_BYPASS_CAP_START, 7, 1)
4200    FIELD(L1_TM_ILL9, ILL_CAL_CAP_START_VAL, 0, 7)
4201REG32(L1_TM_ILL10, 0x5988)
4202    FIELD(L1_TM_ILL10, TM_ILL10_31_8_RSVD, 24, 8)
4203    FIELD(L1_TM_ILL10, G3A_USB3_PCIEG2_PLL_CTR_11_8_BYP_VAL, 4, 4)
4204    FIELD(L1_TM_ILL10, G3B_PLL_CTR_11_8_BYP_VAL, 0, 4)
4205REG32(L1_TM_ILL11, 0x598c)
4206    FIELD(L1_TM_ILL11, TM_ILL11_31_8_RSVD, 24, 8)
4207    FIELD(L1_TM_ILL11, G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL, 4, 4)
4208    FIELD(L1_TM_ILL11, G2B_PLL_CTR_11_8_BYP_VAL, 0, 4)
4209REG32(L1_TM_ILL12, 0x5990)
4210    FIELD(L1_TM_ILL12, TM_ILL12_31_8_RSVD, 24, 8)
4211    FIELD(L1_TM_ILL12, G1A_PLL_CTR_BYP_VAL, 0, 8)
4212REG32(L1_TM_ILL13, 0x5994)
4213    FIELD(L1_TM_ILL13, TM_ILL13_31_8_RSVD, 24, 8)
4214    FIELD(L1_TM_ILL13, ILL_CAL_IDLE_VAL_REFCNT, 0, 3)
4215REG32(L1_TM_ILL14, 0x5998)
4216    FIELD(L1_TM_ILL14, TM_ILL14_31_8_RSVD, 24, 8)
4217    FIELD(L1_TM_ILL14, ILL_CALIB_WAIT, 4, 4)
4218    FIELD(L1_TM_ILL14, ILL_CHG_WAIT, 0, 4)
4219REG32(L1_TM_FRZ_FSM0, 0x599c)
4220    FIELD(L1_TM_FRZ_FSM0, TM_FRZ_FSM0_31_8_RSVD, 24, 8)
4221    FIELD(L1_TM_FRZ_FSM0, FREEZE_HSRX_PWR_SEQ_FSM, 0, 8)
4222REG32(L1_TM_FRZ_FSM1, 0x59a0)
4223    FIELD(L1_TM_FRZ_FSM1, TM_FRZ_FSM1_31_8_RSVD, 24, 8)
4224    FIELD(L1_TM_FRZ_FSM1, UNUSED, 6, 2)
4225    FIELD(L1_TM_FRZ_FSM1, FREEZE_ILL_CALIB_FSM, 0, 6)
4226REG32(L1_TM_RST_DLY, 0x59a4)
4227    FIELD(L1_TM_RST_DLY, TM_RST_DLY_31_8_RSVD, 24, 8)
4228    FIELD(L1_TM_RST_DLY, APB_RST_DLY, 0, 8)
4229REG32(L1_TM_ILL15, 0x59a8)
4230    FIELD(L1_TM_ILL15, TM_ILL15_31_8_RSVD, 24, 8)
4231    FIELD(L1_TM_ILL15, ILL_CAL_REF_CTR_MSB_REG1, 0, 8)
4232REG32(L1_TM_MISC3, 0x59ac)
4233    FIELD(L1_TM_MISC3, TM_MISC3_31_8_RSVD, 24, 8)
4234    FIELD(L1_TM_MISC3, AUX0_BIT_7, 7, 1)
4235    FIELD(L1_TM_MISC3, AUX0_BIT_6, 6, 1)
4236    FIELD(L1_TM_MISC3, AUX0_BIT_5, 5, 1)
4237    FIELD(L1_TM_MISC3, DBG_BUS_SEL, 2, 3)
4238    FIELD(L1_TM_MISC3, CDR_EN_FPL, 1, 1)
4239    FIELD(L1_TM_MISC3, CDR_EN_FFL, 0, 1)
4240REG32(L1_TM_EQ_OFFS1, 0x59b0)
4241    FIELD(L1_TM_EQ_OFFS1, TM_EQ_OFFS1_31_8_RSVD, 24, 8)
4242    FIELD(L1_TM_EQ_OFFS1, EQ_OFFSET_CORR_BYP, 1, 7)
4243    FIELD(L1_TM_EQ_OFFS1, AUX1_BIT_7, 0, 1)
4244REG32(L1_TM_SAMP0, 0x59b4)
4245    FIELD(L1_TM_SAMP0, TM_SAMP0_31_8_RSVD, 24, 8)
4246    FIELD(L1_TM_SAMP0, SAMP_CALIB_CLK_DIV_FACTOR, 1, 7)
4247    FIELD(L1_TM_SAMP0, SAMP_CALIB_CLK_DIV_FORCE, 0, 1)
4248REG32(L1_TM_EQ12, 0x59b8)
4249    FIELD(L1_TM_EQ12, TM_EQ12_31_8_RSVD, 24, 8)
4250    FIELD(L1_TM_EQ12, EQ_CALIB_CLK_DIV_FACTOR, 0, 8)
4251REG32(L1_TM_MISC4, 0x59bc)
4252    FIELD(L1_TM_MISC4, TM_MISC4_31_8_RSVD, 24, 8)
4253    FIELD(L1_TM_MISC4, PSO_CLK_LANE_FRM_PCS, 2, 1)
4254    FIELD(L1_TM_MISC4, BSCAN_MODE_VAL, 1, 1)
4255    FIELD(L1_TM_MISC4, BSCAN_FORCE_MODE, 0, 1)
4256REG32(L1_TM_SAMP_STATUS0, 0x5a80)
4257    FIELD(L1_TM_SAMP_STATUS0, TM_SAMP_STATUS0_31_8_RSVD, 24, 8)
4258    FIELD(L1_TM_SAMP_STATUS0, IQ_SAMP_PH0_CALIB_CODE, 0, 6)
4259REG32(L1_TM_SAMP_STATUS1, 0x5a84)
4260    FIELD(L1_TM_SAMP_STATUS1, TM_SAMP_STATUS1_31_8_RSVD, 24, 8)
4261    FIELD(L1_TM_SAMP_STATUS1, IQ_SAMP_PH90_CALIB_CODE, 0, 6)
4262REG32(L1_TM_SAMP_STATUS2, 0x5a88)
4263    FIELD(L1_TM_SAMP_STATUS2, TM_SAMP_STATUS2_31_8_RSVD, 24, 8)
4264    FIELD(L1_TM_SAMP_STATUS2, IQ_SAMP_PH180_CALIB_CODE, 0, 6)
4265REG32(L1_TM_SAMP_STATUS3, 0x5a8c)
4266    FIELD(L1_TM_SAMP_STATUS3, TM_SAMP_STATUS3_31_8_RSVD, 24, 8)
4267    FIELD(L1_TM_SAMP_STATUS3, IQ_SAMP_PH270_CALIB_CODE, 0, 6)
4268REG32(L1_TM_SAMP_STATUS4, 0x5a90)
4269    FIELD(L1_TM_SAMP_STATUS4, TM_SAMP_STATUS4_31_8_RSVD, 24, 8)
4270    FIELD(L1_TM_SAMP_STATUS4, E_SAMP_PH0_CALIB_CODE, 0, 6)
4271REG32(L1_TM_SAMP_STATUS5, 0x5a94)
4272    FIELD(L1_TM_SAMP_STATUS5, TM_SAMP_STATUS5_31_8_RSVD, 24, 8)
4273    FIELD(L1_TM_SAMP_STATUS5, E_SAMP_PH180_CALIB_CODE, 0, 6)
4274REG32(L1_TM_ILL_STATUS0, 0x5a98)
4275    FIELD(L1_TM_ILL_STATUS0, TM_ILL_STATUS0_31_8_RSVD, 24, 8)
4276    FIELD(L1_TM_ILL_STATUS0, IQ_F0_CALCODE_CALIB_VAL, 0, 7)
4277REG32(L1_TM_ILL_STATUS1, 0x5a9c)
4278    FIELD(L1_TM_ILL_STATUS1, TM_ILL_STATUS1_31_8_RSVD, 24, 8)
4279    FIELD(L1_TM_ILL_STATUS1, IQ_F1_CALCODE_CALIB_VAL, 0, 7)
4280REG32(L1_TM_ILL_STATUS2, 0x5aa0)
4281    FIELD(L1_TM_ILL_STATUS2, TM_ILL_STATUS2_31_8_RSVD, 24, 8)
4282    FIELD(L1_TM_ILL_STATUS2, IQ_F2_CALCODE_CALIB_VAL, 0, 7)
4283REG32(L1_TM_ILL_STATUS3, 0x5aa4)
4284    FIELD(L1_TM_ILL_STATUS3, TM_ILL_STATUS3_31_8_RSVD, 24, 8)
4285    FIELD(L1_TM_ILL_STATUS3, IQ_F3_CALCODE_CALIB_VAL, 0, 7)
4286REG32(L1_TM_ILL_STATUS4, 0x5aa8)
4287    FIELD(L1_TM_ILL_STATUS4, TM_ILL_STATUS4_31_8_RSVD, 24, 8)
4288    FIELD(L1_TM_ILL_STATUS4, IQ_F4_CALCODE_CALIB_VAL, 0, 7)
4289REG32(L1_TM_ILL_STATUS5, 0x5aac)
4290    FIELD(L1_TM_ILL_STATUS5, TM_ILL_STATUS5_31_8_RSVD, 24, 8)
4291    FIELD(L1_TM_ILL_STATUS5, IQ_F5_CALCODE_CALIB_VAL, 0, 7)
4292REG32(L1_TM_ILL_STATUS6, 0x5ab0)
4293    FIELD(L1_TM_ILL_STATUS6, TM_ILL_STATUS6_31_8_RSVD, 24, 8)
4294    FIELD(L1_TM_ILL_STATUS6, E_F0_CALCODE_CALIB_VAL, 0, 7)
4295REG32(L1_TM_ILL_STATUS7, 0x5ab4)
4296    FIELD(L1_TM_ILL_STATUS7, TM_ILL_STATUS7_31_8_RSVD, 24, 8)
4297    FIELD(L1_TM_ILL_STATUS7, E_F1_CALCODE_CALIB_VAL, 0, 7)
4298REG32(L1_TM_ILL_STATUS8, 0x5ab8)
4299    FIELD(L1_TM_ILL_STATUS8, TM_ILL_STATUS8_31_8_RSVD, 24, 8)
4300    FIELD(L1_TM_ILL_STATUS8, E_F2_CALCODE_CALIB_VAL, 0, 7)
4301REG32(L1_TM_ILL_STATUS9, 0x5abc)
4302    FIELD(L1_TM_ILL_STATUS9, TM_ILL_STATUS9_31_8_RSVD, 24, 8)
4303    FIELD(L1_TM_ILL_STATUS9, E_F3_CALCODE_CALIB_VAL, 0, 7)
4304REG32(L1_TM_ILL_STATUS10, 0x5ac0)
4305    FIELD(L1_TM_ILL_STATUS10, TM_ILL_STATUS10_31_8_RSVD, 24, 8)
4306    FIELD(L1_TM_ILL_STATUS10, E_F4_CALCODE_CALIB_VAL, 0, 7)
4307REG32(L1_TM_ILL_STATUS11, 0x5ac4)
4308    FIELD(L1_TM_ILL_STATUS11, TM_ILL_STATUS11_31_8_RSVD, 24, 8)
4309    FIELD(L1_TM_ILL_STATUS11, E_F5_CALCODE_CALIB_VAL, 0, 7)
4310REG32(L1_TM_MISC_ST_0, 0x5ac8)
4311    FIELD(L1_TM_MISC_ST_0, TM_MISC_ST_0_31_8_RSVD, 24, 8)
4312    FIELD(L1_TM_MISC_ST_0, EYE_SURF_DONE, 5, 1)
4313    FIELD(L1_TM_MISC_ST_0, SD_CAL_DONE, 4, 1)
4314    FIELD(L1_TM_MISC_ST_0, SAMP_CAL_DONE, 3, 1)
4315    FIELD(L1_TM_MISC_ST_0, ILL_CAL_DONE, 2, 1)
4316    FIELD(L1_TM_MISC_ST_0, EQ_CAL_DONE, 1, 1)
4317    FIELD(L1_TM_MISC_ST_0, EQ_VALID_ADAPT_CODE, 0, 1)
4318REG32(L1_TM_SD_ST_0, 0x5acc)
4319    FIELD(L1_TM_SD_ST_0, TM_SD_ST_0_31_8_RSVD, 24, 8)
4320    FIELD(L1_TM_SD_ST_0, SD_CAL_CODE, 0, 6)
4321REG32(L1_TM_EYESURF_ST0, 0x5ad0)
4322    FIELD(L1_TM_EYESURF_ST0, TM_EYESURF_ST0_31_8_RSVD, 24, 8)
4323    FIELD(L1_TM_EYESURF_ST0, ERROR_COUNT0, 0, 8)
4324REG32(L1_TM_EYESURF_ST1, 0x5ad4)
4325    FIELD(L1_TM_EYESURF_ST1, TM_EYESURF_ST1_31_8_RSVD, 24, 8)
4326    FIELD(L1_TM_EYESURF_ST1, ERROR_COUNT1, 0, 8)
4327REG32(L1_TM_EQ_ST0, 0x5ad8)
4328    FIELD(L1_TM_EQ_ST0, TM_EQ_ST0_31_8_RSVD, 24, 8)
4329    FIELD(L1_TM_EQ_ST0, EQ_ADAPT_CODE0, 0, 8)
4330REG32(L1_TM_EQ_ST1, 0x5adc)
4331    FIELD(L1_TM_EQ_ST1, TM_EQ_ST1_31_8_RSVD, 24, 8)
4332    FIELD(L1_TM_EQ_ST1, EQ_ADAPT_CODE1, 0, 8)
4333REG32(L1_TM_EQ_ST2, 0x5ae0)
4334    FIELD(L1_TM_EQ_ST2, TM_EQ_ST2_31_8_RSVD, 24, 8)
4335    FIELD(L1_TM_EQ_ST2, EQ_CALIB_CODE, 0, 7)
4336REG32(L1_TM_RXPMA_ST1, 0x5ae4)
4337    FIELD(L1_TM_RXPMA_ST1, TM_RXPMA_ST1_31_8_RSVD, 24, 8)
4338    FIELD(L1_TM_RXPMA_ST1, HSRX_OPMODE_STATUS, 0, 8)
4339REG32(L1_TM_CDR0, 0x5c00)
4340    FIELD(L1_TM_CDR0, TM_CDR0_31_8_RSVD, 24, 8)
4341    FIELD(L1_TM_CDR0, FAST_PHASE_LOCK_FORCE, 7, 1)
4342    FIELD(L1_TM_CDR0, UNUSED, 5, 2)
4343    FIELD(L1_TM_CDR0, CDR_LOOP_CTRL, 2, 3)
4344    FIELD(L1_TM_CDR0, SECOND_ORDER_LOOP_DIS, 1, 1)
4345    FIELD(L1_TM_CDR0, FIRST_ORDER_LOOP_DIS, 0, 1)
4346REG32(L1_TM_CDR1, 0x5c04)
4347    FIELD(L1_TM_CDR1, TM_CDR1_31_8_RSVD, 24, 8)
4348    FIELD(L1_TM_CDR1, RESET_DELAY_2OL, 0, 8)
4349REG32(L1_TM_CDR2, 0x5c08)
4350    FIELD(L1_TM_CDR2, TM_CDR2_31_8_RSVD, 24, 8)
4351    FIELD(L1_TM_CDR2, CLK_SEL_2OL, 6, 2)
4352    FIELD(L1_TM_CDR2, INTEGRATOR_THRESH_2OL, 0, 6)
4353REG32(L1_TM_CDR3, 0x5c0c)
4354    FIELD(L1_TM_CDR3, TM_CDR3_31_8_RSVD, 24, 8)
4355    FIELD(L1_TM_CDR3, UNUSED, 7, 1)
4356    FIELD(L1_TM_CDR3, SIGNAL_THRESH_1OL, 0, 7)
4357REG32(L1_TM_CDR4, 0x5c10)
4358    FIELD(L1_TM_CDR4, TM_CDR4_31_8_RSVD, 24, 8)
4359    FIELD(L1_TM_CDR4, UNUSED, 7, 1)
4360    FIELD(L1_TM_CDR4, SIGNAL_THRESH_2OL, 0, 7)
4361REG32(L1_TM_CDR5, 0x5c14)
4362    FIELD(L1_TM_CDR5, TM_CDR5_31_8_RSVD, 24, 8)
4363    FIELD(L1_TM_CDR5, FPHL_FSM_ACC_CYCLES, 5, 3)
4364    FIELD(L1_TM_CDR5, FFL_PH0_INT_GAIN, 0, 5)
4365REG32(L1_TM_CDR6, 0x5c18)
4366    FIELD(L1_TM_CDR6, TM_CDR6_31_8_RSVD, 24, 8)
4367    FIELD(L1_TM_CDR6, FPHL_FSM_DELAY_CYCLES, 5, 3)
4368    FIELD(L1_TM_CDR6, FFL_PH1_INT_GAIN, 0, 5)
4369REG32(L1_TM_CDR7, 0x5c1c)
4370    FIELD(L1_TM_CDR7, TM_CDR7_31_8_RSVD, 24, 8)
4371    FIELD(L1_TM_CDR7, FPHL_FSM_TRIGGER1_WAIT_CYCLES, 5, 3)
4372    FIELD(L1_TM_CDR7, FFL_PH2_INT_GAIN, 0, 5)
4373REG32(L1_TM_CDR8, 0x5c20)
4374    FIELD(L1_TM_CDR8, TM_CDR8_31_8_RSVD, 24, 8)
4375    FIELD(L1_TM_CDR8, FPHL_FSM_TRIGGER2_WAIT_CYCLES, 5, 3)
4376    FIELD(L1_TM_CDR8, FFL_PH3_INT_GAIN, 0, 5)
4377REG32(L1_TM_CDR9, 0x5c24)
4378    FIELD(L1_TM_CDR9, TM_CDR9_31_8_RSVD, 24, 8)
4379    FIELD(L1_TM_CDR9, FPHL_FSM_TRIGGER3_WAIT_CYCLES, 5, 3)
4380    FIELD(L1_TM_CDR9, FFL_PH4_INT_GAIN, 0, 5)
4381REG32(L1_TM_CDR10, 0x5c28)
4382    FIELD(L1_TM_CDR10, TM_CDR10_31_8_RSVD, 24, 8)
4383    FIELD(L1_TM_CDR10, FFL_TIME_PER_PHASE_10_8, 5, 3)
4384    FIELD(L1_TM_CDR10, FFL_PH5_INT_GAIN, 0, 5)
4385REG32(L1_TM_CDR11, 0x5c2c)
4386    FIELD(L1_TM_CDR11, TM_CDR11_31_8_RSVD, 24, 8)
4387    FIELD(L1_TM_CDR11, UNUSED, 5, 3)
4388    FIELD(L1_TM_CDR11, FFL_PH6_INT_GAIN, 0, 5)
4389REG32(L1_TM_CDR12, 0x5c30)
4390    FIELD(L1_TM_CDR12, TM_CDR12_31_8_RSVD, 24, 8)
4391    FIELD(L1_TM_CDR12, CDRLF_RESET_ON_EN_CDR, 7, 1)
4392    FIELD(L1_TM_CDR12, CDRLF_RESET_ON_INT_MAX_2OL, 6, 1)
4393    FIELD(L1_TM_CDR12, CDRLF_RESET_ON_MODE_CHG, 5, 1)
4394    FIELD(L1_TM_CDR12, FFL_PH7_INT_GAIN, 0, 5)
4395REG32(L1_TM_CDR13, 0x5c34)
4396    FIELD(L1_TM_CDR13, TM_CDR13_31_8_RSVD, 24, 8)
4397    FIELD(L1_TM_CDR13, FFL_TIME_PER_PHASE_7_0, 0, 8)
4398REG32(L1_TM_CDR14, 0x5c38)
4399    FIELD(L1_TM_CDR14, TM_CDR14_31_8_RSVD, 24, 8)
4400    FIELD(L1_TM_CDR14, FFL_PH3_POST_INT_GAIN, 6, 2)
4401    FIELD(L1_TM_CDR14, FFL_PH2_POST_INT_GAIN, 4, 2)
4402    FIELD(L1_TM_CDR14, FFL_PH1_POST_INT_GAIN, 2, 2)
4403    FIELD(L1_TM_CDR14, FFL_PH0_POST_INT_GAIN, 0, 2)
4404REG32(L1_TM_CDR15, 0x5c3c)
4405    FIELD(L1_TM_CDR15, TM_CDR15_31_8_RSVD, 24, 8)
4406    FIELD(L1_TM_CDR15, FFL_PH7_POST_INT_GAIN, 6, 2)
4407    FIELD(L1_TM_CDR15, FFL_PH6_POST_INT_GAIN, 4, 2)
4408    FIELD(L1_TM_CDR15, FFL_PH5_POST_INT_GAIN, 2, 2)
4409    FIELD(L1_TM_CDR15, FFL_PH4_POST_INT_GAIN, 0, 2)
4410REG32(L1_TM_CDR16, 0x5c40)
4411    FIELD(L1_TM_CDR16, TM_CDR16_31_8_RSVD, 24, 8)
4412    FIELD(L1_TM_CDR16, UNUSED, 5, 3)
4413    FIELD(L1_TM_CDR16, FFL_PH0_PROP_GAIN, 0, 5)
4414REG32(L1_TM_CDR17, 0x5c44)
4415    FIELD(L1_TM_CDR17, TM_CDR17_31_8_RSVD, 24, 8)
4416    FIELD(L1_TM_CDR17, UNUSED, 5, 3)
4417    FIELD(L1_TM_CDR17, FFL_PH1_PROP_GAIN, 0, 5)
4418REG32(L1_TM_CDR18, 0x5c48)
4419    FIELD(L1_TM_CDR18, TM_CDR18_31_8_RSVD, 24, 8)
4420    FIELD(L1_TM_CDR18, UNUSED, 5, 3)
4421    FIELD(L1_TM_CDR18, FFL_PH2_PROP_GAIN, 0, 5)
4422REG32(L1_TM_CDR19, 0x5c4c)
4423    FIELD(L1_TM_CDR19, TM_CDR19_31_8_RSVD, 24, 8)
4424    FIELD(L1_TM_CDR19, UNUSED, 5, 3)
4425    FIELD(L1_TM_CDR19, FFL_PH3_PROP_GAIN, 0, 5)
4426REG32(L1_TM_CDR20, 0x5c50)
4427    FIELD(L1_TM_CDR20, TM_CDR20_31_8_RSVD, 24, 8)
4428    FIELD(L1_TM_CDR20, UNUSED, 5, 3)
4429    FIELD(L1_TM_CDR20, FFL_PH4_PROP_GAIN, 0, 5)
4430REG32(L1_TM_CDR21, 0x5c54)
4431    FIELD(L1_TM_CDR21, TM_CDR21_31_8_RSVD, 24, 8)
4432    FIELD(L1_TM_CDR21, UNUSED, 5, 3)
4433    FIELD(L1_TM_CDR21, FFL_PH5_PROP_GAIN, 0, 5)
4434REG32(L1_TM_CDR22, 0x5c58)
4435    FIELD(L1_TM_CDR22, TM_CDR22_31_8_RSVD, 24, 8)
4436    FIELD(L1_TM_CDR22, UNUSED, 5, 3)
4437    FIELD(L1_TM_CDR22, FFL_PH6_PROP_GAIN, 0, 5)
4438REG32(L1_TM_CDR23, 0x5c5c)
4439    FIELD(L1_TM_CDR23, TM_CDR23_31_8_RSVD, 24, 8)
4440    FIELD(L1_TM_CDR23, UNUSED, 7, 1)
4441    FIELD(L1_TM_CDR23, PHASE_LAG_LEAD_RESPONSE, 5, 2)
4442    FIELD(L1_TM_CDR23, FFL_PH7_PROP_GAIN, 0, 5)
4443REG32(L1_TM_MISC0, 0x5c60)
4444    FIELD(L1_TM_MISC0, TM_MISC0_31_8_RSVD, 24, 8)
4445    FIELD(L1_TM_MISC0, UNUSED, 2, 6)
4446    FIELD(L1_TM_MISC0, DBG0_SEL, 0, 2)
4447REG32(L1_TM_HSRX_ST0, 0x5c64)
4448    FIELD(L1_TM_HSRX_ST0, TM_HSRX_ST0_31_8_RSVD, 24, 8)
4449    FIELD(L1_TM_HSRX_ST0, FAST_LOCK_STATUS, 0, 1)
4450REG32(L1_TM_PLL_LS_CLOCK, 0x6000)
4451    FIELD(L1_TM_PLL_LS_CLOCK, TM_PLL_LS_CLOCK_31_8_RSVD, 24, 8)
4452    FIELD(L1_TM_PLL_LS_CLOCK, TM_PLL_LS_CLOCK, 0, 8)
4453REG32(L1_TM_PLL_LOOP_FILT, 0x6004)
4454    FIELD(L1_TM_PLL_LOOP_FILT, TM_PLL_LOOP_FILT_31_8_RSVD, 24, 8)
4455    FIELD(L1_TM_PLL_LOOP_FILT, TM_FORCE_RES_SW_ON, 7, 1)
4456    FIELD(L1_TM_PLL_LOOP_FILT, TM_MPHY_USB3_R2_HIGH_RES_SW_ON, 6, 1)
4457    FIELD(L1_TM_PLL_LOOP_FILT, TM_MPHY_USB3_R2_LOW_RES_SW_ON, 5, 1)
4458    FIELD(L1_TM_PLL_LOOP_FILT, TM_PCIE_R1_DEFAULT_RES_SW_ON, 4, 1)
4459    FIELD(L1_TM_PLL_LOOP_FILT, TM_PCIE_R1_HIGH_RES_SW_ON, 3, 1)
4460    FIELD(L1_TM_PLL_LOOP_FILT, TM_PCIE_R1_LOW_RES_SW_ON, 2, 1)
4461    FIELD(L1_TM_PLL_LOOP_FILT, TM_BYPASS_SEC_LOOP_FILTER, 1, 1)
4462    FIELD(L1_TM_PLL_LOOP_FILT, TM_SEC_LOOP, 0, 1)
4463REG32(L1_TM_PLL_DIG2, 0x6008)
4464    FIELD(L1_TM_PLL_DIG2, TM_PLL_DIG2_31_8_RSVD, 24, 8)
4465    FIELD(L1_TM_PLL_DIG2, TM_FBDIV_0_LSB, 7, 1)
4466    FIELD(L1_TM_PLL_DIG2, TM_PLL_HS_CLOCK_0, 0, 7)
4467REG32(L1_TM_PLL_FBDIV, 0x600c)
4468    FIELD(L1_TM_PLL_FBDIV, TM_PLL_FBDIV_31_8_RSVD, 24, 8)
4469    FIELD(L1_TM_PLL_FBDIV, TM_FBDIV_1, 0, 8)
4470REG32(L1_TM_PLL_DIG4, 0x6010)
4471    FIELD(L1_TM_PLL_DIG4, TM_PLL_DIG4_31_8_RSVD, 24, 8)
4472    FIELD(L1_TM_PLL_DIG4, TM_VCO_CLOCK_PULDN, 7, 1)
4473    FIELD(L1_TM_PLL_DIG4, TM_FORCE_ANA_COARSEDONE, 6, 1)
4474    FIELD(L1_TM_PLL_DIG4, TM_ANA_COARSEDONE, 5, 1)
4475    FIELD(L1_TM_PLL_DIG4, TM_FORCE_COARSE_DONE_INT, 4, 1)
4476    FIELD(L1_TM_PLL_DIG4, TM_COARSE_DONE_INT, 3, 1)
4477    FIELD(L1_TM_PLL_DIG4, TM_FORCE_FBDIV, 2, 1)
4478    FIELD(L1_TM_PLL_DIG4, TM_FBDIV_2, 0, 2)
4479REG32(L1_TM_PLL_DIG5, 0x6014)
4480    FIELD(L1_TM_PLL_DIG5, TM_PLL_DIG5_31_8_RSVD, 24, 8)
4481    FIELD(L1_TM_PLL_DIG5, TM_PD_6GHZ_LOWNOISE_RING, 7, 1)
4482    FIELD(L1_TM_PLL_DIG5, TM_PD_6GHZ_RING, 6, 1)
4483    FIELD(L1_TM_PLL_DIG5, TM_COARSE_PROG, 1, 5)
4484    FIELD(L1_TM_PLL_DIG5, TM_FORCE_VCO_CLOCK_PULDN, 0, 1)
4485REG32(L1_TM_PLL_DIG6, 0x6018)
4486    FIELD(L1_TM_PLL_DIG6, TM_PLL_DIG6_31_8_RSVD, 24, 8)
4487    FIELD(L1_TM_PLL_DIG6, TM_CONFG_CHNG_CYCLES_0_LSB, 7, 1)
4488    FIELD(L1_TM_PLL_DIG6, TM_VCO_SETTLE_CYCLES, 5, 2)
4489    FIELD(L1_TM_PLL_DIG6, TM_INITIAL_WAIT_CYCLES, 3, 2)
4490    FIELD(L1_TM_PLL_DIG6, TM_FORCE_COARSE_PROG_PD_RING, 2, 1)
4491    FIELD(L1_TM_PLL_DIG6, TM_PD_1P5GHZ_RING, 1, 1)
4492    FIELD(L1_TM_PLL_DIG6, TM_PD_3GHZ_RING, 0, 1)
4493REG32(L1_TM_PLL_DIG7, 0x601c)
4494    FIELD(L1_TM_PLL_DIG7, TM_PLL_DIG7_31_8_RSVD, 24, 8)
4495    FIELD(L1_TM_PLL_DIG7, TM_CPUMP_CODE_0_LSB, 7, 1)
4496    FIELD(L1_TM_PLL_DIG7, TM_FORCE_ANA_START_LOOP, 6, 1)
4497    FIELD(L1_TM_PLL_DIG7, TM_ANA_START_LOOP, 5, 1)
4498    FIELD(L1_TM_PLL_DIG7, TM_PLL_LOCK_CYCLES, 3, 2)
4499    FIELD(L1_TM_PLL_DIG7, TM_STAND_BY_SETTLE_CYCLES, 1, 2)
4500    FIELD(L1_TM_PLL_DIG7, TM_CONFG_CHNG_CYCLES_1_MSB, 0, 1)
4501REG32(L1_TM_PLL_CPUMP_CODE_1, 0x6020)
4502    FIELD(L1_TM_PLL_CPUMP_CODE_1, TM_PLL_CPUMP_CODE_1_31_8_RSVD, 24, 8)
4503    FIELD(L1_TM_PLL_CPUMP_CODE_1, TM_CPUMP_CODE_1, 0, 8)
4504REG32(L1_TM_PLL_DIG9, 0x6024)
4505    FIELD(L1_TM_PLL_DIG9, TM_PLL_DIG9_31_8_RSVD, 24, 8)
4506    FIELD(L1_TM_PLL_DIG9, TM_PLL_RSVD, 6, 2)
4507    FIELD(L1_TM_PLL_DIG9, TM_FB_BY2_BYPASS, 5, 1)
4508    FIELD(L1_TM_PLL_DIG9, TM_FORCE_CP_CODE, 4, 1)
4509    FIELD(L1_TM_PLL_DIG9, TM_CPUMP_CODE_2_MSB, 0, 4)
4510REG32(L1_TM_PLL_COARSE_CODE_LSB, 0x6028)
4511    FIELD(L1_TM_PLL_COARSE_CODE_LSB, TM_PLL_COARSE_CODE_LSB_31_8_RSVD, 24, 8)
4512    FIELD(L1_TM_PLL_COARSE_CODE_LSB, TM_COARSE_CODE_LSB, 0, 8)
4513REG32(L1_TM_PLL_DIG11, 0x602c)
4514    FIELD(L1_TM_PLL_DIG11, TM_PLL_DIG11_31_8_RSVD, 24, 8)
4515    FIELD(L1_TM_PLL_DIG11, TM_CONST_NDAC_CNTRL, 4, 4)
4516    FIELD(L1_TM_PLL_DIG11, TM_FORCE_COARSE_CODE, 3, 1)
4517    FIELD(L1_TM_PLL_DIG11, TM_COARSE_CODE_MSB, 0, 3)
4518REG32(L1_TM_PLL_DIG12, 0x6030)
4519    FIELD(L1_TM_PLL_DIG12, TM_PLL_DIG12_31_8_RSVD, 24, 8)
4520    FIELD(L1_TM_PLL_DIG12, TM_FORCE_PTAT_NDAC_CNTRL, 7, 1)
4521    FIELD(L1_TM_PLL_DIG12, TM_PTAT_NDAC_CNTRL, 1, 6)
4522    FIELD(L1_TM_PLL_DIG12, TM_FORCE_CONST_NDAC_CNTRL, 0, 1)
4523REG32(L1_TM_PLL_CONST_PMOS, 0x6034)
4524    FIELD(L1_TM_PLL_CONST_PMOS, TM_PLL_CONST_PMOS_31_8_RSVD, 24, 8)
4525    FIELD(L1_TM_PLL_CONST_PMOS, TM_CONST_PMOS_CNTRL, 0, 8)
4526REG32(L1_TM_PLL_DIG14, 0x6038)
4527    FIELD(L1_TM_PLL_DIG14, TM_PLL_DIG14_31_8_RSVD, 24, 8)
4528    FIELD(L1_TM_PLL_DIG14, TM_COARSE_CODE_AFTER_V2I_0_LSB, 1, 7)
4529    FIELD(L1_TM_PLL_DIG14, TM_FORCE_CONST_PMOS_CNTRL, 0, 1)
4530REG32(L1_TM_PLL_DIG15, 0x603c)
4531    FIELD(L1_TM_PLL_DIG15, TM_PLL_DIG15_31_8_RSVD, 24, 8)
4532    FIELD(L1_TM_PLL_DIG15, TM_V2I_CODE_0_LSB, 5, 3)
4533    FIELD(L1_TM_PLL_DIG15, TM_FORCE_COARSE_CODE_AFTER_V2I, 4, 1)
4534    FIELD(L1_TM_PLL_DIG15, TM_COARSE_CODE_AFTER_V2I_1_MSB, 0, 4)
4535REG32(L1_TM_PLL_DIG16, 0x6040)
4536    FIELD(L1_TM_PLL_DIG16, TM_PLL_DIG16_31_8_RSVD, 24, 8)
4537    FIELD(L1_TM_PLL_DIG16, TM_FORCE_PLL_LOCK, 7, 1)
4538    FIELD(L1_TM_PLL_DIG16, TM_PLL_LOCK, 6, 1)
4539    FIELD(L1_TM_PLL_DIG16, TM_FORCE_SS_NO_STEPS_STEP_SIZE, 5, 1)
4540    FIELD(L1_TM_PLL_DIG16, TM_PLL_RSVD, 4, 1)
4541    FIELD(L1_TM_PLL_DIG16, TM_FORCE_V2I_CODE, 3, 1)
4542    FIELD(L1_TM_PLL_DIG16, TM_V2I_CODE_1_MSB, 0, 3)
4543REG32(L1_TM_PLL_DIG17, 0x6044)
4544    FIELD(L1_TM_PLL_DIG17, TM_PLL_DIG17_31_8_RSVD, 24, 8)
4545    FIELD(L1_TM_PLL_DIG17, TM_FB_CLK, 6, 2)
4546    FIELD(L1_TM_PLL_DIG17, TM_MODE_DEPTH, 3, 3)
4547    FIELD(L1_TM_PLL_DIG17, TM_MODE_RATE, 0, 3)
4548REG32(L1_TM_PLL_DIG18, 0x6048)
4549    FIELD(L1_TM_PLL_DIG18, TM_PLL_DIG18_31_8_RSVD, 24, 8)
4550    FIELD(L1_TM_PLL_DIG18, TM_PLL_LOCK_PULDN, 7, 1)
4551    FIELD(L1_TM_PLL_DIG18, TM_STEP_SIZE_CNTRL, 5, 2)
4552    FIELD(L1_TM_PLL_DIG18, TM_SD_GSHIFT, 3, 2)
4553    FIELD(L1_TM_PLL_DIG18, TM_SD_DITHER, 1, 2)
4554    FIELD(L1_TM_PLL_DIG18, TM_PLL_LOCK_INT, 0, 1)
4555REG32(L1_TM_PLL_DIG19, 0x604c)
4556    FIELD(L1_TM_PLL_DIG19, TM_PLL_DIG19_31_8_RSVD, 24, 8)
4557    FIELD(L1_TM_PLL_DIG19, TM_FORCE_EN_CLOCK_HS_DIV_2, 7, 1)
4558    FIELD(L1_TM_PLL_DIG19, TM_EN_CLOCK_HS_DIV_2, 6, 1)
4559    FIELD(L1_TM_PLL_DIG19, TM_PLL_HS_CLOCK_1, 3, 3)
4560    FIELD(L1_TM_PLL_DIG19, TM_PD_PFD, 2, 1)
4561    FIELD(L1_TM_PLL_DIG19, TM_FORCE_PD_PFD, 1, 1)
4562    FIELD(L1_TM_PLL_DIG19, TM_SELECT_PCI_2P5, 0, 1)
4563REG32(L1_TM_PLL_DIG20, 0x6050)
4564    FIELD(L1_TM_PLL_DIG20, TM_PLL_DIG20_31_8_RSVD, 24, 8)
4565    FIELD(L1_TM_PLL_DIG20, TM_PLL_HALF_FULL_RATE, 7, 1)
4566    FIELD(L1_TM_PLL_DIG20, TM_PLL_RSVD, 6, 1)
4567    FIELD(L1_TM_PLL_DIG20, TM_V2I_PROG, 1, 5)
4568    FIELD(L1_TM_PLL_DIG20, TM_FORCE_V2I_PROG, 0, 1)
4569REG32(L1_TM_PLL_DIG21, 0x6054)
4570    FIELD(L1_TM_PLL_DIG21, TM_PLL_DIG21_31_8_RSVD, 24, 8)
4571    FIELD(L1_TM_PLL_DIG21, TM_FORCE_EN_PLL_LDO_0P9_REF, 7, 1)
4572    FIELD(L1_TM_PLL_DIG21, ANA_TM_EN_PLL_0P9_FORCE_SW, 6, 1)
4573    FIELD(L1_TM_PLL_DIG21, TM_PLL_PD_OPDIV_SYM, 5, 1)
4574    FIELD(L1_TM_PLL_DIG21, TM_FORCE_PLL_PD_OPDIV_SYM, 4, 1)
4575    FIELD(L1_TM_PLL_DIG21, TM_PLL_RSVD_1, 3, 1)
4576    FIELD(L1_TM_PLL_DIG21, TM_PLL_RSVD_2, 2, 1)
4577    FIELD(L1_TM_PLL_DIG21, TM_PLL_EN, 1, 1)
4578    FIELD(L1_TM_PLL_DIG21, TM_FORCE_PLL_EN, 0, 1)
4579REG32(L1_TM_PLL_DIG22, 0x6058)
4580    FIELD(L1_TM_PLL_DIG22, TM_PLL_DIG22_31_8_RSVD, 24, 8)
4581    FIELD(L1_TM_PLL_DIG22, TM_PLL_RSVD, 7, 1)
4582    FIELD(L1_TM_PLL_DIG22, TM_EN_PLL_LDO_0P9_REF_CP, 6, 1)
4583    FIELD(L1_TM_PLL_DIG22, TM_FORCE_EN_PLL_LDO_0P9_REF_CP, 5, 1)
4584    FIELD(L1_TM_PLL_DIG22, TM_FORCE_COARSE_START, 4, 1)
4585    FIELD(L1_TM_PLL_DIG22, TM_FORCE_PD_PLL_LDO_1P4, 3, 1)
4586    FIELD(L1_TM_PLL_DIG22, TM_FORCE_ANA_EN_LL_DELAYED, 2, 1)
4587    FIELD(L1_TM_PLL_DIG22, TM_FORCE_ANA_EN_LL, 1, 1)
4588    FIELD(L1_TM_PLL_DIG22, TM_EN_PLL_LDO_0P9_REF, 0, 1)
4589REG32(L1_TM_PLL_DIG23, 0x605c)
4590    FIELD(L1_TM_PLL_DIG23, TM_PLL_DIG23_31_8_RSVD, 24, 8)
4591    FIELD(L1_TM_PLL_DIG23, BF_7, 7, 1)
4592    FIELD(L1_TM_PLL_DIG23, PLL_TM_VCO_LDO_BYPASS, 6, 1)
4593    FIELD(L1_TM_PLL_DIG23, TM_ANA_EN_LL_DELAYED, 5, 1)
4594    FIELD(L1_TM_PLL_DIG23, TM_ANA_EN_LL, 4, 1)
4595    FIELD(L1_TM_PLL_DIG23, TM_ANA_PD_PLL, 3, 1)
4596    FIELD(L1_TM_PLL_DIG23, TM_FORCE_PLL_PD, 2, 1)
4597    FIELD(L1_TM_PLL_DIG23, TM_ANA_COARSE_START, 1, 1)
4598    FIELD(L1_TM_PLL_DIG23, TM_PD_PLL_LDO_1P4, 0, 1)
4599REG32(L1_TM_PLL_DIG24, 0x6060)
4600    FIELD(L1_TM_PLL_DIG24, TM_PLL_DIG24_31_8_RSVD, 24, 8)
4601    FIELD(L1_TM_PLL_DIG24, TM_PLL_RSVD, 7, 1)
4602    FIELD(L1_TM_PLL_DIG24, PLL_TM_VCO_LDO, 1, 6)
4603    FIELD(L1_TM_PLL_DIG24, PLL_TM_VCO_LDO_BYPASS_WITH_SEQUENCE, 0, 1)
4604REG32(L1_TM_PLL_DIG25, 0x6064)
4605    FIELD(L1_TM_PLL_DIG25, TM_PLL_DIG25_31_8_RSVD, 24, 8)
4606    FIELD(L1_TM_PLL_DIG25, TM_FORCE_RST_N_HSRIPPLE, 7, 1)
4607    FIELD(L1_TM_PLL_DIG25, TM_RST_N_HSRIPPLE, 6, 1)
4608    FIELD(L1_TM_PLL_DIG25, TM_PLL_ATB_CNTRL, 1, 5)
4609    FIELD(L1_TM_PLL_DIG25, TM_PLL_OBSERVE_PTAT_10U, 0, 1)
4610REG32(L1_TM_PLL_DIG26, 0x6068)
4611    FIELD(L1_TM_PLL_DIG26, TM_PLL_DIG26_31_8_RSVD, 24, 8)
4612    FIELD(L1_TM_PLL_DIG26, TM_PLL_RSVD, 7, 1)
4613    FIELD(L1_TM_PLL_DIG26, TM_PD_PLL_PTAT, 6, 1)
4614    FIELD(L1_TM_PLL_DIG26, TM_FORCE_PD_PLL_PTAT, 5, 1)
4615    FIELD(L1_TM_PLL_DIG26, TM_USB3_R2_HIGH_RES_SW_ON, 4, 1)
4616    FIELD(L1_TM_PLL_DIG26, TM_PLL_SEL_VCO_DIV2_LOOP_OUT, 3, 1)
4617    FIELD(L1_TM_PLL_DIG26, TM_PLL_SEL_VCO_DIRECT_LOOP_OUT, 2, 1)
4618    FIELD(L1_TM_PLL_DIG26, TM_PLL_SEL_VCO_HISPEED_DIV2_LOOP_OUT, 1, 1)
4619    FIELD(L1_TM_PLL_DIG26, TM_FORCE_LOOP_PATH, 0, 1)
4620REG32(L1_TM_PLL_CLK_DIST_NTRIM_LSB, 0x606c)
4621    FIELD(L1_TM_PLL_CLK_DIST_NTRIM_LSB, TM_PLL_CLK_DIST_NTRIM_LSB_31_8_RSVD, 24, 8)
4622    FIELD(L1_TM_PLL_CLK_DIST_NTRIM_LSB, TM_CLKDIST_BIAS_NTRIM_LSB, 0, 8)
4623REG32(L1_TM_PLL_CLK_DIST_PTRIM_LSB, 0x6070)
4624    FIELD(L1_TM_PLL_CLK_DIST_PTRIM_LSB, TM_PLL_CLK_DIST_PTRIM_LSB_31_8_RSVD, 24, 8)
4625    FIELD(L1_TM_PLL_CLK_DIST_PTRIM_LSB, TM_CLKDIST_BIAS_PTRIM_LSB, 0, 8)
4626REG32(L1_TM_PLL_DIG_29, 0x6074)
4627    FIELD(L1_TM_PLL_DIG_29, TM_PLL_DIG_29_31_8_RSVD, 24, 8)
4628    FIELD(L1_TM_PLL_DIG_29, TM_CLKDIST_OBSRV_MRSTBUF_SUP, 7, 1)
4629    FIELD(L1_TM_PLL_DIG_29, TM_CLKDIST_OBSRV_LRSTBUF_SUP, 6, 1)
4630    FIELD(L1_TM_PLL_DIG_29, TM_CLKDIST_ENABLE_RST_RPTR, 5, 1)
4631    FIELD(L1_TM_PLL_DIG_29, TM_FORCE_CLKDIST_ENABLE_RST_RPTR, 4, 1)
4632    FIELD(L1_TM_PLL_DIG_29, TM_CLKDIST_ENABLE_CLK_RPTR, 3, 1)
4633    FIELD(L1_TM_PLL_DIG_29, TM_FORCE_CLKDIST_ENABLE_CLK_RPTR, 2, 1)
4634    FIELD(L1_TM_PLL_DIG_29, TM_CLKDIST_BIAS_PTRIM_MSB, 1, 1)
4635    FIELD(L1_TM_PLL_DIG_29, TM_CLKDIST_BIAS_NTRIM_MSB, 0, 1)
4636REG32(L1_TM_PLL_DIG_30, 0x6078)
4637    FIELD(L1_TM_PLL_DIG_30, TM_PLL_DIG_30_31_8_RSVD, 24, 8)
4638    FIELD(L1_TM_PLL_DIG_30, TM_CLKDIST_ENABLE_BIAS, 7, 1)
4639    FIELD(L1_TM_PLL_DIG_30, TM_FORCE_CLKDIST_ENABLE_BIAS, 6, 1)
4640    FIELD(L1_TM_PLL_DIG_30, TM_CLKDIST_ENABLE_CMN_BIAS, 5, 1)
4641    FIELD(L1_TM_PLL_DIG_30, TM_FORCE_CLKDIST_ENABLE_CMN_BIAS, 4, 1)
4642    FIELD(L1_TM_PLL_DIG_30, TM_CLKDIST_SUP_OBSRV, 3, 1)
4643    FIELD(L1_TM_PLL_DIG_30, TM_CLKDIST_OBSRV_RSTMUX_SUP, 2, 1)
4644    FIELD(L1_TM_PLL_DIG_30, TM_CLKDIST_OBSRV_RPTR_RSTBUF_SUP, 1, 1)
4645    FIELD(L1_TM_PLL_DIG_30, TM_CLKDIST_OBSRV_MUS_SUP, 0, 1)
4646REG32(L1_TM_PLL_DIG_31, 0x607c)
4647    FIELD(L1_TM_PLL_DIG_31, TM_PLL_DIG_31_31_8_RSVD, 24, 8)
4648    FIELD(L1_TM_PLL_DIG_31, TM_CLKDIST_ENABLE_MASTER_CLK_DRIVE, 7, 1)
4649    FIELD(L1_TM_PLL_DIG_31, TM_FORCE_CLKDIST_ENABLE_MASTER_CLK_DRIVE, 6, 1)
4650    FIELD(L1_TM_PLL_DIG_31, TM_CLKDIST_ENABLE_LANE_RST_DRIVE, 5, 1)
4651    FIELD(L1_TM_PLL_DIG_31, TM_FORCE_CLKDIST_ENABLE_LANE_RST_DRIVE, 4, 1)
4652    FIELD(L1_TM_PLL_DIG_31, TM_CLKDIST_ENABLE_LANE_CLK_DRIVE, 3, 1)
4653    FIELD(L1_TM_PLL_DIG_31, TM_FORCE_CLKDIST_ENABLE_LANE_CLK_DRIVE, 2, 1)
4654    FIELD(L1_TM_PLL_DIG_31, TM_CLKDIST_BIAS_RATE_SEL, 1, 1)
4655    FIELD(L1_TM_PLL_DIG_31, TM_FORCE_CLKDIST_BIAS_RATE_SEL, 0, 1)
4656REG32(L1_TM_PLL_DIG_32, 0x6080)
4657    FIELD(L1_TM_PLL_DIG_32, TM_PLL_DIG_32_31_8_RSVD, 24, 8)
4658    FIELD(L1_TM_PLL_DIG_32, TM_CLKDIST_MUX_XVCR_CLK_EN, 7, 1)
4659    FIELD(L1_TM_PLL_DIG_32, TM_FORCE_CLKDIST_MUX_XVCR_CLK_EN, 6, 1)
4660    FIELD(L1_TM_PLL_DIG_32, TM_FORCE_LOAD_FBDIV, 5, 1)
4661    FIELD(L1_TM_PLL_DIG_32, TM_LOAD_FBDIV, 4, 1)
4662    FIELD(L1_TM_PLL_DIG_32, TM_FORCE_RST_FDBK_DIV, 3, 1)
4663    FIELD(L1_TM_PLL_DIG_32, TM_RST_FDBK_DIV, 2, 1)
4664    FIELD(L1_TM_PLL_DIG_32, TM_CLKDIST_ENABLE_MASTER_RST_DRIVE, 1, 1)
4665    FIELD(L1_TM_PLL_DIG_32, TM_FORCE_CLKDIST_ENABLE_MASTER_RST_DRIVE, 0, 1)
4666REG32(L1_TM_PLL_DIG_33, 0x6084)
4667    FIELD(L1_TM_PLL_DIG_33, TM_PLL_DIG_33_31_8_RSVD, 24, 8)
4668    FIELD(L1_TM_PLL_DIG_33, TM_FORCE_TX_CLK_RST_REL, 7, 1)
4669    FIELD(L1_TM_PLL_DIG_33, TM_TX_CLK_RST_REL, 6, 1)
4670    FIELD(L1_TM_PLL_DIG_33, TM_CLKDIST_MUX_XCVR_MASTER_RST_EN, 5, 1)
4671    FIELD(L1_TM_PLL_DIG_33, TM_FORCE_CLKDIST_MUX_XCVR_MASTER_RST_EN, 4, 1)
4672    FIELD(L1_TM_PLL_DIG_33, TM_CLKDIST_MUX_MASTER_CLK_SEL, 3, 1)
4673    FIELD(L1_TM_PLL_DIG_33, TM_FORCE_CLKDIST_MUX_MASTER_CLK_SEL, 2, 1)
4674    FIELD(L1_TM_PLL_DIG_33, TM_CLKDIST_MUX_LOCAL_CLK_SEL, 1, 1)
4675    FIELD(L1_TM_PLL_DIG_33, TM_FORCE_CLKDIST_MUX_LOCAL_CLK_SEL, 0, 1)
4676REG32(L1_TM_PLL_DIG_34, 0x6088)
4677    FIELD(L1_TM_PLL_DIG_34, TM_PLL_DIG_34_31_8_RSVD, 24, 8)
4678    FIELD(L1_TM_PLL_DIG_34, TM_PLL_RSVD, 7, 1)
4679    FIELD(L1_TM_PLL_DIG_34, TM_FBDIV_3_MSB, 2, 5)
4680    FIELD(L1_TM_PLL_DIG_34, TM_SEL_VCO_OUT, 1, 1)
4681    FIELD(L1_TM_PLL_DIG_34, TM_FORCE_SEL_VCO_OUT, 0, 1)
4682REG32(L1_TM_PLL_DIG_35, 0x608c)
4683    FIELD(L1_TM_PLL_DIG_35, TM_PLL_DIG_35_31_8_RSVD, 24, 8)
4684    FIELD(L1_TM_PLL_DIG_35, TM_CLKDIST_BIAS_SPARE, 6, 2)
4685    FIELD(L1_TM_PLL_DIG_35, TM_CLKDIST_DRVR_SPARE, 4, 2)
4686    FIELD(L1_TM_PLL_DIG_35, TM_CLKDIST_MUX_SPARE, 2, 2)
4687    FIELD(L1_TM_PLL_DIG_35, TM_CLKDIST_RPTR_SPARE, 0, 2)
4688REG32(L1_TM_PLL_DIG_36, 0x6090)
4689    FIELD(L1_TM_PLL_DIG_36, TM_PLL_DIG_36_31_8_RSVD, 24, 8)
4690    FIELD(L1_TM_PLL_DIG_36, CLKDIST_BIAS_SPARE, 6, 2)
4691    FIELD(L1_TM_PLL_DIG_36, CLKDIST_DRVR_SPARE, 4, 2)
4692    FIELD(L1_TM_PLL_DIG_36, CLKDIST_MUX_SPARE, 2, 2)
4693    FIELD(L1_TM_PLL_DIG_36, CLKDIST_RPTR_SPARE, 0, 2)
4694REG32(L1_TM_PLL_DIG_37, 0x6094)
4695    FIELD(L1_TM_PLL_DIG_37, TM_PLL_DIG_37_31_8_RSVD, 24, 8)
4696    FIELD(L1_TM_PLL_DIG_37, TM_COARSE_CODE_SAT_VALUE_LSB, 5, 3)
4697    FIELD(L1_TM_PLL_DIG_37, TM_ENABLE_COARSE_SATURATION, 4, 1)
4698    FIELD(L1_TM_PLL_DIG_37, W_SPARE_OUTPUTS, 2, 2)
4699    FIELD(L1_TM_PLL_DIG_37, TM_FORCE_EN_IP_DIV_BYPASS, 1, 1)
4700    FIELD(L1_TM_PLL_DIG_37, TM_EN_IP_DIV_BYPASS, 0, 1)
4701REG32(L1_TM_PLL_COARSE_CODE_SAT_MSB, 0x6098)
4702    FIELD(L1_TM_PLL_COARSE_CODE_SAT_MSB, TM_PLL_COARSE_CODE_SAT_MSB_31_8_RSVD, 24, 8)
4703    FIELD(L1_TM_PLL_COARSE_CODE_SAT_MSB, TM_COARSE_CODE_SAT_VALUE_MSB, 0, 8)
4704REG32(L1_MPHY_CFG_HIB8, 0x6300)
4705    FIELD(L1_MPHY_CFG_HIB8, MPHY_CFG_HIB8_31_8_RSVD, 24, 8)
4706    FIELD(L1_MPHY_CFG_HIB8, MPHY_HIBERN8_RSVD, 1, 7)
4707    FIELD(L1_MPHY_CFG_HIB8, MPHY_HIBERN8, 0, 1)
4708REG32(L1_MPHY_CFG_MODE, 0x6304)
4709    FIELD(L1_MPHY_CFG_MODE, MPHY_CFG_MODE_31_8_RSVD, 24, 8)
4710    FIELD(L1_MPHY_CFG_MODE, MPHY_HS_LS_MODE_RSVD, 2, 6)
4711    FIELD(L1_MPHY_CFG_MODE, MPHY_HS_LS_MODE, 0, 2)
4712REG32(L1_MPHY_CFG_HS_GEAR, 0x6308)
4713    FIELD(L1_MPHY_CFG_HS_GEAR, MPHY_CFG_HS_GEAR_31_8_RSVD, 24, 8)
4714    FIELD(L1_MPHY_CFG_HS_GEAR, MPHY_HS_GEAR_RSVD, 2, 6)
4715    FIELD(L1_MPHY_CFG_HS_GEAR, MPHY_HS_GEAR, 0, 2)
4716REG32(L1_MPHY_CFG_HS_RATE, 0x630c)
4717    FIELD(L1_MPHY_CFG_HS_RATE, MPHY_CFG_HS_RATE_31_8_RSVD, 24, 8)
4718    FIELD(L1_MPHY_CFG_HS_RATE, MPHY_RATE_RSVD, 1, 7)
4719    FIELD(L1_MPHY_CFG_HS_RATE, MPHY_RATE, 0, 1)
4720REG32(L1_MPHY_CFG_PWM, 0x6310)
4721    FIELD(L1_MPHY_CFG_PWM, MPHY_CFG_PWM_31_8_RSVD, 24, 8)
4722    FIELD(L1_MPHY_CFG_PWM, MPHY_PWM_GEAR_RSVD, 3, 5)
4723    FIELD(L1_MPHY_CFG_PWM, MPHY_PWM_GEAR, 0, 3)
4724REG32(L1_PLL_OPDIV_LS, 0x6314)
4725    FIELD(L1_PLL_OPDIV_LS, PLL_OPDIV_LS_31_8_RSVD, 24, 8)
4726    FIELD(L1_PLL_OPDIV_LS, TM_SEL_OPDIV_FOR_REFCLK, 7, 1)
4727    FIELD(L1_PLL_OPDIV_LS, ANA_OPDIV_LS, 0, 7)
4728REG32(L1_MPHY_CFG_UPDT, 0x6318)
4729    FIELD(L1_MPHY_CFG_UPDT, MPHY_CFG_UPDT_31_8_RSVD, 24, 8)
4730    FIELD(L1_MPHY_CFG_UPDT, MPHY_CFGUPDT_RSVD, 1, 7)
4731    FIELD(L1_MPHY_CFG_UPDT, MPHY_CFGUPDT, 0, 1)
4732REG32(L1_PLL_TM_DIV_CNTRLS, 0x631c)
4733    FIELD(L1_PLL_TM_DIV_CNTRLS, PLL_TM_DIV_CNTRLS_31_8_RSVD, 24, 8)
4734    FIELD(L1_PLL_TM_DIV_CNTRLS, TM_FORCE_PD_OPDIV_LS, 7, 1)
4735    FIELD(L1_PLL_TM_DIV_CNTRLS, TM_PD_OPDIV_LS, 6, 1)
4736    FIELD(L1_PLL_TM_DIV_CNTRLS, PLL_TM_DIV_CNTRLS_RSVD, 5, 1)
4737    FIELD(L1_PLL_TM_DIV_CNTRLS, TM_BYPASS_OPDIV_LS_MOD, 4, 1)
4738    FIELD(L1_PLL_TM_DIV_CNTRLS, TM_FORCE_PLL_PD_HS, 3, 1)
4739    FIELD(L1_PLL_TM_DIV_CNTRLS, TM_PLL_PD_HS, 2, 1)
4740    FIELD(L1_PLL_TM_DIV_CNTRLS, SEL_IP_MUX_CONTROL, 1, 1)
4741    FIELD(L1_PLL_TM_DIV_CNTRLS, TM_SWAP_OP_MUX_CONTROL, 0, 1)
4742REG32(L1_PLL_FBDIV_G1A_LSB, 0x6320)
4743    FIELD(L1_PLL_FBDIV_G1A_LSB, PLL_FBDIV_G1A_LSB_31_8_RSVD, 24, 8)
4744    FIELD(L1_PLL_FBDIV_G1A_LSB, FBDIV_G1A_LSB, 0, 8)
4745REG32(L1_PLL_FBDIV_G1B_LSB, 0x6324)
4746    FIELD(L1_PLL_FBDIV_G1B_LSB, PLL_FBDIV_G1B_LSB_31_8_RSVD, 24, 8)
4747    FIELD(L1_PLL_FBDIV_G1B_LSB, FBDIV_G1B_LSB, 0, 8)
4748REG32(L1_PLL_FBDIV_G2A_LSB, 0x6328)
4749    FIELD(L1_PLL_FBDIV_G2A_LSB, PLL_FBDIV_G2A_LSB_31_8_RSVD, 24, 8)
4750    FIELD(L1_PLL_FBDIV_G2A_LSB, FBDIV_G2A_LSB, 0, 8)
4751REG32(L1_PLL_FBDIV_G2B_LSB, 0x632c)
4752    FIELD(L1_PLL_FBDIV_G2B_LSB, PLL_FBDIV_G2B_LSB_31_8_RSVD, 24, 8)
4753    FIELD(L1_PLL_FBDIV_G2B_LSB, FBDIV_G2B_LSB, 0, 8)
4754REG32(L1_PLL_FBDIV_G3A_LSB, 0x6330)
4755    FIELD(L1_PLL_FBDIV_G3A_LSB, PLL_FBDIV_G3A_LSB_31_8_RSVD, 24, 8)
4756    FIELD(L1_PLL_FBDIV_G3A_LSB, FBDIV_G3A_LSB, 0, 8)
4757REG32(L1_PLL_FBDIV_G3B_LSB, 0x6334)
4758    FIELD(L1_PLL_FBDIV_G3B_LSB, PLL_FBDIV_G3B_LSB_31_8_RSVD, 24, 8)
4759    FIELD(L1_PLL_FBDIV_G3B_LSB, FBDIV_G3B_LSB, 0, 8)
4760REG32(L1_PLL_FBDIV_G1A_MSB, 0x6338)
4761    FIELD(L1_PLL_FBDIV_G1A_MSB, PLL_FBDIV_G1A_MSB_31_8_RSVD, 24, 8)
4762    FIELD(L1_PLL_FBDIV_G1A_MSB, FBDIV_G1A_MSB, 0, 8)
4763REG32(L1_PLL_FBDIV_G1B_MSB, 0x633c)
4764    FIELD(L1_PLL_FBDIV_G1B_MSB, PLL_FBDIV_G1B_MSB_31_8_RSVD, 24, 8)
4765    FIELD(L1_PLL_FBDIV_G1B_MSB, FBDIV_G1B_MSB, 0, 8)
4766REG32(L1_PLL_FBDIV_G2A_MSB, 0x6340)
4767    FIELD(L1_PLL_FBDIV_G2A_MSB, PLL_FBDIV_G2A_MSB_31_8_RSVD, 24, 8)
4768    FIELD(L1_PLL_FBDIV_G2A_MSB, FBDIV_G2A_MSB, 0, 8)
4769REG32(L1_PLL_FBDIV_G2B_MSB, 0x6344)
4770    FIELD(L1_PLL_FBDIV_G2B_MSB, PLL_FBDIV_G2B_MSB_31_8_RSVD, 24, 8)
4771    FIELD(L1_PLL_FBDIV_G2B_MSB, FBDIV_G2B_MSB, 0, 8)
4772REG32(L1_PLL_FBDIV_G3A_MSB, 0x6348)
4773    FIELD(L1_PLL_FBDIV_G3A_MSB, PLL_FBDIV_G3A_MSB_31_8_RSVD, 24, 8)
4774    FIELD(L1_PLL_FBDIV_G3A_MSB, FBDIV_G3A_MSB, 0, 8)
4775REG32(L1_PLL_FBDIV_G3B_MSB, 0x634c)
4776    FIELD(L1_PLL_FBDIV_G3B_MSB, PLL_FBDIV_G3B_MSB_31_8_RSVD, 24, 8)
4777    FIELD(L1_PLL_FBDIV_G3B_MSB, FBDIV_G3B_MSB, 0, 8)
4778REG32(L1_PLL_IPDIV, 0x6350)
4779    FIELD(L1_PLL_IPDIV, PLL_IPDIV_31_8_RSVD, 24, 8)
4780    FIELD(L1_PLL_IPDIV, PLL_IPDIV, 0, 8)
4781REG32(L1_PLL_FBDIV_FRAC_0_LSB, 0x6354)
4782    FIELD(L1_PLL_FBDIV_FRAC_0_LSB, PLL_FBDIV_FRAC_0_LSB_31_8_RSVD, 24, 8)
4783    FIELD(L1_PLL_FBDIV_FRAC_0_LSB, FBDIV_FRAC_0_LSB, 0, 8)
4784REG32(L1_PLL_FBDIV_FRAC_1, 0x6358)
4785    FIELD(L1_PLL_FBDIV_FRAC_1, PLL_FBDIV_FRAC_1_31_8_RSVD, 24, 8)
4786    FIELD(L1_PLL_FBDIV_FRAC_1, FBDIV_FRAC_1, 0, 8)
4787REG32(L1_PLL_FBDIV_FRAC_2, 0x635c)
4788    FIELD(L1_PLL_FBDIV_FRAC_2, PLL_FBDIV_FRAC_2_31_8_RSVD, 24, 8)
4789    FIELD(L1_PLL_FBDIV_FRAC_2, FBDIV_FRAC_2, 0, 8)
4790REG32(L1_PLL_FBDIV_FRAC_3_MSB, 0x6360)
4791    FIELD(L1_PLL_FBDIV_FRAC_3_MSB, PLL_FBDIV_FRAC_3_MSB_31_8_RSVD, 24, 8)
4792    FIELD(L1_PLL_FBDIV_FRAC_3_MSB, PLL_FBDIV_FRAC_3_MSV_RSVD, 7, 1)
4793    FIELD(L1_PLL_FBDIV_FRAC_3_MSB, TM_FORCE_EN_FRAC, 6, 1)
4794    FIELD(L1_PLL_FBDIV_FRAC_3_MSB, TM_EN_FRAC, 5, 1)
4795    FIELD(L1_PLL_FBDIV_FRAC_3_MSB, FBDIV_FRAC_3_MSB_RSVD, 3, 2)
4796    FIELD(L1_PLL_FBDIV_FRAC_3_MSB, FBDIV_FRAC_3_MSB, 0, 3)
4797REG32(L1_PLL_PWR_SEQ_WAIT_TIME, 0x6364)
4798    FIELD(L1_PLL_PWR_SEQ_WAIT_TIME, PLL_PWR_SEQ_WAIT_TIME_31_8_RSVD, 24, 8)
4799    FIELD(L1_PLL_PWR_SEQ_WAIT_TIME, TM_PLL_SETTLING, 6, 2)
4800    FIELD(L1_PLL_PWR_SEQ_WAIT_TIME, TM_PLL_BIAS_SETTLING, 4, 2)
4801    FIELD(L1_PLL_PWR_SEQ_WAIT_TIME, TM_LDO_SETTLING, 2, 2)
4802    FIELD(L1_PLL_PWR_SEQ_WAIT_TIME, TM_LDO_RELIABILITY, 0, 2)
4803REG32(L1_PLL_SS_STEPS_0_LSB, 0x6368)
4804    FIELD(L1_PLL_SS_STEPS_0_LSB, PLL_SS_STEPS_0_LSB_31_8_RSVD, 24, 8)
4805    FIELD(L1_PLL_SS_STEPS_0_LSB, SS_NUM_OF_STEPS_0_LSB, 0, 8)
4806REG32(L1_PLL_SS_STEPS_1_MSB, 0x636c)
4807    FIELD(L1_PLL_SS_STEPS_1_MSB, PLL_SS_STEPS_1_MSB_31_8_RSVD, 24, 8)
4808    FIELD(L1_PLL_SS_STEPS_1_MSB, SS_NUM_OF_STEPS_1_MSB_RSVD, 3, 5)
4809    FIELD(L1_PLL_SS_STEPS_1_MSB, SS_NUM_OF_STEPS_1_MSB, 0, 3)
4810REG32(L1_PLL_SS_STEP_SIZE_0_LSB, 0x6370)
4811    FIELD(L1_PLL_SS_STEP_SIZE_0_LSB, PLL_SS_STEP_SIZE_0_LSB_31_8_RSVD, 24, 8)
4812    FIELD(L1_PLL_SS_STEP_SIZE_0_LSB, SS_STEP_SIZE_0_LSB, 0, 8)
4813REG32(L1_PLL_SS_STEP_SIZE_1, 0x6374)
4814    FIELD(L1_PLL_SS_STEP_SIZE_1, PLL_SS_STEP_SIZE_1_31_8_RSVD, 24, 8)
4815    FIELD(L1_PLL_SS_STEP_SIZE_1, SS_STEP_SIZE_1, 0, 8)
4816REG32(L1_PLL_SS_STEP_SIZE_2, 0x6378)
4817    FIELD(L1_PLL_SS_STEP_SIZE_2, PLL_SS_STEP_SIZE_2_31_8_RSVD, 24, 8)
4818    FIELD(L1_PLL_SS_STEP_SIZE_2, SS_STEP_SIZE_2, 0, 8)
4819REG32(L1_PLL_SS_STEP_SIZE_3_MSB, 0x637c)
4820    FIELD(L1_PLL_SS_STEP_SIZE_3_MSB, PLL_SS_STEP_SIZE_3_MSB_31_8_RSVD, 24, 8)
4821    FIELD(L1_PLL_SS_STEP_SIZE_3_MSB, TM_FORCE_EN_SS, 7, 1)
4822    FIELD(L1_PLL_SS_STEP_SIZE_3_MSB, TM_EN_SS, 6, 1)
4823    FIELD(L1_PLL_SS_STEP_SIZE_3_MSB, FORCE_SS_NUM_OF_STEPS, 5, 1)
4824    FIELD(L1_PLL_SS_STEP_SIZE_3_MSB, FORCE_SS_STEP_SIZE, 4, 1)
4825    FIELD(L1_PLL_SS_STEP_SIZE_3_MSB, SS_SPREAD_TYPE, 2, 2)
4826    FIELD(L1_PLL_SS_STEP_SIZE_3_MSB, SS_STEP_SIZE_3_MSB, 0, 2)
4827REG32(L1_TM_MASK_CFG_UPDT, 0x6380)
4828    FIELD(L1_TM_MASK_CFG_UPDT, TM_MASK_CFG_UPDT_31_8_RSVD, 24, 8)
4829    FIELD(L1_TM_MASK_CFG_UPDT, TM_MASK_CFG_UPDT_RSVD, 7, 1)
4830    FIELD(L1_TM_MASK_CFG_UPDT, HIBERN8_MASK_CFG_UPDT, 6, 1)
4831    FIELD(L1_TM_MASK_CFG_UPDT, HS_MODE_MASK_CFG_UPDT, 5, 1)
4832    FIELD(L1_TM_MASK_CFG_UPDT, LS_MODE_MASK_CFG_UPDT, 4, 1)
4833    FIELD(L1_TM_MASK_CFG_UPDT, OPDIV_LS_MASK_CFG_UPDT, 3, 1)
4834    FIELD(L1_TM_MASK_CFG_UPDT, PWM_GEAR_MASK_CFG_UPDT, 2, 1)
4835    FIELD(L1_TM_MASK_CFG_UPDT, HS_GEAR_MASK_CFG_UPDT, 1, 1)
4836    FIELD(L1_TM_MASK_CFG_UPDT, HS_RATE_MASK_CFG_UPDT, 0, 1)
4837REG32(L1_PLL_TM_FORCE_DIV, 0x6384)
4838    FIELD(L1_PLL_TM_FORCE_DIV, PLL_TM_FORCE_DIV_31_8_RSVD, 24, 8)
4839    FIELD(L1_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_FRAC, 7, 1)
4840    FIELD(L1_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G3B, 6, 1)
4841    FIELD(L1_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G3A, 5, 1)
4842    FIELD(L1_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G2B, 4, 1)
4843    FIELD(L1_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G2A, 3, 1)
4844    FIELD(L1_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G1B, 2, 1)
4845    FIELD(L1_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G1A, 1, 1)
4846    FIELD(L1_PLL_TM_FORCE_DIV, TM_FORCE_IPDIV, 0, 1)
4847REG32(L1_PLL_TM_COARSE_CODE_1_LSB, 0x6388)
4848    FIELD(L1_PLL_TM_COARSE_CODE_1_LSB, PLL_TM_COARSE_CODE_1_LSB_31_8_RSVD, 24, 8)
4849    FIELD(L1_PLL_TM_COARSE_CODE_1_LSB, TM_COARSE_CODE_1_LSB, 0, 8)
4850REG32(L1_PLL_TM_COARSE_CODE_2_LSB, 0x638c)
4851    FIELD(L1_PLL_TM_COARSE_CODE_2_LSB, PLL_TM_COARSE_CODE_2_LSB_31_8_RSVD, 24, 8)
4852    FIELD(L1_PLL_TM_COARSE_CODE_2_LSB, TM_COARSE_CODE_2_LSB, 0, 8)
4853REG32(L1_PLL_TM_COARSE_CODE_3_LSB, 0x6390)
4854    FIELD(L1_PLL_TM_COARSE_CODE_3_LSB, PLL_TM_COARSE_CODE_3_LSB_31_8_RSVD, 24, 8)
4855    FIELD(L1_PLL_TM_COARSE_CODE_3_LSB, TM_COARSE_CODE_3_LSB, 0, 8)
4856REG32(L1_PLL_TM_COARSE_CODE_4_LSB, 0x6394)
4857    FIELD(L1_PLL_TM_COARSE_CODE_4_LSB, PLL_TM_COARSE_CODE_4_LSB_31_8_RSVD, 24, 8)
4858    FIELD(L1_PLL_TM_COARSE_CODE_4_LSB, TM_COARSE_CODE_4_LSB, 0, 8)
4859REG32(L1_PLL_TM_COARSE_CODE_5_LSB, 0x6398)
4860    FIELD(L1_PLL_TM_COARSE_CODE_5_LSB, PLL_TM_COARSE_CODE_5_LSB_31_8_RSVD, 24, 8)
4861    FIELD(L1_PLL_TM_COARSE_CODE_5_LSB, TM_COARSE_CODE_5_LSB, 0, 8)
4862REG32(L1_PLL_TM_COARSE_CODE_6_LSB, 0x639c)
4863    FIELD(L1_PLL_TM_COARSE_CODE_6_LSB, PLL_TM_COARSE_CODE_6_LSB_31_8_RSVD, 24, 8)
4864    FIELD(L1_PLL_TM_COARSE_CODE_6_LSB, TM_COARSE_CODE_6_LSB, 0, 8)
4865REG32(L1_PLL_TM_COARSE_CODE_1_2_MSB, 0x63a0)
4866    FIELD(L1_PLL_TM_COARSE_CODE_1_2_MSB, PLL_TM_COARSE_CODE_1_2_MSB_31_8_RSVD, 24, 8)
4867    FIELD(L1_PLL_TM_COARSE_CODE_1_2_MSB, TM_COARSE_CODE_G1_AB_MSB_RSVD, 6, 2)
4868    FIELD(L1_PLL_TM_COARSE_CODE_1_2_MSB, TM_COARSE_CODE_2_MSB, 3, 3)
4869    FIELD(L1_PLL_TM_COARSE_CODE_1_2_MSB, TM_COARSE_CODE_1_MSB, 0, 3)
4870REG32(L1_PLL_TM_COARSE_CODE_3_4_MSB, 0x63a4)
4871    FIELD(L1_PLL_TM_COARSE_CODE_3_4_MSB, PLL_TM_COARSE_CODE_3_4_MSB_31_8_RSVD, 24, 8)
4872    FIELD(L1_PLL_TM_COARSE_CODE_3_4_MSB, TM_COARSE_CODE_G2_AB_MSB_RSVD, 6, 2)
4873    FIELD(L1_PLL_TM_COARSE_CODE_3_4_MSB, TM_COARSE_CODE_4_MSB, 3, 3)
4874    FIELD(L1_PLL_TM_COARSE_CODE_3_4_MSB, TM_COARSE_CODE_3_MSB, 0, 3)
4875REG32(L1_PLL_TM_COARSE_CODE_5_6_MSB, 0x63a8)
4876    FIELD(L1_PLL_TM_COARSE_CODE_5_6_MSB, PLL_TM_COARSE_CODE_5_6_MSB_31_8_RSVD, 24, 8)
4877    FIELD(L1_PLL_TM_COARSE_CODE_5_6_MSB, TM_COARSE_CODE_G3_AB_MSB_RSVD, 6, 2)
4878    FIELD(L1_PLL_TM_COARSE_CODE_5_6_MSB, TM_COARSE_CODE_6_MSB, 3, 3)
4879    FIELD(L1_PLL_TM_COARSE_CODE_5_6_MSB, TM_COARSE_CODE_5_MSB, 0, 3)
4880REG32(L1_PLL_TM_SHARED_0, 0x63ac)
4881    FIELD(L1_PLL_TM_SHARED_0, PLL_TM_SHARED_0_31_8_RSVD, 24, 8)
4882    FIELD(L1_PLL_TM_SHARED_0, TM_FORCE_EXTSIGNAL_FOR_HIBERN8, 7, 1)
4883    FIELD(L1_PLL_TM_SHARED_0, TM_FORCE_REGBIT_FOR_HIBERN8, 6, 1)
4884    FIELD(L1_PLL_TM_SHARED_0, TM_FORCE_PLL_STANDBY, 5, 1)
4885    FIELD(L1_PLL_TM_SHARED_0, TM_PLL_STANDBY, 4, 1)
4886    FIELD(L1_PLL_TM_SHARED_0, TM_SLOWN_FAST_BRING_UP_ALWAYS, 3, 1)
4887    FIELD(L1_PLL_TM_SHARED_0, EN_TM_FOR_BRING_UP_SCHEME, 2, 1)
4888    FIELD(L1_PLL_TM_SHARED_0, SELECT_HS_FB_DIVIDER, 1, 1)
4889    FIELD(L1_PLL_TM_SHARED_0, TM_BYPASS_COARSE_SEARCH, 0, 1)
4890REG32(L1_PLL_TM_FRAC_OFFSET_0, 0x63b0)
4891    FIELD(L1_PLL_TM_FRAC_OFFSET_0, PLL_TM_FRAC_OFFSET_0_31_8_RSVD, 24, 8)
4892    FIELD(L1_PLL_TM_FRAC_OFFSET_0, TM_FRAC_OFFSET_LSB_0, 0, 8)
4893REG32(L1_PLL_TM_FRAC_OFFSET_1, 0x63b4)
4894    FIELD(L1_PLL_TM_FRAC_OFFSET_1, PLL_TM_FRAC_OFFSET_1_31_8_RSVD, 24, 8)
4895    FIELD(L1_PLL_TM_FRAC_OFFSET_1, TM_FRAC_OFFSET_1, 0, 8)
4896REG32(L1_PLL_TM_FRAC_OFFSET_2, 0x63b8)
4897    FIELD(L1_PLL_TM_FRAC_OFFSET_2, PLL_TM_FRAC_OFFSET_2_31_8_RSVD, 24, 8)
4898    FIELD(L1_PLL_TM_FRAC_OFFSET_2, TM_PLL_RSVD, 2, 6)
4899    FIELD(L1_PLL_TM_FRAC_OFFSET_2, TM_FORCE_FBDIV_FRAC_OFFSET, 1, 1)
4900    FIELD(L1_PLL_TM_FRAC_OFFSET_2, TM_FRAC_OFFSET_MSB_2, 0, 1)
4901REG32(L1_PLL_STATUS_READ_0, 0x63e0)
4902    FIELD(L1_PLL_STATUS_READ_0, PLL_STATUS_READ_0_31_8_RSVD, 24, 8)
4903    FIELD(L1_PLL_STATUS_READ_0, PLL_COARSE_CODE_LSB_STATUS_READ, 0, 8)
4904REG32(L1_PLL_STATUS_READ_1, 0x63e4)
4905    FIELD(L1_PLL_STATUS_READ_1, PLL_STATUS_READ_1_31_8_RSVD, 24, 8)
4906    FIELD(L1_PLL_STATUS_READ_1, PLL_STATUS_READ_1_RSVD, 6, 2)
4907    FIELD(L1_PLL_STATUS_READ_1, PLL_START_LOOP_STATUS_READ, 5, 1)
4908    FIELD(L1_PLL_STATUS_READ_1, PLL_LOCK_STATUS_READ, 4, 1)
4909    FIELD(L1_PLL_STATUS_READ_1, PLL_COARSE_DONE_STATUS_READ, 3, 1)
4910    FIELD(L1_PLL_STATUS_READ_1, PLL_COARSE_CODE_MSB_STATUS_READ, 0, 3)
4911REG32(L1_UPHY_GLOBAL_CTRL, 0x7000)
4912    FIELD(L1_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_31_8_RSVD, 24, 8)
4913    FIELD(L1_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_7_RSVD, 7, 1)
4914    FIELD(L1_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_6_RSVD, 6, 1)
4915    FIELD(L1_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_5_RSVD, 5, 1)
4916    FIELD(L1_UPHY_GLOBAL_CTRL, PCLK_SELECT, 4, 1)
4917    FIELD(L1_UPHY_GLOBAL_CTRL, MPHY_G3_BIST_ENABLE, 3, 1)
4918    FIELD(L1_UPHY_GLOBAL_CTRL, MULTI_RATE_ENABLE, 2, 1)
4919    FIELD(L1_UPHY_GLOBAL_CTRL, MPHY_GEAR_SELECT, 0, 2)
4920REG32(L1_BIST_CTRL_1, 0x7004)
4921    FIELD(L1_BIST_CTRL_1, BIST_CTRL_1_31_8_RSVD, 24, 8)
4922    FIELD(L1_BIST_CTRL_1, REPETITIVE_PATTERN_ENABLE, 7, 1)
4923    FIELD(L1_BIST_CTRL_1, PRBS_PATTERNS, 5, 2)
4924    FIELD(L1_BIST_CTRL_1, BIST_PATTERN_SELECT, 2, 3)
4925    FIELD(L1_BIST_CTRL_1, BIST_INFINITE_MODE_ENABLE, 1, 1)
4926    FIELD(L1_BIST_CTRL_1, BIST_ENABLE, 0, 1)
4927REG32(L1_BIST_CTRL_2, 0x7008)
4928    FIELD(L1_BIST_CTRL_2, BIST_CTRL_2_31_8_RSVD, 24, 8)
4929    FIELD(L1_BIST_CTRL_2, BIST_CTRL_2_7_3_RSVD, 3, 5)
4930    FIELD(L1_BIST_CTRL_2, BIST_TRAINIG_SEQUENCE_SELECT, 1, 2)
4931    FIELD(L1_BIST_CTRL_2, BIST_ERROR_INJECTION_ENABLE, 0, 1)
4932REG32(L1_BIST_RUN_LEN_L, 0x700c)
4933    FIELD(L1_BIST_RUN_LEN_L, BIST_RUN_LEN_L_31_8_RSVD, 24, 8)
4934    FIELD(L1_BIST_RUN_LEN_L, BIST_RUN_LEN_L, 0, 8)
4935REG32(L1_BIST_ERR_INJ_POINT_L, 0x7010)
4936    FIELD(L1_BIST_ERR_INJ_POINT_L, BIST_ERR_INJ_POINT_L_31_8_RSVD, 24, 8)
4937    FIELD(L1_BIST_ERR_INJ_POINT_L, BIST_ERROR_INJ_POINT_L, 0, 8)
4938REG32(L1_BIST_RUNLEN_ERR_INJ_H, 0x7014)
4939    FIELD(L1_BIST_RUNLEN_ERR_INJ_H, BIST_RUNLEN_ERR_INJ_H_31_8_RSVD, 24, 8)
4940    FIELD(L1_BIST_RUNLEN_ERR_INJ_H, BIST_RUN_LEN_H, 4, 4)
4941    FIELD(L1_BIST_RUNLEN_ERR_INJ_H, BIST_ERROR_INJ_POINT_H, 0, 4)
4942REG32(L1_BIST_IDLE_TIME, 0x7018)
4943    FIELD(L1_BIST_IDLE_TIME, BIST_IDLE_TIME_31_8_RSVD, 24, 8)
4944    FIELD(L1_BIST_IDLE_TIME, BIST_IDLE_TIME, 0, 8)
4945REG32(L1_BIST_MARKER_L, 0x701c)
4946    FIELD(L1_BIST_MARKER_L, BIST_MARKER_L_31_8_RSVD, 24, 8)
4947    FIELD(L1_BIST_MARKER_L, BIST_MARKER_L, 0, 8)
4948REG32(L1_BIST_IDLE_CHAR_L, 0x7020)
4949    FIELD(L1_BIST_IDLE_CHAR_L, BIST_IDLE_CHAR_L_31_8_RSVD, 24, 8)
4950    FIELD(L1_BIST_IDLE_CHAR_L, BIST_IDLE_CHAR_L, 0, 8)
4951REG32(L1_BIST_MARKER_IDLE_H, 0x7024)
4952    FIELD(L1_BIST_MARKER_IDLE_H, BIST_MARKER_IDLE_H_31_8_RSVD, 24, 8)
4953    FIELD(L1_BIST_MARKER_IDLE_H, BIST_MARKER_IDLE_RESERVED_7, 6, 2)
4954    FIELD(L1_BIST_MARKER_IDLE_H, BIST_MARKER_H, 4, 2)
4955    FIELD(L1_BIST_MARKER_IDLE_H, BIST_MARKER_IDLE_RESERVED_3, 2, 2)
4956    FIELD(L1_BIST_MARKER_IDLE_H, BIST_IDLE_CHAR_H, 0, 2)
4957REG32(L1_BIST_LOW_PULSE_TIME, 0x7028)
4958    FIELD(L1_BIST_LOW_PULSE_TIME, BIST_LOW_PULSE_TIME_31_8_RSVD, 24, 8)
4959    FIELD(L1_BIST_LOW_PULSE_TIME, BIST_LOW_PULSE_TIME, 0, 8)
4960REG32(L1_BIST_TOTAL_PULSE_TIME, 0x702c)
4961    FIELD(L1_BIST_TOTAL_PULSE_TIME, BIST_TOTAL_PULSE_TIME_31_8_RSVD, 24, 8)
4962    FIELD(L1_BIST_TOTAL_PULSE_TIME, BIST_TOTAL_PULSE_TIME, 0, 8)
4963REG32(L1_BIST_TEST_PAT_1, 0x7030)
4964    FIELD(L1_BIST_TEST_PAT_1, BIST_TEST_PAT_1_31_8_RSVD, 24, 8)
4965    FIELD(L1_BIST_TEST_PAT_1, BIST_TEST_PAT_1_L, 0, 8)
4966REG32(L1_BIST_TEST_PAT_2, 0x7034)
4967    FIELD(L1_BIST_TEST_PAT_2, BIST_TEST_PAT_2_31_8_RSVD, 24, 8)
4968    FIELD(L1_BIST_TEST_PAT_2, BIST_TEST_PAT_2_L, 0, 8)
4969REG32(L1_BIST_TEST_PAT_3, 0x7038)
4970    FIELD(L1_BIST_TEST_PAT_3, BIST_TEST_PAT_3_31_8_RSVD, 24, 8)
4971    FIELD(L1_BIST_TEST_PAT_3, BIST_TEST_PAT_3_L, 0, 8)
4972REG32(L1_BIST_TEST_PAT_4, 0x703c)
4973    FIELD(L1_BIST_TEST_PAT_4, BIST_TEST_PAT_4_31_8_RSVD, 24, 8)
4974    FIELD(L1_BIST_TEST_PAT_4, BIST_TEST_PAT_4_L, 0, 8)
4975REG32(L1_BIST_TEST_PAT_MSBS, 0x7040)
4976    FIELD(L1_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_MSBS_31_8_RSVD, 24, 8)
4977    FIELD(L1_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_4_H, 6, 2)
4978    FIELD(L1_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_3_H, 4, 2)
4979    FIELD(L1_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_2_H, 2, 2)
4980    FIELD(L1_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_1_H, 0, 2)
4981REG32(L1_BIST_PKT_NUM, 0x7044)
4982    FIELD(L1_BIST_PKT_NUM, BIST_PKT_NUM_31_8_RSVD, 24, 8)
4983    FIELD(L1_BIST_PKT_NUM, BIST_PKT_NUM, 0, 8)
4984REG32(L1_BIST_FRM_IDLE_TIME, 0x7048)
4985    FIELD(L1_BIST_FRM_IDLE_TIME, BIST_FRM_IDLE_TIME_31_8_RSVD, 24, 8)
4986    FIELD(L1_BIST_FRM_IDLE_TIME, BIST_FRM_IDLE_TIME, 0, 8)
4987REG32(L1_BIST_PKT_CTR_L, 0x704c)
4988    FIELD(L1_BIST_PKT_CTR_L, BIST_PKT_CTR_L_31_8_RSVD, 24, 8)
4989    FIELD(L1_BIST_PKT_CTR_L, BIST_PKT_CTR_L, 0, 8)
4990REG32(L1_BIST_PKT_CTR_H, 0x7050)
4991    FIELD(L1_BIST_PKT_CTR_H, BIST_PKT_CTR_H_31_8_RSVD, 24, 8)
4992    FIELD(L1_BIST_PKT_CTR_H, BIST_PKT_CTR_H, 0, 8)
4993REG32(L1_BIST_ERR_CTR_L, 0x7054)
4994    FIELD(L1_BIST_ERR_CTR_L, BIST_ERR_CTR_L_31_8_RSVD, 24, 8)
4995    FIELD(L1_BIST_ERR_CTR_L, BIST_ERR_CTR_L, 0, 8)
4996REG32(L1_BIST_ERR_CTR_H, 0x7058)
4997    FIELD(L1_BIST_ERR_CTR_H, BIST_ERR_CTR_H_31_8_RSVD, 24, 8)
4998    FIELD(L1_BIST_ERR_CTR_H, BIST_ERR_CTR_H, 0, 8)
4999REG32(L1_CLK_DIV_CNT, 0x705c)
5000    FIELD(L1_CLK_DIV_CNT, CLK_DIV_CNT_31_8_RSVD, 24, 8)

5001    FIELD(L1_CLK_DIV_CNT, REF_CLK_BYPASS_GT_50MHZ, 7, 1)
5002    FIELD(L1_CLK_DIV_CNT, SLOW_CNT_REG, 0, 7)
5003REG32(L1_DATA_BUS_WID, 0x7060)
5004    FIELD(L1_DATA_BUS_WID, DATA_BUS_WID_31_8_RSVD, 24, 8)
5005    FIELD(L1_DATA_BUS_WID, RATE_CHANGE_BYPASS, 7, 1)
5006    FIELD(L1_DATA_BUS_WID, PCLK_RATIO_BY_4, 6, 1)
5007    FIELD(L1_DATA_BUS_WID, PCLK_RATIO_BY_2, 5, 1)
5008    FIELD(L1_DATA_BUS_WID, RATE_CHANGE_DELAY_SEL, 4, 1)
5009    FIELD(L1_DATA_BUS_WID, RATE_CHANGE_DELAY_COUNT, 0, 4)
5010REG32(L1_ANADIG_BYPASS, 0x7064)
5011    FIELD(L1_ANADIG_BYPASS, ANADIG_BYPASS_31_8_RSVD, 24, 8)
5012    FIELD(L1_ANADIG_BYPASS, ANA_DIG_COUNTER_SELECT, 7, 1)
5013    FIELD(L1_ANADIG_BYPASS, ANADIG_COUNT, 0, 7)
5014REG32(L1_BIST_FILLER_OUT, 0x7068)
5015    FIELD(L1_BIST_FILLER_OUT, BIST_FILLER_OUT_31_8_RSVD, 24, 8)
5016    FIELD(L1_BIST_FILLER_OUT, BIST_FILLER_OUT_RESERVED, 2, 6)
5017    FIELD(L1_BIST_FILLER_OUT, BIST_FILLER_OUT_ENABLE, 1, 1)
5018    FIELD(L1_BIST_FILLER_OUT, BIST_TX_RX_LOOPBACK_ENABLE, 0, 1)
5019REG32(L1_BIST_FORCE_MK_RST, 0x706c)
5020    FIELD(L1_BIST_FORCE_MK_RST, BIST_FORCE_MK_RST_31_8_RSVD, 24, 8)
5021    FIELD(L1_BIST_FORCE_MK_RST, BIST_FORCE_RESET, 1, 1)
5022    FIELD(L1_BIST_FORCE_MK_RST, BIST_ENABLE_MK_FROM_REG, 0, 1)
5023REG32(L1_SPARE_IN, 0x7070)
5024    FIELD(L1_SPARE_IN, SPARE_IN_31_8_RSVD, 24, 8)
5025    FIELD(L1_SPARE_IN, SPARE_IN, 0, 8)
5026REG32(L1_SPARE_OUT, 0x7074)
5027    FIELD(L1_SPARE_OUT, SPARE_OUT_31_8_RSVD, 24, 8)
5028    FIELD(L1_SPARE_OUT, SPARE_OUT, 0, 8)
5029REG32(L2_TX_ANA_TM_0, 0x8000)
5030    FIELD(L2_TX_ANA_TM_0, TX_ANA_TM_0_31_8_RSVD, 24, 8)
5031    FIELD(L2_TX_ANA_TM_0, ANA_BYP0_7_6_RSVD, 6, 2)
5032    FIELD(L2_TX_ANA_TM_0, PIPE_TX_DN_RXDET, 5, 1)
5033    FIELD(L2_TX_ANA_TM_0, FORCE_PIPE_TX_DN_RXDET, 4, 1)
5034    FIELD(L2_TX_ANA_TM_0, PIPE_TX_DP_RXDET, 3, 1)
5035    FIELD(L2_TX_ANA_TM_0, FORCE_PIPE_TX_DP_RXDET, 2, 1)
5036    FIELD(L2_TX_ANA_TM_0, ANA_BYP0_1_0_RSVD, 0, 2)
5037REG32(L2_TX_ANA_TM_3, 0x800c)
5038    FIELD(L2_TX_ANA_TM_3, TX_ANA_TM_3_31_8_RSVD, 24, 8)
5039    FIELD(L2_TX_ANA_TM_3, TX_HS_SER_RSTB, 7, 1)
5040    FIELD(L2_TX_ANA_TM_3, FORCE_TX_HS_SER_RSTB, 6, 1)
5041    FIELD(L2_TX_ANA_TM_3, TX_HS_BURST, 5, 1)
5042    FIELD(L2_TX_ANA_TM_3, FORCE_TX_HS_BURST, 4, 1)
5043    FIELD(L2_TX_ANA_TM_3, TX_SERIALIZER_ENABLE, 3, 1)
5044    FIELD(L2_TX_ANA_TM_3, FORCE_TX_SERIALIZER_ENABLE, 2, 1)
5045    FIELD(L2_TX_ANA_TM_3, TX_ENABLE_SUPPLY_SERIALIZER, 1, 1)
5046    FIELD(L2_TX_ANA_TM_3, FORCE_TX_ENABLE_SUPPLY_SERIALIZER, 0, 1)
5047REG32(L2_TX_ANA_TM_4, 0x8010)
5048    FIELD(L2_TX_ANA_TM_4, TX_ANA_TM_4_31_8_RSVD, 24, 8)
5049    FIELD(L2_TX_ANA_TM_4, ANA_BYP4_7_RSVD, 7, 1)
5050    FIELD(L2_TX_ANA_TM_4, TX_LSEG_DN_RESCAL_CODE, 1, 6)
5051    FIELD(L2_TX_ANA_TM_4, FORCE_TX_LSEG_DN_RESCAL_CODE, 0, 1)
5052REG32(L2_TX_ANA_TM_5, 0x8014)
5053    FIELD(L2_TX_ANA_TM_5, TX_ANA_TM_5_31_8_RSVD, 24, 8)
5054    FIELD(L2_TX_ANA_TM_5, ANA_BYP5_7_RSVD, 7, 1)
5055    FIELD(L2_TX_ANA_TM_5, TX_USEG_DP_RESCAL_CODE, 1, 6)
5056    FIELD(L2_TX_ANA_TM_5, FORCE_TX_USEG_DP_RESCAL_CODE, 0, 1)
5057REG32(L2_TX_ANA_TM_9, 0x8024)
5058    FIELD(L2_TX_ANA_TM_9, TX_ANA_TM_9_31_8_RSVD, 24, 8)
5059    FIELD(L2_TX_ANA_TM_9, MPHY_TX_HS_SLEWRATE, 0, 8)
5060REG32(L2_TX_ANA_TM_10, 0x8028)
5061    FIELD(L2_TX_ANA_TM_10, TX_ANA_TM_10_31_8_RSVD, 24, 8)
5062    FIELD(L2_TX_ANA_TM_10, MPHY_HS_POWERUP_TIME, 4, 4)
5063    FIELD(L2_TX_ANA_TM_10, MPHY_TX_HS_EQUALIZER_SETTING, 1, 3)
5064    FIELD(L2_TX_ANA_TM_10, FORCE_MPHY_TX_HS_EQUALIZER_SETTING, 0, 1)
5065REG32(L2_TX_ANA_TM_13, 0x8034)
5066    FIELD(L2_TX_ANA_TM_13, TX_ANA_TM_13_31_8_RSVD, 24, 8)
5067    FIELD(L2_TX_ANA_TM_13, ANA_BYP13_7_4_RSVD, 4, 4)
5068    FIELD(L2_TX_ANA_TM_13, TX_SWAP_POLARITY, 3, 1)
5069    FIELD(L2_TX_ANA_TM_13, FORCE_TX_SWAP_POLARITY, 2, 1)
5070    FIELD(L2_TX_ANA_TM_13, MPHY_TX_TRISTATE, 1, 1)
5071    FIELD(L2_TX_ANA_TM_13, FORCE_MPHY_TX_TRISTATE, 0, 1)
5072REG32(L2_TX_ANA_TM_14, 0x8038)
5073    FIELD(L2_TX_ANA_TM_14, TX_ANA_TM_14_31_8_RSVD, 24, 8)
5074    FIELD(L2_TX_ANA_TM_14, ANA_BYP14_7_6_RSVD, 6, 2)
5075    FIELD(L2_TX_ANA_TM_14, PIPE_TX_FAST_EST_COMMON_MODE, 5, 1)
5076    FIELD(L2_TX_ANA_TM_14, FORCE_PIPE_TX_FAST_EST_COMMON_MODE, 4, 1)
5077    FIELD(L2_TX_ANA_TM_14, ANA_BYP14_3_0_RSVD, 0, 4)
5078REG32(L2_TX_ANA_TM_15, 0x803c)
5079    FIELD(L2_TX_ANA_TM_15, TX_ANA_TM_15_31_8_RSVD, 24, 8)
5080    FIELD(L2_TX_ANA_TM_15, PIPE_TX_SWING, 7, 1)
5081    FIELD(L2_TX_ANA_TM_15, FORCE_PIPE_TX_SWING, 6, 1)
5082    FIELD(L2_TX_ANA_TM_15, PIPE_TX_RXDET_DISCHARGE, 5, 1)
5083    FIELD(L2_TX_ANA_TM_15, FORCE_PIPE_TX_RXDET_DISCHARGE, 4, 1)
5084    FIELD(L2_TX_ANA_TM_15, PIPE_TX_RXDET_CHARGE, 3, 1)
5085    FIELD(L2_TX_ANA_TM_15, FORCE_PIPE_TX_RXDET_CHARGE, 2, 1)
5086    FIELD(L2_TX_ANA_TM_15, PIPE_TX_ENABLE_RXDET, 1, 1)
5087    FIELD(L2_TX_ANA_TM_15, FORCE_PIPE_TX_ENABLE_RXDET, 0, 1)
5088REG32(L2_TX_ANA_TM_16, 0x8040)
5089    FIELD(L2_TX_ANA_TM_16, TX_ANA_TM_16_31_8_RSVD, 24, 8)
5090    FIELD(L2_TX_ANA_TM_16, ANA_BYP16_7_4_RSVD, 4, 4)
5091    FIELD(L2_TX_ANA_TM_16, PIPE_TX_MARGIN, 1, 3)
5092    FIELD(L2_TX_ANA_TM_16, FORCE_PIPE_TX_MARGIN, 0, 1)
5093REG32(L2_TX_ANA_TM_18, 0x8048)
5094    FIELD(L2_TX_ANA_TM_18, TX_ANA_TM_18_31_8_RSVD, 24, 8)
5095    FIELD(L2_TX_ANA_TM_18, PIPE_TX_DEEMPH_7_0, 0, 8)
5096REG32(L2_TX_ANA_TM_19, 0x804c)
5097    FIELD(L2_TX_ANA_TM_19, TX_ANA_TM_19_31_8_RSVD, 24, 8)
5098    FIELD(L2_TX_ANA_TM_19, PIPE_TX_DEEMPH_15_8, 0, 8)
5099REG32(L2_TX_ANA_TM_20, 0x8050)
5100    FIELD(L2_TX_ANA_TM_20, TX_ANA_TM_20_31_8_RSVD, 24, 8)
5101    FIELD(L2_TX_ANA_TM_20, ANA_BYP20_7_5_RSVD, 5, 3)
5102    FIELD(L2_TX_ANA_TM_20, TX_SERIALIZER_RST_REL, 4, 1)
5103    FIELD(L2_TX_ANA_TM_20, FORCE_TX_SERIALIZER_RST_REL, 3, 1)
5104    FIELD(L2_TX_ANA_TM_20, FORCE_MPHY_TX_HS_SLEWRATE, 2, 1)
5105    FIELD(L2_TX_ANA_TM_20, PIPE_TX_DEEMPH_17_16, 0, 2)
5106REG32(L2_TX_ANA_TM_21, 0x8054)
5107    FIELD(L2_TX_ANA_TM_21, TX_ANA_TM_21_31_8_RSVD, 24, 8)
5108    FIELD(L2_TX_ANA_TM_21, ANA_BYP21_7_6_RSVD, 6, 2)
5109    FIELD(L2_TX_ANA_TM_21, PIPE_TX_COEF_CALC_CLK, 5, 1)
5110    FIELD(L2_TX_ANA_TM_21, FORCE_PIPE_TX_COEF_CALC_CLK, 4, 1)
5111    FIELD(L2_TX_ANA_TM_21, PIPE_TX_COEF_CALC_FSM_RESET_B, 3, 1)
5112    FIELD(L2_TX_ANA_TM_21, FORCE_PIPE_TX_COEF_CALC_FSM_RESET_B, 2, 1)
5113    FIELD(L2_TX_ANA_TM_21, PIPE_TX_DEEMPH_CTRL_SEL, 1, 1)
5114    FIELD(L2_TX_ANA_TM_21, FORCE_PIPE_TX_DEEMPH_CTRL_SEL, 0, 1)
5115REG32(L2_TX_DIG_TM_61, 0x80f4)
5116    FIELD(L2_TX_DIG_TM_61, TX_DIG_TM_61_31_8_RSVD, 24, 8)
5117    FIELD(L2_TX_DIG_TM_61, MPHY_PLL_GEAR, 6, 2)
5118    FIELD(L2_TX_DIG_TM_61, DIG_BYP1_5_4_RSVD, 4, 2)
5119    FIELD(L2_TX_DIG_TM_61, BYPASS_ENC, 3, 1)
5120    FIELD(L2_TX_DIG_TM_61, DIG_BYP1_2_RSVD, 2, 1)
5121    FIELD(L2_TX_DIG_TM_61, BYPASS_SCRAM, 1, 1)
5122    FIELD(L2_TX_DIG_TM_61, FORCE_BYPASS_SCRAM, 0, 1)
5123REG32(L2_TX_DIG_TM_62, 0x80f8)
5124    FIELD(L2_TX_DIG_TM_62, TX_DIG_TM_62_31_8_RSVD, 24, 8)
5125    FIELD(L2_TX_DIG_TM_62, G0_BIT_PER_CNT, 0, 8)
5126REG32(L2_TX_DIG_TM_65, 0x8104)
5127    FIELD(L2_TX_DIG_TM_65, TX_DIG_TM_65_31_8_RSVD, 24, 8)
5128    FIELD(L2_TX_DIG_TM_65, FORCE_TX_RXDET_PROBE_THRESHOLD, 7, 1)
5129    FIELD(L2_TX_DIG_TM_65, FORCE_TX_RXDET_END_CH_THRESHOLD, 6, 1)
5130    FIELD(L2_TX_DIG_TM_65, FORCE_TX_RXDET_START_CH_THRESHOLD, 5, 1)
5131    FIELD(L2_TX_DIG_TM_65, FORCE_TX_RXDET_END_DCH_THRESHOLD, 4, 1)
5132    FIELD(L2_TX_DIG_TM_65, FORCE_TX_RXDET_START_DCH_THRESHOLD, 3, 1)
5133    FIELD(L2_TX_DIG_TM_65, TX_EN_FULL_CALIB, 2, 1)
5134    FIELD(L2_TX_DIG_TM_65, FORCE_TX_EN_FULL_CALIB, 1, 1)
5135    FIELD(L2_TX_DIG_TM_65, DIG_BYP5_0_RSVD, 0, 1)
5136REG32(L2_TX_DIG_TM_67, 0x810c)
5137    FIELD(L2_TX_DIG_TM_67, TX_DIG_TM_67_31_8_RSVD, 24, 8)
5138    FIELD(L2_TX_DIG_TM_67, TX_MPHY_SER_THRESHOLD, 0, 8)
5139REG32(L2_TX_DIG_TM_68, 0x8110)
5140    FIELD(L2_TX_DIG_TM_68, TX_DIG_TM_68_31_8_RSVD, 24, 8)
5141    FIELD(L2_TX_DIG_TM_68, TX_SER_SUP_THRESHOLD, 0, 8)
5142REG32(L2_TX_DIG_TM_69, 0x8114)
5143    FIELD(L2_TX_DIG_TM_69, TX_DIG_TM_69_31_8_RSVD, 24, 8)
5144    FIELD(L2_TX_DIG_TM_69, TX_MPHY_SUP_THRESHOLD, 0, 8)
5145REG32(L2_TX_DIG_TM_76, 0x8130)
5146    FIELD(L2_TX_DIG_TM_76, TX_DIG_TM_76_31_8_RSVD, 24, 8)
5147    FIELD(L2_TX_DIG_TM_76, TX_RXDET_START_DCH_THRESHOLD_7_0, 0, 8)
5148REG32(L2_TX_DIG_TM_77, 0x8134)
5149    FIELD(L2_TX_DIG_TM_77, TX_DIG_TM_77_31_8_RSVD, 24, 8)
5150    FIELD(L2_TX_DIG_TM_77, TX_RXDET_END_DCH_THRESHOLD_11_8, 4, 4)
5151    FIELD(L2_TX_DIG_TM_77, TX_RXDET_START_DCH_THRESHOLD_11_8, 0, 4)
5152REG32(L2_TX_DIG_TM_78, 0x8138)
5153    FIELD(L2_TX_DIG_TM_78, TX_DIG_TM_78_31_8_RSVD, 24, 8)
5154    FIELD(L2_TX_DIG_TM_78, TX_RXDET_END_DCH_THRESHOLD_7_0, 0, 8)
5155REG32(L2_TX_DIG_TM_79, 0x813c)
5156    FIELD(L2_TX_DIG_TM_79, TX_DIG_TM_79_31_8_RSVD, 24, 8)
5157    FIELD(L2_TX_DIG_TM_79, TX_RXDET_START_CH_THRESHOLD_7_0, 0, 8)
5158REG32(L2_TX_DIG_TM_80, 0x8140)
5159    FIELD(L2_TX_DIG_TM_80, TX_DIG_TM_80_31_8_RSVD, 24, 8)
5160    FIELD(L2_TX_DIG_TM_80, TX_RXDET_END_CH_THRESHOLD_11_8, 4, 4)
5161    FIELD(L2_TX_DIG_TM_80, TX_RXDET_START_CH_THRESHOLD_11_8, 0, 4)
5162REG32(L2_TX_DIG_TM_81, 0x8144)
5163    FIELD(L2_TX_DIG_TM_81, TX_DIG_TM_81_31_8_RSVD, 24, 8)
5164    FIELD(L2_TX_DIG_TM_81, TX_RXDET_END_CH_THRESHOLD_7_0, 0, 8)
5165REG32(L2_TX_DIG_TM_82, 0x8148)
5166    FIELD(L2_TX_DIG_TM_82, TX_DIG_TM_82_31_8_RSVD, 24, 8)
5167    FIELD(L2_TX_DIG_TM_82, TX_RXDET_PROBE_THRESHOLD_7_0, 0, 8)
5168REG32(L2_TX_DIG_TM_83, 0x814c)
5169    FIELD(L2_TX_DIG_TM_83, TX_DIG_TM_83_31_8_RSVD, 24, 8)
5170    FIELD(L2_TX_DIG_TM_83, DIG_BYP23_7_4_RSVD, 4, 4)
5171    FIELD(L2_TX_DIG_TM_83, TX_RXDET_PROBE_THRESHOLD_11_8, 0, 4)
5172REG32(L2_TX_DIG_TM_84, 0x8150)
5173    FIELD(L2_TX_DIG_TM_84, TX_DIG_TM_84_31_8_RSVD, 24, 8)
5174    FIELD(L2_TX_DIG_TM_84, TX_DIF_P, 7, 1)
5175    FIELD(L2_TX_DIG_TM_84, TX_DITHER_1P, 6, 1)
5176    FIELD(L2_TX_DIG_TM_84, TX_DITHER_1N, 5, 1)
5177    FIELD(L2_TX_DIG_TM_84, TX_DITHER_EN, 4, 1)
5178    FIELD(L2_TX_DIG_TM_84, DIG_BYP24_3_RSVD, 3, 1)
5179    FIELD(L2_TX_DIG_TM_84, TX_PHYDIRDY_SOC_MODE, 2, 1)
5180    FIELD(L2_TX_DIG_TM_84, DIG_BYP24_1_RSVD, 1, 1)
5181    FIELD(L2_TX_DIG_TM_84, TX_READ_SHADOW, 0, 1)
5182REG32(L2_TX_ANA_TM_85, 0x8154)
5183    FIELD(L2_TX_ANA_TM_85, TX_ANA_TM_85_31_8_RSVD, 24, 8)
5184    FIELD(L2_TX_ANA_TM_85, DIG_BYP25_7_6_RSVD, 6, 2)
5185    FIELD(L2_TX_ANA_TM_85, TX_HIBERN8_CTRL, 5, 1)
5186    FIELD(L2_TX_ANA_TM_85, TX_ALLOW_INLNCFG_FROM_TOP, 4, 1)
5187    FIELD(L2_TX_ANA_TM_85, DIG_BYP25_3_RSVD, 3, 1)
5188    FIELD(L2_TX_ANA_TM_85, TX_SEND_MSB_FIRST, 2, 1)
5189    FIELD(L2_TX_ANA_TM_85, DIG_BYP25_1_RSVD, 1, 1)
5190    FIELD(L2_TX_ANA_TM_85, TX_DIF_N, 0, 1)
5191REG32(L2_TX_ANA_TM_87, 0x815c)
5192    FIELD(L2_TX_ANA_TM_87, TX_ANA_TM_87_31_8_RSVD, 24, 8)
5193    FIELD(L2_TX_ANA_TM_87, DIG_BYP27_7_4_RSVD, 4, 4)
5194    FIELD(L2_TX_ANA_TM_87, TX_SM_STATUS, 0, 4)
5195REG32(L2_TX_ANA_TM_88, 0x8160)
5196    FIELD(L2_TX_ANA_TM_88, TX_ANA_TM_88_31_8_RSVD, 24, 8)
5197    FIELD(L2_TX_ANA_TM_88, TX_COMP_PAT_HIGH_TIME_REGS, 0, 8)
5198REG32(L2_TX_ANA_TM_89, 0x8164)
5199    FIELD(L2_TX_ANA_TM_89, TX_ANA_TM_89_31_8_RSVD, 24, 8)
5200    FIELD(L2_TX_ANA_TM_89, DIG_BYP29_7_6_RSVD, 6, 2)
5201    FIELD(L2_TX_ANA_TM_89, TX_DATAPATH_CTRL_1_REGS, 5, 1)
5202    FIELD(L2_TX_ANA_TM_89, DIG_BYP29_4_3_RSVD, 3, 2)
5203    FIELD(L2_TX_ANA_TM_89, INITIAL_DISPARITY, 2, 1)
5204    FIELD(L2_TX_ANA_TM_89, SCRAMBLER_ENABLE, 1, 1)
5205    FIELD(L2_TX_ANA_TM_89, DIG_BYP29_0_RSVD, 0, 1)
5206REG32(L2_TX_ANA_TM_90, 0x8168)
5207    FIELD(L2_TX_ANA_TM_90, TX_ANA_TM_90_31_8_RSVD, 24, 8)
5208    FIELD(L2_TX_ANA_TM_90, DIG_BYP30_7_6_RSVD, 6, 2)
5209    FIELD(L2_TX_ANA_TM_90, TX_BYPASS_BCNT_LPBACK_REGS, 5, 1)
5210    FIELD(L2_TX_ANA_TM_90, DIG_BYP30_4_0_RSVD, 0, 5)
5211REG32(L2_TX_DIG_TM_91, 0x816c)
5212    FIELD(L2_TX_DIG_TM_91, TX_DIG_TM_91_31_8_RSVD, 24, 8)
5213    FIELD(L2_TX_DIG_TM_91, TX_CFGCLK_FREQ, 0, 8)
5214REG32(L2_TX_DIG_TM_92, 0x8170)
5215    FIELD(L2_TX_DIG_TM_92, TX_DIG_TM_92_31_8_RSVD, 24, 8)
5216    FIELD(L2_TX_DIG_TM_92, TX_PHYDIRDY_PULL_UP_LATENCY, 0, 8)
5217REG32(L2_TX_ANA_TM_95, 0x817c)
5218    FIELD(L2_TX_ANA_TM_95, TX_ANA_TM_95_31_8_RSVD, 24, 8)
5219    FIELD(L2_TX_ANA_TM_95, ANA_BYP63_7_6_RSVD, 6, 2)
5220    FIELD(L2_TX_ANA_TM_95, TX_TM_EN_PROG_SYNC_PATTERN, 5, 1)
5221    FIELD(L2_TX_ANA_TM_95, TX_EXTRA_HS_BURST_IN_LCC, 2, 3)
5222    FIELD(L2_TX_ANA_TM_95, ANA_BYP22_1_0_RSVD, 0, 2)
5223REG32(L2_TX_ANA_TM_96, 0x8180)
5224    FIELD(L2_TX_ANA_TM_96, TX_ANA_TM_96_31_8_RSVD, 24, 8)
5225    FIELD(L2_TX_ANA_TM_96, TX_TM_PROG_SYNC_PATTERN1, 0, 8)
5226REG32(L2_TX_ANA_TM_97, 0x8184)
5227    FIELD(L2_TX_ANA_TM_97, TX_ANA_TM_97_31_8_RSVD, 24, 8)
5228    FIELD(L2_TX_ANA_TM_97, TX_TM_PROG_SYNC_PATTERN2, 0, 8)
5229REG32(L2_TX_DIG_TM_98, 0x8188)
5230    FIELD(L2_TX_DIG_TM_98, TX_DIG_TM_98_31_8_RSVD, 24, 8)
5231    FIELD(L2_TX_DIG_TM_98, DIG_BYP33_7_6_RSVD, 6, 2)
5232    FIELD(L2_TX_DIG_TM_98, FORCE_RD_VALUE, 5, 1)
5233    FIELD(L2_TX_DIG_TM_98, FORCE_RD, 4, 1)
5234    FIELD(L2_TX_DIG_TM_98, TX_SER_ISO_CTRL_BAR, 3, 1)
5235    FIELD(L2_TX_DIG_TM_98, FORCE_TX_SER_ISO_CTRL_BAR, 2, 1)
5236    FIELD(L2_TX_DIG_TM_98, TX_ISO_CTRL_BAR, 1, 1)
5237    FIELD(L2_TX_DIG_TM_98, FORCE_TX_ISO_CTRL_BAR, 0, 1)
5238REG32(L2_TX_DIG_TM_99, 0x818c)
5239    FIELD(L2_TX_DIG_TM_99, TX_DIG_TM_99_31_8_RSVD, 24, 8)
5240    FIELD(L2_TX_DIG_TM_99, TX_PIPE_SUPPLY_ENABLE_THRESHOLD, 0, 8)
5241REG32(L2_TX_DIG_TM_100, 0x8190)
5242    FIELD(L2_TX_DIG_TM_100, TX_DIG_TM_100_31_8_RSVD, 24, 8)
5243    FIELD(L2_TX_DIG_TM_100, TX_SERIALISER_SUPPLY_ENABLE_THRESHOLD, 0, 8)
5244REG32(L2_TX_DIG_TM_101, 0x8194)
5245    FIELD(L2_TX_DIG_TM_101, TX_DIG_TM_101_31_8_RSVD, 24, 8)
5246    FIELD(L2_TX_DIG_TM_101, TX_SERIALISER_ENABLE_THRESHOLD, 0, 8)
5247REG32(L2_TX_DIG_TM_102, 0x8198)
5248    FIELD(L2_TX_DIG_TM_102, TX_DIG_TM_102_31_8_RSVD, 24, 8)
5249    FIELD(L2_TX_DIG_TM_102, FORCE_TX_ANA_LL_EN, 7, 1)
5250    FIELD(L2_TX_DIG_TM_102, TX_ANA_LL_EN, 6, 1)
5251    FIELD(L2_TX_DIG_TM_102, FORCE_DELAY_CNT_THRESHOLD, 5, 1)
5252    FIELD(L2_TX_DIG_TM_102, FORCE_TX_MPHY_TRST_THRESHOLD, 4, 1)
5253    FIELD(L2_TX_DIG_TM_102, FORCE_TX_LDO_THRESHOLD, 3, 1)
5254    FIELD(L2_TX_DIG_TM_102, FORCE_TX_SERIALISER_ENABLE_THRESHOLD, 2, 1)
5255    FIELD(L2_TX_DIG_TM_102, FORCE_TX_SERIALISER_SUPPLY_ENABLE_THRESHOLD, 1, 1)
5256    FIELD(L2_TX_DIG_TM_102, FORCE_TX_PIPE_SUPPLY_ENABLE_THRESHOLD, 0, 1)
5257REG32(L2_TX_DIG_TM_103, 0x819c)
5258    FIELD(L2_TX_DIG_TM_103, TX_DIG_TM_103_31_8_RSVD, 24, 8)
5259    FIELD(L2_TX_DIG_TM_103, FORCE_BG_EN, 7, 1)
5260    FIELD(L2_TX_DIG_TM_103, FORCE_CALIB_EN, 6, 1)
5261    FIELD(L2_TX_DIG_TM_103, FORCE_PLL_EN, 5, 1)
5262    FIELD(L2_TX_DIG_TM_103, FORCE_PSO, 4, 1)
5263    FIELD(L2_TX_DIG_TM_103, BG_EN, 3, 1)
5264    FIELD(L2_TX_DIG_TM_103, CALIB_EN, 2, 1)
5265    FIELD(L2_TX_DIG_TM_103, PLL_EN, 1, 1)
5266    FIELD(L2_TX_DIG_TM_103, PSO, 0, 1)
5267REG32(L2_TX_DIG_TM_104, 0x81a0)
5268    FIELD(L2_TX_DIG_TM_104, TX_DIG_TM_104_31_8_RSVD, 24, 8)
5269    FIELD(L2_TX_DIG_TM_104, TX_LDO_THRESHOLD, 0, 8)
5270REG32(L2_TX_DIG_TM_105, 0x81a4)
5271    FIELD(L2_TX_DIG_TM_105, TX_DIG_TM_105_31_8_RSVD, 24, 8)
5272    FIELD(L2_TX_DIG_TM_105, TX_MPHY_TRST_THRESHOLD, 0, 8)
5273REG32(L2_TX_DIG_TM_106, 0x81a8)
5274    FIELD(L2_TX_DIG_TM_106, TX_DIG_TM_106_31_8_RSVD, 24, 8)
5275    FIELD(L2_TX_DIG_TM_106, DELAY_CNT_THRESHOLD, 0, 8)
5276REG32(L2_TX_DIG_TM_107, 0x81ac)
5277    FIELD(L2_TX_DIG_TM_107, TX_DIG_TM_107_31_8_RSVD, 24, 8)
5278    FIELD(L2_TX_DIG_TM_107, DIG_BYP42_7_RSVD, 7, 1)
5279    FIELD(L2_TX_DIG_TM_107, FORCE_P3TOP0_PHYSTATUS_PULSE, 6, 1)
5280    FIELD(L2_TX_DIG_TM_107, ENABLE_HS_CLK_DIVISION, 5, 1)
5281    FIELD(L2_TX_DIG_TM_107, TESTDIGOUT_SEL, 1, 4)
5282    FIELD(L2_TX_DIG_TM_107, FORCE_TESTDIGOUT_SEL, 0, 1)
5283REG32(L2_TX_DIG_TM_108, 0x81b0)
5284    FIELD(L2_TX_DIG_TM_108, TX_DIG_TM_108_31_8_RSVD, 24, 8)
5285    FIELD(L2_TX_DIG_TM_108, ANA_BYP43_7_RSVD, 7, 1)
5286    FIELD(L2_TX_DIG_TM_108, TX_EXT_DATA_DELAY, 3, 4)
5287    FIELD(L2_TX_DIG_TM_108, FORCE_TX_EXT_DATA_DELAY, 2, 1)
5288    FIELD(L2_TX_DIG_TM_108, FORCE_TX_DATA_DELAY, 1, 1)
5289    FIELD(L2_TX_DIG_TM_108, FORCE_UPHY_TXPMA_OPMODE, 0, 1)
5290REG32(L2_TX_DIG_TM_109, 0x81b4)
5291    FIELD(L2_TX_DIG_TM_109, TX_DIG_TM_109_31_8_RSVD, 24, 8)
5292    FIELD(L2_TX_DIG_TM_109, UPHY_TXPMA_OPMODE, 0, 8)
5293REG32(L2_TX_DIG_TM_110, 0x81b8)
5294    FIELD(L2_TX_DIG_TM_110, TX_DIG_TM_110_31_8_RSVD, 24, 8)
5295    FIELD(L2_TX_DIG_TM_110, TX_DATA_DELAY, 0, 8)
5296REG32(L2_TX_DIG_TM_111, 0x81bc)
5297    FIELD(L2_TX_DIG_TM_111, TX_DIG_TM_111_31_8_RSVD, 24, 8)
5298    FIELD(L2_TX_DIG_TM_111, TX_DA_SPARE, 0, 8)
5299REG32(L2_TX_ANA_TM_112, 0x81c0)
5300    FIELD(L2_TX_ANA_TM_112, TX_ANA_TM_112_31_8_RSVD, 24, 8)
5301    FIELD(L2_TX_ANA_TM_112, ANA_BYP25_7_6_RSVD, 6, 2)
5302    FIELD(L2_TX_ANA_TM_112, PIPE_TX_ENABLE_LFPS, 4, 2)
5303    FIELD(L2_TX_ANA_TM_112, FORCE_PIPE_TX_ENABLE_LFPS, 3, 1)
5304    FIELD(L2_TX_ANA_TM_112, PIPE_TX_ENABLE_IDLE_MODE, 1, 2)
5305    FIELD(L2_TX_ANA_TM_112, FORCE_PIPE_TX_ENABLE_IDLE_MODE, 0, 1)
5306REG32(L2_TX_ANA_TM_113, 0x81c4)
5307    FIELD(L2_TX_ANA_TM_113, TX_ANA_TM_113_31_8_RSVD, 24, 8)
5308    FIELD(L2_TX_ANA_TM_113, MPHY_TX_DRIVERLDO_PROG, 0, 8)
5309REG32(L2_TX_ANA_TM_114, 0x81c8)
5310    FIELD(L2_TX_ANA_TM_114, TX_ANA_TM_114_31_8_RSVD, 24, 8)
5311    FIELD(L2_TX_ANA_TM_114, ANA_BYP27_7_5_RSVD, 5, 3)
5312    FIELD(L2_TX_ANA_TM_114, FORCE_MPHY_TX_DRIVERLDO_PROG, 4, 1)
5313    FIELD(L2_TX_ANA_TM_114, MPHY_TX_DRIVERLDO_PROG, 0, 4)
5314REG32(L2_TX_ANA_TM_115, 0x81cc)
5315    FIELD(L2_TX_ANA_TM_115, TX_ANA_TM_115_31_8_RSVD, 24, 8)
5316    FIELD(L2_TX_ANA_TM_115, ANA_BYP28_7_RSVD, 7, 1)
5317    FIELD(L2_TX_ANA_TM_115, PIPE_TX_GETLOCALPRESETCOEFFICIENTS, 6, 1)
5318    FIELD(L2_TX_ANA_TM_115, FORCE_PIPE_TX_GETLOCALPRESETCOEFFICIENTS, 5, 1)
5319    FIELD(L2_TX_ANA_TM_115, TX_PMADIG_DIGITAL_RESET_N, 4, 1)
5320    FIELD(L2_TX_ANA_TM_115, FORCE_TX_PMADIG_DIGITAL_RESET_N, 3, 1)
5321    FIELD(L2_TX_ANA_TM_115, TX_ANA_IF_RATE, 1, 2)
5322    FIELD(L2_TX_ANA_TM_115, FORCE_TX_ANA_IF_RATE, 0, 1)
5323REG32(L2_TX_ANA_TM_116, 0x81d0)
5324    FIELD(L2_TX_ANA_TM_116, TX_ANA_TM_116_31_8_RSVD, 24, 8)
5325    FIELD(L2_TX_ANA_TM_116, ANA_BYP29_7_RSVD, 7, 1)
5326    FIELD(L2_TX_ANA_TM_116, PIPE_TX_LOCALPRESETINDEX, 3, 4)
5327    FIELD(L2_TX_ANA_TM_116, FORCE_PIPE_TX_LOCALPRESETINDEX, 2, 1)
5328    FIELD(L2_TX_ANA_TM_116, MPHY_TX_EN_LANE_LS_CLK, 1, 1)
5329    FIELD(L2_TX_ANA_TM_116, FORCE_MPHY_TX_EN_LANE_LS_CLK, 0, 1)
5330REG32(L2_TX_ANA_TM_117, 0x81d4)
5331    FIELD(L2_TX_ANA_TM_117, TX_ANA_TM_117_31_8_RSVD, 24, 8)
5332    FIELD(L2_TX_ANA_TM_117, MULTILANE_BYP1_7_6_RSVD, 6, 2)
5333    FIELD(L2_TX_ANA_TM_117, TX_PCIE_4X_CFG_EN, 5, 1)
5334    FIELD(L2_TX_ANA_TM_117, FORCE_TX_PCIE_4X_CFG_EN, 4, 1)
5335    FIELD(L2_TX_ANA_TM_117, TX_PCIE_2X_CFG_EN, 3, 1)
5336    FIELD(L2_TX_ANA_TM_117, FORCE_TX_PCIE_2X_CFG_EN, 2, 1)
5337    FIELD(L2_TX_ANA_TM_117, TX_DP_MULTILANE_CFG_EN, 1, 1)
5338    FIELD(L2_TX_ANA_TM_117, FORCE_TX_DP_MULTILANE_CFG_EN, 0, 1)
5339REG32(L2_TX_ANA_TM_118, 0x81d8)
5340    FIELD(L2_TX_ANA_TM_118, TX_ANA_TM_118_31_8_RSVD, 24, 8)
5341    FIELD(L2_TX_ANA_TM_118, ANA_BYP30_7_4_RSVD, 4, 4)
5342    FIELD(L2_TX_ANA_TM_118, FORCE_TX_DEEMPH_17_12, 3, 1)
5343    FIELD(L2_TX_ANA_TM_118, FORCE_TX_DEEMPH_11_6, 2, 1)
5344    FIELD(L2_TX_ANA_TM_118, FORCE_TX_DEEMPH_5_0, 1, 1)
5345    FIELD(L2_TX_ANA_TM_118, FORCE_TX_DEEMPH_17_0, 0, 1)
5346REG32(L2_TXPMA_TM_0, 0x8800)
5347    FIELD(L2_TXPMA_TM_0, TXPMA_TM_0_31_8_RSVD, 24, 8)
5348    FIELD(L2_TXPMA_TM_0, TM_TX_ENABLE_SUPPLY_MPHY, 7, 1)
5349    FIELD(L2_TXPMA_TM_0, TM_FORCE_TX_ENABLE_SUPPLY_MPHY, 6, 1)
5350    FIELD(L2_TXPMA_TM_0, TM_MPHY_TX_ENABLE_SUPPLY_LS_CLOCK, 5, 1)
5351    FIELD(L2_TXPMA_TM_0, TM_FORCE_MPHY_TX_ENABLE_SUPPLY_LS_CLOCK, 4, 1)
5352    FIELD(L2_TXPMA_TM_0, TM_MPHY_TX_ENABLE_SA_MODE, 3, 1)
5353    FIELD(L2_TXPMA_TM_0, TM_FORCE_MPHY_TX_ENABLE_SA_MODE, 2, 1)
5354    FIELD(L2_TXPMA_TM_0, TM_MPHY_TX_ENABLE_HS_NT, 1, 1)
5355    FIELD(L2_TXPMA_TM_0, TM_FORCE_MPHY_TX_ENABLE_HS_NT, 0, 1)
5356REG32(L2_TXPMA_TM_1, 0x8804)
5357    FIELD(L2_TXPMA_TM_1, TXPMA_TM_1_31_8_RSVD, 24, 8)
5358    FIELD(L2_TXPMA_TM_1, ANA_MPHY_BYP1_7_4_RSVD, 4, 4)
5359    FIELD(L2_TXPMA_TM_1, TM_MPHY_TX_HS_DITHER_VAL, 1, 3)
5360    FIELD(L2_TXPMA_TM_1, TM_FORCE_MPHY_TX_HS_DITHER_VAL, 0, 1)
5361REG32(L2_TXPMA_TM_2, 0x8808)
5362    FIELD(L2_TXPMA_TM_2, TXPMA_TM_2_31_8_RSVD, 24, 8)
5363    FIELD(L2_TXPMA_TM_2, TM_MPHY_TX_DRIVERLDO_PROG_6_0, 1, 7)
5364    FIELD(L2_TXPMA_TM_2, TM_FORCE_MPHY_TX_DRIVERLDO_PROG, 0, 1)
5365REG32(L2_TXPMA_TM_3, 0x880c)
5366    FIELD(L2_TXPMA_TM_3, TXPMA_TM_3_31_8_RSVD, 24, 8)
5367    FIELD(L2_TXPMA_TM_3, ANA_MPHY_BYP3_7_5_RSVD, 5, 3)
5368    FIELD(L2_TXPMA_TM_3, TM_MPHY_TX_DRIVERLDO_PROG_11_7, 0, 5)
5369REG32(L2_TXPMA_TM_4, 0x8810)
5370    FIELD(L2_TXPMA_TM_4, TXPMA_TM_4_31_8_RSVD, 24, 8)
5371    FIELD(L2_TXPMA_TM_4, TM_PIPE_TX_TX_DATA_WIDTH, 5, 3)
5372    FIELD(L2_TXPMA_TM_4, TM_FORCE_PIPE_TX_TX_DATA_WIDTH, 4, 1)
5373    FIELD(L2_TXPMA_TM_4, TM_PIPE_TX_POWERDOWN_VCM_HOLD, 3, 1)
5374    FIELD(L2_TXPMA_TM_4, TM_FORCE_PIPE_TX_POWERDOWN_VCM_HOLD, 2, 1)
5375    FIELD(L2_TXPMA_TM_4, TM_PIPE_TX_ANABOOST_POWERDOWN, 1, 1)
5376    FIELD(L2_TXPMA_TM_4, ANA_PIPE_BYP0_0_RSVD, 0, 1)
5377REG32(L2_TXPMA_TM_5, 0x8814)
5378    FIELD(L2_TXPMA_TM_5, TXPMA_TM_5_31_8_RSVD, 24, 8)
5379    FIELD(L2_TXPMA_TM_5, ANA_BSCAN_BYP0_7_4_RSVD, 4, 4)
5380    FIELD(L2_TXPMA_TM_5, TM_TX_BSCAN_SEL, 3, 1)
5381    FIELD(L2_TXPMA_TM_5, TM_FORCE_TX_BSCAN_SEL, 2, 1)
5382    FIELD(L2_TXPMA_TM_5, TM_TX_BSCAN_DATA, 1, 1)
5383    FIELD(L2_TXPMA_TM_5, TM_FORCE_TX_BSCAN_DATA, 0, 1)
5384REG32(L2_TXPMA_TM_6, 0x8818)
5385    FIELD(L2_TXPMA_TM_6, TXPMA_TM_6_31_8_RSVD, 24, 8)
5386    FIELD(L2_TXPMA_TM_6, TM_TX_ENABLE_ISI_LPBK, 7, 1)
5387    FIELD(L2_TXPMA_TM_6, TM_FORCE_TX_ENABLE_ISI_LPBK, 6, 1)
5388    FIELD(L2_TXPMA_TM_6, TM_TX_ENABLE_SER_LPBK, 5, 1)
5389    FIELD(L2_TXPMA_TM_6, TM_FORCE_TX_ENABLE_SER_LPBK, 4, 1)
5390    FIELD(L2_TXPMA_TM_6, TM_TX_ENABLE_RX_LIN_LPBK, 3, 1)
5391    FIELD(L2_TXPMA_TM_6, TM_FORCE_TX_ENABLE_RX_LIN_LPBK, 2, 1)
5392    FIELD(L2_TXPMA_TM_6, TM_TX_ENABLE_RCRVD_DATA_LPBK, 1, 1)
5393    FIELD(L2_TXPMA_TM_6, TM_FORCE_TX_ENABLE_RCRVD_DATA_LPBK, 0, 1)
5394REG32(L2_TXPMA_TM_7, 0x881c)
5395    FIELD(L2_TXPMA_TM_7, TXPMA_TM_7_31_8_RSVD, 24, 8)
5396    FIELD(L2_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_UPHY, 7, 1)
5397    FIELD(L2_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_UPHY, 6, 1)
5398    FIELD(L2_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_SERIALIZER, 5, 1)
5399    FIELD(L2_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_SERIALIZER, 4, 1)
5400    FIELD(L2_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_PIPE, 3, 1)
5401    FIELD(L2_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_PIPE, 2, 1)
5402    FIELD(L2_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_HSCLK, 1, 1)
5403    FIELD(L2_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_HSCLK, 0, 1)
5404REG32(L2_TXPMA_TM_8, 0x8820)
5405    FIELD(L2_TXPMA_TM_8, TXPMA_TM_8_31_8_RSVD, 24, 8)
5406    FIELD(L2_TXPMA_TM_8, ANA_LS_LFPS_BYP0_7_2_RSVD, 2, 6)
5407    FIELD(L2_TXPMA_TM_8, TM_TX_LS_LFPS_DATA, 1, 1)
5408    FIELD(L2_TXPMA_TM_8, TM_FORCE_TX_LS_LFPS_DATA, 0, 1)
5409REG32(L2_TXPMA_TM_9, 0x8824)
5410    FIELD(L2_TXPMA_TM_9, TXPMA_TM_9_31_8_RSVD, 24, 8)
5411    FIELD(L2_TXPMA_TM_9, ANA_MISC0_7_RSVD, 7, 1)
5412    FIELD(L2_TXPMA_TM_9, TM_TX_SERIALIZER_MODE, 6, 1)
5413    FIELD(L2_TXPMA_TM_9, TM_FORCE_TX_SERIALIZER_MODE, 5, 1)
5414    FIELD(L2_TXPMA_TM_9, TM_TX_ENABLE_HSCLK_DIVISION, 3, 2)
5415    FIELD(L2_TXPMA_TM_9, TM_FORCE_TX_ENABLE_HSCLK_DIVISION, 2, 1)
5416    FIELD(L2_TXPMA_TM_9, TM_TX_DRIVER_POLARITY, 1, 1)
5417    FIELD(L2_TXPMA_TM_9, TM_FORCE_TX_DRIVER_POLARITY, 0, 1)
5418REG32(L2_TXPMA_TM_10, 0x8828)
5419    FIELD(L2_TXPMA_TM_10, TXPMA_TM_10_31_8_RSVD, 24, 8)
5420    FIELD(L2_TXPMA_TM_10, ANA_MISC1_7_6_RSVD, 6, 2)
5421    FIELD(L2_TXPMA_TM_10, TM_TX_ENABLE_LOWLEAKAGE, 5, 1)
5422    FIELD(L2_TXPMA_TM_10, TM_FORCE_TX_ENABLE_LOWLEAKAGE, 4, 1)
5423    FIELD(L2_TXPMA_TM_10, TM_TX_ENABLE_REF, 3, 1)
5424    FIELD(L2_TXPMA_TM_10, TM_FORCE_TX_ENABLE_REF, 2, 1)
5425    FIELD(L2_TXPMA_TM_10, TM_TX_ENABLE_LDO, 1, 1)
5426    FIELD(L2_TXPMA_TM_10, TM_FORCE_TX_ENABLE_LDO, 0, 1)
5427REG32(L2_TXPMA_TM_11, 0x882c)
5428    FIELD(L2_TXPMA_TM_11, TXPMA_TM_11_31_8_RSVD, 24, 8)
5429    FIELD(L2_TXPMA_TM_11, ANA_VCM_BYP0_7_5_RSVD, 5, 3)
5430    FIELD(L2_TXPMA_TM_11, TM_TX_VCMHOLD_PROG, 1, 4)
5431    FIELD(L2_TXPMA_TM_11, TM_TX_VCMHOLD_OBSRV, 0, 1)
5432REG32(L2_TXPMA_TM_12, 0x8830)
5433    FIELD(L2_TXPMA_TM_12, TXPMA_TM_12_31_8_RSVD, 24, 8)
5434    FIELD(L2_TXPMA_TM_12, TM_TX_SER_POWERISLAND_OBSRV, 5, 3)
5435    FIELD(L2_TXPMA_TM_12, TM_TX_CLK_POWERISLAND_OBSRV, 1, 4)
5436    FIELD(L2_TXPMA_TM_12, ANA_PWR_ISLAND_BYP0_0_RSVD, 0, 1)
5437REG32(L2_TXPMA_TM_13, 0x8834)
5438    FIELD(L2_TXPMA_TM_13, TXPMA_TM_13_31_8_RSVD, 24, 8)
5439    FIELD(L2_TXPMA_TM_13, TM_TX_POWERISLAND_OBSRV, 0, 8)
5440REG32(L2_TXPMA_TM_14, 0x8838)
5441    FIELD(L2_TXPMA_TM_14, TXPMA_TM_14_31_8_RSVD, 24, 8)
5442    FIELD(L2_TXPMA_TM_14, ANA_MISC2_7_5_RSVD, 5, 3)
5443    FIELD(L2_TXPMA_TM_14, TM_TX_POWERISLAND_OBSRV, 3, 2)
5444    FIELD(L2_TXPMA_TM_14, PIPE_TM_TX_ANABOOST_POWER_OBSRV, 2, 1)
5445    FIELD(L2_TXPMA_TM_14, MPHY_TM_TX_ENABLE_DRIVERLDO_OBSRV, 1, 1)
5446    FIELD(L2_TXPMA_TM_14, MPHY_TM_TX_DRIVERLDO_REDC_SINKIQ, 0, 1)
5447REG32(L2_TXPMA_TM_15, 0x883c)
5448    FIELD(L2_TXPMA_TM_15, TXPMA_TM_15_31_8_RSVD, 24, 8)
5449    FIELD(L2_TXPMA_TM_15, PIPE_TM_TX_ANABOOST_PROG_7_0, 0, 8)
5450REG32(L2_TXPMA_TM_16, 0x8840)
5451    FIELD(L2_TXPMA_TM_16, TXPMA_TM_16_31_8_RSVD, 24, 8)
5452    FIELD(L2_TXPMA_TM_16, PIPE_TM_TX_ANABOOST_PROG_15_8, 0, 8)
5453REG32(L2_TXPMA_TM_17, 0x8844)
5454    FIELD(L2_TXPMA_TM_17, TXPMA_TM_17_31_8_RSVD, 24, 8)
5455    FIELD(L2_TXPMA_TM_17, TM_TX_RSVD2, 0, 8)
5456REG32(L2_TXPMA_TM_18, 0x8848)
5457    FIELD(L2_TXPMA_TM_18, TXPMA_TM_18_31_8_RSVD, 24, 8)
5458    FIELD(L2_TXPMA_TM_18, TM_TX_ENABLE_VDDREF_CORE, 7, 1)
5459    FIELD(L2_TXPMA_TM_18, TM_FORCE_TX_ENABLE_VDDREF_CORE, 6, 1)
5460    FIELD(L2_TXPMA_TM_18, TM_TX_ENABLE_RBYRFB_CORE, 5, 1)
5461    FIELD(L2_TXPMA_TM_18, TM_FORCE_TX_ENABLE_RBYRFB_CORE, 4, 1)
5462    FIELD(L2_TXPMA_TM_18, TM_TX_ENABLE_BGREF_CORE, 3, 1)
5463    FIELD(L2_TXPMA_TM_18, TM_FORCE_TX_ENABLE_BGREF_CORE, 2, 1)
5464    FIELD(L2_TXPMA_TM_18, TM_TX_ENABLE_BGFB_CORE, 1, 1)
5465    FIELD(L2_TXPMA_TM_18, TM_FORCE_TX_ENABLE_BGFB_CORE, 0, 1)
5466REG32(L2_TXPMA_TM_19, 0x884c)
5467    FIELD(L2_TXPMA_TM_19, TXPMA_TM_19_31_8_RSVD, 24, 8)
5468    FIELD(L2_TXPMA_TM_19, ANA_SATA_BYP0_RSVD, 6, 2)
5469    FIELD(L2_TXPMA_TM_19, TM_ZDIF_TX_SATA_OFFSET, 0, 6)
5470REG32(L2_TXPMA_TM_20, 0x8850)
5471    FIELD(L2_TXPMA_TM_20, TXPMA_TM_20_31_8_RSVD, 24, 8)
5472    FIELD(L2_TXPMA_TM_20, TM_TX_ELEC_IDLE_DELAY_ENTRY, 0, 8)
5473REG32(L2_TXPMA_TM_21, 0x8854)
5474    FIELD(L2_TXPMA_TM_21, TXPMA_TM_21_31_8_RSVD, 24, 8)
5475    FIELD(L2_TXPMA_TM_21, TM_TX_ELEC_IDLE_DELAY_EXIT, 0, 8)
5476REG32(L2_TXPMA_TM_22, 0x8858)
5477    FIELD(L2_TXPMA_TM_22, TXPMA_TM_22_31_8_RSVD, 24, 8)
5478    FIELD(L2_TXPMA_TM_22, TM_TX_ENABLE_LFPS_DELAY_ENTRY, 0, 8)
5479REG32(L2_TXPMA_TM_23, 0x885c)
5480    FIELD(L2_TXPMA_TM_23, TXPMA_TM_23_31_8_RSVD, 24, 8)
5481    FIELD(L2_TXPMA_TM_23, TM_TX_ENABLE_LFPS_DELAY_EXIT, 0, 8)
5482REG32(L2_TXPMA_TM_24, 0x8860)
5483    FIELD(L2_TXPMA_TM_24, TXPMA_TM_24_31_8_RSVD, 24, 8)
5484    FIELD(L2_TXPMA_TM_24, ANA_MISC6_7_RSVD, 7, 1)
5485    FIELD(L2_TXPMA_TM_24, TM_TX_EN_ANA_SUBLP_MODE, 6, 1)
5486    FIELD(L2_TXPMA_TM_24, TM_FORCE_TX_EN_ANA_SUBLP_MODE, 5, 1)
5487    FIELD(L2_TXPMA_TM_24, TM_TX_EN_DIG_SUBLP_MODE, 4, 1)
5488    FIELD(L2_TXPMA_TM_24, TM_FORCE_TX_EN_DIG_SUBLP_MODE, 3, 1)
5489    FIELD(L2_TXPMA_TM_24, TM_TX_DP_LVLDB0_OVRRD, 2, 1)
5490    FIELD(L2_TXPMA_TM_24, TM_FORCE_TX_DP_LVLDB0_OVRRD, 1, 1)
5491    FIELD(L2_TXPMA_TM_24, TM_TX_CLOCK_STOP_REQ, 0, 1)
5492REG32(L2_TXPMA_TM_25, 0x8864)
5493    FIELD(L2_TXPMA_TM_25, TXPMA_TM_25_31_8_RSVD, 24, 8)
5494    FIELD(L2_TXPMA_TM_25, ANA_MISC6_7_6_RSVD, 6, 2)
5495    FIELD(L2_TXPMA_TM_25, TM_TX_WRRD_SYNC_SUP_OBSRV_PLL, 5, 1)
5496    FIELD(L2_TXPMA_TM_25, TM_TX_WRRD_SYNC_SUP_OBSRV_RX, 4, 1)
5497    FIELD(L2_TXPMA_TM_25, TM_TX_LANE_LNG, 3, 1)
5498    FIELD(L2_TXPMA_TM_25, TM_FORCE_TX_LANE_LNG, 2, 1)
5499    FIELD(L2_TXPMA_TM_25, TM_TX_LANE_MASTER, 1, 1)
5500    FIELD(L2_TXPMA_TM_25, TM_FORCE_TX_LANE_MASTER, 0, 1)
5501REG32(L2_TXPMA_TM_26, 0x8868)
5502    FIELD(L2_TXPMA_TM_26, TXPMA_TM_26_31_8_RSVD, 24, 8)
5503    FIELD(L2_TXPMA_TM_26, TM_TXPMD_APB_RESET_DELAY, 0, 8)
5504REG32(L2_TXPMA_TM_27, 0x886c)
5505    FIELD(L2_TXPMA_TM_27, TXPMA_TM_27_31_8_RSVD, 24, 8)
5506    FIELD(L2_TXPMA_TM_27, TM_BSCAN_MODE_EN, 7, 1)
5507    FIELD(L2_TXPMA_TM_27, TM_FORCE_BSCAN_MODE_EN, 6, 1)
5508    FIELD(L2_TXPMA_TM_27, TM_PIPE_TX_FAST_EST_COMMON_MODE, 5, 1)
5509    FIELD(L2_TXPMA_TM_27, TM_FORCE_PIPE_TX_FAST_EST_COMMON_MODE, 4, 1)
5510    FIELD(L2_TXPMA_TM_27, TM_TX_PIPE_TX_ENABLE_LFPS, 3, 1)
5511    FIELD(L2_TXPMA_TM_27, TM_FORCE_TX_PIPE_TX_ENABLE_LFPS, 2, 1)
5512    FIELD(L2_TXPMA_TM_27, TM_TX_PIPE_TX_ENABLE_IDLE_MODE, 1, 1)
5513    FIELD(L2_TXPMA_TM_27, TM_FORCE_TX_PIPE_TX_ENABLE_IDLE_MODE, 0, 1)
5514REG32(L2_TXPMA_ST_0, 0x8b00)
5515    FIELD(L2_TXPMA_ST_0, TXPMA_ST_0_31_8_RSVD, 24, 8)
5516    FIELD(L2_TXPMA_ST_0, TX_PHY_MODE, 4, 4)
5517    FIELD(L2_TXPMA_ST_0, TX_PHY_GEAR, 0, 4)
5518REG32(L2_TXPMA_ST_1, 0x8b04)
5519    FIELD(L2_TXPMA_ST_1, TXPMA_ST_1_31_8_RSVD, 24, 8)
5520    FIELD(L2_TXPMA_ST_1, TX_ENABLE_HSCLK_DIVISION, 6, 2)
5521    FIELD(L2_TXPMA_ST_1, PIPE_TX_TRISTATE, 5, 1)
5522    FIELD(L2_TXPMA_ST_1, TX_ENABLE_SUPPLY_SERIALIZER, 4, 1)
5523    FIELD(L2_TXPMA_ST_1, TX_ENABLE_SUPPLY_HSCLK, 3, 1)
5524    FIELD(L2_TXPMA_ST_1, TX_ENABLE_SUPPLY_MPHY, 2, 1)
5525    FIELD(L2_TXPMA_ST_1, TX_ENABLE_SUPPLY_PIPE, 1, 1)
5526    FIELD(L2_TXPMA_ST_1, TX_ENABLE_SUPPLY_UPHY, 0, 1)
5527REG32(L2_TXPMA_ST_2, 0x8b08)
5528    FIELD(L2_TXPMA_ST_2, TXPMA_ST_2_31_8_RSVD, 24, 8)
5529    FIELD(L2_TXPMA_ST_2, ANA_ST2_7_5_SPARE, 5, 3)
5530    FIELD(L2_TXPMA_ST_2, PIPE_TX_ENABLE_RXDET, 4, 1)
5531    FIELD(L2_TXPMA_ST_2, PIPE_TX_ENABLE_IDLE_MODE, 2, 2)
5532    FIELD(L2_TXPMA_ST_2, PIPE_TX_ENABLE_LFPS, 0, 2)
5533REG32(L2_TXPMA_ST_3, 0x8b0c)
5534    FIELD(L2_TXPMA_ST_3, TXPMA_ST_3_31_8_RSVD, 24, 8)
5535    FIELD(L2_TXPMA_ST_3, ANA_ST3_7_6_SPARE, 6, 2)
5536    FIELD(L2_TXPMA_ST_3, TX_LSEG_DN_RESCAL_CODE, 0, 6)
5537REG32(L2_TXPMA_ST_4, 0x8b10)
5538    FIELD(L2_TXPMA_ST_4, TXPMA_ST_4_31_8_RSVD, 24, 8)
5539    FIELD(L2_TXPMA_ST_4, ANA_ST4_7_6_SPARE, 6, 2)
5540    FIELD(L2_TXPMA_ST_4, TX_USEG_DP_RESCAL_CODE, 0, 6)
5541REG32(L2_TXPMA_ST_5, 0x8b14)
5542    FIELD(L2_TXPMA_ST_5, TXPMA_ST_5_31_8_RSVD, 24, 8)
5543    FIELD(L2_TXPMA_ST_5, ANA_ST5_7_6_SPARE, 6, 2)
5544    FIELD(L2_TXPMA_ST_5, PIPE_TX_LOCALFS, 0, 6)
5545REG32(L2_TXPMA_ST_6, 0x8b18)
5546    FIELD(L2_TXPMA_ST_6, TXPMA_ST_6_31_8_RSVD, 24, 8)
5547    FIELD(L2_TXPMA_ST_6, ANA_ST6_7_SPARE, 7, 1)
5548    FIELD(L2_TXPMA_ST_6, PIPE_TX_LOCALTXCOEFFICIENTSVALID, 6, 1)
5549    FIELD(L2_TXPMA_ST_6, PIPE_TX_LOCALLF, 0, 6)
5550REG32(L2_TXPMA_ST_7, 0x8b1c)
5551    FIELD(L2_TXPMA_ST_7, TXPMA_ST_7_31_8_RSVD, 24, 8)
5552    FIELD(L2_TXPMA_ST_7, PIPE_TX_LOCALTXPRESETCOEFFICIENTS_7_0, 0, 8)
5553REG32(L2_TXPMA_ST_8, 0x8b20)
5554    FIELD(L2_TXPMA_ST_8, TXPMA_ST_8_31_8_RSVD, 24, 8)
5555    FIELD(L2_TXPMA_ST_8, PIPE_TX_LOCALTXPRESETCOEFFICIENTS_15_8, 0, 8)
5556REG32(L2_TXPMA_ST_9, 0x8b24)
5557    FIELD(L2_TXPMA_ST_9, TXPMA_ST_9_31_8_RSVD, 24, 8)
5558    FIELD(L2_TXPMA_ST_9, ANA_ST9_7_2_SPARE, 2, 6)
5559    FIELD(L2_TXPMA_ST_9, PIPE_TX_LOCALTXPRESETCOEFFICIENTS_17_16, 0, 2)
5560REG32(L2_TXPMD_TM_0, 0x8c00)
5561    FIELD(L2_TXPMD_TM_0, TXPMD_TM_0_31_8_RSVD, 24, 8)
5562    FIELD(L2_TXPMD_TM_0, PIPE_TM_TX_USEG_POST_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
5563    FIELD(L2_TXPMD_TM_0, PIPE_TM_TX_USEG_POST_DISABLE_ENDPOS, 0, 5)
5564REG32(L2_TXPMD_TM_1, 0x8c04)
5565    FIELD(L2_TXPMD_TM_1, TXPMD_TM_1_31_8_RSVD, 24, 8)
5566    FIELD(L2_TXPMD_TM_1, PIPE_TM_TX_USEG_POST_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
5567    FIELD(L2_TXPMD_TM_1, PIPE_TM_TX_USEG_POST_DISABLE_STARTPOS, 0, 5)
5568REG32(L2_TXPMD_TM_2, 0x8c08)
5569    FIELD(L2_TXPMD_TM_2, TXPMD_TM_2_31_8_RSVD, 24, 8)
5570    FIELD(L2_TXPMD_TM_2, PIPE_TM_TX_USEG_POST_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
5571    FIELD(L2_TXPMD_TM_2, PIPE_TM_TX_USEG_POST_EMPHASIS_ENDPOS, 0, 5)
5572REG32(L2_TXPMD_TM_3, 0x8c0c)
5573    FIELD(L2_TXPMD_TM_3, TXPMD_TM_3_31_8_RSVD, 24, 8)
5574    FIELD(L2_TXPMD_TM_3, PIPE_TM_TX_USEG_POST_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
5575    FIELD(L2_TXPMD_TM_3, PIPE_TM_TX_USEG_POST_EMPHASIS_STARTPOS, 0, 5)
5576REG32(L2_TXPMD_TM_4, 0x8c10)
5577    FIELD(L2_TXPMD_TM_4, TXPMD_TM_4_31_8_RSVD, 24, 8)
5578    FIELD(L2_TXPMD_TM_4, PIPE_TM_TX_USEG_POST_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
5579    FIELD(L2_TXPMD_TM_4, PIPE_TM_TX_USEG_POST_MAINSEL_ENDPOS, 0, 5)
5580REG32(L2_TXPMD_TM_5, 0x8c14)
5581    FIELD(L2_TXPMD_TM_5, TXPMD_TM_5_31_8_RSVD, 24, 8)
5582    FIELD(L2_TXPMD_TM_5, PIPE_TM_TX_USEG_POST_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
5583    FIELD(L2_TXPMD_TM_5, PIPE_TM_TX_USEG_POST_MAINSEL_STARTPOS, 0, 5)
5584REG32(L2_TXPMD_TM_6, 0x8c18)
5585    FIELD(L2_TXPMD_TM_6, TXPMD_TM_6_31_8_RSVD, 24, 8)
5586    FIELD(L2_TXPMD_TM_6, PIPE_TM_TX_USEG_POST_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
5587    FIELD(L2_TXPMD_TM_6, PIPE_TM_TX_USEG_POST_MARGIN_ENDPOS, 0, 5)
5588REG32(L2_TXPMD_TM_7, 0x8c1c)
5589    FIELD(L2_TXPMD_TM_7, TXPMD_TM_7_31_8_RSVD, 24, 8)
5590    FIELD(L2_TXPMD_TM_7, PIPE_TM_TX_USEG_POST_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
5591    FIELD(L2_TXPMD_TM_7, PIPE_TM_TX_USEG_POST_MARGIN_STARTPOS, 0, 5)
5592REG32(L2_TXPMD_TM_8, 0x8c20)
5593    FIELD(L2_TXPMD_TM_8, TXPMD_TM_8_31_8_RSVD, 24, 8)
5594    FIELD(L2_TXPMD_TM_8, PIPE_TM_TX_USEG_PRE_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
5595    FIELD(L2_TXPMD_TM_8, PIPE_TM_TX_USEG_PRE_DISABLE_ENDPOS, 0, 5)
5596REG32(L2_TXPMD_TM_9, 0x8c24)
5597    FIELD(L2_TXPMD_TM_9, TXPMD_TM_9_31_8_RSVD, 24, 8)
5598    FIELD(L2_TXPMD_TM_9, PIPE_TM_TX_USEG_PRE_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
5599    FIELD(L2_TXPMD_TM_9, PIPE_TM_TX_USEG_PRE_DISABLE_STARTPOS, 0, 5)
5600REG32(L2_TXPMD_TM_10, 0x8c28)
5601    FIELD(L2_TXPMD_TM_10, TXPMD_TM_10_31_8_RSVD, 24, 8)
5602    FIELD(L2_TXPMD_TM_10, PIPE_TM_TX_USEG_PRE_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
5603    FIELD(L2_TXPMD_TM_10, PIPE_TM_TX_USEG_PRE_EMPHASIS_ENDPOS, 0, 5)
5604REG32(L2_TXPMD_TM_11, 0x8c2c)
5605    FIELD(L2_TXPMD_TM_11, TXPMD_TM_11_31_8_RSVD, 24, 8)
5606    FIELD(L2_TXPMD_TM_11, PIPE_TM_TX_USEG_PRE_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
5607    FIELD(L2_TXPMD_TM_11, PIPE_TM_TX_USEG_PRE_EMPHASIS_STARTPOS, 0, 5)
5608REG32(L2_TXPMD_TM_12, 0x8c30)
5609    FIELD(L2_TXPMD_TM_12, TXPMD_TM_12_31_8_RSVD, 24, 8)
5610    FIELD(L2_TXPMD_TM_12, PIPE_TM_TX_USEG_PRE_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
5611    FIELD(L2_TXPMD_TM_12, PIPE_TM_TX_USEG_PRE_MAINSEL_ENDPOS, 0, 5)
5612REG32(L2_TXPMD_TM_13, 0x8c34)
5613    FIELD(L2_TXPMD_TM_13, TXPMD_TM_13_31_8_RSVD, 24, 8)
5614    FIELD(L2_TXPMD_TM_13, PIPE_TM_TX_USEG_PRE_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
5615    FIELD(L2_TXPMD_TM_13, PIPE_TM_TX_USEG_PRE_MAINSEL_STARTPOS, 0, 5)
5616REG32(L2_TXPMD_TM_14, 0x8c38)
5617    FIELD(L2_TXPMD_TM_14, TXPMD_TM_14_31_8_RSVD, 24, 8)
5618    FIELD(L2_TXPMD_TM_14, PIPE_TM_TX_USEG_PRE_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
5619    FIELD(L2_TXPMD_TM_14, PIPE_TM_TX_USEG_PRE_MARGIN_ENDPOS, 0, 5)
5620REG32(L2_TXPMD_TM_15, 0x8c3c)
5621    FIELD(L2_TXPMD_TM_15, TXPMD_TM_15_31_8_RSVD, 24, 8)
5622    FIELD(L2_TXPMD_TM_15, PIPE_TM_TX_USEG_PRE_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
5623    FIELD(L2_TXPMD_TM_15, PIPE_TM_TX_USEG_PRE_MARGIN_STARTPOS, 0, 5)
5624REG32(L2_TXPMD_TM_16, 0x8c40)
5625    FIELD(L2_TXPMD_TM_16, TXPMD_TM_16_31_8_RSVD, 24, 8)
5626    FIELD(L2_TXPMD_TM_16, PIPE_TM_TX_LSEG_POST_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
5627    FIELD(L2_TXPMD_TM_16, PIPE_TM_TX_LSEG_POST_DISABLE_ENDPOS, 0, 5)
5628REG32(L2_TXPMD_TM_17, 0x8c44)
5629    FIELD(L2_TXPMD_TM_17, TXPMD_TM_17_31_8_RSVD, 24, 8)
5630    FIELD(L2_TXPMD_TM_17, PIPE_TM_TX_LSEG_POST_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
5631    FIELD(L2_TXPMD_TM_17, PIPE_TM_TX_LSEG_POST_DISABLE_STARTPOS, 0, 5)
5632REG32(L2_TXPMD_TM_18, 0x8c48)
5633    FIELD(L2_TXPMD_TM_18, TXPMD_TM_18_31_8_RSVD, 24, 8)
5634    FIELD(L2_TXPMD_TM_18, PIPE_TM_TX_LSEG_POST_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
5635    FIELD(L2_TXPMD_TM_18, PIPE_TM_TX_LSEG_POST_EMPHASIS_ENDPOS, 0, 5)
5636REG32(L2_TXPMD_TM_19, 0x8c4c)
5637    FIELD(L2_TXPMD_TM_19, TXPMD_TM_19_31_8_RSVD, 24, 8)
5638    FIELD(L2_TXPMD_TM_19, PIPE_TM_TX_LSEG_POST_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
5639    FIELD(L2_TXPMD_TM_19, PIPE_TM_TX_LSEG_POST_EMPHASIS_STARTPOS, 0, 5)
5640REG32(L2_TXPMD_TM_20, 0x8c50)
5641    FIELD(L2_TXPMD_TM_20, TXPMD_TM_20_31_8_RSVD, 24, 8)
5642    FIELD(L2_TXPMD_TM_20, PIPE_TM_TX_LSEG_POST_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
5643    FIELD(L2_TXPMD_TM_20, PIPE_TM_TX_LSEG_POST_MAINSEL_ENDPOS, 0, 5)
5644REG32(L2_TXPMD_TM_21, 0x8c54)
5645    FIELD(L2_TXPMD_TM_21, TXPMD_TM_21_31_8_RSVD, 24, 8)
5646    FIELD(L2_TXPMD_TM_21, PIPE_TM_TX_LSEG_POST_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
5647    FIELD(L2_TXPMD_TM_21, PIPE_TM_TX_LSEG_POST_MAINSEL_STARTPOS, 0, 5)
5648REG32(L2_TXPMD_TM_22, 0x8c58)
5649    FIELD(L2_TXPMD_TM_22, TXPMD_TM_22_31_8_RSVD, 24, 8)
5650    FIELD(L2_TXPMD_TM_22, PIPE_TM_TX_LSEG_POST_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
5651    FIELD(L2_TXPMD_TM_22, PIPE_TM_TX_LSEG_POST_MARGIN_ENDPOS, 0, 5)
5652REG32(L2_TXPMD_TM_23, 0x8c5c)
5653    FIELD(L2_TXPMD_TM_23, TXPMD_TM_23_31_8_RSVD, 24, 8)
5654    FIELD(L2_TXPMD_TM_23, PIPE_TM_TX_LSEG_POST_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
5655    FIELD(L2_TXPMD_TM_23, PIPE_TM_TX_LSEG_POST_MARGIN_STARTPOS, 0, 5)
5656REG32(L2_TXPMD_TM_24, 0x8c60)
5657    FIELD(L2_TXPMD_TM_24, TXPMD_TM_24_31_8_RSVD, 24, 8)
5658    FIELD(L2_TXPMD_TM_24, PIPE_TM_TX_LSEG_PRE_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
5659    FIELD(L2_TXPMD_TM_24, PIPE_TM_TX_LSEG_PRE_DISABLE_ENDPOS, 0, 5)
5660REG32(L2_TXPMD_TM_25, 0x8c64)
5661    FIELD(L2_TXPMD_TM_25, TXPMD_TM_25_31_8_RSVD, 24, 8)
5662    FIELD(L2_TXPMD_TM_25, PIPE_TM_TX_LSEG_PRE_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
5663    FIELD(L2_TXPMD_TM_25, PIPE_TM_TX_LSEG_PRE_DISABLE_STARTPOS, 0, 5)
5664REG32(L2_TXPMD_TM_26, 0x8c68)
5665    FIELD(L2_TXPMD_TM_26, TXPMD_TM_26_31_8_RSVD, 24, 8)
5666    FIELD(L2_TXPMD_TM_26, PIPE_TM_TX_LSEG_PRE_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
5667    FIELD(L2_TXPMD_TM_26, PIPE_TM_TX_LSEG_PRE_EMPHASIS_ENDPOS, 0, 5)
5668REG32(L2_TXPMD_TM_27, 0x8c6c)
5669    FIELD(L2_TXPMD_TM_27, TXPMD_TM_27_31_8_RSVD, 24, 8)
5670    FIELD(L2_TXPMD_TM_27, PIPE_TM_TX_LSEG_PRE_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
5671    FIELD(L2_TXPMD_TM_27, PIPE_TM_TX_LSEG_PRE_EMPHASIS_STARTPOS, 0, 5)
5672REG32(L2_TXPMD_TM_28, 0x8c70)
5673    FIELD(L2_TXPMD_TM_28, TXPMD_TM_28_31_8_RSVD, 24, 8)
5674    FIELD(L2_TXPMD_TM_28, PIPE_TM_TX_LSEG_PRE_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
5675    FIELD(L2_TXPMD_TM_28, PIPE_TM_TX_LSEG_PRE_MAINSEL_ENDPOS, 0, 5)
5676REG32(L2_TXPMD_TM_29, 0x8c74)
5677    FIELD(L2_TXPMD_TM_29, TXPMD_TM_29_31_8_RSVD, 24, 8)
5678    FIELD(L2_TXPMD_TM_29, PIPE_TM_TX_LSEG_PRE_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
5679    FIELD(L2_TXPMD_TM_29, PIPE_TM_TX_LSEG_PRE_MAINSEL_STARTPOS, 0, 5)
5680REG32(L2_TXPMD_TM_30, 0x8c78)
5681    FIELD(L2_TXPMD_TM_30, TXPMD_TM_30_31_8_RSVD, 24, 8)
5682    FIELD(L2_TXPMD_TM_30, PIPE_TM_TX_LSEG_PRE_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
5683    FIELD(L2_TXPMD_TM_30, PIPE_TM_TX_LSEG_PRE_MARGIN_ENDPOS, 0, 5)
5684REG32(L2_TXPMD_TM_31, 0x8c7c)
5685    FIELD(L2_TXPMD_TM_31, TXPMD_TM_31_31_8_RSVD, 24, 8)
5686    FIELD(L2_TXPMD_TM_31, PIPE_TM_TX_LSEG_PRE_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
5687    FIELD(L2_TXPMD_TM_31, PIPE_TM_TX_LSEG_PRE_MARGIN_STARTPOS, 0, 5)
5688REG32(L2_TXPMD_TM_32, 0x8c80)
5689    FIELD(L2_TXPMD_TM_32, TXPMD_TM_32_31_8_RSVD, 24, 8)
5690    FIELD(L2_TXPMD_TM_32, PIPE_TM_TX_PRE_FS_DIVISION_COEF_7_0, 0, 8)
5691REG32(L2_TXPMD_TM_33, 0x8c84)
5692    FIELD(L2_TXPMD_TM_33, TXPMD_TM_33_31_8_RSVD, 24, 8)
5693    FIELD(L2_TXPMD_TM_33, PIPE_TM_TX_PRE_FS_DIVISION_COEF_15_8, 0, 8)
5694REG32(L2_TXPMD_TM_34, 0x8c88)
5695    FIELD(L2_TXPMD_TM_34, TXPMD_TM_34_31_8_RSVD, 24, 8)
5696    FIELD(L2_TXPMD_TM_34, PIPE_TM_TX_MAIN_FS_DIVISION_COEF_7_0, 0, 8)
5697REG32(L2_TXPMD_TM_35, 0x8c8c)
5698    FIELD(L2_TXPMD_TM_35, TXPMD_TM_35_31_8_RSVD, 24, 8)
5699    FIELD(L2_TXPMD_TM_35, PIPE_TM_TX_MAIN_FS_DIVISION_COEF_15_8, 0, 8)
5700REG32(L2_TXPMD_TM_36, 0x8c90)
5701    FIELD(L2_TXPMD_TM_36, TXPMD_TM_36_31_8_RSVD, 24, 8)
5702    FIELD(L2_TXPMD_TM_36, PIPE_TM_TX_POST_FS_DIVISION_COEF_7_0, 0, 8)
5703REG32(L2_TXPMD_TM_37, 0x8c94)
5704    FIELD(L2_TXPMD_TM_37, TXPMD_TM_37_31_8_RSVD, 24, 8)
5705    FIELD(L2_TXPMD_TM_37, PIPE_TM_TX_POST_FS_DIVISION_COEF_15_8, 0, 8)
5706REG32(L2_TXPMD_TM_38, 0x8c98)
5707    FIELD(L2_TXPMD_TM_38, TXPMD_TM_38_31_8_RSVD, 24, 8)
5708    FIELD(L2_TXPMD_TM_38, ANA_MISC0_7_RSVD, 7, 1)
5709    FIELD(L2_TXPMD_TM_38, PIPE_TM_TX_ENABLE_SWNW_CNTRL_BYP, 6, 1)
5710    FIELD(L2_TXPMD_TM_38, PIPE_TM_TX_ENABLE_TRISTATE_BYP, 5, 1)
5711    FIELD(L2_TXPMD_TM_38, PIPE_TM_TX_TRISTATE, 4, 1)
5712    FIELD(L2_TXPMD_TM_38, TM_TX_DRIVERLDO_RXDET_BYP, 3, 1)
5713    FIELD(L2_TXPMD_TM_38, TM_TX_DRIVERLDO_IDLE_BYP, 2, 1)
5714    FIELD(L2_TXPMD_TM_38, TM_TX_DRIVERLDO_EN_RXDET_BYP, 1, 1)
5715    FIELD(L2_TXPMD_TM_38, TM_TX_DRIVERLDO_EN_IDLE_BYP, 0, 1)
5716REG32(L2_TXPMD_TM_39, 0x8c9c)
5717    FIELD(L2_TXPMD_TM_39, TXPMD_TM_39_31_8_RSVD, 24, 8)
5718    FIELD(L2_TXPMD_TM_39, ANA_MPHY_BYP0_7_3_RSVD, 3, 5)
5719    FIELD(L2_TXPMD_TM_39, MPHY_TM_TX_OVRD_DEEMPH_TRIM, 2, 1)
5720    FIELD(L2_TXPMD_TM_39, MPHY_TM_TX_ENABLE_DEEMPH, 1, 1)
5721    FIELD(L2_TXPMD_TM_39, MPHY_TM_TX_OVRD_ENABLE_DEEMPH, 0, 1)
5722REG32(L2_TXPMD_TM_40, 0x8ca0)
5723    FIELD(L2_TXPMD_TM_40, TXPMD_TM_40_31_8_RSVD, 24, 8)
5724    FIELD(L2_TXPMD_TM_40, MPHY_TM_TX_DEEMPH_TRIM_7_0, 0, 8)
5725REG32(L2_TXPMD_TM_41, 0x8ca4)
5726    FIELD(L2_TXPMD_TM_41, TXPMD_TM_41_31_8_RSVD, 24, 8)
5727    FIELD(L2_TXPMD_TM_41, MPHY_TM_TX_DEEMPH_TRIM_15_8, 0, 8)
5728REG32(L2_TXPMD_TM_42, 0x8ca8)
5729    FIELD(L2_TXPMD_TM_42, TXPMD_TM_42_31_8_RSVD, 24, 8)
5730    FIELD(L2_TXPMD_TM_42, ANA_MPHY_BYP3_7_5_RSVD, 5, 3)
5731    FIELD(L2_TXPMD_TM_42, MPHY_TM_TX_OVRD_LS_DATA, 1, 4)
5732    FIELD(L2_TXPMD_TM_42, MPHY_TM_TX_ENABLE_OVRD_LS_DATA, 0, 1)
5733REG32(L2_TXPMD_TM_43, 0x8cac)
5734    FIELD(L2_TXPMD_TM_43, TXPMD_TM_43_31_8_RSVD, 24, 8)
5735    FIELD(L2_TXPMD_TM_43, ANA_MPHY_BYP4_7_4_RSVD, 4, 4)
5736    FIELD(L2_TXPMD_TM_43, MPHY_TM_TX_OVRD_LS_DATA_BAR, 0, 4)
5737REG32(L2_TXPMD_TM_44, 0x8cb0)
5738    FIELD(L2_TXPMD_TM_44, TXPMD_TM_44_31_8_RSVD, 24, 8)
5739    FIELD(L2_TXPMD_TM_44, ANA_PIPE_BYP38_7_6_RSVD, 6, 2)
5740    FIELD(L2_TXPMD_TM_44, PIPE_TM_TX_EN_PRE_LFPS_PATH, 5, 1)
5741    FIELD(L2_TXPMD_TM_44, PIPE_TM_TX_OVRD_EN_PRE_LFPS_PATH, 4, 1)
5742    FIELD(L2_TXPMD_TM_44, PIPE_TM_TX_EN_POST_LFPS_PATH, 3, 1)
5743    FIELD(L2_TXPMD_TM_44, PIPE_TM_TX_OVRD_EN_POST_LFPS_PATH, 2, 1)
5744    FIELD(L2_TXPMD_TM_44, PIPE_TM_TX_EN_MAIN_LFPS_PATH, 1, 1)
5745    FIELD(L2_TXPMD_TM_44, PIPE_TM_TX_OVRD_EN_MAIN_LFPS_PATH, 0, 1)
5746REG32(L2_TXPMD_TM_45, 0x8cb4)
5747    FIELD(L2_TXPMD_TM_45, TXPMD_TM_45_31_8_RSVD, 24, 8)
5748    FIELD(L2_TXPMD_TM_45, ANA_DP_BYP0_7_6_RSVD, 6, 2)
5749    FIELD(L2_TXPMD_TM_45, DP_TM_TX_DP_ENABLE_POST2_PATH, 5, 1)
5750    FIELD(L2_TXPMD_TM_45, DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH, 4, 1)
5751    FIELD(L2_TXPMD_TM_45, DP_TM_TX_DP_ENABLE_POST1_PATH, 3, 1)
5752    FIELD(L2_TXPMD_TM_45, DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH, 2, 1)
5753    FIELD(L2_TXPMD_TM_45, DP_TM_TX_DP_ENABLE_MAIN_PATH, 1, 1)
5754    FIELD(L2_TXPMD_TM_45, DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH, 0, 1)
5755REG32(L2_TXPMD_TM_46, 0x8cb8)
5756    FIELD(L2_TXPMD_TM_46, TXPMD_TM_46_31_8_RSVD, 24, 8)
5757    FIELD(L2_TXPMD_TM_46, ANA_PIPE_BYP39_7_6_RSVD, 6, 2)
5758    FIELD(L2_TXPMD_TM_46, PIPE_TM_TX_PIPE_ENABLE_PRE_PATH, 5, 1)
5759    FIELD(L2_TXPMD_TM_46, PIPE_TM_TX_OVRD_PIPE_ENABLE_PRE_PATH, 4, 1)
5760    FIELD(L2_TXPMD_TM_46, PIPE_TM_TX_PIPE_ENABLE_POST_PATH, 3, 1)
5761    FIELD(L2_TXPMD_TM_46, PIPE_TM_TX_OVRD_PIPE_ENABLE_POST_PATH, 2, 1)
5762    FIELD(L2_TXPMD_TM_46, PIPE_TM_TX_PIPE_ENABLE_MAIN_PATH, 1, 1)
5763    FIELD(L2_TXPMD_TM_46, PIPE_TM_TX_OVRD_PIPE_ENABLE_MAIN_PATH, 0, 1)
5764REG32(L2_TXPMD_TM_47, 0x8cbc)
5765    FIELD(L2_TXPMD_TM_47, TXPMD_TM_47_31_8_RSVD, 24, 8)
5766    FIELD(L2_TXPMD_TM_47, TM_TX_RSVD1, 0, 8)
5767REG32(L2_TXPMD_TM_48, 0x8cc0)
5768    FIELD(L2_TXPMD_TM_48, TXPMD_TM_48_31_8_RSVD, 24, 8)
5769    FIELD(L2_TXPMD_TM_48, ANA_MISC2_7_6_RSVD, 6, 2)
5770    FIELD(L2_TXPMD_TM_48, TM_FORCE_RESULTANT_MARGINING_FACTOR, 5, 1)
5771    FIELD(L2_TXPMD_TM_48, TM_RESULTANT_MARGINING_FACTOR, 0, 5)
5772REG32(L2_TM_ANA_BYP_1, 0x9004)
5773    FIELD(L2_TM_ANA_BYP_1, TM_ANA_BYP_1_31_8_RSVD, 24, 8)
5774    FIELD(L2_TM_ANA_BYP_1, MPHY_PWM_DES_PDZ, 7, 1)
5775    FIELD(L2_TM_ANA_BYP_1, FORCE_MPHY_PWM_DES_PDZ, 6, 1)
5776    FIELD(L2_TM_ANA_BYP_1, MPHY_PWMB_SYS_ENABLE, 5, 1)
5777    FIELD(L2_TM_ANA_BYP_1, FORCE_MPHY_PWMB_SYS_ENABLE, 4, 1)
5778    FIELD(L2_TM_ANA_BYP_1, MPHY_PSO_SQUELCH, 3, 1)
5779    FIELD(L2_TM_ANA_BYP_1, FORCE_MPHY_PSO_SQUELCH, 2, 1)
5780    FIELD(L2_TM_ANA_BYP_1, MPHY_PSO_LSRX, 1, 1)
5781    FIELD(L2_TM_ANA_BYP_1, FORCE_MPHY_PSO_LSRX, 0, 1)
5782REG32(L2_TM_ANA_BYP_2, 0x9008)
5783    FIELD(L2_TM_ANA_BYP_2, TM_ANA_BYP_2_31_8_RSVD, 24, 8)
5784    FIELD(L2_TM_ANA_BYP_2, MPHY_PWM_LSPREAMP_PD, 7, 1)
5785    FIELD(L2_TM_ANA_BYP_2, FORCE_MPHY_PWM_LSPREAMP_PD, 6, 1)
5786    FIELD(L2_TM_ANA_BYP_2, MPHY_PWM_GEAR_SEL, 3, 3)
5787    FIELD(L2_TM_ANA_BYP_2, FORCE_MPHY_PWM_GEAR_SEL, 2, 1)
5788    FIELD(L2_TM_ANA_BYP_2, MPHY_PWM_DET_PD, 1, 1)
5789    FIELD(L2_TM_ANA_BYP_2, FORCE_MPHY_PWM_DET_PD, 0, 1)
5790REG32(L2_TM_ANA_BYP_3, 0x900c)
5791    FIELD(L2_TM_ANA_BYP_3, TM_ANA_BYP_3_31_8_RSVD, 24, 8)
5792    FIELD(L2_TM_ANA_BYP_3, MPHY_RX_MASK_BURST_START, 7, 1)
5793    FIELD(L2_TM_ANA_BYP_3, FORCE_MPHY_RX_MASK_BURST_START, 6, 1)
5794    FIELD(L2_TM_ANA_BYP_3, MPHY_RX_GATE_SYMBOL_CLK, 5, 1)
5795    FIELD(L2_TM_ANA_BYP_3, FORCE_MPHY_RX_GATE_SYMBOL_CLK, 4, 1)
5796    FIELD(L2_TM_ANA_BYP_3, MPHY_PWM_PREAMP_BIAS_PD, 3, 1)
5797    FIELD(L2_TM_ANA_BYP_3, FORCE_MPHY_PWM_PREAMP_BIAS_PD, 2, 1)
5798    FIELD(L2_TM_ANA_BYP_3, MPHY_PWM_LSPREAMP_STANDBYSLEEPSTALL, 1, 1)
5799    FIELD(L2_TM_ANA_BYP_3, FORCE_MPHY_PWM_LSPREAMP_STANDBYSLEEPSTAL, 0, 1)
5800REG32(L2_TM_ANA_BYP_4, 0x9010)
5801    FIELD(L2_TM_ANA_BYP_4, TM_ANA_BYP_4_31_8_RSVD, 24, 8)
5802    FIELD(L2_TM_ANA_BYP_4, HSRX_RSTB, 7, 1)
5803    FIELD(L2_TM_ANA_BYP_4, FORCE_HSRX_RSTB, 6, 1)
5804    FIELD(L2_TM_ANA_BYP_4, MPHY_RX_TERM_ENABLE, 5, 1)
5805    FIELD(L2_TM_ANA_BYP_4, FORCE_MPHY_RX_TERM_ENABLE, 4, 1)
5806    FIELD(L2_TM_ANA_BYP_4, MPHY_RX_MUX_TYP1B_TYP2, 3, 1)
5807    FIELD(L2_TM_ANA_BYP_4, FORCE_MPHY_RX_MUX_TYP1B_TYP2, 2, 1)
5808    FIELD(L2_TM_ANA_BYP_4, MPHY_RX_MUX_HSB_LS, 1, 1)
5809    FIELD(L2_TM_ANA_BYP_4, FORCE_MPHY_RX_MUX_HSB_LS, 0, 1)
5810REG32(L2_TM_ANA_BYP_5, 0x9014)
5811    FIELD(L2_TM_ANA_BYP_5, TM_ANA_BYP_5_31_8_RSVD, 24, 8)
5812    FIELD(L2_TM_ANA_BYP_5, MPHY_SQ_SWAP_POLARITY, 5, 1)
5813    FIELD(L2_TM_ANA_BYP_5, FORCE_MPHY_SQ_SWAP_POLARITY, 4, 1)
5814    FIELD(L2_TM_ANA_BYP_5, MPHY_SQ_PD, 3, 1)
5815    FIELD(L2_TM_ANA_BYP_5, FORCE_MPHY_SQ_PD, 2, 1)
5816    FIELD(L2_TM_ANA_BYP_5, MPHY_SQ_DETECTOR_PD, 1, 1)
5817    FIELD(L2_TM_ANA_BYP_5, FORCE_MPHY_SQ_DETECTOR_PD, 0, 1)
5818REG32(L2_TM_ANA_BYP_7, 0x9018)
5819    FIELD(L2_TM_ANA_BYP_7, TM_ANA_BYP_7_31_8_RSVD, 24, 8)
5820    FIELD(L2_TM_ANA_BYP_7, PIPE_RXEQTRAINING, 7, 1)
5821    FIELD(L2_TM_ANA_BYP_7, FORCE_PIPE_RXEQTRAINING, 6, 1)
5822    FIELD(L2_TM_ANA_BYP_7, PIPE_RX_TERM_ENABLE, 5, 1)
5823    FIELD(L2_TM_ANA_BYP_7, FORCE_PIPE_RX_TERM_ENABLE, 4, 1)
5824REG32(L2_TM_ANA_BYP_8, 0x901c)
5825    FIELD(L2_TM_ANA_BYP_8, TM_ANA_BYP_8_31_8_RSVD, 24, 8)
5826    FIELD(L2_TM_ANA_BYP_8, UPHY_BIASGEN_IRCONST_IO_MIRROR_ENABLE, 7, 1)
5827    FIELD(L2_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_IRCONST_IO_MIRROR_ENABLE, 6, 1)
5828    FIELD(L2_TM_ANA_BYP_8, UPHY_BIASGEN_IRCONST_CORE_MIRROR_ENABLE, 5, 1)
5829    FIELD(L2_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_IRCONST_CORE_MIRROR_ENABLE, 4, 1)
5830    FIELD(L2_TM_ANA_BYP_8, UPHY_BIASGEN_ICONST_IO_MIRROR_ENABLE, 3, 1)
5831    FIELD(L2_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_ICONST_IO_MIRROR_ENABLE, 2, 1)
5832    FIELD(L2_TM_ANA_BYP_8, UPHY_BIASGEN_ICONST_CORE_MIRROR_ENABLE, 1, 1)
5833    FIELD(L2_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_ICONST_CORE_MIRROR_ENABLE, 0, 1)
5834REG32(L2_TM_ANA_BYP_9, 0x9020)
5835    FIELD(L2_TM_ANA_BYP_9, TM_ANA_BYP_9_31_8_RSVD, 24, 8)
5836    FIELD(L2_TM_ANA_BYP_9, UPHY_RECLPBK_CLK_DATAZ_ENABLE_CORE, 7, 1)
5837    FIELD(L2_TM_ANA_BYP_9, FORCE_UPHY_RECLPBK_CLK_DATAZ_ENABLE_CORE, 6, 1)
5838    FIELD(L2_TM_ANA_BYP_9, UPHY_PSO_SAMP_LPBK, 5, 1)
5839    FIELD(L2_TM_ANA_BYP_9, FORCE_UPHY_PSO_SAMP_LPBK, 4, 1)
5840    FIELD(L2_TM_ANA_BYP_9, UPHY_EQ_LPBK_ENABLE_CORE, 3, 1)
5841    FIELD(L2_TM_ANA_BYP_9, FORCE_UPHY_EQ_LPBK_ENABLE_CORE, 2, 1)
5842    FIELD(L2_TM_ANA_BYP_9, UPHY_EQ_AC_DCZ_COUPLED_CORE, 1, 1)
5843    FIELD(L2_TM_ANA_BYP_9, FORCE_UPHY_EQ_AC_DCZ_COUPLED_CORE, 0, 1)
5844REG32(L2_TM_ANA_BYP_10, 0x9024)
5845    FIELD(L2_TM_ANA_BYP_10, TM_ANA_BYP_10_31_8_RSVD, 24, 8)
5846    FIELD(L2_TM_ANA_BYP_10, UPHY_LPBK_CLK_DATA_SEL, 5, 1)
5847    FIELD(L2_TM_ANA_BYP_10, UPHY_LPBK_CENTRE_EDGEZ_ENABLE_CORE, 4, 1)
5848    FIELD(L2_TM_ANA_BYP_10, UPHY_HSRX_LPBK_SEL, 1, 3)
5849    FIELD(L2_TM_ANA_BYP_10, FORCE_UPHY_HSRX_LPBK_SEL, 0, 1)
5850REG32(L2_TM_ANA_BYP_11, 0x9028)
5851    FIELD(L2_TM_ANA_BYP_11, TM_ANA_BYP_11_31_8_RSVD, 24, 8)
5852    FIELD(L2_TM_ANA_BYP_11, UPHY_PD_PI_DIV_PATH, 5, 1)
5853    FIELD(L2_TM_ANA_BYP_11, UPHY_PSO_CLK_LANE, 4, 1)
5854    FIELD(L2_TM_ANA_BYP_11, FORCE_UPHY_PSO_CLK_LANE, 3, 1)
5855    FIELD(L2_TM_ANA_BYP_11, UPHY_HSCLK_DIVISION_FACTOR, 1, 2)
5856    FIELD(L2_TM_ANA_BYP_11, FORCE_UPHY_HSCLK_DIVISION_FACTOR, 0, 1)
5857REG32(L2_TM_ANA_BYP_12, 0x902c)
5858    FIELD(L2_TM_ANA_BYP_12, TM_ANA_BYP_12_31_8_RSVD, 24, 8)
5859    FIELD(L2_TM_ANA_BYP_12, UPHY_PSO_HSRXDIG, 7, 1)
5860    FIELD(L2_TM_ANA_BYP_12, FORCE_UPHY_PSO_HSRXDIG, 6, 1)
5861    FIELD(L2_TM_ANA_BYP_12, UPHY_PDN_HS_DES, 5, 1)
5862    FIELD(L2_TM_ANA_BYP_12, FORCE_UPHY_PDN_HS_DES, 4, 1)
5863    FIELD(L2_TM_ANA_BYP_12, UPHY_RST_GF_MUX, 3, 1)
5864    FIELD(L2_TM_ANA_BYP_12, FORCE_UPHY_RST_GF_MUX, 2, 1)
5865    FIELD(L2_TM_ANA_BYP_12, UPHY_ENABLE_CDR, 1, 1)
5866    FIELD(L2_TM_ANA_BYP_12, FORCE_UPHY_ENABLE_CDR, 0, 1)
5867REG32(L2_TM_ANA_BYP_13, 0x9030)
5868    FIELD(L2_TM_ANA_BYP_13, TM_ANA_BYP_13_31_8_RSVD, 24, 8)
5869    FIELD(L2_TM_ANA_BYP_13, UPHY_PSO_SAMP_FLOPS, 1, 1)
5870    FIELD(L2_TM_ANA_BYP_13, FORCE_UPHY_PSO_SAMP_FLOPS, 0, 1)
5871REG32(L2_TM_ANA_BYP_14, 0x9034)
5872    FIELD(L2_TM_ANA_BYP_14, TM_ANA_BYP_14_31_8_RSVD, 24, 8)
5873    FIELD(L2_TM_ANA_BYP_14, UPHY_PSO_EPI, 7, 1)
5874    FIELD(L2_TM_ANA_BYP_14, FORCE_UPHY_PSO_EPI, 6, 1)
5875    FIELD(L2_TM_ANA_BYP_14, UPHY_PD_SAMP_C2C_ECLK, 5, 1)
5876    FIELD(L2_TM_ANA_BYP_14, FORCE_UPHY_PD_SAMP_C2C_ECLK, 4, 1)
5877    FIELD(L2_TM_ANA_BYP_14, UPHY_PSO_IQPI, 1, 1)
5878    FIELD(L2_TM_ANA_BYP_14, FORCE_UPHY_PSO_IQPI, 0, 1)
5879REG32(L2_TM_ANA_BYP_15, 0x9038)
5880    FIELD(L2_TM_ANA_BYP_15, TM_ANA_BYP_15_31_8_RSVD, 24, 8)
5881    FIELD(L2_TM_ANA_BYP_15, UPHY_ENABLE_LOW_LEAKAGE, 7, 1)
5882    FIELD(L2_TM_ANA_BYP_15, FORCE_UPHY_ENABLE_LOW_LEAKAGE, 6, 1)
5883    FIELD(L2_TM_ANA_BYP_15, UPHY_PD_SAMP_C2C, 5, 1)
5884    FIELD(L2_TM_ANA_BYP_15, FORCE_UPHY_PD_SAMP_C2C, 4, 1)
5885    FIELD(L2_TM_ANA_BYP_15, UPHY_PSO_CORE_EQ, 3, 1)
5886    FIELD(L2_TM_ANA_BYP_15, FORCE_UPHY_PSO_CORE_EQ, 2, 1)
5887    FIELD(L2_TM_ANA_BYP_15, UPHY_PSO_IO_EQ, 1, 1)
5888    FIELD(L2_TM_ANA_BYP_15, FORCE_UPHY_PSO_IO_EQ, 0, 1)
5889REG32(L2_TM_ANA_BYP_16, 0x903c)
5890    FIELD(L2_TM_ANA_BYP_16, TM_ANA_BYP_16_31_8_RSVD, 24, 8)
5891    FIELD(L2_TM_ANA_BYP_16, UPHY_PSO_SIGDET, 7, 1)
5892    FIELD(L2_TM_ANA_BYP_16, FORCE_UPHY_PSO_SIGDET, 6, 1)
5893    FIELD(L2_TM_ANA_BYP_16, UPHY_RX_LANE_POLARITY_SWAP, 5, 1)
5894    FIELD(L2_TM_ANA_BYP_16, FORCE_UPHY_RX_LANE_POLARITY_SWAP, 4, 1)
5895    FIELD(L2_TM_ANA_BYP_16, UPHY_RUN_CALIB, 3, 1)
5896    FIELD(L2_TM_ANA_BYP_16, FORCE_UPHY_RUN_CALIB, 2, 1)
5897    FIELD(L2_TM_ANA_BYP_16, UPHY_RESTORE_CALCODE, 1, 1)
5898    FIELD(L2_TM_ANA_BYP_16, FORCE_UPHY_RESTORE_CALCODE, 0, 1)
5899REG32(L2_TM_ANA_BYP_17, 0x9040)
5900    FIELD(L2_TM_ANA_BYP_17, TM_ANA_BYP_17_31_8_RSVD, 24, 8)
5901    FIELD(L2_TM_ANA_BYP_17, UPHY_STARTLOOP_PLL, 6, 1)
5902    FIELD(L2_TM_ANA_BYP_17, FORCE_UPHY_STARTLOOP_PLL, 5, 1)
5903    FIELD(L2_TM_ANA_BYP_17, UPHY_RX_RESCALIB_CODE, 1, 4)
5904    FIELD(L2_TM_ANA_BYP_17, FORCE_UPHY_RX_RESCALIB_CODE, 0, 1)
5905REG32(L2_TM_ANA_BYP_18, 0x9044)
5906    FIELD(L2_TM_ANA_BYP_18, TM_ANA_BYP_18_31_8_RSVD, 24, 8)
5907    FIELD(L2_TM_ANA_BYP_18, FORCE_UPHY_RESTORE_CALCODE_DATA, 3, 1)
5908    FIELD(L2_TM_ANA_BYP_18, FORCE_UPHY_RX_PMA_OPMODE, 2, 1)
5909    FIELD(L2_TM_ANA_BYP_18, UPHY_PSO_LFPSBCN, 1, 1)
5910    FIELD(L2_TM_ANA_BYP_18, FORCE_UPHY_PSO_LFPSBCN, 0, 1)
5911REG32(L2_TM_ANA_BYP_20, 0x9048)
5912    FIELD(L2_TM_ANA_BYP_20, TM_ANA_BYP_20_31_8_RSVD, 24, 8)
5913    FIELD(L2_TM_ANA_BYP_20, UPHY_RX_PMA_OPMODE, 0, 8)
5914REG32(L2_TM_ANA_BYP_21, 0x904c)
5915    FIELD(L2_TM_ANA_BYP_21, TM_ANA_BYP_21_31_8_RSVD, 24, 8)
5916    FIELD(L2_TM_ANA_BYP_21, UPHY_RESTORE_CALCODE_DATA, 0, 8)
5917REG32(L2_TM_ANA_BYP_22, 0x9050)
5918    FIELD(L2_TM_ANA_BYP_22, TM_ANA_BYP_22_31_8_RSVD, 24, 8)
5919    FIELD(L2_TM_ANA_BYP_22, ISO_HSRX_CTRL_BAR, 7, 1)
5920    FIELD(L2_TM_ANA_BYP_22, FORCE_ISO_HSRX_CTRL_BAR, 6, 1)
5921    FIELD(L2_TM_ANA_BYP_22, HSRX_CLOCK_STOP_REQ, 5, 1)
5922    FIELD(L2_TM_ANA_BYP_22, FORCE_HSRX_CLOCK_STOP_REQ, 4, 1)
5923    FIELD(L2_TM_ANA_BYP_22, UPHY_SBRX_RUN_CALIB, 3, 1)
5924    FIELD(L2_TM_ANA_BYP_22, FORCE_UPHY_SBRX_RUN_CALIB, 2, 1)
5925    FIELD(L2_TM_ANA_BYP_22, RXPMA_RSTB, 1, 1)
5926    FIELD(L2_TM_ANA_BYP_22, FORCE_RXPMA_RSTB, 0, 1)
5927REG32(L2_TM_ANA_BYP_23, 0x9054)
5928    FIELD(L2_TM_ANA_BYP_23, TM_ANA_BYP_23_31_8_RSVD, 24, 8)
5929    FIELD(L2_TM_ANA_BYP_23, ISO_SIGDET_CTRL_BAR, 7, 1)
5930    FIELD(L2_TM_ANA_BYP_23, FORCE_ISO_SIGDET_CTRL_BAR, 6, 1)
5931    FIELD(L2_TM_ANA_BYP_23, ISO_LFPS_CTRL_BAR, 5, 1)
5932    FIELD(L2_TM_ANA_BYP_23, FORCE_ISO_LFPS_CTRL_BAR, 4, 1)
5933    FIELD(L2_TM_ANA_BYP_23, ISO_MPHY_LSRX_CTRL_BAR, 3, 1)
5934    FIELD(L2_TM_ANA_BYP_23, FORCE_ISO_MPHY_LSRX_CTRL_BAR, 2, 1)
5935    FIELD(L2_TM_ANA_BYP_23, ISO_MPHY_SQUELCH_CTRL_BAR, 1, 1)
5936    FIELD(L2_TM_ANA_BYP_23, FORCE_ISO_MPHY_SQUELCH_CTRL_BAR, 0, 1)
5937REG32(L2_TM_DIG_1, 0x9058)
5938    FIELD(L2_TM_DIG_1, TM_DIG_1_31_8_RSVD, 24, 8)
5939    FIELD(L2_TM_DIG_1, EN_TXRX_DIFGEAR, 7, 1)
5940    FIELD(L2_TM_DIG_1, MPHY_HS_TERM_PT_SEL, 6, 1)
5941    FIELD(L2_TM_DIG_1, TX_ALLOW_INLNCFG_FROM_TOP, 5, 1)
5942    FIELD(L2_TM_DIG_1, BYPASS_MARKER_DETECTOR, 4, 1)
5943    FIELD(L2_TM_DIG_1, BYPASS_EXIT_VAL, 0, 4)
5944REG32(L2_TM_DIG_2, 0x905c)
5945    FIELD(L2_TM_DIG_2, TM_DIG_2_31_8_RSVD, 24, 8)
5946    FIELD(L2_TM_DIG_2, MPHY_SYM_STATE, 1, 5)
5947    FIELD(L2_TM_DIG_2, FORCE_MPHY_SYM_STATE, 0, 1)
5948REG32(L2_TM_DIG_3, 0x9060)
5949    FIELD(L2_TM_DIG_3, TM_DIG_3_31_8_RSVD, 24, 8)
5950    FIELD(L2_TM_DIG_3, MPHY_SQUELCH_DETECT, 7, 1)
5951    FIELD(L2_TM_DIG_3, FORCE_MPHY_SQUELCH_DETECT, 6, 1)
5952    FIELD(L2_TM_DIG_3, MPHY_CFG_STATE, 1, 5)
5953    FIELD(L2_TM_DIG_3, FORCE_MPHY_CFG_STATE, 0, 1)
5954REG32(L2_TM_DIG_4, 0x9064)
5955    FIELD(L2_TM_DIG_4, TM_DIG_4_31_8_RSVD, 24, 8)
5956    FIELD(L2_TM_DIG_4, STATUS_REG_VAL, 4, 4)
5957    FIELD(L2_TM_DIG_4, READ_SHADOW, 3, 1)
5958REG32(L2_TM_DIG_5, 0x9068)
5959    FIELD(L2_TM_DIG_5, TM_DIG_5_31_8_RSVD, 24, 8)
5960    FIELD(L2_TM_DIG_5, SYMBOL_CLK_ALWAYS_ON_N, 2, 1)
5961    FIELD(L2_TM_DIG_5, BYPASS_DIFN_DETECT, 1, 1)
5962    FIELD(L2_TM_DIG_5, HIBERN8_CTRL, 0, 1)
5963REG32(L2_TM_DIG_6, 0x906c)
5964    FIELD(L2_TM_DIG_6, TM_DIG_6_31_8_RSVD, 24, 8)
5965    FIELD(L2_TM_DIG_6, FORCE_BYPASS_ON_ERR, 6, 1)
5966    FIELD(L2_TM_DIG_6, SUPPRESS_ERR, 5, 1)
5967    FIELD(L2_TM_DIG_6, BYPASS_OHC, 4, 1)
5968    FIELD(L2_TM_DIG_6, BYPASS_DECODER, 3, 1)
5969    FIELD(L2_TM_DIG_6, FORCE_BYPASS_DEC, 2, 1)
5970    FIELD(L2_TM_DIG_6, BYPASS_DESCRAM, 1, 1)
5971    FIELD(L2_TM_DIG_6, FORCE_BYPASS_DESCRAM, 0, 1)
5972REG32(L2_TM_DIG_7, 0x9070)
5973    FIELD(L2_TM_DIG_7, TM_DIG_7_31_8_RSVD, 24, 8)
5974    FIELD(L2_TM_DIG_7, BYPASS_ON_ERR_CHAR, 0, 8)
5975REG32(L2_TM_DIG_8, 0x9074)
5976    FIELD(L2_TM_DIG_8, TM_DIG_8_31_8_RSVD, 24, 8)
5977    FIELD(L2_TM_DIG_8, EYESURF_ENABLE, 4, 1)
5978    FIELD(L2_TM_DIG_8, USE_EB_IN_MPHY, 3, 1)
5979    FIELD(L2_TM_DIG_8, BYPASS_EB, 2, 1)
5980    FIELD(L2_TM_DIG_8, EB_MODE, 1, 1)
5981    FIELD(L2_TM_DIG_8, FORCE_EB_MODE, 0, 1)
5982REG32(L2_TM_DIG_9, 0x9078)
5983    FIELD(L2_TM_DIG_9, TM_DIG_9_31_8_RSVD, 24, 8)
5984    FIELD(L2_TM_DIG_9, FLIP_ENDIAN, 3, 1)
5985    FIELD(L2_TM_DIG_9, DEC_ERR_CNT_THRESHOLD, 0, 3)
5986REG32(L2_TM_DIG_10, 0x907c)
5987    FIELD(L2_TM_DIG_10, TM_DIG_10_31_8_RSVD, 24, 8)
5988    FIELD(L2_TM_DIG_10, CDR_BIT_LOCK_TIME, 0, 4)
5989REG32(L2_TM_DIG_11, 0x9080)
5990    FIELD(L2_TM_DIG_11, TM_DIG_11_31_8_RSVD, 24, 8)
5991    FIELD(L2_TM_DIG_11, BYPASS_CDR_ERR_MASK, 7, 1)
5992    FIELD(L2_TM_DIG_11, SYMB_ERR_SEL, 5, 2)
5993    FIELD(L2_TM_DIG_11, SYMB_ERR, 4, 1)
5994REG32(L2_TM_DIG_12, 0x9084)
5995    FIELD(L2_TM_DIG_12, TM_DIG_12_31_8_RSVD, 24, 8)
5996    FIELD(L2_TM_DIG_12, FLIP_ENDIAN_EB_DATA_OUT, 5, 1)
5997    FIELD(L2_TM_DIG_12, FLIP_ENDIAN_EB_DATA_IN, 4, 1)
5998    FIELD(L2_TM_DIG_12, OVERFLOW_BYP, 3, 1)
5999    FIELD(L2_TM_DIG_12, UNDERFLOW_BYP, 2, 1)
6000    FIELD(L2_TM_DIG_12, OVERFLOW_BYP_VAL, 1, 1)

6001    FIELD(L2_TM_DIG_12, UNDERFLOW_BYP_VAL, 0, 1)
6002REG32(L2_TM_DIG_13, 0x9088)
6003    FIELD(L2_TM_DIG_13, TM_DIG_13_31_8_RSVD, 24, 8)
6004    FIELD(L2_TM_DIG_13, OMC_PRESENTN, 6, 1)
6005    FIELD(L2_TM_DIG_13, CFG_CLK_FREQ, 0, 6)
6006REG32(L2_TM_DIG_14, 0x908c)
6007    FIELD(L2_TM_DIG_14, TM_DIG_14_31_8_RSVD, 24, 8)
6008    FIELD(L2_TM_DIG_14, LFPS_OUTPUT_SEL, 6, 2)
6009    FIELD(L2_TM_DIG_14, LFPS_STRETCH, 4, 2)
6010REG32(L2_TM_DIG_15, 0x9090)
6011    FIELD(L2_TM_DIG_15, TM_DIG_15_31_8_RSVD, 24, 8)
6012    FIELD(L2_TM_DIG_15, FORCE_LFPS_FILTER_THRESH, 5, 1)
6013    FIELD(L2_TM_DIG_15, LFPS_FILTER_THRESH, 0, 5)
6014REG32(L2_TM_DIG_16, 0x9094)
6015    FIELD(L2_TM_DIG_16, TM_DIG_16_31_8_RSVD, 24, 8)
6016    FIELD(L2_TM_DIG_16, TESTDIGOUT_SEL, 1, 4)
6017    FIELD(L2_TM_DIG_16, FORCE_TESTDIGOUT_SEL, 0, 1)
6018REG32(L2_TM_DIG_17, 0x9098)
6019    FIELD(L2_TM_DIG_17, TM_DIG_17_31_8_RSVD, 24, 8)
6020    FIELD(L2_TM_DIG_17, FORCE_SATA_RX_VALID_CNT, 4, 1)
6021    FIELD(L2_TM_DIG_17, SATA_RX_VALID_CNT, 0, 4)
6022REG32(L2_TM_DIG_18, 0x909c)
6023    FIELD(L2_TM_DIG_18, TM_DIG_18_31_8_RSVD, 24, 8)
6024    FIELD(L2_TM_DIG_18, CLK_DIST_SETTLE_TIME, 4, 4)
6025    FIELD(L2_TM_DIG_18, BIASGEN_SETTLE_TIME, 0, 4)
6026REG32(L2_TM_DIG_19, 0x90a0)
6027    FIELD(L2_TM_DIG_19, TM_DIG_19_31_8_RSVD, 24, 8)
6028    FIELD(L2_TM_DIG_19, HSRX_ANA_SETTLE_TIME, 4, 4)
6029    FIELD(L2_TM_DIG_19, SBRX_ANA_SETTLE_TIME, 0, 4)
6030REG32(L2_TM_DIG_20, 0x90a4)
6031    FIELD(L2_TM_DIG_20, TM_DIG_20_31_8_RSVD, 24, 8)
6032    FIELD(L2_TM_DIG_20, HSRX_COOLING_TIME, 3, 4)
6033    FIELD(L2_TM_DIG_20, FORCE_RX_CAL, 2, 1)
6034    FIELD(L2_TM_DIG_20, BYPASS_HSRX_CAL, 1, 1)
6035    FIELD(L2_TM_DIG_20, BYPASS_SBRX_CAL, 0, 1)
6036REG32(L2_TM_DIG_21, 0x90a8)
6037    FIELD(L2_TM_DIG_21, TM_DIG_21_31_8_RSVD, 24, 8)
6038    FIELD(L2_TM_DIG_21, COMMA_LOCATION_RST, 4, 1)
6039    FIELD(L2_TM_DIG_21, SSC_WAIT_CNT, 2, 2)
6040    FIELD(L2_TM_DIG_21, COMMA_PRE_LOCK_THRESH, 0, 2)
6041REG32(L2_TM_DIG_22, 0x90ac)
6042    FIELD(L2_TM_DIG_22, TM_DIG_22_31_8_RSVD, 24, 8)
6043    FIELD(L2_TM_DIG_22, DIS_DEFAULT_CDR_GATE_LOGIC, 5, 1)
6044    FIELD(L2_TM_DIG_22, INV_POL_SIGDET_HIGH, 4, 1)
6045    FIELD(L2_TM_DIG_22, INV_POL_SIGDET_LOW, 3, 1)
6046    FIELD(L2_TM_DIG_22, SIGDET_LFPS_BAR_EN, 2, 1)
6047    FIELD(L2_TM_DIG_22, OBSRV_SIGDET_OUTPUT, 1, 1)
6048    FIELD(L2_TM_DIG_22, RX_SIGDET_EN, 0, 1)
6049REG32(L2_TM_DIG_23, 0x90b0)
6050    FIELD(L2_TM_DIG_23, TM_DIG_23_31_8_RSVD, 24, 8)
6051    FIELD(L2_TM_DIG_23, DELAY_TIMER_LOAD_VAL_HIGH_1, 6, 2)
6052    FIELD(L2_TM_DIG_23, FORCE_RX_SIGDET_SEL, 5, 1)
6053    FIELD(L2_TM_DIG_23, RX_SIGDET_SEL_VAL, 4, 1)
6054    FIELD(L2_TM_DIG_23, FORCE_RX_SIG_DET_FILT_FUNC_SEL, 3, 1)
6055    FIELD(L2_TM_DIG_23, RX_SIG_DET_FILT_FUNC_SEL, 0, 3)
6056REG32(L2_TM_DIG_24, 0x90b4)
6057    FIELD(L2_TM_DIG_24, TM_DIG_24_31_8_RSVD, 24, 8)
6058    FIELD(L2_TM_DIG_24, FILTER_TIMER_LOAD_VAL_HIGH_1, 6, 2)
6059    FIELD(L2_TM_DIG_24, MIN_TIMER_LOAD_VAL_HIGH_1, 4, 2)
6060    FIELD(L2_TM_DIG_24, FILTER_TIMER_LOAD_VAL_LOW_1, 2, 2)
6061    FIELD(L2_TM_DIG_24, MIN_TIMER_LOAD_VAL_LOW_1, 0, 2)
6062REG32(L2_TM_DIG_25, 0x90b8)
6063    FIELD(L2_TM_DIG_25, TM_DIG_25_31_8_RSVD, 24, 8)
6064    FIELD(L2_TM_DIG_25, FILTER_TIMER_LOAD_VAL_HIGH_0, 0, 8)
6065REG32(L2_TM_DIG_26, 0x90bc)
6066    FIELD(L2_TM_DIG_26, TM_DIG_26_31_8_RSVD, 24, 8)
6067    FIELD(L2_TM_DIG_26, DELAY_TIMER_LOAD_VAL_HIGH_0, 0, 8)
6068REG32(L2_TM_DIG_27, 0x90c0)
6069    FIELD(L2_TM_DIG_27, TM_DIG_27_31_8_RSVD, 24, 8)
6070    FIELD(L2_TM_DIG_27, MIN_TIMER_LOAD_VAL_HIGH_0, 0, 8)
6071REG32(L2_TM_DIG_28, 0x90c4)
6072    FIELD(L2_TM_DIG_28, TM_DIG_28_31_8_RSVD, 24, 8)
6073    FIELD(L2_TM_DIG_28, FILTER_TIMER_LOAD_VAL_LOW_0, 0, 8)
6074REG32(L2_TM_DIG_29, 0x90c8)
6075    FIELD(L2_TM_DIG_29, TM_DIG_29_31_8_RSVD, 24, 8)
6076    FIELD(L2_TM_DIG_29, MIN_TIMER_LOAD_VAL_LOW_0, 0, 8)
6077REG32(L2_TM_AUX_0, 0x90cc)
6078    FIELD(L2_TM_AUX_0, TM_AUX_0_31_8_RSVD, 24, 8)
6079    FIELD(L2_TM_AUX_0, BIT_0, 7, 1)
6080    FIELD(L2_TM_AUX_0, BIT_1, 6, 1)
6081    FIELD(L2_TM_AUX_0, BIT_2, 5, 1)
6082    FIELD(L2_TM_AUX_0, BIT_3, 4, 1)
6083    FIELD(L2_TM_AUX_0, BIT_4, 3, 1)
6084    FIELD(L2_TM_AUX_0, BIT_5, 2, 1)
6085    FIELD(L2_TM_AUX_0, BIT_6, 1, 1)
6086    FIELD(L2_TM_AUX_0, BIT_7, 0, 1)
6087REG32(L2_TM_AUX_1, 0x90d0)
6088    FIELD(L2_TM_AUX_1, TM_AUX_1_31_8_RSVD, 24, 8)
6089    FIELD(L2_TM_AUX_1, BIT_0, 7, 1)
6090    FIELD(L2_TM_AUX_1, BIT_1, 6, 1)
6091    FIELD(L2_TM_AUX_1, BIT_2, 5, 1)
6092    FIELD(L2_TM_AUX_1, BIT_3, 4, 1)
6093    FIELD(L2_TM_AUX_1, BIT_4, 3, 1)
6094    FIELD(L2_TM_AUX_1, BIT_5, 2, 1)
6095    FIELD(L2_TM_AUX_1, BIT_6, 1, 1)
6096    FIELD(L2_TM_AUX_1, BIT_7, 0, 1)
6097REG32(L2_TM_AUX_2, 0x90d4)
6098    FIELD(L2_TM_AUX_2, TM_AUX_2_31_8_RSVD, 24, 8)
6099    FIELD(L2_TM_AUX_2, BIT_0, 7, 1)
6100    FIELD(L2_TM_AUX_2, BIT_1, 6, 1)
6101    FIELD(L2_TM_AUX_2, BIT_2, 5, 1)
6102    FIELD(L2_TM_AUX_2, BIT_3, 4, 1)
6103    FIELD(L2_TM_AUX_2, BIT_4, 3, 1)
6104    FIELD(L2_TM_AUX_2, BIT_5, 2, 1)
6105    FIELD(L2_TM_AUX_2, BIT_6, 1, 1)
6106    FIELD(L2_TM_AUX_2, BIT_7, 0, 1)
6107REG32(L2_TM_AUX_3, 0x90d8)
6108    FIELD(L2_TM_AUX_3, TM_AUX_3_31_8_RSVD, 24, 8)
6109    FIELD(L2_TM_AUX_3, BIT_0, 7, 1)
6110    FIELD(L2_TM_AUX_3, BIT_1, 6, 1)
6111    FIELD(L2_TM_AUX_3, BIT_2, 5, 1)
6112    FIELD(L2_TM_AUX_3, BIT_3, 4, 1)
6113    FIELD(L2_TM_AUX_3, BIT_4, 3, 1)
6114    FIELD(L2_TM_AUX_3, BIT_5, 2, 1)
6115    FIELD(L2_TM_AUX_3, BIT_6, 1, 1)
6116    FIELD(L2_TM_AUX_3, BIT_7, 0, 1)
6117REG32(L2_TM_AUX_4, 0x90dc)
6118    FIELD(L2_TM_AUX_4, TM_AUX_4_31_8_RSVD, 24, 8)
6119    FIELD(L2_TM_AUX_4, BIT_0, 7, 1)
6120    FIELD(L2_TM_AUX_4, BIT_1, 6, 1)
6121    FIELD(L2_TM_AUX_4, BIT_2, 5, 1)
6122    FIELD(L2_TM_AUX_4, BIT_3, 4, 1)
6123    FIELD(L2_TM_AUX_4, BIT_4, 3, 1)
6124    FIELD(L2_TM_AUX_4, BIT_5, 2, 1)
6125    FIELD(L2_TM_AUX_4, BIT_6, 1, 1)
6126    FIELD(L2_TM_AUX_4, BIT_7, 0, 1)
6127REG32(L2_TM_DIG_30, 0x90e0)
6128    FIELD(L2_TM_DIG_30, TM_DIG_30_31_8_RSVD, 24, 8)
6129    FIELD(L2_TM_DIG_30, SD_LD_BAR_FILTER_TIME_VAL_1, 4, 2)
6130    FIELD(L2_TM_DIG_30, SD_LD_BAR_DLY_TIME_VAL_1, 2, 2)
6131    FIELD(L2_TM_DIG_30, SD_LD_BAR_MIN_TIMER_VAL_1, 0, 2)
6132REG32(L2_TM_DIG_31, 0x90e4)
6133    FIELD(L2_TM_DIG_31, TM_DIG_31_31_8_RSVD, 24, 8)
6134    FIELD(L2_TM_DIG_31, SD_LD_BAR_FILTER_TIME_VAL_0, 0, 8)
6135REG32(L2_TM_DIG_32, 0x90e8)
6136    FIELD(L2_TM_DIG_32, TM_DIG_32_31_8_RSVD, 24, 8)
6137    FIELD(L2_TM_DIG_32, SD_LD_BAR_DLY_TIME_VAL_0, 0, 8)
6138REG32(L2_TM_DIG_33, 0x90ec)
6139    FIELD(L2_TM_DIG_33, TM_DIG_33_31_8_RSVD, 24, 8)
6140    FIELD(L2_TM_DIG_33, SD_LD_BAR_MIN_TIMER_VAL_0, 0, 8)
6141REG32(L2_TM_DIG_34, 0x90f0)
6142    FIELD(L2_TM_DIG_34, TM_DIG_34_31_8_RSVD, 24, 8)
6143    FIELD(L2_TM_DIG_34, SATA_JUNK_DATA_TIMEOUT_VAL, 0, 6)
6144REG32(L2_TM_DIG_35, 0x90f4)
6145    FIELD(L2_TM_DIG_35, TM_DIG_35_31_8_RSVD, 24, 8)
6146    FIELD(L2_TM_DIG_35, SATA_CDR_LOCK_WAIT_TIMEOUT_VAL, 0, 6)
6147REG32(L2_TM_DIG_36, 0x90f8)
6148    FIELD(L2_TM_DIG_36, TM_DIG_36_31_8_RSVD, 24, 8)
6149    FIELD(L2_TM_DIG_36, COM_DET_THRESH_VAL_0, 0, 8)
6150REG32(L2_TM_DIG_37, 0x90fc)
6151    FIELD(L2_TM_DIG_37, TM_DIG_37_31_8_RSVD, 24, 8)
6152    FIELD(L2_TM_DIG_37, FORCE_COM_DETECT_THRESH, 4, 1)
6153    FIELD(L2_TM_DIG_37, COM_DET_THRESH_VAL_1, 0, 4)
6154REG32(L2_TM_LFPS_1, 0x9800)
6155    FIELD(L2_TM_LFPS_1, TM_LFPS_1_31_8_RSVD, 24, 8)
6156    FIELD(L2_TM_LFPS_1, PROG_REFP, 4, 4)
6157    FIELD(L2_TM_LFPS_1, PROG_REFM, 0, 4)
6158REG32(L2_TM_LFPS_2, 0x9804)
6159    FIELD(L2_TM_LFPS_2, TM_LFPS_2_31_8_RSVD, 24, 8)
6160    FIELD(L2_TM_LFPS_2, PROG_VCM, 4, 3)
6161    FIELD(L2_TM_LFPS_2, PROG_FILTER_CAP, 0, 4)
6162REG32(L2_TM_LFPS_3, 0x9808)
6163    FIELD(L2_TM_LFPS_3, TM_LFPS_3_31_8_RSVD, 24, 8)
6164    FIELD(L2_TM_LFPS_3, PROG_C2, 5, 3)
6165    FIELD(L2_TM_LFPS_3, PROG_C1, 2, 3)
6166    FIELD(L2_TM_LFPS_3, PROG_PADINTF, 0, 2)
6167REG32(L2_TM_LFPS_4, 0x980c)
6168    FIELD(L2_TM_LFPS_4, TM_LFPS_4_31_8_RSVD, 24, 8)
6169    FIELD(L2_TM_LFPS_4, TESTBIT, 0, 6)
6170REG32(L2_TM_RXPMA_1, 0x9810)
6171    FIELD(L2_TM_RXPMA_1, TM_RXPMA_1_31_8_RSVD, 24, 8)
6172    FIELD(L2_TM_RXPMA_1, UPHY_TESTBIT, 0, 8)
6173REG32(L2_TM_BSCAN_1, 0x9814)
6174    FIELD(L2_TM_BSCAN_1, TM_BSCAN_1_31_8_RSVD, 24, 8)
6175    FIELD(L2_TM_BSCAN_1, BSCAN_LPF_RES, 0, 3)
6176REG32(L2_TM_MPHY_SQ_1, 0x9818)
6177    FIELD(L2_TM_MPHY_SQ_1, TM_MPHY_SQ_1_31_8_RSVD, 24, 8)
6178    FIELD(L2_TM_MPHY_SQ_1, TB_REDUCE_OFFSET, 4, 1)
6179    FIELD(L2_TM_MPHY_SQ_1, TB_INCREASE_OFFSET, 3, 1)
6180    FIELD(L2_TM_MPHY_SQ_1, TB_DRIVE_RES_SEL, 1, 2)
6181    FIELD(L2_TM_MPHY_SQ_1, TB_BYPASS_HYST, 0, 1)
6182REG32(L2_TM_LSRX_1, 0x981c)
6183    FIELD(L2_TM_LSRX_1, TM_LSRX_1_31_8_RSVD, 24, 8)
6184    FIELD(L2_TM_LSRX_1, LSRX_TESTBITS_0, 0, 8)
6185REG32(L2_TM_LSRX_2, 0x9820)
6186    FIELD(L2_TM_LSRX_2, TM_LSRX_2_31_8_RSVD, 24, 8)
6187    FIELD(L2_TM_LSRX_2, LSRX_TESTBITS_1, 0, 6)
6188REG32(L2_TM_SIGDET_1, 0x9824)
6189    FIELD(L2_TM_SIGDET_1, TM_SIGDET_1_31_8_RSVD, 24, 8)
6190    FIELD(L2_TM_SIGDET_1, BIASTRIM, 4, 3)
6191    FIELD(L2_TM_SIGDET_1, RELIABPROT, 2, 2)
6192    FIELD(L2_TM_SIGDET_1, STRESSPORT, 0, 2)
6193REG32(L2_TM_SIGDET_2, 0x9828)
6194    FIELD(L2_TM_SIGDET_2, TM_SIGDET_2_31_8_RSVD, 24, 8)
6195    FIELD(L2_TM_SIGDET_2, VSENSETRIM, 0, 8)
6196REG32(L2_TM_DFT_1, 0x982c)
6197    FIELD(L2_TM_DFT_1, TM_DFT_1_31_8_RSVD, 24, 8)
6198    FIELD(L2_TM_DFT_1, LFPS_DFT_SEL_P, 4, 4)
6199    FIELD(L2_TM_DFT_1, LFPS_DFT_ENABLE, 3, 1)
6200REG32(L2_TM_DFT_2, 0x9830)
6201    FIELD(L2_TM_DFT_2, TM_DFT_2_31_8_RSVD, 24, 8)
6202    FIELD(L2_TM_DFT_2, SIGDET_DFT_SEL_P, 0, 3)
6203REG32(L2_TM_DFT_3, 0x9834)
6204    FIELD(L2_TM_DFT_3, TM_DFT_3_31_8_RSVD, 24, 8)
6205    FIELD(L2_TM_DFT_3, BSCAN_DFT_ENABLE, 4, 1)
6206    FIELD(L2_TM_DFT_3, BSCAN_DFT_SEL_P, 0, 4)
6207REG32(L2_TM_DFT_4, 0x9838)
6208    FIELD(L2_TM_DFT_4, TM_DFT_4_31_8_RSVD, 24, 8)
6209    FIELD(L2_TM_DFT_4, IQPI_DFT_ENABLE, 1, 1)
6210    FIELD(L2_TM_DFT_4, EPI_DFT_ENABLE, 0, 1)
6211REG32(L2_TM_DFT_5, 0x983c)
6212    FIELD(L2_TM_DFT_5, TM_DFT_5_31_8_RSVD, 24, 8)
6213    FIELD(L2_TM_DFT_5, IQPI_DFT_SEL, 0, 8)
6214REG32(L2_TM_DFT_6, 0x9840)
6215    FIELD(L2_TM_DFT_6, TM_DFT_6_31_8_RSVD, 24, 8)
6216    FIELD(L2_TM_DFT_6, EPI_DFT_SEL, 0, 8)
6217REG32(L2_TM_DFT_7, 0x9844)
6218    FIELD(L2_TM_DFT_7, TM_DFT_7_31_8_RSVD, 24, 8)
6219    FIELD(L2_TM_DFT_7, EQ_DFT_ENABLE, 4, 1)
6220    FIELD(L2_TM_DFT_7, EQ_DFT_SEL_P, 0, 4)
6221REG32(L2_TM_DFT_8, 0x9848)
6222    FIELD(L2_TM_DFT_8, TM_DFT_8_31_8_RSVD, 24, 8)
6223    FIELD(L2_TM_DFT_8, LSRX_DFT_ENABLE, 4, 1)
6224    FIELD(L2_TM_DFT_8, LSRX_DFT_SEL_P, 0, 4)
6225REG32(L2_TM_DFT_9, 0x984c)
6226    FIELD(L2_TM_DFT_9, TM_DFT_9_31_8_RSVD, 24, 8)
6227    FIELD(L2_TM_DFT_9, SAMP_DFT_SEL_P_0, 0, 8)
6228REG32(L2_TM_DFT_10, 0x9850)
6229    FIELD(L2_TM_DFT_10, TM_DFT_10_31_8_RSVD, 24, 8)
6230    FIELD(L2_TM_DFT_10, CLKLANE_DFT_SEL, 2, 2)
6231    FIELD(L2_TM_DFT_10, SAMP_DFT_SEL_P_1, 0, 2)
6232REG32(L2_TM_BG_1, 0x9854)
6233    FIELD(L2_TM_BG_1, TM_BG_1_31_8_RSVD, 24, 8)
6234    FIELD(L2_TM_BG_1, BIASGEN_CURRENT_PROG_0, 0, 8)
6235REG32(L2_TM_BG_2, 0x9858)
6236    FIELD(L2_TM_BG_2, TM_BG_2_31_8_RSVD, 24, 8)
6237    FIELD(L2_TM_BG_2, BIASGEN_CURRENT_PROG_1, 0, 8)
6238REG32(L2_TM_BG_3, 0x985c)
6239    FIELD(L2_TM_BG_3, TM_BG_3_31_8_RSVD, 24, 8)
6240    FIELD(L2_TM_BG_3, BIASGEN_CURRENT_PROG_2, 0, 8)
6241REG32(L2_TM_BG_4, 0x9860)
6242    FIELD(L2_TM_BG_4, TM_BG_4_31_8_RSVD, 24, 8)
6243    FIELD(L2_TM_BG_4, BIASGEN_CURRENT_PROG_3, 0, 8)
6244REG32(L2_TM_BG_5, 0x9864)
6245    FIELD(L2_TM_BG_5, TM_BG_5_31_8_RSVD, 24, 8)
6246    FIELD(L2_TM_BG_5, BIASGEN_CURRENT_PROG_4, 0, 8)
6247REG32(L2_TM_BG_6, 0x9868)
6248    FIELD(L2_TM_BG_6, TM_BG_6_31_8_RSVD, 24, 8)
6249    FIELD(L2_TM_BG_6, BIASGEN_CURRENT_PROG_5, 0, 8)
6250REG32(L2_TM_BG_7, 0x986c)
6251    FIELD(L2_TM_BG_7, TM_BG_7_31_8_RSVD, 24, 8)
6252    FIELD(L2_TM_BG_7, BIASGEN_CURRENT_PROG_6, 0, 8)
6253REG32(L2_TM_BG_8, 0x9870)
6254    FIELD(L2_TM_BG_8, TM_BG_8_31_8_RSVD, 24, 8)
6255    FIELD(L2_TM_BG_8, BIASGEN_CURRENT_PROG_7, 0, 8)
6256REG32(L2_TM_BG_9, 0x9874)
6257    FIELD(L2_TM_BG_9, TM_BG_9_31_8_RSVD, 24, 8)
6258    FIELD(L2_TM_BG_9, BIASGEN_CURRENT_PROG_8, 0, 8)
6259REG32(L2_TM_BG_10, 0x9878)
6260    FIELD(L2_TM_BG_10, TM_BG_10_31_8_RSVD, 24, 8)
6261    FIELD(L2_TM_BG_10, BIASGEN_CURRENT_PROG_9, 0, 8)
6262REG32(L2_TM_SD0, 0x987c)
6263    FIELD(L2_TM_SD0, TM_SD0_31_8_RSVD, 24, 8)
6264    FIELD(L2_TM_SD0, SD_CAL_OVERRIDE_CODE, 2, 6)
6265    FIELD(L2_TM_SD0, SD_CAL_OVERRIDE_EN, 1, 1)
6266    FIELD(L2_TM_SD0, SD_CAL_DIR, 0, 1)
6267REG32(L2_TM_SD1, 0x9880)
6268    FIELD(L2_TM_SD1, TM_SD1_31_8_RSVD, 24, 8)
6269    FIELD(L2_TM_SD1, SD_BYPASS_ANA_CAL_EN_VAL, 7, 1)
6270    FIELD(L2_TM_SD1, SD_BYPASS_ANA_CAL_EN, 6, 1)
6271    FIELD(L2_TM_SD1, SD_CAL_CODE_START, 0, 6)
6272REG32(L2_TM_SD2, 0x9884)
6273    FIELD(L2_TM_SD2, TM_SD2_31_8_RSVD, 24, 8)
6274    FIELD(L2_TM_SD2, SD_CAL_FORCE_CAL, 7, 1)
6275    FIELD(L2_TM_SD2, SD_CAL_CODE_TUNE_BYP, 6, 1)
6276    FIELD(L2_TM_SD2, SD_CAL_CODE_TUNE, 0, 6)
6277REG32(L2_TM_SD3, 0x9888)
6278    FIELD(L2_TM_SD3, TM_SD3_31_8_RSVD, 24, 8)
6279    FIELD(L2_TM_SD3, SD_CAL_ITER_WAIT_0, 0, 8)
6280REG32(L2_TM_SD4, 0x988c)
6281    FIELD(L2_TM_SD4, TM_SD4_31_8_RSVD, 24, 8)
6282    FIELD(L2_TM_SD4, SD_CAL_ITER_WAIT_BYPASS, 4, 1)
6283    FIELD(L2_TM_SD4, SD_CAL_ITER_WAIT_1, 0, 4)
6284REG32(L2_TM_SD5, 0x9890)
6285    FIELD(L2_TM_SD5, TM_SD5_31_8_RSVD, 24, 8)
6286    FIELD(L2_TM_SD5, SD_CAL_INIT_WAIT_0, 0, 8)
6287REG32(L2_TM_SD6, 0x9894)
6288    FIELD(L2_TM_SD6, TM_SD6_31_8_RSVD, 24, 8)
6289    FIELD(L2_TM_SD6, SD_CAL_INIT_WAIT_BYPASS, 4, 1)
6290    FIELD(L2_TM_SD6, SD_CAL_INIT_WAIT_1, 0, 4)
6291REG32(L2_TM_MISC1, 0x9898)
6292    FIELD(L2_TM_MISC1, TM_MISC1_31_8_RSVD, 24, 8)
6293    FIELD(L2_TM_MISC1, HSRX_POLARITY_FLIP, 7, 1)
6294    FIELD(L2_TM_MISC1, RXTERM_BIAS_PROG, 3, 4)
6295    FIELD(L2_TM_MISC1, LSRX_OR_SYS_POLARITY_FLIP, 2, 1)
6296    FIELD(L2_TM_MISC1, FORCE_SATAG1_DCC_MODE, 1, 1)
6297    FIELD(L2_TM_MISC1, SATAG1_DCC_MODE_VAL, 0, 1)
6298REG32(L2_TM_MISC2, 0x989c)
6299    FIELD(L2_TM_MISC2, TM_MISC2_31_8_RSVD, 24, 8)
6300    FIELD(L2_TM_MISC2, ILL_CAL_BYPASS_COUNTS, 7, 1)
6301    FIELD(L2_TM_MISC2, PWR_SEQ_SAMP_CAL_ALWAYS, 6, 1)
6302    FIELD(L2_TM_MISC2, PWR_SEQ_BYP_CAL_DONE, 5, 1)
6303    FIELD(L2_TM_MISC2, PWR_SEQ_BYP_CAL_DONE_VAL, 4, 1)
6304    FIELD(L2_TM_MISC2, SAMP_BYPASS_CAL_TO_EQ, 3, 1)
6305    FIELD(L2_TM_MISC2, SAMP_BYPASS_CAL_TO_EQ_VAL, 2, 1)
6306    FIELD(L2_TM_MISC2, UNUSED, 0, 2)
6307REG32(L2_TM_EYE_SURF0, 0x98a0)
6308    FIELD(L2_TM_EYE_SURF0, TM_EYE_SURF0_31_8_RSVD, 24, 8)
6309    FIELD(L2_TM_EYE_SURF0, UNUSED, 7, 1)
6310    FIELD(L2_TM_EYE_SURF0, EYE_SURF_RUN, 6, 1)
6311    FIELD(L2_TM_EYE_SURF0, COORD_EW_DIR, 5, 1)
6312    FIELD(L2_TM_EYE_SURF0, COORD_EW_OFFSET, 0, 5)
6313REG32(L2_TM_EYE_SURF1, 0x98a4)
6314    FIELD(L2_TM_EYE_SURF1, TM_EYE_SURF1_31_8_RSVD, 24, 8)
6315    FIELD(L2_TM_EYE_SURF1, COORD_NS_DIR, 7, 1)
6316    FIELD(L2_TM_EYE_SURF1, COORD_NS_OFFSET, 0, 7)
6317REG32(L2_TM_EYE_SURF2, 0x98a8)
6318    FIELD(L2_TM_EYE_SURF2, TM_EYE_SURF2_31_8_RSVD, 24, 8)
6319    FIELD(L2_TM_EYE_SURF2, TIMER_DELAY_TIME0, 0, 8)
6320REG32(L2_TM_EYE_SURF3, 0x98ac)
6321    FIELD(L2_TM_EYE_SURF3, TM_EYE_SURF3_31_8_RSVD, 24, 8)
6322    FIELD(L2_TM_EYE_SURF3, TIMER_DELAY_TIME1, 0, 8)
6323REG32(L2_TM_EYE_SURF4, 0x98b0)
6324    FIELD(L2_TM_EYE_SURF4, TM_EYE_SURF4_31_8_RSVD, 24, 8)
6325    FIELD(L2_TM_EYE_SURF4, TIMER_DELAY_TIME2, 0, 8)
6326REG32(L2_TM_EYE_SURF5, 0x98b4)
6327    FIELD(L2_TM_EYE_SURF5, TM_EYE_SURF5_31_8_RSVD, 24, 8)
6328    FIELD(L2_TM_EYE_SURF5, TIMER_DELAY_TIME3, 0, 8)
6329REG32(L2_TM_EYE_SURF6, 0x98b8)
6330    FIELD(L2_TM_EYE_SURF6, TM_EYE_SURF6_31_8_RSVD, 24, 8)
6331    FIELD(L2_TM_EYE_SURF6, TIMER_TEST_TIME0, 0, 8)
6332REG32(L2_TM_EYE_SURF7, 0x98bc)
6333    FIELD(L2_TM_EYE_SURF7, TM_EYE_SURF7_31_8_RSVD, 24, 8)
6334    FIELD(L2_TM_EYE_SURF7, TIMER_TEST_TIME1, 0, 8)
6335REG32(L2_TM_EYE_SURF8, 0x98c0)
6336    FIELD(L2_TM_EYE_SURF8, TM_EYE_SURF8_31_8_RSVD, 24, 8)
6337    FIELD(L2_TM_EYE_SURF8, TIMER_TEST_TIME2, 0, 8)
6338REG32(L2_TM_EYE_SURF9, 0x98c4)
6339    FIELD(L2_TM_EYE_SURF9, TM_EYE_SURF9_31_8_RSVD, 24, 8)
6340    FIELD(L2_TM_EYE_SURF9, TIMER_TEST_TIME3, 0, 8)
6341REG32(L2_TM_SPARE, 0x98c8)
6342    FIELD(L2_TM_SPARE, TM_SPARE_31_8_RSVD, 24, 8)
6343    FIELD(L2_TM_SPARE, RXDA_SPARE_PORT, 0, 8)
6344REG32(L2_TM_ANA_EQ1, 0x98cc)
6345    FIELD(L2_TM_ANA_EQ1, TM_ANA_EQ1_31_8_RSVD, 24, 8)
6346    FIELD(L2_TM_ANA_EQ1, UNUSED, 5, 3)
6347    FIELD(L2_TM_ANA_EQ1, EQ_INPUT_CM_PROG, 2, 3)
6348    FIELD(L2_TM_ANA_EQ1, EQ_PADINTF_HQ_PROG, 0, 2)
6349REG32(L2_TM_ANA_E_PI0, 0x98d0)
6350    FIELD(L2_TM_ANA_E_PI0, TM_ANA_E_PI0_31_8_RSVD, 24, 8)
6351    FIELD(L2_TM_ANA_E_PI0, EPI_BIASTRIM, 5, 3)
6352    FIELD(L2_TM_ANA_E_PI0, UNUSED, 0, 5)
6353REG32(L2_TM_ANA_IQ_PI0, 0x98d4)
6354    FIELD(L2_TM_ANA_IQ_PI0, TM_ANA_IQ_PI0_31_8_RSVD, 24, 8)
6355    FIELD(L2_TM_ANA_IQ_PI0, IQPI_BIASTRIM, 5, 3)
6356    FIELD(L2_TM_ANA_IQ_PI0, UNUSED, 0, 5)
6357REG32(L2_TM_ANA_MISC0, 0x98d8)
6358    FIELD(L2_TM_ANA_MISC0, TM_ANA_MISC0_31_8_RSVD, 24, 8)
6359    FIELD(L2_TM_ANA_MISC0, EPI_CALIB_EN, 7, 1)
6360    FIELD(L2_TM_ANA_MISC0, IQPI_CALIB_EN, 6, 1)
6361    FIELD(L2_TM_ANA_MISC0, UNUSED, 0, 6)
6362REG32(L2_TM_SAMP_CODE_IQ_PH0, 0x98dc)
6363    FIELD(L2_TM_SAMP_CODE_IQ_PH0, TM_SAMP_CODE_IQ_PH0_31_8_RSVD, 24, 8)
6364    FIELD(L2_TM_SAMP_CODE_IQ_PH0, UNUSED, 7, 1)
6365    FIELD(L2_TM_SAMP_CODE_IQ_PH0, SAMP_CALIB_BYP, 6, 1)
6366    FIELD(L2_TM_SAMP_CODE_IQ_PH0, IQ_PH0_SAMP_CODE, 0, 6)
6367REG32(L2_TM_SAMP_CODE_IQ_PH90, 0x98e0)
6368    FIELD(L2_TM_SAMP_CODE_IQ_PH90, TM_SAMP_CODE_IQ_PH90_31_8_RSVD, 24, 8)
6369    FIELD(L2_TM_SAMP_CODE_IQ_PH90, CALIB_SWEEP_DIR, 6, 2)
6370    FIELD(L2_TM_SAMP_CODE_IQ_PH90, IQ_PH90_SAMP_CODE, 0, 6)
6371REG32(L2_TM_SAMP_CODE_IQ_PH180, 0x98e4)
6372    FIELD(L2_TM_SAMP_CODE_IQ_PH180, TM_SAMP_CODE_IQ_PH180_31_8_RSVD, 24, 8)
6373    FIELD(L2_TM_SAMP_CODE_IQ_PH180, UNUSED, 6, 2)
6374    FIELD(L2_TM_SAMP_CODE_IQ_PH180, IQ_PH180_SAMP_CODE, 0, 6)
6375REG32(L2_TM_SAMP_CODE_IQ_PH270, 0x98e8)
6376    FIELD(L2_TM_SAMP_CODE_IQ_PH270, TM_SAMP_CODE_IQ_PH270_31_8_RSVD, 24, 8)
6377    FIELD(L2_TM_SAMP_CODE_IQ_PH270, HSRX_DBG_BUS_SEL, 6, 2)
6378    FIELD(L2_TM_SAMP_CODE_IQ_PH270, IQ_PH270_SAMP_CODE, 0, 6)
6379REG32(L2_TM_SAMP_CODE_E_PH0, 0x98ec)
6380    FIELD(L2_TM_SAMP_CODE_E_PH0, TM_SAMP_CODE_E_PH0_31_8_RSVD, 24, 8)
6381    FIELD(L2_TM_SAMP_CODE_E_PH0, UNUSED, 6, 2)
6382    FIELD(L2_TM_SAMP_CODE_E_PH0, E_PH90_SAMP_CODE, 0, 6)
6383REG32(L2_TM_SAMP_CODE_E_PH180, 0x98f0)
6384    FIELD(L2_TM_SAMP_CODE_E_PH180, TM_SAMP_CODE_E_PH180_31_8_RSVD, 24, 8)
6385    FIELD(L2_TM_SAMP_CODE_E_PH180, UNUSED, 6, 2)
6386    FIELD(L2_TM_SAMP_CODE_E_PH180, E_PH270_SAMP_CODE, 0, 6)
6387REG32(L2_TM_IQ_ILL0, 0x98f4)
6388    FIELD(L2_TM_IQ_ILL0, TM_IQ_ILL0_31_8_RSVD, 24, 8)
6389    FIELD(L2_TM_IQ_ILL0, ILL_BYPASS_IQ_CAL_EN, 7, 1)
6390    FIELD(L2_TM_IQ_ILL0, IQ_ILL_PLOADTRIM_BYP_VAL, 2, 5)
6391    FIELD(L2_TM_IQ_ILL0, IQ_ILL_PLOADTRIM_BYP, 1, 1)
6392    FIELD(L2_TM_IQ_ILL0, ILL_BYPASS_IQ_CODES, 0, 1)
6393REG32(L2_TM_IQ_ILL1, 0x98f8)
6394    FIELD(L2_TM_IQ_ILL1, TM_IQ_ILL1_31_8_RSVD, 24, 8)
6395    FIELD(L2_TM_IQ_ILL1, ILL_BYPASS_IQ_CALCODE_F0, 0, 8)
6396REG32(L2_TM_IQ_ILL2, 0x98fc)
6397    FIELD(L2_TM_IQ_ILL2, TM_IQ_ILL2_31_8_RSVD, 24, 8)
6398    FIELD(L2_TM_IQ_ILL2, ILL_BYPASS_IQ_CALCODE_F1, 0, 8)
6399REG32(L2_TM_IQ_ILL3, 0x9900)
6400    FIELD(L2_TM_IQ_ILL3, TM_IQ_ILL3_31_8_RSVD, 24, 8)
6401    FIELD(L2_TM_IQ_ILL3, ILL_BYPASS_IQ_CALCODE_F2, 0, 8)
6402REG32(L2_TM_IQ_ILL4, 0x9904)
6403    FIELD(L2_TM_IQ_ILL4, TM_IQ_ILL4_31_8_RSVD, 24, 8)
6404    FIELD(L2_TM_IQ_ILL4, ILL_BYPASS_IQ_CALCODE_F3, 0, 8)
6405REG32(L2_TM_IQ_ILL5, 0x9908)
6406    FIELD(L2_TM_IQ_ILL5, TM_IQ_ILL5_31_8_RSVD, 24, 8)
6407    FIELD(L2_TM_IQ_ILL5, ILL_BYPASS_IQ_CALCODE_F4, 0, 8)
6408REG32(L2_TM_IQ_ILL6, 0x990c)
6409    FIELD(L2_TM_IQ_ILL6, TM_IQ_ILL6_31_8_RSVD, 24, 8)
6410    FIELD(L2_TM_IQ_ILL6, ILL_BYPASS_IQ_CALCODE_F5, 0, 8)
6411REG32(L2_TM_IQ_ILL7, 0x9910)
6412    FIELD(L2_TM_IQ_ILL7, TM_IQ_ILL7_31_8_RSVD, 24, 8)
6413    FIELD(L2_TM_IQ_ILL7, ILL_BYPASS_IQ_CNSTGMTRIM_VAL, 0, 8)
6414REG32(L2_TM_IQ_ILL8, 0x9914)
6415    FIELD(L2_TM_IQ_ILL8, TM_IQ_ILL8_31_8_RSVD, 24, 8)
6416    FIELD(L2_TM_IQ_ILL8, ILL_BYPASS_IQ_POLYTRIM_VAL, 0, 8)
6417REG32(L2_TM_IQ_ILL9, 0x9918)
6418    FIELD(L2_TM_IQ_ILL9, TM_IQ_ILL9_31_8_RSVD, 24, 8)
6419    FIELD(L2_TM_IQ_ILL9, UNUSED, 4, 4)
6420    FIELD(L2_TM_IQ_ILL9, ILL_BYPASS_IQ_LFEN, 3, 1)
6421    FIELD(L2_TM_IQ_ILL9, ILL_BYPASS_IQ_LFEN_VAL, 2, 1)
6422    FIELD(L2_TM_IQ_ILL9, ILL_BYPASS_IQ_CNSTGMTRIM, 1, 1)
6423    FIELD(L2_TM_IQ_ILL9, ILL_BYPASS_IQ_POLYTIM, 0, 1)
6424REG32(L2_TM_IQ_ILL10, 0x991c)
6425    FIELD(L2_TM_IQ_ILL10, TM_IQ_ILL10_31_8_RSVD, 24, 8)
6426    FIELD(L2_TM_IQ_ILL10, UNUSED, 6, 2)
6427    FIELD(L2_TM_IQ_ILL10, IQPI_CALCTRIM, 4, 2)
6428    FIELD(L2_TM_IQ_ILL10, IQPI_REPLICATRIM, 0, 4)
6429REG32(L2_TM_E_ILL0, 0x9920)
6430    FIELD(L2_TM_E_ILL0, TM_E_ILL0_31_8_RSVD, 24, 8)
6431    FIELD(L2_TM_E_ILL0, E_ILL_CALIB_CTRL, 7, 1)
6432    FIELD(L2_TM_E_ILL0, E_ILL_PLOADTRIM_BYP_VAL, 2, 5)
6433    FIELD(L2_TM_E_ILL0, E_ILL_PLOADTRIM_BYP, 1, 1)
6434    FIELD(L2_TM_E_ILL0, E_ILL_CALIB_BYP, 0, 1)
6435REG32(L2_TM_E_ILL1, 0x9924)
6436    FIELD(L2_TM_E_ILL1, TM_E_ILL1_31_8_RSVD, 24, 8)
6437    FIELD(L2_TM_E_ILL1, ILL_BYPASS_E_CALCODE_F0, 0, 8)
6438REG32(L2_TM_E_ILL2, 0x9928)
6439    FIELD(L2_TM_E_ILL2, TM_E_ILL2_31_8_RSVD, 24, 8)
6440    FIELD(L2_TM_E_ILL2, ILL_BYPASS_E_CALCODE_F1, 0, 8)
6441REG32(L2_TM_E_ILL3, 0x992c)
6442    FIELD(L2_TM_E_ILL3, TM_E_ILL3_31_8_RSVD, 24, 8)
6443    FIELD(L2_TM_E_ILL3, ILL_BYPASS_E_CALCODE_F2, 0, 8)
6444REG32(L2_TM_E_ILL4, 0x9930)
6445    FIELD(L2_TM_E_ILL4, TM_E_ILL4_31_8_RSVD, 24, 8)
6446    FIELD(L2_TM_E_ILL4, ILL_BYPASS_E_CALCODE_F3, 0, 8)
6447REG32(L2_TM_E_ILL5, 0x9934)
6448    FIELD(L2_TM_E_ILL5, TM_E_ILL5_31_8_RSVD, 24, 8)
6449    FIELD(L2_TM_E_ILL5, ILL_BYPASS_E_CALCODE_F4, 0, 8)
6450REG32(L2_TM_E_ILL6, 0x9938)
6451    FIELD(L2_TM_E_ILL6, TM_E_ILL6_31_8_RSVD, 24, 8)
6452    FIELD(L2_TM_E_ILL6, ILL_BYPASS_E_CALCODE_F5, 0, 8)
6453REG32(L2_TM_E_ILL7, 0x993c)
6454    FIELD(L2_TM_E_ILL7, TM_E_ILL7_31_8_RSVD, 24, 8)
6455    FIELD(L2_TM_E_ILL7, ILL_BYPASS_E_CNSTGMTRIM_VAL, 0, 8)
6456REG32(L2_TM_E_ILL8, 0x9940)
6457    FIELD(L2_TM_E_ILL8, TM_E_ILL8_31_8_RSVD, 24, 8)
6458    FIELD(L2_TM_E_ILL8, ILL_BYPASS_E_POLYTRIM_VAL, 0, 8)
6459REG32(L2_TM_E_ILL9, 0x9944)
6460    FIELD(L2_TM_E_ILL9, TM_E_ILL9_31_8_RSVD, 24, 8)
6461    FIELD(L2_TM_E_ILL9, UNUSED, 4, 4)
6462    FIELD(L2_TM_E_ILL9, ILL_BYPASS_E_LFEN, 3, 1)
6463    FIELD(L2_TM_E_ILL9, ILL_BYPASS_E_LFEN_VAL, 2, 1)
6464    FIELD(L2_TM_E_ILL9, ILL_BYPASS_E_CNSTGMTRIM, 1, 1)
6465    FIELD(L2_TM_E_ILL9, ILL_BYPASS_E_POLYTIM, 0, 1)
6466REG32(L2_TM_E_ILL10, 0x9948)
6467    FIELD(L2_TM_E_ILL10, TM_E_ILL10_31_8_RSVD, 24, 8)
6468    FIELD(L2_TM_E_ILL10, UNUSED, 6, 2)
6469    FIELD(L2_TM_E_ILL10, EPI_CALCTRIM, 4, 2)
6470    FIELD(L2_TM_E_ILL10, EPI_REPLICATRIM, 0, 4)
6471REG32(L2_TM_EQ0, 0x994c)
6472    FIELD(L2_TM_EQ0, TM_EQ0_31_8_RSVD, 24, 8)
6473    FIELD(L2_TM_EQ0, EQ_STG1_RL_PROG_MSB, 7, 1)
6474    FIELD(L2_TM_EQ0, EQ_STG1_CTRL_BYP, 6, 1)
6475    FIELD(L2_TM_EQ0, EQ_STG2_CTRL_BYP, 5, 1)
6476    FIELD(L2_TM_EQ0, EQ_ADAPTATION_FORCE, 4, 1)
6477    FIELD(L2_TM_EQ0, EQ_ADAPTATION_FORCE_VAL, 3, 1)
6478    FIELD(L2_TM_EQ0, EQ_ISOURCE_EN_VAL, 0, 3)
6479REG32(L2_TM_EQ1, 0x9950)
6480    FIELD(L2_TM_EQ1, TM_EQ1_31_8_RSVD, 24, 8)
6481    FIELD(L2_TM_EQ1, EQ_STG1_PREAMP_MODE_VAL, 7, 1)
6482    FIELD(L2_TM_EQ1, EQ_STG1_RL_PROG, 5, 2)
6483    FIELD(L2_TM_EQ1, EQ_STG2_CM_PROG, 3, 2)
6484    FIELD(L2_TM_EQ1, EQ_STG2_PREAMP_MODE_VAL, 2, 1)
6485    FIELD(L2_TM_EQ1, EQ_STG2_RL_PROG, 0, 2)
6486REG32(L2_TM_EQ2, 0x9954)
6487    FIELD(L2_TM_EQ2, TM_EQ2_31_8_RSVD, 24, 8)
6488    FIELD(L2_TM_EQ2, UNUSED, 7, 1)
6489    FIELD(L2_TM_EQ2, EQ_EN_BACKGND_ADAPT, 6, 1)
6490    FIELD(L2_TM_EQ2, EQ_COUNT_STRAYS, 5, 1)
6491    FIELD(L2_TM_EQ2, EQ_WINDOW_SIZE, 3, 2)
6492    FIELD(L2_TM_EQ2, EQ_MAJ_THRESH, 1, 2)
6493    FIELD(L2_TM_EQ2, EQ_BIAS_CTRL_BYP, 0, 1)
6494REG32(L2_TM_EQ3, 0x9958)
6495    FIELD(L2_TM_EQ3, TM_EQ3_31_8_RSVD, 24, 8)
6496    FIELD(L2_TM_EQ3, UNUSED, 5, 3)
6497    FIELD(L2_TM_EQ3, EQ_BYPASS_ISINK_ENZ_VAL, 0, 5)
6498REG32(L2_TM_EQ4, 0x995c)
6499    FIELD(L2_TM_EQ4, TM_EQ4_31_8_RSVD, 24, 8)
6500    FIELD(L2_TM_EQ4, UNUSED, 5, 3)
6501    FIELD(L2_TM_EQ4, BYPASS_EQ_C_STG1, 4, 1)
6502    FIELD(L2_TM_EQ4, BYPASS_EQ_C_VAL_STG1, 0, 4)
6503REG32(L2_TM_EQ5, 0x9960)
6504    FIELD(L2_TM_EQ5, TM_EQ5_31_8_RSVD, 24, 8)
6505    FIELD(L2_TM_EQ5, UNUSED, 6, 2)
6506    FIELD(L2_TM_EQ5, BYPASS_EQ_R_STG1, 5, 1)
6507    FIELD(L2_TM_EQ5, BYPASS_EQ_R_VAL_STG1, 0, 5)
6508REG32(L2_TM_EQ6, 0x9964)
6509    FIELD(L2_TM_EQ6, TM_EQ6_31_8_RSVD, 24, 8)
6510    FIELD(L2_TM_EQ6, UNUSED, 5, 3)
6511    FIELD(L2_TM_EQ6, BYPASS_EQ_C_STG2, 4, 1)
6512    FIELD(L2_TM_EQ6, BYPASS_EQ_C_VAL_STG2, 0, 4)
6513REG32(L2_TM_EQ7, 0x9968)
6514    FIELD(L2_TM_EQ7, TM_EQ7_31_8_RSVD, 24, 8)
6515    FIELD(L2_TM_EQ7, UNUSED, 6, 2)
6516    FIELD(L2_TM_EQ7, BYPASS_EQ_R_STG2, 5, 1)
6517    FIELD(L2_TM_EQ7, BYPASS_EQ_R_VAL_STG2, 0, 5)
6518REG32(L2_TM_EQ8, 0x996c)
6519    FIELD(L2_TM_EQ8, TM_EQ8_31_8_RSVD, 24, 8)
6520    FIELD(L2_TM_EQ8, EQ_BYPASS_CALIB, 7, 1)
6521    FIELD(L2_TM_EQ8, EQ_SWEEP, 5, 2)
6522    FIELD(L2_TM_EQ8, SEL_SAMP, 2, 3)
6523    FIELD(L2_TM_EQ8, BYPASS_EQ_CAL, 1, 1)
6524    FIELD(L2_TM_EQ8, BYPASS_EQ_CAL_VAL, 0, 1)
6525REG32(L2_TM_EQ9, 0x9970)
6526    FIELD(L2_TM_EQ9, TM_EQ9_31_8_RSVD, 24, 8)
6527    FIELD(L2_TM_EQ9, UNUSED, 7, 1)
6528    FIELD(L2_TM_EQ9, EQ_BYPASS_CALIB_CODE, 0, 7)
6529REG32(L2_TM_EQ10, 0x9974)
6530    FIELD(L2_TM_EQ10, TM_EQ10_31_8_RSVD, 24, 8)
6531    FIELD(L2_TM_EQ10, UNUSED, 7, 1)
6532    FIELD(L2_TM_EQ10, OFFSET_COEF_SCALER, 4, 3)
6533    FIELD(L2_TM_EQ10, DIAG_OUTPUT_SEL, 0, 4)
6534REG32(L2_TM_EQ11, 0x9978)
6535    FIELD(L2_TM_EQ11, TM_EQ11_31_8_RSVD, 24, 8)
6536    FIELD(L2_TM_EQ11, EQ_CALIB_CLK_DIV_FORCE, 7, 1)
6537    FIELD(L2_TM_EQ11, EDGE_IS_FIRST, 6, 1)
6538    FIELD(L2_TM_EQ11, FORCE_EQ_OFFS_ON, 5, 1)
6539    FIELD(L2_TM_EQ11, FORCE_EQ_OFFS_OFF, 4, 1)
6540    FIELD(L2_TM_EQ11, EQ_OFFS_WITH_ADAPT, 3, 1)
6541    FIELD(L2_TM_EQ11, OFFSET_VOTER_OVERRIDE_EN, 2, 1)
6542    FIELD(L2_TM_EQ11, OFFSET_VOTER_OVERRIDE_NEG, 1, 1)
6543    FIELD(L2_TM_EQ11, OFFSET_VOTER_OVERRIDE_POS, 0, 1)
6544REG32(L2_TM_ILL7, 0x997c)
6545    FIELD(L2_TM_ILL7, TM_ILL7_31_8_RSVD, 24, 8)
6546    FIELD(L2_TM_ILL7, ILL_CAL_INIT_WAIT, 0, 8)
6547REG32(L2_TM_ILL8, 0x9980)
6548    FIELD(L2_TM_ILL8, TM_ILL8_31_8_RSVD, 24, 8)
6549    FIELD(L2_TM_ILL8, ILL_CAL_ITER_WAIT, 0, 8)
6550REG32(L2_TM_ILL9, 0x9984)
6551    FIELD(L2_TM_ILL9, TM_ILL9_31_8_RSVD, 24, 8)
6552    FIELD(L2_TM_ILL9, ILL_CAL_BYPASS_CAP_START, 7, 1)
6553    FIELD(L2_TM_ILL9, ILL_CAL_CAP_START_VAL, 0, 7)
6554REG32(L2_TM_ILL10, 0x9988)
6555    FIELD(L2_TM_ILL10, TM_ILL10_31_8_RSVD, 24, 8)
6556    FIELD(L2_TM_ILL10, G3A_USB3_PCIEG2_PLL_CTR_11_8_BYP_VAL, 4, 4)
6557    FIELD(L2_TM_ILL10, G3B_PLL_CTR_11_8_BYP_VAL, 0, 4)
6558REG32(L2_TM_ILL11, 0x998c)
6559    FIELD(L2_TM_ILL11, TM_ILL11_31_8_RSVD, 24, 8)
6560    FIELD(L2_TM_ILL11, G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL, 4, 4)
6561    FIELD(L2_TM_ILL11, G2B_PLL_CTR_11_8_BYP_VAL, 0, 4)
6562REG32(L2_TM_ILL12, 0x9990)
6563    FIELD(L2_TM_ILL12, TM_ILL12_31_8_RSVD, 24, 8)
6564    FIELD(L2_TM_ILL12, G1A_PLL_CTR_BYP_VAL, 0, 8)
6565REG32(L2_TM_ILL13, 0x9994)
6566    FIELD(L2_TM_ILL13, TM_ILL13_31_8_RSVD, 24, 8)
6567    FIELD(L2_TM_ILL13, ILL_CAL_IDLE_VAL_REFCNT, 0, 3)
6568REG32(L2_TM_ILL14, 0x9998)
6569    FIELD(L2_TM_ILL14, TM_ILL14_31_8_RSVD, 24, 8)
6570    FIELD(L2_TM_ILL14, ILL_CALIB_WAIT, 4, 4)
6571    FIELD(L2_TM_ILL14, ILL_CHG_WAIT, 0, 4)
6572REG32(L2_TM_FRZ_FSM0, 0x999c)
6573    FIELD(L2_TM_FRZ_FSM0, TM_FRZ_FSM0_31_8_RSVD, 24, 8)
6574    FIELD(L2_TM_FRZ_FSM0, FREEZE_HSRX_PWR_SEQ_FSM, 0, 8)
6575REG32(L2_TM_FRZ_FSM1, 0x99a0)
6576    FIELD(L2_TM_FRZ_FSM1, TM_FRZ_FSM1_31_8_RSVD, 24, 8)
6577    FIELD(L2_TM_FRZ_FSM1, UNUSED, 6, 2)
6578    FIELD(L2_TM_FRZ_FSM1, FREEZE_ILL_CALIB_FSM, 0, 6)
6579REG32(L2_TM_RST_DLY, 0x99a4)
6580    FIELD(L2_TM_RST_DLY, TM_RST_DLY_31_8_RSVD, 24, 8)
6581    FIELD(L2_TM_RST_DLY, APB_RST_DLY, 0, 8)
6582REG32(L2_TM_ILL15, 0x99a8)
6583    FIELD(L2_TM_ILL15, TM_ILL15_31_8_RSVD, 24, 8)
6584    FIELD(L2_TM_ILL15, ILL_CAL_REF_CTR_MSB_REG1, 0, 8)
6585REG32(L2_TM_MISC3, 0x99ac)
6586    FIELD(L2_TM_MISC3, TM_MISC3_31_8_RSVD, 24, 8)
6587    FIELD(L2_TM_MISC3, AUX0_BIT_7, 7, 1)
6588    FIELD(L2_TM_MISC3, AUX0_BIT_6, 6, 1)
6589    FIELD(L2_TM_MISC3, AUX0_BIT_5, 5, 1)
6590    FIELD(L2_TM_MISC3, DBG_BUS_SEL, 2, 3)
6591    FIELD(L2_TM_MISC3, CDR_EN_FPL, 1, 1)
6592    FIELD(L2_TM_MISC3, CDR_EN_FFL, 0, 1)
6593REG32(L2_TM_EQ_OFFS1, 0x99b0)
6594    FIELD(L2_TM_EQ_OFFS1, TM_EQ_OFFS1_31_8_RSVD, 24, 8)
6595    FIELD(L2_TM_EQ_OFFS1, EQ_OFFSET_CORR_BYP, 1, 7)
6596    FIELD(L2_TM_EQ_OFFS1, AUX1_BIT_7, 0, 1)
6597REG32(L2_TM_SAMP0, 0x99b4)
6598    FIELD(L2_TM_SAMP0, TM_SAMP0_31_8_RSVD, 24, 8)
6599    FIELD(L2_TM_SAMP0, SAMP_CALIB_CLK_DIV_FACTOR, 1, 7)
6600    FIELD(L2_TM_SAMP0, SAMP_CALIB_CLK_DIV_FORCE, 0, 1)
6601REG32(L2_TM_EQ12, 0x99b8)
6602    FIELD(L2_TM_EQ12, TM_EQ12_31_8_RSVD, 24, 8)
6603    FIELD(L2_TM_EQ12, EQ_CALIB_CLK_DIV_FACTOR, 0, 8)
6604REG32(L2_TM_MISC4, 0x99bc)
6605    FIELD(L2_TM_MISC4, TM_MISC4_31_8_RSVD, 24, 8)
6606    FIELD(L2_TM_MISC4, PSO_CLK_LANE_FRM_PCS, 2, 1)
6607    FIELD(L2_TM_MISC4, BSCAN_MODE_VAL, 1, 1)
6608    FIELD(L2_TM_MISC4, BSCAN_FORCE_MODE, 0, 1)
6609REG32(L2_TM_SAMP_STATUS0, 0x9a80)
6610    FIELD(L2_TM_SAMP_STATUS0, TM_SAMP_STATUS0_31_8_RSVD, 24, 8)
6611    FIELD(L2_TM_SAMP_STATUS0, IQ_SAMP_PH0_CALIB_CODE, 0, 6)
6612REG32(L2_TM_SAMP_STATUS1, 0x9a84)
6613    FIELD(L2_TM_SAMP_STATUS1, TM_SAMP_STATUS1_31_8_RSVD, 24, 8)
6614    FIELD(L2_TM_SAMP_STATUS1, IQ_SAMP_PH90_CALIB_CODE, 0, 6)
6615REG32(L2_TM_SAMP_STATUS2, 0x9a88)
6616    FIELD(L2_TM_SAMP_STATUS2, TM_SAMP_STATUS2_31_8_RSVD, 24, 8)
6617    FIELD(L2_TM_SAMP_STATUS2, IQ_SAMP_PH180_CALIB_CODE, 0, 6)
6618REG32(L2_TM_SAMP_STATUS3, 0x9a8c)
6619    FIELD(L2_TM_SAMP_STATUS3, TM_SAMP_STATUS3_31_8_RSVD, 24, 8)
6620    FIELD(L2_TM_SAMP_STATUS3, IQ_SAMP_PH270_CALIB_CODE, 0, 6)
6621REG32(L2_TM_SAMP_STATUS4, 0x9a90)
6622    FIELD(L2_TM_SAMP_STATUS4, TM_SAMP_STATUS4_31_8_RSVD, 24, 8)
6623    FIELD(L2_TM_SAMP_STATUS4, E_SAMP_PH0_CALIB_CODE, 0, 6)
6624REG32(L2_TM_SAMP_STATUS5, 0x9a94)
6625    FIELD(L2_TM_SAMP_STATUS5, TM_SAMP_STATUS5_31_8_RSVD, 24, 8)
6626    FIELD(L2_TM_SAMP_STATUS5, E_SAMP_PH180_CALIB_CODE, 0, 6)
6627REG32(L2_TM_ILL_STATUS0, 0x9a98)
6628    FIELD(L2_TM_ILL_STATUS0, TM_ILL_STATUS0_31_8_RSVD, 24, 8)
6629    FIELD(L2_TM_ILL_STATUS0, IQ_F0_CALCODE_CALIB_VAL, 0, 7)
6630REG32(L2_TM_ILL_STATUS1, 0x9a9c)
6631    FIELD(L2_TM_ILL_STATUS1, TM_ILL_STATUS1_31_8_RSVD, 24, 8)
6632    FIELD(L2_TM_ILL_STATUS1, IQ_F1_CALCODE_CALIB_VAL, 0, 7)
6633REG32(L2_TM_ILL_STATUS2, 0x9aa0)
6634    FIELD(L2_TM_ILL_STATUS2, TM_ILL_STATUS2_31_8_RSVD, 24, 8)
6635    FIELD(L2_TM_ILL_STATUS2, IQ_F2_CALCODE_CALIB_VAL, 0, 7)
6636REG32(L2_TM_ILL_STATUS3, 0x9aa4)
6637    FIELD(L2_TM_ILL_STATUS3, TM_ILL_STATUS3_31_8_RSVD, 24, 8)
6638    FIELD(L2_TM_ILL_STATUS3, IQ_F3_CALCODE_CALIB_VAL, 0, 7)
6639REG32(L2_TM_ILL_STATUS4, 0x9aa8)
6640    FIELD(L2_TM_ILL_STATUS4, TM_ILL_STATUS4_31_8_RSVD, 24, 8)
6641    FIELD(L2_TM_ILL_STATUS4, IQ_F4_CALCODE_CALIB_VAL, 0, 7)
6642REG32(L2_TM_ILL_STATUS5, 0x9aac)
6643    FIELD(L2_TM_ILL_STATUS5, TM_ILL_STATUS5_31_8_RSVD, 24, 8)
6644    FIELD(L2_TM_ILL_STATUS5, IQ_F5_CALCODE_CALIB_VAL, 0, 7)
6645REG32(L2_TM_ILL_STATUS6, 0x9ab0)
6646    FIELD(L2_TM_ILL_STATUS6, TM_ILL_STATUS6_31_8_RSVD, 24, 8)
6647    FIELD(L2_TM_ILL_STATUS6, E_F0_CALCODE_CALIB_VAL, 0, 7)
6648REG32(L2_TM_ILL_STATUS7, 0x9ab4)
6649    FIELD(L2_TM_ILL_STATUS7, TM_ILL_STATUS7_31_8_RSVD, 24, 8)
6650    FIELD(L2_TM_ILL_STATUS7, E_F1_CALCODE_CALIB_VAL, 0, 7)
6651REG32(L2_TM_ILL_STATUS8, 0x9ab8)
6652    FIELD(L2_TM_ILL_STATUS8, TM_ILL_STATUS8_31_8_RSVD, 24, 8)
6653    FIELD(L2_TM_ILL_STATUS8, E_F2_CALCODE_CALIB_VAL, 0, 7)
6654REG32(L2_TM_ILL_STATUS9, 0x9abc)
6655    FIELD(L2_TM_ILL_STATUS9, TM_ILL_STATUS9_31_8_RSVD, 24, 8)
6656    FIELD(L2_TM_ILL_STATUS9, E_F3_CALCODE_CALIB_VAL, 0, 7)
6657REG32(L2_TM_ILL_STATUS10, 0x9ac0)
6658    FIELD(L2_TM_ILL_STATUS10, TM_ILL_STATUS10_31_8_RSVD, 24, 8)
6659    FIELD(L2_TM_ILL_STATUS10, E_F4_CALCODE_CALIB_VAL, 0, 7)
6660REG32(L2_TM_ILL_STATUS11, 0x9ac4)
6661    FIELD(L2_TM_ILL_STATUS11, TM_ILL_STATUS11_31_8_RSVD, 24, 8)
6662    FIELD(L2_TM_ILL_STATUS11, E_F5_CALCODE_CALIB_VAL, 0, 7)
6663REG32(L2_TM_MISC_ST_0, 0x9ac8)
6664    FIELD(L2_TM_MISC_ST_0, TM_MISC_ST_0_31_8_RSVD, 24, 8)
6665    FIELD(L2_TM_MISC_ST_0, EYE_SURF_DONE, 5, 1)
6666    FIELD(L2_TM_MISC_ST_0, SD_CAL_DONE, 4, 1)
6667    FIELD(L2_TM_MISC_ST_0, SAMP_CAL_DONE, 3, 1)
6668    FIELD(L2_TM_MISC_ST_0, ILL_CAL_DONE, 2, 1)
6669    FIELD(L2_TM_MISC_ST_0, EQ_CAL_DONE, 1, 1)
6670    FIELD(L2_TM_MISC_ST_0, EQ_VALID_ADAPT_CODE, 0, 1)
6671REG32(L2_TM_SD_ST_0, 0x9acc)
6672    FIELD(L2_TM_SD_ST_0, TM_SD_ST_0_31_8_RSVD, 24, 8)
6673    FIELD(L2_TM_SD_ST_0, SD_CAL_CODE, 0, 6)
6674REG32(L2_TM_EYESURF_ST0, 0x9ad0)
6675    FIELD(L2_TM_EYESURF_ST0, TM_EYESURF_ST0_31_8_RSVD, 24, 8)
6676    FIELD(L2_TM_EYESURF_ST0, ERROR_COUNT0, 0, 8)
6677REG32(L2_TM_EYESURF_ST1, 0x9ad4)
6678    FIELD(L2_TM_EYESURF_ST1, TM_EYESURF_ST1_31_8_RSVD, 24, 8)
6679    FIELD(L2_TM_EYESURF_ST1, ERROR_COUNT1, 0, 8)
6680REG32(L2_TM_EQ_ST0, 0x9ad8)
6681    FIELD(L2_TM_EQ_ST0, TM_EQ_ST0_31_8_RSVD, 24, 8)
6682    FIELD(L2_TM_EQ_ST0, EQ_ADAPT_CODE0, 0, 8)
6683REG32(L2_TM_EQ_ST1, 0x9adc)
6684    FIELD(L2_TM_EQ_ST1, TM_EQ_ST1_31_8_RSVD, 24, 8)
6685    FIELD(L2_TM_EQ_ST1, EQ_ADAPT_CODE1, 0, 8)
6686REG32(L2_TM_EQ_ST2, 0x9ae0)
6687    FIELD(L2_TM_EQ_ST2, TM_EQ_ST2_31_8_RSVD, 24, 8)
6688    FIELD(L2_TM_EQ_ST2, EQ_CALIB_CODE, 0, 7)
6689REG32(L2_TM_RXPMA_ST1, 0x9ae4)
6690    FIELD(L2_TM_RXPMA_ST1, TM_RXPMA_ST1_31_8_RSVD, 24, 8)
6691    FIELD(L2_TM_RXPMA_ST1, HSRX_OPMODE_STATUS, 0, 8)
6692REG32(L2_TM_CDR0, 0x9c00)
6693    FIELD(L2_TM_CDR0, TM_CDR0_31_8_RSVD, 24, 8)
6694    FIELD(L2_TM_CDR0, FAST_PHASE_LOCK_FORCE, 7, 1)
6695    FIELD(L2_TM_CDR0, UNUSED, 5, 2)
6696    FIELD(L2_TM_CDR0, CDR_LOOP_CTRL, 2, 3)
6697    FIELD(L2_TM_CDR0, SECOND_ORDER_LOOP_DIS, 1, 1)
6698    FIELD(L2_TM_CDR0, FIRST_ORDER_LOOP_DIS, 0, 1)
6699REG32(L2_TM_CDR1, 0x9c04)
6700    FIELD(L2_TM_CDR1, TM_CDR1_31_8_RSVD, 24, 8)
6701    FIELD(L2_TM_CDR1, RESET_DELAY_2OL, 0, 8)
6702REG32(L2_TM_CDR2, 0x9c08)
6703    FIELD(L2_TM_CDR2, TM_CDR2_31_8_RSVD, 24, 8)
6704    FIELD(L2_TM_CDR2, CLK_SEL_2OL, 6, 2)
6705    FIELD(L2_TM_CDR2, INTEGRATOR_THRESH_2OL, 0, 6)
6706REG32(L2_TM_CDR3, 0x9c0c)
6707    FIELD(L2_TM_CDR3, TM_CDR3_31_8_RSVD, 24, 8)
6708    FIELD(L2_TM_CDR3, UNUSED, 7, 1)
6709    FIELD(L2_TM_CDR3, SIGNAL_THRESH_1OL, 0, 7)
6710REG32(L2_TM_CDR4, 0x9c10)
6711    FIELD(L2_TM_CDR4, TM_CDR4_31_8_RSVD, 24, 8)
6712    FIELD(L2_TM_CDR4, UNUSED, 7, 1)
6713    FIELD(L2_TM_CDR4, SIGNAL_THRESH_2OL, 0, 7)
6714REG32(L2_TM_CDR5, 0x9c14)
6715    FIELD(L2_TM_CDR5, TM_CDR5_31_8_RSVD, 24, 8)
6716    FIELD(L2_TM_CDR5, FPHL_FSM_ACC_CYCLES, 5, 3)
6717    FIELD(L2_TM_CDR5, FFL_PH0_INT_GAIN, 0, 5)
6718REG32(L2_TM_CDR6, 0x9c18)
6719    FIELD(L2_TM_CDR6, TM_CDR6_31_8_RSVD, 24, 8)
6720    FIELD(L2_TM_CDR6, FPHL_FSM_DELAY_CYCLES, 5, 3)
6721    FIELD(L2_TM_CDR6, FFL_PH1_INT_GAIN, 0, 5)
6722REG32(L2_TM_CDR7, 0x9c1c)
6723    FIELD(L2_TM_CDR7, TM_CDR7_31_8_RSVD, 24, 8)
6724    FIELD(L2_TM_CDR7, FPHL_FSM_TRIGGER1_WAIT_CYCLES, 5, 3)
6725    FIELD(L2_TM_CDR7, FFL_PH2_INT_GAIN, 0, 5)
6726REG32(L2_TM_CDR8, 0x9c20)
6727    FIELD(L2_TM_CDR8, TM_CDR8_31_8_RSVD, 24, 8)
6728    FIELD(L2_TM_CDR8, FPHL_FSM_TRIGGER2_WAIT_CYCLES, 5, 3)
6729    FIELD(L2_TM_CDR8, FFL_PH3_INT_GAIN, 0, 5)
6730REG32(L2_TM_CDR9, 0x9c24)
6731    FIELD(L2_TM_CDR9, TM_CDR9_31_8_RSVD, 24, 8)
6732    FIELD(L2_TM_CDR9, FPHL_FSM_TRIGGER3_WAIT_CYCLES, 5, 3)
6733    FIELD(L2_TM_CDR9, FFL_PH4_INT_GAIN, 0, 5)
6734REG32(L2_TM_CDR10, 0x9c28)
6735    FIELD(L2_TM_CDR10, TM_CDR10_31_8_RSVD, 24, 8)
6736    FIELD(L2_TM_CDR10, FFL_TIME_PER_PHASE_10_8, 5, 3)
6737    FIELD(L2_TM_CDR10, FFL_PH5_INT_GAIN, 0, 5)
6738REG32(L2_TM_CDR11, 0x9c2c)
6739    FIELD(L2_TM_CDR11, TM_CDR11_31_8_RSVD, 24, 8)
6740    FIELD(L2_TM_CDR11, UNUSED, 5, 3)
6741    FIELD(L2_TM_CDR11, FFL_PH6_INT_GAIN, 0, 5)
6742REG32(L2_TM_CDR12, 0x9c30)
6743    FIELD(L2_TM_CDR12, TM_CDR12_31_8_RSVD, 24, 8)
6744    FIELD(L2_TM_CDR12, CDRLF_RESET_ON_EN_CDR, 7, 1)
6745    FIELD(L2_TM_CDR12, CDRLF_RESET_ON_INT_MAX_2OL, 6, 1)
6746    FIELD(L2_TM_CDR12, CDRLF_RESET_ON_MODE_CHG, 5, 1)
6747    FIELD(L2_TM_CDR12, FFL_PH7_INT_GAIN, 0, 5)
6748REG32(L2_TM_CDR13, 0x9c34)
6749    FIELD(L2_TM_CDR13, TM_CDR13_31_8_RSVD, 24, 8)
6750    FIELD(L2_TM_CDR13, FFL_TIME_PER_PHASE_7_0, 0, 8)
6751REG32(L2_TM_CDR14, 0x9c38)
6752    FIELD(L2_TM_CDR14, TM_CDR14_31_8_RSVD, 24, 8)
6753    FIELD(L2_TM_CDR14, FFL_PH3_POST_INT_GAIN, 6, 2)
6754    FIELD(L2_TM_CDR14, FFL_PH2_POST_INT_GAIN, 4, 2)
6755    FIELD(L2_TM_CDR14, FFL_PH1_POST_INT_GAIN, 2, 2)
6756    FIELD(L2_TM_CDR14, FFL_PH0_POST_INT_GAIN, 0, 2)
6757REG32(L2_TM_CDR15, 0x9c3c)
6758    FIELD(L2_TM_CDR15, TM_CDR15_31_8_RSVD, 24, 8)
6759    FIELD(L2_TM_CDR15, FFL_PH7_POST_INT_GAIN, 6, 2)
6760    FIELD(L2_TM_CDR15, FFL_PH6_POST_INT_GAIN, 4, 2)
6761    FIELD(L2_TM_CDR15, FFL_PH5_POST_INT_GAIN, 2, 2)
6762    FIELD(L2_TM_CDR15, FFL_PH4_POST_INT_GAIN, 0, 2)
6763REG32(L2_TM_CDR16, 0x9c40)
6764    FIELD(L2_TM_CDR16, TM_CDR16_31_8_RSVD, 24, 8)
6765    FIELD(L2_TM_CDR16, UNUSED, 5, 3)
6766    FIELD(L2_TM_CDR16, FFL_PH0_PROP_GAIN, 0, 5)
6767REG32(L2_TM_CDR17, 0x9c44)
6768    FIELD(L2_TM_CDR17, TM_CDR17_31_8_RSVD, 24, 8)
6769    FIELD(L2_TM_CDR17, UNUSED, 5, 3)
6770    FIELD(L2_TM_CDR17, FFL_PH1_PROP_GAIN, 0, 5)
6771REG32(L2_TM_CDR18, 0x9c48)
6772    FIELD(L2_TM_CDR18, TM_CDR18_31_8_RSVD, 24, 8)
6773    FIELD(L2_TM_CDR18, UNUSED, 5, 3)
6774    FIELD(L2_TM_CDR18, FFL_PH2_PROP_GAIN, 0, 5)
6775REG32(L2_TM_CDR19, 0x9c4c)
6776    FIELD(L2_TM_CDR19, TM_CDR19_31_8_RSVD, 24, 8)
6777    FIELD(L2_TM_CDR19, UNUSED, 5, 3)
6778    FIELD(L2_TM_CDR19, FFL_PH3_PROP_GAIN, 0, 5)
6779REG32(L2_TM_CDR20, 0x9c50)
6780    FIELD(L2_TM_CDR20, TM_CDR20_31_8_RSVD, 24, 8)
6781    FIELD(L2_TM_CDR20, UNUSED, 5, 3)
6782    FIELD(L2_TM_CDR20, FFL_PH4_PROP_GAIN, 0, 5)
6783REG32(L2_TM_CDR21, 0x9c54)
6784    FIELD(L2_TM_CDR21, TM_CDR21_31_8_RSVD, 24, 8)
6785    FIELD(L2_TM_CDR21, UNUSED, 5, 3)
6786    FIELD(L2_TM_CDR21, FFL_PH5_PROP_GAIN, 0, 5)
6787REG32(L2_TM_CDR22, 0x9c58)
6788    FIELD(L2_TM_CDR22, TM_CDR22_31_8_RSVD, 24, 8)
6789    FIELD(L2_TM_CDR22, UNUSED, 5, 3)
6790    FIELD(L2_TM_CDR22, FFL_PH6_PROP_GAIN, 0, 5)
6791REG32(L2_TM_CDR23, 0x9c5c)
6792    FIELD(L2_TM_CDR23, TM_CDR23_31_8_RSVD, 24, 8)
6793    FIELD(L2_TM_CDR23, UNUSED, 7, 1)
6794    FIELD(L2_TM_CDR23, PHASE_LAG_LEAD_RESPONSE, 5, 2)
6795    FIELD(L2_TM_CDR23, FFL_PH7_PROP_GAIN, 0, 5)
6796REG32(L2_TM_MISC0, 0x9c60)
6797    FIELD(L2_TM_MISC0, TM_MISC0_31_8_RSVD, 24, 8)
6798    FIELD(L2_TM_MISC0, UNUSED, 2, 6)
6799    FIELD(L2_TM_MISC0, DBG0_SEL, 0, 2)
6800REG32(L2_TM_HSRX_ST0, 0x9c64)
6801    FIELD(L2_TM_HSRX_ST0, TM_HSRX_ST0_31_8_RSVD, 24, 8)
6802    FIELD(L2_TM_HSRX_ST0, FAST_LOCK_STATUS, 0, 1)
6803REG32(L2_TM_PLL_LS_CLOCK, 0xa000)
6804    FIELD(L2_TM_PLL_LS_CLOCK, TM_PLL_LS_CLOCK_31_8_RSVD, 24, 8)
6805    FIELD(L2_TM_PLL_LS_CLOCK, TM_PLL_LS_CLOCK, 0, 8)
6806REG32(L2_TM_PLL_LOOP_FILT, 0xa004)
6807    FIELD(L2_TM_PLL_LOOP_FILT, TM_PLL_LOOP_FILT_31_8_RSVD, 24, 8)
6808    FIELD(L2_TM_PLL_LOOP_FILT, TM_FORCE_RES_SW_ON, 7, 1)
6809    FIELD(L2_TM_PLL_LOOP_FILT, TM_MPHY_USB3_R2_HIGH_RES_SW_ON, 6, 1)
6810    FIELD(L2_TM_PLL_LOOP_FILT, TM_MPHY_USB3_R2_LOW_RES_SW_ON, 5, 1)
6811    FIELD(L2_TM_PLL_LOOP_FILT, TM_PCIE_R1_DEFAULT_RES_SW_ON, 4, 1)
6812    FIELD(L2_TM_PLL_LOOP_FILT, TM_PCIE_R1_HIGH_RES_SW_ON, 3, 1)
6813    FIELD(L2_TM_PLL_LOOP_FILT, TM_PCIE_R1_LOW_RES_SW_ON, 2, 1)
6814    FIELD(L2_TM_PLL_LOOP_FILT, TM_BYPASS_SEC_LOOP_FILTER, 1, 1)
6815    FIELD(L2_TM_PLL_LOOP_FILT, TM_SEC_LOOP, 0, 1)
6816REG32(L2_TM_PLL_DIG2, 0xa008)
6817    FIELD(L2_TM_PLL_DIG2, TM_PLL_DIG2_31_8_RSVD, 24, 8)
6818    FIELD(L2_TM_PLL_DIG2, TM_FBDIV_0_LSB, 7, 1)
6819    FIELD(L2_TM_PLL_DIG2, TM_PLL_HS_CLOCK_0, 0, 7)
6820REG32(L2_TM_PLL_FBDIV, 0xa00c)
6821    FIELD(L2_TM_PLL_FBDIV, TM_PLL_FBDIV_31_8_RSVD, 24, 8)
6822    FIELD(L2_TM_PLL_FBDIV, TM_FBDIV_1, 0, 8)
6823REG32(L2_TM_PLL_DIG4, 0xa010)
6824    FIELD(L2_TM_PLL_DIG4, TM_PLL_DIG4_31_8_RSVD, 24, 8)
6825    FIELD(L2_TM_PLL_DIG4, TM_VCO_CLOCK_PULDN, 7, 1)
6826    FIELD(L2_TM_PLL_DIG4, TM_FORCE_ANA_COARSEDONE, 6, 1)
6827    FIELD(L2_TM_PLL_DIG4, TM_ANA_COARSEDONE, 5, 1)
6828    FIELD(L2_TM_PLL_DIG4, TM_FORCE_COARSE_DONE_INT, 4, 1)
6829    FIELD(L2_TM_PLL_DIG4, TM_COARSE_DONE_INT, 3, 1)
6830    FIELD(L2_TM_PLL_DIG4, TM_FORCE_FBDIV, 2, 1)
6831    FIELD(L2_TM_PLL_DIG4, TM_FBDIV_2, 0, 2)
6832REG32(L2_TM_PLL_DIG5, 0xa014)
6833    FIELD(L2_TM_PLL_DIG5, TM_PLL_DIG5_31_8_RSVD, 24, 8)
6834    FIELD(L2_TM_PLL_DIG5, TM_PD_6GHZ_LOWNOISE_RING, 7, 1)
6835    FIELD(L2_TM_PLL_DIG5, TM_PD_6GHZ_RING, 6, 1)
6836    FIELD(L2_TM_PLL_DIG5, TM_COARSE_PROG, 1, 5)
6837    FIELD(L2_TM_PLL_DIG5, TM_FORCE_VCO_CLOCK_PULDN, 0, 1)
6838REG32(L2_TM_PLL_DIG6, 0xa018)
6839    FIELD(L2_TM_PLL_DIG6, TM_PLL_DIG6_31_8_RSVD, 24, 8)
6840    FIELD(L2_TM_PLL_DIG6, TM_CONFG_CHNG_CYCLES_0_LSB, 7, 1)
6841    FIELD(L2_TM_PLL_DIG6, TM_VCO_SETTLE_CYCLES, 5, 2)
6842    FIELD(L2_TM_PLL_DIG6, TM_INITIAL_WAIT_CYCLES, 3, 2)
6843    FIELD(L2_TM_PLL_DIG6, TM_FORCE_COARSE_PROG_PD_RING, 2, 1)
6844    FIELD(L2_TM_PLL_DIG6, TM_PD_1P5GHZ_RING, 1, 1)
6845    FIELD(L2_TM_PLL_DIG6, TM_PD_3GHZ_RING, 0, 1)
6846REG32(L2_TM_PLL_DIG7, 0xa01c)
6847    FIELD(L2_TM_PLL_DIG7, TM_PLL_DIG7_31_8_RSVD, 24, 8)
6848    FIELD(L2_TM_PLL_DIG7, TM_CPUMP_CODE_0_LSB, 7, 1)
6849    FIELD(L2_TM_PLL_DIG7, TM_FORCE_ANA_START_LOOP, 6, 1)
6850    FIELD(L2_TM_PLL_DIG7, TM_ANA_START_LOOP, 5, 1)
6851    FIELD(L2_TM_PLL_DIG7, TM_PLL_LOCK_CYCLES, 3, 2)
6852    FIELD(L2_TM_PLL_DIG7, TM_STAND_BY_SETTLE_CYCLES, 1, 2)
6853    FIELD(L2_TM_PLL_DIG7, TM_CONFG_CHNG_CYCLES_1_MSB, 0, 1)
6854REG32(L2_TM_PLL_CPUMP_CODE_1, 0xa020)
6855    FIELD(L2_TM_PLL_CPUMP_CODE_1, TM_PLL_CPUMP_CODE_1_31_8_RSVD, 24, 8)
6856    FIELD(L2_TM_PLL_CPUMP_CODE_1, TM_CPUMP_CODE_1, 0, 8)
6857REG32(L2_TM_PLL_DIG9, 0xa024)
6858    FIELD(L2_TM_PLL_DIG9, TM_PLL_DIG9_31_8_RSVD, 24, 8)
6859    FIELD(L2_TM_PLL_DIG9, TM_PLL_RSVD, 6, 2)
6860    FIELD(L2_TM_PLL_DIG9, TM_FB_BY2_BYPASS, 5, 1)
6861    FIELD(L2_TM_PLL_DIG9, TM_FORCE_CP_CODE, 4, 1)
6862    FIELD(L2_TM_PLL_DIG9, TM_CPUMP_CODE_2_MSB, 0, 4)
6863REG32(L2_TM_PLL_COARSE_CODE_LSB, 0xa028)
6864    FIELD(L2_TM_PLL_COARSE_CODE_LSB, TM_PLL_COARSE_CODE_LSB_31_8_RSVD, 24, 8)
6865    FIELD(L2_TM_PLL_COARSE_CODE_LSB, TM_COARSE_CODE_LSB, 0, 8)
6866REG32(L2_TM_PLL_DIG11, 0xa02c)
6867    FIELD(L2_TM_PLL_DIG11, TM_PLL_DIG11_31_8_RSVD, 24, 8)
6868    FIELD(L2_TM_PLL_DIG11, TM_CONST_NDAC_CNTRL, 4, 4)
6869    FIELD(L2_TM_PLL_DIG11, TM_FORCE_COARSE_CODE, 3, 1)
6870    FIELD(L2_TM_PLL_DIG11, TM_COARSE_CODE_MSB, 0, 3)
6871REG32(L2_TM_PLL_DIG12, 0xa030)
6872    FIELD(L2_TM_PLL_DIG12, TM_PLL_DIG12_31_8_RSVD, 24, 8)
6873    FIELD(L2_TM_PLL_DIG12, TM_FORCE_PTAT_NDAC_CNTRL, 7, 1)
6874    FIELD(L2_TM_PLL_DIG12, TM_PTAT_NDAC_CNTRL, 1, 6)
6875    FIELD(L2_TM_PLL_DIG12, TM_FORCE_CONST_NDAC_CNTRL, 0, 1)
6876REG32(L2_TM_PLL_CONST_PMOS, 0xa034)
6877    FIELD(L2_TM_PLL_CONST_PMOS, TM_PLL_CONST_PMOS_31_8_RSVD, 24, 8)
6878    FIELD(L2_TM_PLL_CONST_PMOS, TM_CONST_PMOS_CNTRL, 0, 8)
6879REG32(L2_TM_PLL_DIG14, 0xa038)
6880    FIELD(L2_TM_PLL_DIG14, TM_PLL_DIG14_31_8_RSVD, 24, 8)
6881    FIELD(L2_TM_PLL_DIG14, TM_COARSE_CODE_AFTER_V2I_0_LSB, 1, 7)
6882    FIELD(L2_TM_PLL_DIG14, TM_FORCE_CONST_PMOS_CNTRL, 0, 1)
6883REG32(L2_TM_PLL_DIG15, 0xa03c)
6884    FIELD(L2_TM_PLL_DIG15, TM_PLL_DIG15_31_8_RSVD, 24, 8)
6885    FIELD(L2_TM_PLL_DIG15, TM_V2I_CODE_0_LSB, 5, 3)
6886    FIELD(L2_TM_PLL_DIG15, TM_FORCE_COARSE_CODE_AFTER_V2I, 4, 1)
6887    FIELD(L2_TM_PLL_DIG15, TM_COARSE_CODE_AFTER_V2I_1_MSB, 0, 4)
6888REG32(L2_TM_PLL_DIG16, 0xa040)
6889    FIELD(L2_TM_PLL_DIG16, TM_PLL_DIG16_31_8_RSVD, 24, 8)
6890    FIELD(L2_TM_PLL_DIG16, TM_FORCE_PLL_LOCK, 7, 1)
6891    FIELD(L2_TM_PLL_DIG16, TM_PLL_LOCK, 6, 1)
6892    FIELD(L2_TM_PLL_DIG16, TM_FORCE_SS_NO_STEPS_STEP_SIZE, 5, 1)
6893    FIELD(L2_TM_PLL_DIG16, TM_PLL_RSVD, 4, 1)
6894    FIELD(L2_TM_PLL_DIG16, TM_FORCE_V2I_CODE, 3, 1)
6895    FIELD(L2_TM_PLL_DIG16, TM_V2I_CODE_1_MSB, 0, 3)
6896REG32(L2_TM_PLL_DIG17, 0xa044)
6897    FIELD(L2_TM_PLL_DIG17, TM_PLL_DIG17_31_8_RSVD, 24, 8)
6898    FIELD(L2_TM_PLL_DIG17, TM_FB_CLK, 6, 2)
6899    FIELD(L2_TM_PLL_DIG17, TM_MODE_DEPTH, 3, 3)
6900    FIELD(L2_TM_PLL_DIG17, TM_MODE_RATE, 0, 3)
6901REG32(L2_TM_PLL_DIG18, 0xa048)
6902    FIELD(L2_TM_PLL_DIG18, TM_PLL_DIG18_31_8_RSVD, 24, 8)
6903    FIELD(L2_TM_PLL_DIG18, TM_PLL_LOCK_PULDN, 7, 1)
6904    FIELD(L2_TM_PLL_DIG18, TM_STEP_SIZE_CNTRL, 5, 2)
6905    FIELD(L2_TM_PLL_DIG18, TM_SD_GSHIFT, 3, 2)
6906    FIELD(L2_TM_PLL_DIG18, TM_SD_DITHER, 1, 2)
6907    FIELD(L2_TM_PLL_DIG18, TM_PLL_LOCK_INT, 0, 1)
6908REG32(L2_TM_PLL_DIG19, 0xa04c)
6909    FIELD(L2_TM_PLL_DIG19, TM_PLL_DIG19_31_8_RSVD, 24, 8)
6910    FIELD(L2_TM_PLL_DIG19, TM_FORCE_EN_CLOCK_HS_DIV_2, 7, 1)
6911    FIELD(L2_TM_PLL_DIG19, TM_EN_CLOCK_HS_DIV_2, 6, 1)
6912    FIELD(L2_TM_PLL_DIG19, TM_PLL_HS_CLOCK_1, 3, 3)
6913    FIELD(L2_TM_PLL_DIG19, TM_PD_PFD, 2, 1)
6914    FIELD(L2_TM_PLL_DIG19, TM_FORCE_PD_PFD, 1, 1)
6915    FIELD(L2_TM_PLL_DIG19, TM_SELECT_PCI_2P5, 0, 1)
6916REG32(L2_TM_PLL_DIG20, 0xa050)
6917    FIELD(L2_TM_PLL_DIG20, TM_PLL_DIG20_31_8_RSVD, 24, 8)
6918    FIELD(L2_TM_PLL_DIG20, TM_PLL_HALF_FULL_RATE, 7, 1)
6919    FIELD(L2_TM_PLL_DIG20, TM_PLL_RSVD, 6, 1)
6920    FIELD(L2_TM_PLL_DIG20, TM_V2I_PROG, 1, 5)
6921    FIELD(L2_TM_PLL_DIG20, TM_FORCE_V2I_PROG, 0, 1)
6922REG32(L2_TM_PLL_DIG21, 0xa054)
6923    FIELD(L2_TM_PLL_DIG21, TM_PLL_DIG21_31_8_RSVD, 24, 8)
6924    FIELD(L2_TM_PLL_DIG21, TM_FORCE_EN_PLL_LDO_0P9_REF, 7, 1)
6925    FIELD(L2_TM_PLL_DIG21, ANA_TM_EN_PLL_0P9_FORCE_SW, 6, 1)
6926    FIELD(L2_TM_PLL_DIG21, TM_PLL_PD_OPDIV_SYM, 5, 1)
6927    FIELD(L2_TM_PLL_DIG21, TM_FORCE_PLL_PD_OPDIV_SYM, 4, 1)
6928    FIELD(L2_TM_PLL_DIG21, TM_PLL_RSVD_1, 3, 1)
6929    FIELD(L2_TM_PLL_DIG21, TM_PLL_RSVD_2, 2, 1)
6930    FIELD(L2_TM_PLL_DIG21, TM_PLL_EN, 1, 1)
6931    FIELD(L2_TM_PLL_DIG21, TM_FORCE_PLL_EN, 0, 1)
6932REG32(L2_TM_PLL_DIG22, 0xa058)
6933    FIELD(L2_TM_PLL_DIG22, TM_PLL_DIG22_31_8_RSVD, 24, 8)
6934    FIELD(L2_TM_PLL_DIG22, TM_PLL_RSVD, 7, 1)
6935    FIELD(L2_TM_PLL_DIG22, TM_EN_PLL_LDO_0P9_REF_CP, 6, 1)
6936    FIELD(L2_TM_PLL_DIG22, TM_FORCE_EN_PLL_LDO_0P9_REF_CP, 5, 1)
6937    FIELD(L2_TM_PLL_DIG22, TM_FORCE_COARSE_START, 4, 1)
6938    FIELD(L2_TM_PLL_DIG22, TM_FORCE_PD_PLL_LDO_1P4, 3, 1)
6939    FIELD(L2_TM_PLL_DIG22, TM_FORCE_ANA_EN_LL_DELAYED, 2, 1)
6940    FIELD(L2_TM_PLL_DIG22, TM_FORCE_ANA_EN_LL, 1, 1)
6941    FIELD(L2_TM_PLL_DIG22, TM_EN_PLL_LDO_0P9_REF, 0, 1)
6942REG32(L2_TM_PLL_DIG23, 0xa05c)
6943    FIELD(L2_TM_PLL_DIG23, TM_PLL_DIG23_31_8_RSVD, 24, 8)
6944    FIELD(L2_TM_PLL_DIG23, BF_7, 7, 1)
6945    FIELD(L2_TM_PLL_DIG23, PLL_TM_VCO_LDO_BYPASS, 6, 1)
6946    FIELD(L2_TM_PLL_DIG23, TM_ANA_EN_LL_DELAYED, 5, 1)
6947    FIELD(L2_TM_PLL_DIG23, TM_ANA_EN_LL, 4, 1)
6948    FIELD(L2_TM_PLL_DIG23, TM_ANA_PD_PLL, 3, 1)
6949    FIELD(L2_TM_PLL_DIG23, TM_FORCE_PLL_PD, 2, 1)
6950    FIELD(L2_TM_PLL_DIG23, TM_ANA_COARSE_START, 1, 1)
6951    FIELD(L2_TM_PLL_DIG23, TM_PD_PLL_LDO_1P4, 0, 1)
6952REG32(L2_TM_PLL_DIG24, 0xa060)
6953    FIELD(L2_TM_PLL_DIG24, TM_PLL_DIG24_31_8_RSVD, 24, 8)
6954    FIELD(L2_TM_PLL_DIG24, TM_PLL_RSVD, 7, 1)
6955    FIELD(L2_TM_PLL_DIG24, PLL_TM_VCO_LDO, 1, 6)
6956    FIELD(L2_TM_PLL_DIG24, PLL_TM_VCO_LDO_BYPASS_WITH_SEQUENCE, 0, 1)
6957REG32(L2_TM_PLL_DIG25, 0xa064)
6958    FIELD(L2_TM_PLL_DIG25, TM_PLL_DIG25_31_8_RSVD, 24, 8)
6959    FIELD(L2_TM_PLL_DIG25, TM_FORCE_RST_N_HSRIPPLE, 7, 1)
6960    FIELD(L2_TM_PLL_DIG25, TM_RST_N_HSRIPPLE, 6, 1)
6961    FIELD(L2_TM_PLL_DIG25, TM_PLL_ATB_CNTRL, 1, 5)
6962    FIELD(L2_TM_PLL_DIG25, TM_PLL_OBSERVE_PTAT_10U, 0, 1)
6963REG32(L2_TM_PLL_DIG26, 0xa068)
6964    FIELD(L2_TM_PLL_DIG26, TM_PLL_DIG26_31_8_RSVD, 24, 8)
6965    FIELD(L2_TM_PLL_DIG26, TM_PLL_RSVD, 7, 1)
6966    FIELD(L2_TM_PLL_DIG26, TM_PD_PLL_PTAT, 6, 1)
6967    FIELD(L2_TM_PLL_DIG26, TM_FORCE_PD_PLL_PTAT, 5, 1)
6968    FIELD(L2_TM_PLL_DIG26, TM_USB3_R2_HIGH_RES_SW_ON, 4, 1)
6969    FIELD(L2_TM_PLL_DIG26, TM_PLL_SEL_VCO_DIV2_LOOP_OUT, 3, 1)
6970    FIELD(L2_TM_PLL_DIG26, TM_PLL_SEL_VCO_DIRECT_LOOP_OUT, 2, 1)
6971    FIELD(L2_TM_PLL_DIG26, TM_PLL_SEL_VCO_HISPEED_DIV2_LOOP_OUT, 1, 1)
6972    FIELD(L2_TM_PLL_DIG26, TM_FORCE_LOOP_PATH, 0, 1)
6973REG32(L2_TM_PLL_CLK_DIST_NTRIM_LSB, 0xa06c)
6974    FIELD(L2_TM_PLL_CLK_DIST_NTRIM_LSB, TM_PLL_CLK_DIST_NTRIM_LSB_31_8_RSVD, 24, 8)
6975    FIELD(L2_TM_PLL_CLK_DIST_NTRIM_LSB, TM_CLKDIST_BIAS_NTRIM_LSB, 0, 8)
6976REG32(L2_TM_PLL_CLK_DIST_PTRIM_LSB, 0xa070)
6977    FIELD(L2_TM_PLL_CLK_DIST_PTRIM_LSB, TM_PLL_CLK_DIST_PTRIM_LSB_31_8_RSVD, 24, 8)
6978    FIELD(L2_TM_PLL_CLK_DIST_PTRIM_LSB, TM_CLKDIST_BIAS_PTRIM_LSB, 0, 8)
6979REG32(L2_TM_PLL_DIG_29, 0xa074)
6980    FIELD(L2_TM_PLL_DIG_29, TM_PLL_DIG_29_31_8_RSVD, 24, 8)
6981    FIELD(L2_TM_PLL_DIG_29, TM_CLKDIST_OBSRV_MRSTBUF_SUP, 7, 1)
6982    FIELD(L2_TM_PLL_DIG_29, TM_CLKDIST_OBSRV_LRSTBUF_SUP, 6, 1)
6983    FIELD(L2_TM_PLL_DIG_29, TM_CLKDIST_ENABLE_RST_RPTR, 5, 1)
6984    FIELD(L2_TM_PLL_DIG_29, TM_FORCE_CLKDIST_ENABLE_RST_RPTR, 4, 1)
6985    FIELD(L2_TM_PLL_DIG_29, TM_CLKDIST_ENABLE_CLK_RPTR, 3, 1)
6986    FIELD(L2_TM_PLL_DIG_29, TM_FORCE_CLKDIST_ENABLE_CLK_RPTR, 2, 1)
6987    FIELD(L2_TM_PLL_DIG_29, TM_CLKDIST_BIAS_PTRIM_MSB, 1, 1)
6988    FIELD(L2_TM_PLL_DIG_29, TM_CLKDIST_BIAS_NTRIM_MSB, 0, 1)
6989REG32(L2_TM_PLL_DIG_30, 0xa078)
6990    FIELD(L2_TM_PLL_DIG_30, TM_PLL_DIG_30_31_8_RSVD, 24, 8)
6991    FIELD(L2_TM_PLL_DIG_30, TM_CLKDIST_ENABLE_BIAS, 7, 1)
6992    FIELD(L2_TM_PLL_DIG_30, TM_FORCE_CLKDIST_ENABLE_BIAS, 6, 1)
6993    FIELD(L2_TM_PLL_DIG_30, TM_CLKDIST_ENABLE_CMN_BIAS, 5, 1)
6994    FIELD(L2_TM_PLL_DIG_30, TM_FORCE_CLKDIST_ENABLE_CMN_BIAS, 4, 1)
6995    FIELD(L2_TM_PLL_DIG_30, TM_CLKDIST_SUP_OBSRV, 3, 1)
6996    FIELD(L2_TM_PLL_DIG_30, TM_CLKDIST_OBSRV_RSTMUX_SUP, 2, 1)
6997    FIELD(L2_TM_PLL_DIG_30, TM_CLKDIST_OBSRV_RPTR_RSTBUF_SUP, 1, 1)
6998    FIELD(L2_TM_PLL_DIG_30, TM_CLKDIST_OBSRV_MUS_SUP, 0, 1)
6999REG32(L2_TM_PLL_DIG_31, 0xa07c)
7000    FIELD(L2_TM_PLL_DIG_31, TM_PLL_DIG_31_31_8_RSVD, 24, 8)

7001    FIELD(L2_TM_PLL_DIG_31, TM_CLKDIST_ENABLE_MASTER_CLK_DRIVE, 7, 1)
7002    FIELD(L2_TM_PLL_DIG_31, TM_FORCE_CLKDIST_ENABLE_MASTER_CLK_DRIVE, 6, 1)
7003    FIELD(L2_TM_PLL_DIG_31, TM_CLKDIST_ENABLE_LANE_RST_DRIVE, 5, 1)
7004    FIELD(L2_TM_PLL_DIG_31, TM_FORCE_CLKDIST_ENABLE_LANE_RST_DRIVE, 4, 1)
7005    FIELD(L2_TM_PLL_DIG_31, TM_CLKDIST_ENABLE_LANE_CLK_DRIVE, 3, 1)
7006    FIELD(L2_TM_PLL_DIG_31, TM_FORCE_CLKDIST_ENABLE_LANE_CLK_DRIVE, 2, 1)
7007    FIELD(L2_TM_PLL_DIG_31, TM_CLKDIST_BIAS_RATE_SEL, 1, 1)
7008    FIELD(L2_TM_PLL_DIG_31, TM_FORCE_CLKDIST_BIAS_RATE_SEL, 0, 1)
7009REG32(L2_TM_PLL_DIG_32, 0xa080)
7010    FIELD(L2_TM_PLL_DIG_32, TM_PLL_DIG_32_31_8_RSVD, 24, 8)
7011    FIELD(L2_TM_PLL_DIG_32, TM_CLKDIST_MUX_XVCR_CLK_EN, 7, 1)
7012    FIELD(L2_TM_PLL_DIG_32, TM_FORCE_CLKDIST_MUX_XVCR_CLK_EN, 6, 1)
7013    FIELD(L2_TM_PLL_DIG_32, TM_FORCE_LOAD_FBDIV, 5, 1)
7014    FIELD(L2_TM_PLL_DIG_32, TM_LOAD_FBDIV, 4, 1)
7015    FIELD(L2_TM_PLL_DIG_32, TM_FORCE_RST_FDBK_DIV, 3, 1)
7016    FIELD(L2_TM_PLL_DIG_32, TM_RST_FDBK_DIV, 2, 1)
7017    FIELD(L2_TM_PLL_DIG_32, TM_CLKDIST_ENABLE_MASTER_RST_DRIVE, 1, 1)
7018    FIELD(L2_TM_PLL_DIG_32, TM_FORCE_CLKDIST_ENABLE_MASTER_RST_DRIVE, 0, 1)
7019REG32(L2_TM_PLL_DIG_33, 0xa084)
7020    FIELD(L2_TM_PLL_DIG_33, TM_PLL_DIG_33_31_8_RSVD, 24, 8)
7021    FIELD(L2_TM_PLL_DIG_33, TM_FORCE_TX_CLK_RST_REL, 7, 1)
7022    FIELD(L2_TM_PLL_DIG_33, TM_TX_CLK_RST_REL, 6, 1)
7023    FIELD(L2_TM_PLL_DIG_33, TM_CLKDIST_MUX_XCVR_MASTER_RST_EN, 5, 1)
7024    FIELD(L2_TM_PLL_DIG_33, TM_FORCE_CLKDIST_MUX_XCVR_MASTER_RST_EN, 4, 1)
7025    FIELD(L2_TM_PLL_DIG_33, TM_CLKDIST_MUX_MASTER_CLK_SEL, 3, 1)
7026    FIELD(L2_TM_PLL_DIG_33, TM_FORCE_CLKDIST_MUX_MASTER_CLK_SEL, 2, 1)
7027    FIELD(L2_TM_PLL_DIG_33, TM_CLKDIST_MUX_LOCAL_CLK_SEL, 1, 1)
7028    FIELD(L2_TM_PLL_DIG_33, TM_FORCE_CLKDIST_MUX_LOCAL_CLK_SEL, 0, 1)
7029REG32(L2_TM_PLL_DIG_34, 0xa088)
7030    FIELD(L2_TM_PLL_DIG_34, TM_PLL_DIG_34_31_8_RSVD, 24, 8)
7031    FIELD(L2_TM_PLL_DIG_34, TM_PLL_RSVD, 7, 1)
7032    FIELD(L2_TM_PLL_DIG_34, TM_FBDIV_3_MSB, 2, 5)
7033    FIELD(L2_TM_PLL_DIG_34, TM_SEL_VCO_OUT, 1, 1)
7034    FIELD(L2_TM_PLL_DIG_34, TM_FORCE_SEL_VCO_OUT, 0, 1)
7035REG32(L2_TM_PLL_DIG_35, 0xa08c)
7036    FIELD(L2_TM_PLL_DIG_35, TM_PLL_DIG_35_31_8_RSVD, 24, 8)
7037    FIELD(L2_TM_PLL_DIG_35, TM_CLKDIST_BIAS_SPARE, 6, 2)
7038    FIELD(L2_TM_PLL_DIG_35, TM_CLKDIST_DRVR_SPARE, 4, 2)
7039    FIELD(L2_TM_PLL_DIG_35, TM_CLKDIST_MUX_SPARE, 2, 2)
7040    FIELD(L2_TM_PLL_DIG_35, TM_CLKDIST_RPTR_SPARE, 0, 2)
7041REG32(L2_TM_PLL_DIG_36, 0xa090)
7042    FIELD(L2_TM_PLL_DIG_36, TM_PLL_DIG_36_31_8_RSVD, 24, 8)
7043    FIELD(L2_TM_PLL_DIG_36, CLKDIST_BIAS_SPARE, 6, 2)
7044    FIELD(L2_TM_PLL_DIG_36, CLKDIST_DRVR_SPARE, 4, 2)
7045    FIELD(L2_TM_PLL_DIG_36, CLKDIST_MUX_SPARE, 2, 2)
7046    FIELD(L2_TM_PLL_DIG_36, CLKDIST_RPTR_SPARE, 0, 2)
7047REG32(L2_TM_PLL_DIG_37, 0xa094)
7048    FIELD(L2_TM_PLL_DIG_37, TM_PLL_DIG_37_31_8_RSVD, 24, 8)
7049    FIELD(L2_TM_PLL_DIG_37, TM_COARSE_CODE_SAT_VALUE_LSB, 5, 3)
7050    FIELD(L2_TM_PLL_DIG_37, TM_ENABLE_COARSE_SATURATION, 4, 1)
7051    FIELD(L2_TM_PLL_DIG_37, W_SPARE_OUTPUTS, 2, 2)
7052    FIELD(L2_TM_PLL_DIG_37, TM_FORCE_EN_IP_DIV_BYPASS, 1, 1)
7053    FIELD(L2_TM_PLL_DIG_37, TM_EN_IP_DIV_BYPASS, 0, 1)
7054REG32(L2_TM_PLL_COARSE_CODE_SAT_MSB, 0xa098)
7055    FIELD(L2_TM_PLL_COARSE_CODE_SAT_MSB, TM_PLL_COARSE_CODE_SAT_MSB_31_8_RSVD, 24, 8)
7056    FIELD(L2_TM_PLL_COARSE_CODE_SAT_MSB, TM_COARSE_CODE_SAT_VALUE_MSB, 0, 8)
7057REG32(L2_MPHY_CFG_HIB8, 0xa300)
7058    FIELD(L2_MPHY_CFG_HIB8, MPHY_CFG_HIB8_31_8_RSVD, 24, 8)
7059    FIELD(L2_MPHY_CFG_HIB8, MPHY_HIBERN8_RSVD, 1, 7)
7060    FIELD(L2_MPHY_CFG_HIB8, MPHY_HIBERN8, 0, 1)
7061REG32(L2_MPHY_CFG_MODE, 0xa304)
7062    FIELD(L2_MPHY_CFG_MODE, MPHY_CFG_MODE_31_8_RSVD, 24, 8)
7063    FIELD(L2_MPHY_CFG_MODE, MPHY_HS_LS_MODE_RSVD, 2, 6)
7064    FIELD(L2_MPHY_CFG_MODE, MPHY_HS_LS_MODE, 0, 2)
7065REG32(L2_MPHY_CFG_HS_GEAR, 0xa308)
7066    FIELD(L2_MPHY_CFG_HS_GEAR, MPHY_CFG_HS_GEAR_31_8_RSVD, 24, 8)
7067    FIELD(L2_MPHY_CFG_HS_GEAR, MPHY_HS_GEAR_RSVD, 2, 6)
7068    FIELD(L2_MPHY_CFG_HS_GEAR, MPHY_HS_GEAR, 0, 2)
7069REG32(L2_MPHY_CFG_HS_RATE, 0xa30c)
7070    FIELD(L2_MPHY_CFG_HS_RATE, MPHY_CFG_HS_RATE_31_8_RSVD, 24, 8)
7071    FIELD(L2_MPHY_CFG_HS_RATE, MPHY_RATE_RSVD, 1, 7)
7072    FIELD(L2_MPHY_CFG_HS_RATE, MPHY_RATE, 0, 1)
7073REG32(L2_MPHY_CFG_PWM, 0xa310)
7074    FIELD(L2_MPHY_CFG_PWM, MPHY_CFG_PWM_31_8_RSVD, 24, 8)
7075    FIELD(L2_MPHY_CFG_PWM, MPHY_PWM_GEAR_RSVD, 3, 5)
7076    FIELD(L2_MPHY_CFG_PWM, MPHY_PWM_GEAR, 0, 3)
7077REG32(L2_PLL_OPDIV_LS, 0xa314)
7078    FIELD(L2_PLL_OPDIV_LS, PLL_OPDIV_LS_31_8_RSVD, 24, 8)
7079    FIELD(L2_PLL_OPDIV_LS, TM_SEL_OPDIV_FOR_REFCLK, 7, 1)
7080    FIELD(L2_PLL_OPDIV_LS, ANA_OPDIV_LS, 0, 7)
7081REG32(L2_MPHY_CFG_UPDT, 0xa318)
7082    FIELD(L2_MPHY_CFG_UPDT, MPHY_CFG_UPDT_31_8_RSVD, 24, 8)
7083    FIELD(L2_MPHY_CFG_UPDT, MPHY_CFGUPDT_RSVD, 1, 7)
7084    FIELD(L2_MPHY_CFG_UPDT, MPHY_CFGUPDT, 0, 1)
7085REG32(L2_PLL_TM_DIV_CNTRLS, 0xa31c)
7086    FIELD(L2_PLL_TM_DIV_CNTRLS, PLL_TM_DIV_CNTRLS_31_8_RSVD, 24, 8)
7087    FIELD(L2_PLL_TM_DIV_CNTRLS, TM_FORCE_PD_OPDIV_LS, 7, 1)
7088    FIELD(L2_PLL_TM_DIV_CNTRLS, TM_PD_OPDIV_LS, 6, 1)
7089    FIELD(L2_PLL_TM_DIV_CNTRLS, PLL_TM_DIV_CNTRLS_RSVD, 5, 1)
7090    FIELD(L2_PLL_TM_DIV_CNTRLS, TM_BYPASS_OPDIV_LS_MOD, 4, 1)
7091    FIELD(L2_PLL_TM_DIV_CNTRLS, TM_FORCE_PLL_PD_HS, 3, 1)
7092    FIELD(L2_PLL_TM_DIV_CNTRLS, TM_PLL_PD_HS, 2, 1)
7093    FIELD(L2_PLL_TM_DIV_CNTRLS, SEL_IP_MUX_CONTROL, 1, 1)
7094    FIELD(L2_PLL_TM_DIV_CNTRLS, TM_SWAP_OP_MUX_CONTROL, 0, 1)
7095REG32(L2_PLL_FBDIV_G1A_LSB, 0xa320)
7096    FIELD(L2_PLL_FBDIV_G1A_LSB, PLL_FBDIV_G1A_LSB_31_8_RSVD, 24, 8)
7097    FIELD(L2_PLL_FBDIV_G1A_LSB, FBDIV_G1A_LSB, 0, 8)
7098REG32(L2_PLL_FBDIV_G1B_LSB, 0xa324)
7099    FIELD(L2_PLL_FBDIV_G1B_LSB, PLL_FBDIV_G1B_LSB_31_8_RSVD, 24, 8)
7100    FIELD(L2_PLL_FBDIV_G1B_LSB, FBDIV_G1B_LSB, 0, 8)
7101REG32(L2_PLL_FBDIV_G2A_LSB, 0xa328)
7102    FIELD(L2_PLL_FBDIV_G2A_LSB, PLL_FBDIV_G2A_LSB_31_8_RSVD, 24, 8)
7103    FIELD(L2_PLL_FBDIV_G2A_LSB, FBDIV_G2A_LSB, 0, 8)
7104REG32(L2_PLL_FBDIV_G2B_LSB, 0xa32c)
7105    FIELD(L2_PLL_FBDIV_G2B_LSB, PLL_FBDIV_G2B_LSB_31_8_RSVD, 24, 8)
7106    FIELD(L2_PLL_FBDIV_G2B_LSB, FBDIV_G2B_LSB, 0, 8)
7107REG32(L2_PLL_FBDIV_G3A_LSB, 0xa330)
7108    FIELD(L2_PLL_FBDIV_G3A_LSB, PLL_FBDIV_G3A_LSB_31_8_RSVD, 24, 8)
7109    FIELD(L2_PLL_FBDIV_G3A_LSB, FBDIV_G3A_LSB, 0, 8)
7110REG32(L2_PLL_FBDIV_G3B_LSB, 0xa334)
7111    FIELD(L2_PLL_FBDIV_G3B_LSB, PLL_FBDIV_G3B_LSB_31_8_RSVD, 24, 8)
7112    FIELD(L2_PLL_FBDIV_G3B_LSB, FBDIV_G3B_LSB, 0, 8)
7113REG32(L2_PLL_FBDIV_G1A_MSB, 0xa338)
7114    FIELD(L2_PLL_FBDIV_G1A_MSB, PLL_FBDIV_G1A_MSB_31_8_RSVD, 24, 8)
7115    FIELD(L2_PLL_FBDIV_G1A_MSB, FBDIV_G1A_MSB, 0, 8)
7116REG32(L2_PLL_FBDIV_G1B_MSB, 0xa33c)
7117    FIELD(L2_PLL_FBDIV_G1B_MSB, PLL_FBDIV_G1B_MSB_31_8_RSVD, 24, 8)
7118    FIELD(L2_PLL_FBDIV_G1B_MSB, FBDIV_G1B_MSB, 0, 8)
7119REG32(L2_PLL_FBDIV_G2A_MSB, 0xa340)
7120    FIELD(L2_PLL_FBDIV_G2A_MSB, PLL_FBDIV_G2A_MSB_31_8_RSVD, 24, 8)
7121    FIELD(L2_PLL_FBDIV_G2A_MSB, FBDIV_G2A_MSB, 0, 8)
7122REG32(L2_PLL_FBDIV_G2B_MSB, 0xa344)
7123    FIELD(L2_PLL_FBDIV_G2B_MSB, PLL_FBDIV_G2B_MSB_31_8_RSVD, 24, 8)
7124    FIELD(L2_PLL_FBDIV_G2B_MSB, FBDIV_G2B_MSB, 0, 8)
7125REG32(L2_PLL_FBDIV_G3A_MSB, 0xa348)
7126    FIELD(L2_PLL_FBDIV_G3A_MSB, PLL_FBDIV_G3A_MSB_31_8_RSVD, 24, 8)
7127    FIELD(L2_PLL_FBDIV_G3A_MSB, FBDIV_G3A_MSB, 0, 8)
7128REG32(L2_PLL_FBDIV_G3B_MSB, 0xa34c)
7129    FIELD(L2_PLL_FBDIV_G3B_MSB, PLL_FBDIV_G3B_MSB_31_8_RSVD, 24, 8)
7130    FIELD(L2_PLL_FBDIV_G3B_MSB, FBDIV_G3B_MSB, 0, 8)
7131REG32(L2_PLL_IPDIV, 0xa350)
7132    FIELD(L2_PLL_IPDIV, PLL_IPDIV_31_8_RSVD, 24, 8)
7133    FIELD(L2_PLL_IPDIV, PLL_IPDIV, 0, 8)
7134REG32(L2_PLL_FBDIV_FRAC_0_LSB, 0xa354)
7135    FIELD(L2_PLL_FBDIV_FRAC_0_LSB, PLL_FBDIV_FRAC_0_LSB_31_8_RSVD, 24, 8)
7136    FIELD(L2_PLL_FBDIV_FRAC_0_LSB, FBDIV_FRAC_0_LSB, 0, 8)
7137REG32(L2_PLL_FBDIV_FRAC_1, 0xa358)
7138    FIELD(L2_PLL_FBDIV_FRAC_1, PLL_FBDIV_FRAC_1_31_8_RSVD, 24, 8)
7139    FIELD(L2_PLL_FBDIV_FRAC_1, FBDIV_FRAC_1, 0, 8)
7140REG32(L2_PLL_FBDIV_FRAC_2, 0xa35c)
7141    FIELD(L2_PLL_FBDIV_FRAC_2, PLL_FBDIV_FRAC_2_31_8_RSVD, 24, 8)
7142    FIELD(L2_PLL_FBDIV_FRAC_2, FBDIV_FRAC_2, 0, 8)
7143REG32(L2_PLL_FBDIV_FRAC_3_MSB, 0xa360)
7144    FIELD(L2_PLL_FBDIV_FRAC_3_MSB, PLL_FBDIV_FRAC_3_MSB_31_8_RSVD, 24, 8)
7145    FIELD(L2_PLL_FBDIV_FRAC_3_MSB, PLL_FBDIV_FRAC_3_MSV_RSVD, 7, 1)
7146    FIELD(L2_PLL_FBDIV_FRAC_3_MSB, TM_FORCE_EN_FRAC, 6, 1)
7147    FIELD(L2_PLL_FBDIV_FRAC_3_MSB, TM_EN_FRAC, 5, 1)
7148    FIELD(L2_PLL_FBDIV_FRAC_3_MSB, FBDIV_FRAC_3_MSB_RSVD, 3, 2)
7149    FIELD(L2_PLL_FBDIV_FRAC_3_MSB, FBDIV_FRAC_3_MSB, 0, 3)
7150REG32(L2_PLL_PWR_SEQ_WAIT_TIME, 0xa364)
7151    FIELD(L2_PLL_PWR_SEQ_WAIT_TIME, PLL_PWR_SEQ_WAIT_TIME_31_8_RSVD, 24, 8)
7152    FIELD(L2_PLL_PWR_SEQ_WAIT_TIME, TM_PLL_SETTLING, 6, 2)
7153    FIELD(L2_PLL_PWR_SEQ_WAIT_TIME, TM_PLL_BIAS_SETTLING, 4, 2)
7154    FIELD(L2_PLL_PWR_SEQ_WAIT_TIME, TM_LDO_SETTLING, 2, 2)
7155    FIELD(L2_PLL_PWR_SEQ_WAIT_TIME, TM_LDO_RELIABILITY, 0, 2)
7156REG32(L2_PLL_SS_STEPS_0_LSB, 0xa368)
7157    FIELD(L2_PLL_SS_STEPS_0_LSB, PLL_SS_STEPS_0_LSB_31_8_RSVD, 24, 8)
7158    FIELD(L2_PLL_SS_STEPS_0_LSB, SS_NUM_OF_STEPS_0_LSB, 0, 8)
7159REG32(L2_PLL_SS_STEPS_1_MSB, 0xa36c)
7160    FIELD(L2_PLL_SS_STEPS_1_MSB, PLL_SS_STEPS_1_MSB_31_8_RSVD, 24, 8)
7161    FIELD(L2_PLL_SS_STEPS_1_MSB, SS_NUM_OF_STEPS_1_MSB_RSVD, 3, 5)
7162    FIELD(L2_PLL_SS_STEPS_1_MSB, SS_NUM_OF_STEPS_1_MSB, 0, 3)
7163REG32(L2_PLL_SS_STEP_SIZE_0_LSB, 0xa370)
7164    FIELD(L2_PLL_SS_STEP_SIZE_0_LSB, PLL_SS_STEP_SIZE_0_LSB_31_8_RSVD, 24, 8)
7165    FIELD(L2_PLL_SS_STEP_SIZE_0_LSB, SS_STEP_SIZE_0_LSB, 0, 8)
7166REG32(L2_PLL_SS_STEP_SIZE_1, 0xa374)
7167    FIELD(L2_PLL_SS_STEP_SIZE_1, PLL_SS_STEP_SIZE_1_31_8_RSVD, 24, 8)
7168    FIELD(L2_PLL_SS_STEP_SIZE_1, SS_STEP_SIZE_1, 0, 8)
7169REG32(L2_PLL_SS_STEP_SIZE_2, 0xa378)
7170    FIELD(L2_PLL_SS_STEP_SIZE_2, PLL_SS_STEP_SIZE_2_31_8_RSVD, 24, 8)
7171    FIELD(L2_PLL_SS_STEP_SIZE_2, SS_STEP_SIZE_2, 0, 8)
7172REG32(L2_PLL_SS_STEP_SIZE_3_MSB, 0xa37c)
7173    FIELD(L2_PLL_SS_STEP_SIZE_3_MSB, PLL_SS_STEP_SIZE_3_MSB_31_8_RSVD, 24, 8)
7174    FIELD(L2_PLL_SS_STEP_SIZE_3_MSB, TM_FORCE_EN_SS, 7, 1)
7175    FIELD(L2_PLL_SS_STEP_SIZE_3_MSB, TM_EN_SS, 6, 1)
7176    FIELD(L2_PLL_SS_STEP_SIZE_3_MSB, FORCE_SS_NUM_OF_STEPS, 5, 1)
7177    FIELD(L2_PLL_SS_STEP_SIZE_3_MSB, FORCE_SS_STEP_SIZE, 4, 1)
7178    FIELD(L2_PLL_SS_STEP_SIZE_3_MSB, SS_SPREAD_TYPE, 2, 2)
7179    FIELD(L2_PLL_SS_STEP_SIZE_3_MSB, SS_STEP_SIZE_3_MSB, 0, 2)
7180REG32(L2_TM_MASK_CFG_UPDT, 0xa380)
7181    FIELD(L2_TM_MASK_CFG_UPDT, TM_MASK_CFG_UPDT_31_8_RSVD, 24, 8)
7182    FIELD(L2_TM_MASK_CFG_UPDT, TM_MASK_CFG_UPDT_RSVD, 7, 1)
7183    FIELD(L2_TM_MASK_CFG_UPDT, HIBERN8_MASK_CFG_UPDT, 6, 1)
7184    FIELD(L2_TM_MASK_CFG_UPDT, HS_MODE_MASK_CFG_UPDT, 5, 1)
7185    FIELD(L2_TM_MASK_CFG_UPDT, LS_MODE_MASK_CFG_UPDT, 4, 1)
7186    FIELD(L2_TM_MASK_CFG_UPDT, OPDIV_LS_MASK_CFG_UPDT, 3, 1)
7187    FIELD(L2_TM_MASK_CFG_UPDT, PWM_GEAR_MASK_CFG_UPDT, 2, 1)
7188    FIELD(L2_TM_MASK_CFG_UPDT, HS_GEAR_MASK_CFG_UPDT, 1, 1)
7189    FIELD(L2_TM_MASK_CFG_UPDT, HS_RATE_MASK_CFG_UPDT, 0, 1)
7190REG32(L2_PLL_TM_FORCE_DIV, 0xa384)
7191    FIELD(L2_PLL_TM_FORCE_DIV, PLL_TM_FORCE_DIV_31_8_RSVD, 24, 8)
7192    FIELD(L2_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_FRAC, 7, 1)
7193    FIELD(L2_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G3B, 6, 1)
7194    FIELD(L2_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G3A, 5, 1)
7195    FIELD(L2_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G2B, 4, 1)
7196    FIELD(L2_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G2A, 3, 1)
7197    FIELD(L2_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G1B, 2, 1)
7198    FIELD(L2_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G1A, 1, 1)
7199    FIELD(L2_PLL_TM_FORCE_DIV, TM_FORCE_IPDIV, 0, 1)
7200REG32(L2_PLL_TM_COARSE_CODE_1_LSB, 0xa388)
7201    FIELD(L2_PLL_TM_COARSE_CODE_1_LSB, PLL_TM_COARSE_CODE_1_LSB_31_8_RSVD, 24, 8)
7202    FIELD(L2_PLL_TM_COARSE_CODE_1_LSB, TM_COARSE_CODE_1_LSB, 0, 8)
7203REG32(L2_PLL_TM_COARSE_CODE_2_LSB, 0xa38c)
7204    FIELD(L2_PLL_TM_COARSE_CODE_2_LSB, PLL_TM_COARSE_CODE_2_LSB_31_8_RSVD, 24, 8)
7205    FIELD(L2_PLL_TM_COARSE_CODE_2_LSB, TM_COARSE_CODE_2_LSB, 0, 8)
7206REG32(L2_PLL_TM_COARSE_CODE_3_LSB, 0xa390)
7207    FIELD(L2_PLL_TM_COARSE_CODE_3_LSB, PLL_TM_COARSE_CODE_3_LSB_31_8_RSVD, 24, 8)
7208    FIELD(L2_PLL_TM_COARSE_CODE_3_LSB, TM_COARSE_CODE_3_LSB, 0, 8)
7209REG32(L2_PLL_TM_COARSE_CODE_4_LSB, 0xa394)
7210    FIELD(L2_PLL_TM_COARSE_CODE_4_LSB, PLL_TM_COARSE_CODE_4_LSB_31_8_RSVD, 24, 8)
7211    FIELD(L2_PLL_TM_COARSE_CODE_4_LSB, TM_COARSE_CODE_4_LSB, 0, 8)
7212REG32(L2_PLL_TM_COARSE_CODE_5_LSB, 0xa398)
7213    FIELD(L2_PLL_TM_COARSE_CODE_5_LSB, PLL_TM_COARSE_CODE_5_LSB_31_8_RSVD, 24, 8)
7214    FIELD(L2_PLL_TM_COARSE_CODE_5_LSB, TM_COARSE_CODE_5_LSB, 0, 8)
7215REG32(L2_PLL_TM_COARSE_CODE_6_LSB, 0xa39c)
7216    FIELD(L2_PLL_TM_COARSE_CODE_6_LSB, PLL_TM_COARSE_CODE_6_LSB_31_8_RSVD, 24, 8)
7217    FIELD(L2_PLL_TM_COARSE_CODE_6_LSB, TM_COARSE_CODE_6_LSB, 0, 8)
7218REG32(L2_PLL_TM_COARSE_CODE_1_2_MSB, 0xa3a0)
7219    FIELD(L2_PLL_TM_COARSE_CODE_1_2_MSB, PLL_TM_COARSE_CODE_1_2_MSB_31_8_RSVD, 24, 8)
7220    FIELD(L2_PLL_TM_COARSE_CODE_1_2_MSB, TM_COARSE_CODE_G1_AB_MSB_RSVD, 6, 2)
7221    FIELD(L2_PLL_TM_COARSE_CODE_1_2_MSB, TM_COARSE_CODE_2_MSB, 3, 3)
7222    FIELD(L2_PLL_TM_COARSE_CODE_1_2_MSB, TM_COARSE_CODE_1_MSB, 0, 3)
7223REG32(L2_PLL_TM_COARSE_CODE_3_4_MSB, 0xa3a4)
7224    FIELD(L2_PLL_TM_COARSE_CODE_3_4_MSB, PLL_TM_COARSE_CODE_3_4_MSB_31_8_RSVD, 24, 8)
7225    FIELD(L2_PLL_TM_COARSE_CODE_3_4_MSB, TM_COARSE_CODE_G2_AB_MSB_RSVD, 6, 2)
7226    FIELD(L2_PLL_TM_COARSE_CODE_3_4_MSB, TM_COARSE_CODE_4_MSB, 3, 3)
7227    FIELD(L2_PLL_TM_COARSE_CODE_3_4_MSB, TM_COARSE_CODE_3_MSB, 0, 3)
7228REG32(L2_PLL_TM_COARSE_CODE_5_6_MSB, 0xa3a8)
7229    FIELD(L2_PLL_TM_COARSE_CODE_5_6_MSB, PLL_TM_COARSE_CODE_5_6_MSB_31_8_RSVD, 24, 8)
7230    FIELD(L2_PLL_TM_COARSE_CODE_5_6_MSB, TM_COARSE_CODE_G3_AB_MSB_RSVD, 6, 2)
7231    FIELD(L2_PLL_TM_COARSE_CODE_5_6_MSB, TM_COARSE_CODE_6_MSB, 3, 3)
7232    FIELD(L2_PLL_TM_COARSE_CODE_5_6_MSB, TM_COARSE_CODE_5_MSB, 0, 3)
7233REG32(L2_PLL_TM_SHARED_0, 0xa3ac)
7234    FIELD(L2_PLL_TM_SHARED_0, PLL_TM_SHARED_0_31_8_RSVD, 24, 8)
7235    FIELD(L2_PLL_TM_SHARED_0, TM_FORCE_EXTSIGNAL_FOR_HIBERN8, 7, 1)
7236    FIELD(L2_PLL_TM_SHARED_0, TM_FORCE_REGBIT_FOR_HIBERN8, 6, 1)
7237    FIELD(L2_PLL_TM_SHARED_0, TM_FORCE_PLL_STANDBY, 5, 1)
7238    FIELD(L2_PLL_TM_SHARED_0, TM_PLL_STANDBY, 4, 1)
7239    FIELD(L2_PLL_TM_SHARED_0, TM_SLOWN_FAST_BRING_UP_ALWAYS, 3, 1)
7240    FIELD(L2_PLL_TM_SHARED_0, EN_TM_FOR_BRING_UP_SCHEME, 2, 1)
7241    FIELD(L2_PLL_TM_SHARED_0, SELECT_HS_FB_DIVIDER, 1, 1)
7242    FIELD(L2_PLL_TM_SHARED_0, TM_BYPASS_COARSE_SEARCH, 0, 1)
7243REG32(L2_PLL_TM_FRAC_OFFSET_0, 0xa3b0)
7244    FIELD(L2_PLL_TM_FRAC_OFFSET_0, PLL_TM_FRAC_OFFSET_0_31_8_RSVD, 24, 8)
7245    FIELD(L2_PLL_TM_FRAC_OFFSET_0, TM_FRAC_OFFSET_LSB_0, 0, 8)
7246REG32(L2_PLL_TM_FRAC_OFFSET_1, 0xa3b4)
7247    FIELD(L2_PLL_TM_FRAC_OFFSET_1, PLL_TM_FRAC_OFFSET_1_31_8_RSVD, 24, 8)
7248    FIELD(L2_PLL_TM_FRAC_OFFSET_1, TM_FRAC_OFFSET_1, 0, 8)
7249REG32(L2_PLL_TM_FRAC_OFFSET_2, 0xa3b8)
7250    FIELD(L2_PLL_TM_FRAC_OFFSET_2, PLL_TM_FRAC_OFFSET_2_31_8_RSVD, 24, 8)
7251    FIELD(L2_PLL_TM_FRAC_OFFSET_2, TM_PLL_RSVD, 2, 6)
7252    FIELD(L2_PLL_TM_FRAC_OFFSET_2, TM_FORCE_FBDIV_FRAC_OFFSET, 1, 1)
7253    FIELD(L2_PLL_TM_FRAC_OFFSET_2, TM_FRAC_OFFSET_MSB_2, 0, 1)
7254REG32(L2_PLL_STATUS_READ_0, 0xa3e0)
7255    FIELD(L2_PLL_STATUS_READ_0, PLL_STATUS_READ_0_31_8_RSVD, 24, 8)
7256    FIELD(L2_PLL_STATUS_READ_0, PLL_COARSE_CODE_LSB_STATUS_READ, 0, 8)
7257REG32(L2_PLL_STATUS_READ_1, 0xa3e4)
7258    FIELD(L2_PLL_STATUS_READ_1, PLL_STATUS_READ_1_31_8_RSVD, 24, 8)
7259    FIELD(L2_PLL_STATUS_READ_1, PLL_STATUS_READ_1_RSVD, 6, 2)
7260    FIELD(L2_PLL_STATUS_READ_1, PLL_START_LOOP_STATUS_READ, 5, 1)
7261    FIELD(L2_PLL_STATUS_READ_1, PLL_LOCK_STATUS_READ, 4, 1)
7262    FIELD(L2_PLL_STATUS_READ_1, PLL_COARSE_DONE_STATUS_READ, 3, 1)
7263    FIELD(L2_PLL_STATUS_READ_1, PLL_COARSE_CODE_MSB_STATUS_READ, 0, 3)
7264REG32(L2_UPHY_GLOBAL_CTRL, 0xb000)
7265    FIELD(L2_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_31_8_RSVD, 24, 8)
7266    FIELD(L2_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_7_RSVD, 7, 1)
7267    FIELD(L2_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_6_RSVD, 6, 1)
7268    FIELD(L2_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_5_RSVD, 5, 1)
7269    FIELD(L2_UPHY_GLOBAL_CTRL, PCLK_SELECT, 4, 1)
7270    FIELD(L2_UPHY_GLOBAL_CTRL, MPHY_G3_BIST_ENABLE, 3, 1)
7271    FIELD(L2_UPHY_GLOBAL_CTRL, MULTI_RATE_ENABLE, 2, 1)
7272    FIELD(L2_UPHY_GLOBAL_CTRL, MPHY_GEAR_SELECT, 0, 2)
7273REG32(L2_BIST_CTRL_1, 0xb004)
7274    FIELD(L2_BIST_CTRL_1, BIST_CTRL_1_31_8_RSVD, 24, 8)
7275    FIELD(L2_BIST_CTRL_1, REPETITIVE_PATTERN_ENABLE, 7, 1)
7276    FIELD(L2_BIST_CTRL_1, PRBS_PATTERNS, 5, 2)
7277    FIELD(L2_BIST_CTRL_1, BIST_PATTERN_SELECT, 2, 3)
7278    FIELD(L2_BIST_CTRL_1, BIST_INFINITE_MODE_ENABLE, 1, 1)
7279    FIELD(L2_BIST_CTRL_1, BIST_ENABLE, 0, 1)
7280REG32(L2_BIST_CTRL_2, 0xb008)
7281    FIELD(L2_BIST_CTRL_2, BIST_CTRL_2_31_8_RSVD, 24, 8)
7282    FIELD(L2_BIST_CTRL_2, BIST_CTRL_2_7_3_RSVD, 3, 5)
7283    FIELD(L2_BIST_CTRL_2, BIST_TRAINIG_SEQUENCE_SELECT, 1, 2)
7284    FIELD(L2_BIST_CTRL_2, BIST_ERROR_INJECTION_ENABLE, 0, 1)
7285REG32(L2_BIST_RUN_LEN_L, 0xb00c)
7286    FIELD(L2_BIST_RUN_LEN_L, BIST_RUN_LEN_L_31_8_RSVD, 24, 8)
7287    FIELD(L2_BIST_RUN_LEN_L, BIST_RUN_LEN_L, 0, 8)
7288REG32(L2_BIST_ERR_INJ_POINT_L, 0xb010)
7289    FIELD(L2_BIST_ERR_INJ_POINT_L, BIST_ERR_INJ_POINT_L_31_8_RSVD, 24, 8)
7290    FIELD(L2_BIST_ERR_INJ_POINT_L, BIST_ERROR_INJ_POINT_L, 0, 8)
7291REG32(L2_BIST_RUNLEN_ERR_INJ_H, 0xb014)
7292    FIELD(L2_BIST_RUNLEN_ERR_INJ_H, BIST_RUNLEN_ERR_INJ_H_31_8_RSVD, 24, 8)
7293    FIELD(L2_BIST_RUNLEN_ERR_INJ_H, BIST_RUN_LEN_H, 4, 4)
7294    FIELD(L2_BIST_RUNLEN_ERR_INJ_H, BIST_ERROR_INJ_POINT_H, 0, 4)
7295REG32(L2_BIST_IDLE_TIME, 0xb018)
7296    FIELD(L2_BIST_IDLE_TIME, BIST_IDLE_TIME_31_8_RSVD, 24, 8)
7297    FIELD(L2_BIST_IDLE_TIME, BIST_IDLE_TIME, 0, 8)
7298REG32(L2_BIST_MARKER_L, 0xb01c)
7299    FIELD(L2_BIST_MARKER_L, BIST_MARKER_L_31_8_RSVD, 24, 8)
7300    FIELD(L2_BIST_MARKER_L, BIST_MARKER_L, 0, 8)
7301REG32(L2_BIST_IDLE_CHAR_L, 0xb020)
7302    FIELD(L2_BIST_IDLE_CHAR_L, BIST_IDLE_CHAR_L_31_8_RSVD, 24, 8)
7303    FIELD(L2_BIST_IDLE_CHAR_L, BIST_IDLE_CHAR_L, 0, 8)
7304REG32(L2_BIST_MARKER_IDLE_H, 0xb024)
7305    FIELD(L2_BIST_MARKER_IDLE_H, BIST_MARKER_IDLE_H_31_8_RSVD, 24, 8)
7306    FIELD(L2_BIST_MARKER_IDLE_H, BIST_MARKER_IDLE_RESERVED_7, 6, 2)
7307    FIELD(L2_BIST_MARKER_IDLE_H, BIST_MARKER_H, 4, 2)
7308    FIELD(L2_BIST_MARKER_IDLE_H, BIST_MARKER_IDLE_RESERVED_3, 2, 2)
7309    FIELD(L2_BIST_MARKER_IDLE_H, BIST_IDLE_CHAR_H, 0, 2)
7310REG32(L2_BIST_LOW_PULSE_TIME, 0xb028)
7311    FIELD(L2_BIST_LOW_PULSE_TIME, BIST_LOW_PULSE_TIME_31_8_RSVD, 24, 8)
7312    FIELD(L2_BIST_LOW_PULSE_TIME, BIST_LOW_PULSE_TIME, 0, 8)
7313REG32(L2_BIST_TOTAL_PULSE_TIME, 0xb02c)
7314    FIELD(L2_BIST_TOTAL_PULSE_TIME, BIST_TOTAL_PULSE_TIME_31_8_RSVD, 24, 8)
7315    FIELD(L2_BIST_TOTAL_PULSE_TIME, BIST_TOTAL_PULSE_TIME, 0, 8)
7316REG32(L2_BIST_TEST_PAT_1, 0xb030)
7317    FIELD(L2_BIST_TEST_PAT_1, BIST_TEST_PAT_1_31_8_RSVD, 24, 8)
7318    FIELD(L2_BIST_TEST_PAT_1, BIST_TEST_PAT_1_L, 0, 8)
7319REG32(L2_BIST_TEST_PAT_2, 0xb034)
7320    FIELD(L2_BIST_TEST_PAT_2, BIST_TEST_PAT_2_31_8_RSVD, 24, 8)
7321    FIELD(L2_BIST_TEST_PAT_2, BIST_TEST_PAT_2_L, 0, 8)
7322REG32(L2_BIST_TEST_PAT_3, 0xb038)
7323    FIELD(L2_BIST_TEST_PAT_3, BIST_TEST_PAT_3_31_8_RSVD, 24, 8)
7324    FIELD(L2_BIST_TEST_PAT_3, BIST_TEST_PAT_3_L, 0, 8)
7325REG32(L2_BIST_TEST_PAT_4, 0xb03c)
7326    FIELD(L2_BIST_TEST_PAT_4, BIST_TEST_PAT_4_31_8_RSVD, 24, 8)
7327    FIELD(L2_BIST_TEST_PAT_4, BIST_TEST_PAT_4_L, 0, 8)
7328REG32(L2_BIST_TEST_PAT_MSBS, 0xb040)
7329    FIELD(L2_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_MSBS_31_8_RSVD, 24, 8)
7330    FIELD(L2_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_4_H, 6, 2)
7331    FIELD(L2_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_3_H, 4, 2)
7332    FIELD(L2_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_2_H, 2, 2)
7333    FIELD(L2_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_1_H, 0, 2)
7334REG32(L2_BIST_PKT_NUM, 0xb044)
7335    FIELD(L2_BIST_PKT_NUM, BIST_PKT_NUM_31_8_RSVD, 24, 8)
7336    FIELD(L2_BIST_PKT_NUM, BIST_PKT_NUM, 0, 8)
7337REG32(L2_BIST_FRM_IDLE_TIME, 0xb048)
7338    FIELD(L2_BIST_FRM_IDLE_TIME, BIST_FRM_IDLE_TIME_31_8_RSVD, 24, 8)
7339    FIELD(L2_BIST_FRM_IDLE_TIME, BIST_FRM_IDLE_TIME, 0, 8)
7340REG32(L2_BIST_PKT_CTR_L, 0xb04c)
7341    FIELD(L2_BIST_PKT_CTR_L, BIST_PKT_CTR_L_31_8_RSVD, 24, 8)
7342    FIELD(L2_BIST_PKT_CTR_L, BIST_PKT_CTR_L, 0, 8)
7343REG32(L2_BIST_PKT_CTR_H, 0xb050)
7344    FIELD(L2_BIST_PKT_CTR_H, BIST_PKT_CTR_H_31_8_RSVD, 24, 8)
7345    FIELD(L2_BIST_PKT_CTR_H, BIST_PKT_CTR_H, 0, 8)
7346REG32(L2_BIST_ERR_CTR_L, 0xb054)
7347    FIELD(L2_BIST_ERR_CTR_L, BIST_ERR_CTR_L_31_8_RSVD, 24, 8)
7348    FIELD(L2_BIST_ERR_CTR_L, BIST_ERR_CTR_L, 0, 8)
7349REG32(L2_BIST_ERR_CTR_H, 0xb058)
7350    FIELD(L2_BIST_ERR_CTR_H, BIST_ERR_CTR_H_31_8_RSVD, 24, 8)
7351    FIELD(L2_BIST_ERR_CTR_H, BIST_ERR_CTR_H, 0, 8)
7352REG32(L2_CLK_DIV_CNT, 0xb05c)
7353    FIELD(L2_CLK_DIV_CNT, CLK_DIV_CNT_31_8_RSVD, 24, 8)
7354    FIELD(L2_CLK_DIV_CNT, REF_CLK_BYPASS_GT_50MHZ, 7, 1)
7355    FIELD(L2_CLK_DIV_CNT, SLOW_CNT_REG, 0, 7)
7356REG32(L2_DATA_BUS_WID, 0xb060)
7357    FIELD(L2_DATA_BUS_WID, DATA_BUS_WID_31_8_RSVD, 24, 8)
7358    FIELD(L2_DATA_BUS_WID, RATE_CHANGE_BYPASS, 7, 1)
7359    FIELD(L2_DATA_BUS_WID, PCLK_RATIO_BY_4, 6, 1)
7360    FIELD(L2_DATA_BUS_WID, PCLK_RATIO_BY_2, 5, 1)
7361    FIELD(L2_DATA_BUS_WID, RATE_CHANGE_DELAY_SEL, 4, 1)
7362    FIELD(L2_DATA_BUS_WID, RATE_CHANGE_DELAY_COUNT, 0, 4)
7363REG32(L2_ANADIG_BYPASS, 0xb064)
7364    FIELD(L2_ANADIG_BYPASS, ANADIG_BYPASS_31_8_RSVD, 24, 8)
7365    FIELD(L2_ANADIG_BYPASS, ANA_DIG_COUNTER_SELECT, 7, 1)
7366    FIELD(L2_ANADIG_BYPASS, ANADIG_COUNT, 0, 7)
7367REG32(L2_BIST_FILLER_OUT, 0xb068)
7368    FIELD(L2_BIST_FILLER_OUT, BIST_FILLER_OUT_31_8_RSVD, 24, 8)
7369    FIELD(L2_BIST_FILLER_OUT, BIST_FILLER_OUT_RESERVED, 2, 6)
7370    FIELD(L2_BIST_FILLER_OUT, BIST_FILLER_OUT_ENABLE, 1, 1)
7371    FIELD(L2_BIST_FILLER_OUT, BIST_TX_RX_LOOPBACK_ENABLE, 0, 1)
7372REG32(L2_BIST_FORCE_MK_RST, 0xb06c)
7373    FIELD(L2_BIST_FORCE_MK_RST, BIST_FORCE_MK_RST_31_8_RSVD, 24, 8)
7374    FIELD(L2_BIST_FORCE_MK_RST, BIST_FORCE_RESET, 1, 1)
7375    FIELD(L2_BIST_FORCE_MK_RST, BIST_ENABLE_MK_FROM_REG, 0, 1)
7376REG32(L2_SPARE_IN, 0xb070)
7377    FIELD(L2_SPARE_IN, SPARE_IN_31_8_RSVD, 24, 8)
7378    FIELD(L2_SPARE_IN, SPARE_IN, 0, 8)
7379REG32(L2_SPARE_OUT, 0xb074)
7380    FIELD(L2_SPARE_OUT, SPARE_OUT_31_8_RSVD, 24, 8)
7381    FIELD(L2_SPARE_OUT, SPARE_OUT, 0, 8)
7382REG32(L3_TX_ANA_TM_0, 0xc000)
7383    FIELD(L3_TX_ANA_TM_0, TX_ANA_TM_0_31_8_RSVD, 24, 8)
7384    FIELD(L3_TX_ANA_TM_0, ANA_BYP0_7_6_RSVD, 6, 2)
7385    FIELD(L3_TX_ANA_TM_0, PIPE_TX_DN_RXDET, 5, 1)
7386    FIELD(L3_TX_ANA_TM_0, FORCE_PIPE_TX_DN_RXDET, 4, 1)
7387    FIELD(L3_TX_ANA_TM_0, PIPE_TX_DP_RXDET, 3, 1)
7388    FIELD(L3_TX_ANA_TM_0, FORCE_PIPE_TX_DP_RXDET, 2, 1)
7389    FIELD(L3_TX_ANA_TM_0, ANA_BYP0_1_0_RSVD, 0, 2)
7390REG32(L3_TX_ANA_TM_3, 0xc00c)
7391    FIELD(L3_TX_ANA_TM_3, TX_ANA_TM_3_31_8_RSVD, 24, 8)
7392    FIELD(L3_TX_ANA_TM_3, TX_HS_SER_RSTB, 7, 1)
7393    FIELD(L3_TX_ANA_TM_3, FORCE_TX_HS_SER_RSTB, 6, 1)
7394    FIELD(L3_TX_ANA_TM_3, TX_HS_BURST, 5, 1)
7395    FIELD(L3_TX_ANA_TM_3, FORCE_TX_HS_BURST, 4, 1)
7396    FIELD(L3_TX_ANA_TM_3, TX_SERIALIZER_ENABLE, 3, 1)
7397    FIELD(L3_TX_ANA_TM_3, FORCE_TX_SERIALIZER_ENABLE, 2, 1)
7398    FIELD(L3_TX_ANA_TM_3, TX_ENABLE_SUPPLY_SERIALIZER, 1, 1)
7399    FIELD(L3_TX_ANA_TM_3, FORCE_TX_ENABLE_SUPPLY_SERIALIZER, 0, 1)
7400REG32(L3_TX_ANA_TM_4, 0xc010)
7401    FIELD(L3_TX_ANA_TM_4, TX_ANA_TM_4_31_8_RSVD, 24, 8)
7402    FIELD(L3_TX_ANA_TM_4, ANA_BYP4_7_RSVD, 7, 1)
7403    FIELD(L3_TX_ANA_TM_4, TX_LSEG_DN_RESCAL_CODE, 1, 6)
7404    FIELD(L3_TX_ANA_TM_4, FORCE_TX_LSEG_DN_RESCAL_CODE, 0, 1)
7405REG32(L3_TX_ANA_TM_5, 0xc014)
7406    FIELD(L3_TX_ANA_TM_5, TX_ANA_TM_5_31_8_RSVD, 24, 8)
7407    FIELD(L3_TX_ANA_TM_5, ANA_BYP5_7_RSVD, 7, 1)
7408    FIELD(L3_TX_ANA_TM_5, TX_USEG_DP_RESCAL_CODE, 1, 6)
7409    FIELD(L3_TX_ANA_TM_5, FORCE_TX_USEG_DP_RESCAL_CODE, 0, 1)
7410REG32(L3_TX_ANA_TM_9, 0xc024)
7411    FIELD(L3_TX_ANA_TM_9, TX_ANA_TM_9_31_8_RSVD, 24, 8)
7412    FIELD(L3_TX_ANA_TM_9, MPHY_TX_HS_SLEWRATE, 0, 8)
7413REG32(L3_TX_ANA_TM_10, 0xc028)
7414    FIELD(L3_TX_ANA_TM_10, TX_ANA_TM_10_31_8_RSVD, 24, 8)
7415    FIELD(L3_TX_ANA_TM_10, MPHY_HS_POWERUP_TIME, 4, 4)
7416    FIELD(L3_TX_ANA_TM_10, MPHY_TX_HS_EQUALIZER_SETTING, 1, 3)
7417    FIELD(L3_TX_ANA_TM_10, FORCE_MPHY_TX_HS_EQUALIZER_SETTING, 0, 1)
7418REG32(L3_TX_ANA_TM_13, 0xc034)
7419    FIELD(L3_TX_ANA_TM_13, TX_ANA_TM_13_31_8_RSVD, 24, 8)
7420    FIELD(L3_TX_ANA_TM_13, ANA_BYP13_7_4_RSVD, 4, 4)
7421    FIELD(L3_TX_ANA_TM_13, TX_SWAP_POLARITY, 3, 1)
7422    FIELD(L3_TX_ANA_TM_13, FORCE_TX_SWAP_POLARITY, 2, 1)
7423    FIELD(L3_TX_ANA_TM_13, MPHY_TX_TRISTATE, 1, 1)
7424    FIELD(L3_TX_ANA_TM_13, FORCE_MPHY_TX_TRISTATE, 0, 1)
7425REG32(L3_TX_ANA_TM_14, 0xc038)
7426    FIELD(L3_TX_ANA_TM_14, TX_ANA_TM_14_31_8_RSVD, 24, 8)
7427    FIELD(L3_TX_ANA_TM_14, ANA_BYP14_7_6_RSVD, 6, 2)
7428    FIELD(L3_TX_ANA_TM_14, PIPE_TX_FAST_EST_COMMON_MODE, 5, 1)
7429    FIELD(L3_TX_ANA_TM_14, FORCE_PIPE_TX_FAST_EST_COMMON_MODE, 4, 1)
7430    FIELD(L3_TX_ANA_TM_14, ANA_BYP14_3_0_RSVD, 0, 4)
7431REG32(L3_TX_ANA_TM_15, 0xc03c)
7432    FIELD(L3_TX_ANA_TM_15, TX_ANA_TM_15_31_8_RSVD, 24, 8)
7433    FIELD(L3_TX_ANA_TM_15, PIPE_TX_SWING, 7, 1)
7434    FIELD(L3_TX_ANA_TM_15, FORCE_PIPE_TX_SWING, 6, 1)
7435    FIELD(L3_TX_ANA_TM_15, PIPE_TX_RXDET_DISCHARGE, 5, 1)
7436    FIELD(L3_TX_ANA_TM_15, FORCE_PIPE_TX_RXDET_DISCHARGE, 4, 1)
7437    FIELD(L3_TX_ANA_TM_15, PIPE_TX_RXDET_CHARGE, 3, 1)
7438    FIELD(L3_TX_ANA_TM_15, FORCE_PIPE_TX_RXDET_CHARGE, 2, 1)
7439    FIELD(L3_TX_ANA_TM_15, PIPE_TX_ENABLE_RXDET, 1, 1)
7440    FIELD(L3_TX_ANA_TM_15, FORCE_PIPE_TX_ENABLE_RXDET, 0, 1)
7441REG32(L3_TX_ANA_TM_16, 0xc040)
7442    FIELD(L3_TX_ANA_TM_16, TX_ANA_TM_16_31_8_RSVD, 24, 8)
7443    FIELD(L3_TX_ANA_TM_16, ANA_BYP16_7_4_RSVD, 4, 4)
7444    FIELD(L3_TX_ANA_TM_16, PIPE_TX_MARGIN, 1, 3)
7445    FIELD(L3_TX_ANA_TM_16, FORCE_PIPE_TX_MARGIN, 0, 1)
7446REG32(L3_TX_ANA_TM_18, 0xc048)
7447    FIELD(L3_TX_ANA_TM_18, TX_ANA_TM_18_31_8_RSVD, 24, 8)
7448    FIELD(L3_TX_ANA_TM_18, PIPE_TX_DEEMPH_7_0, 0, 8)
7449REG32(L3_TX_ANA_TM_19, 0xc04c)
7450    FIELD(L3_TX_ANA_TM_19, TX_ANA_TM_19_31_8_RSVD, 24, 8)
7451    FIELD(L3_TX_ANA_TM_19, PIPE_TX_DEEMPH_15_8, 0, 8)
7452REG32(L3_TX_ANA_TM_20, 0xc050)
7453    FIELD(L3_TX_ANA_TM_20, TX_ANA_TM_20_31_8_RSVD, 24, 8)
7454    FIELD(L3_TX_ANA_TM_20, ANA_BYP20_7_5_RSVD, 5, 3)
7455    FIELD(L3_TX_ANA_TM_20, TX_SERIALIZER_RST_REL, 4, 1)
7456    FIELD(L3_TX_ANA_TM_20, FORCE_TX_SERIALIZER_RST_REL, 3, 1)
7457    FIELD(L3_TX_ANA_TM_20, FORCE_MPHY_TX_HS_SLEWRATE, 2, 1)
7458    FIELD(L3_TX_ANA_TM_20, PIPE_TX_DEEMPH_17_16, 0, 2)
7459REG32(L3_TX_ANA_TM_21, 0xc054)
7460    FIELD(L3_TX_ANA_TM_21, TX_ANA_TM_21_31_8_RSVD, 24, 8)
7461    FIELD(L3_TX_ANA_TM_21, ANA_BYP21_7_6_RSVD, 6, 2)
7462    FIELD(L3_TX_ANA_TM_21, PIPE_TX_COEF_CALC_CLK, 5, 1)
7463    FIELD(L3_TX_ANA_TM_21, FORCE_PIPE_TX_COEF_CALC_CLK, 4, 1)
7464    FIELD(L3_TX_ANA_TM_21, PIPE_TX_COEF_CALC_FSM_RESET_B, 3, 1)
7465    FIELD(L3_TX_ANA_TM_21, FORCE_PIPE_TX_COEF_CALC_FSM_RESET_B, 2, 1)
7466    FIELD(L3_TX_ANA_TM_21, PIPE_TX_DEEMPH_CTRL_SEL, 1, 1)
7467    FIELD(L3_TX_ANA_TM_21, FORCE_PIPE_TX_DEEMPH_CTRL_SEL, 0, 1)
7468REG32(L3_TX_DIG_TM_61, 0xc0f4)
7469    FIELD(L3_TX_DIG_TM_61, TX_DIG_TM_61_31_8_RSVD, 24, 8)
7470    FIELD(L3_TX_DIG_TM_61, MPHY_PLL_GEAR, 6, 2)
7471    FIELD(L3_TX_DIG_TM_61, DIG_BYP1_5_4_RSVD, 4, 2)
7472    FIELD(L3_TX_DIG_TM_61, BYPASS_ENC, 3, 1)
7473    FIELD(L3_TX_DIG_TM_61, DIG_BYP1_2_RSVD, 2, 1)
7474    FIELD(L3_TX_DIG_TM_61, BYPASS_SCRAM, 1, 1)
7475    FIELD(L3_TX_DIG_TM_61, FORCE_BYPASS_SCRAM, 0, 1)
7476REG32(L3_TX_DIG_TM_62, 0xc0f8)
7477    FIELD(L3_TX_DIG_TM_62, TX_DIG_TM_62_31_8_RSVD, 24, 8)
7478    FIELD(L3_TX_DIG_TM_62, G0_BIT_PER_CNT, 0, 8)
7479REG32(L3_TX_DIG_TM_65, 0xc104)
7480    FIELD(L3_TX_DIG_TM_65, TX_DIG_TM_65_31_8_RSVD, 24, 8)
7481    FIELD(L3_TX_DIG_TM_65, FORCE_TX_RXDET_PROBE_THRESHOLD, 7, 1)
7482    FIELD(L3_TX_DIG_TM_65, FORCE_TX_RXDET_END_CH_THRESHOLD, 6, 1)
7483    FIELD(L3_TX_DIG_TM_65, FORCE_TX_RXDET_START_CH_THRESHOLD, 5, 1)
7484    FIELD(L3_TX_DIG_TM_65, FORCE_TX_RXDET_END_DCH_THRESHOLD, 4, 1)
7485    FIELD(L3_TX_DIG_TM_65, FORCE_TX_RXDET_START_DCH_THRESHOLD, 3, 1)
7486    FIELD(L3_TX_DIG_TM_65, TX_EN_FULL_CALIB, 2, 1)
7487    FIELD(L3_TX_DIG_TM_65, FORCE_TX_EN_FULL_CALIB, 1, 1)
7488    FIELD(L3_TX_DIG_TM_65, DIG_BYP5_0_RSVD, 0, 1)
7489REG32(L3_TX_DIG_TM_67, 0xc10c)
7490    FIELD(L3_TX_DIG_TM_67, TX_DIG_TM_67_31_8_RSVD, 24, 8)
7491    FIELD(L3_TX_DIG_TM_67, TX_MPHY_SER_THRESHOLD, 0, 8)
7492REG32(L3_TX_DIG_TM_68, 0xc110)
7493    FIELD(L3_TX_DIG_TM_68, TX_DIG_TM_68_31_8_RSVD, 24, 8)
7494    FIELD(L3_TX_DIG_TM_68, TX_SER_SUP_THRESHOLD, 0, 8)
7495REG32(L3_TX_DIG_TM_69, 0xc114)
7496    FIELD(L3_TX_DIG_TM_69, TX_DIG_TM_69_31_8_RSVD, 24, 8)
7497    FIELD(L3_TX_DIG_TM_69, TX_MPHY_SUP_THRESHOLD, 0, 8)
7498REG32(L3_TX_DIG_TM_76, 0xc130)
7499    FIELD(L3_TX_DIG_TM_76, TX_DIG_TM_76_31_8_RSVD, 24, 8)
7500    FIELD(L3_TX_DIG_TM_76, TX_RXDET_START_DCH_THRESHOLD_7_0, 0, 8)
7501REG32(L3_TX_DIG_TM_77, 0xc134)
7502    FIELD(L3_TX_DIG_TM_77, TX_DIG_TM_77_31_8_RSVD, 24, 8)
7503    FIELD(L3_TX_DIG_TM_77, TX_RXDET_END_DCH_THRESHOLD_11_8, 4, 4)
7504    FIELD(L3_TX_DIG_TM_77, TX_RXDET_START_DCH_THRESHOLD_11_8, 0, 4)
7505REG32(L3_TX_DIG_TM_78, 0xc138)
7506    FIELD(L3_TX_DIG_TM_78, TX_DIG_TM_78_31_8_RSVD, 24, 8)
7507    FIELD(L3_TX_DIG_TM_78, TX_RXDET_END_DCH_THRESHOLD_7_0, 0, 8)
7508REG32(L3_TX_DIG_TM_79, 0xc13c)
7509    FIELD(L3_TX_DIG_TM_79, TX_DIG_TM_79_31_8_RSVD, 24, 8)
7510    FIELD(L3_TX_DIG_TM_79, TX_RXDET_START_CH_THRESHOLD_7_0, 0, 8)
7511REG32(L3_TX_DIG_TM_80, 0xc140)
7512    FIELD(L3_TX_DIG_TM_80, TX_DIG_TM_80_31_8_RSVD, 24, 8)
7513    FIELD(L3_TX_DIG_TM_80, TX_RXDET_END_CH_THRESHOLD_11_8, 4, 4)
7514    FIELD(L3_TX_DIG_TM_80, TX_RXDET_START_CH_THRESHOLD_11_8, 0, 4)
7515REG32(L3_TX_DIG_TM_81, 0xc144)
7516    FIELD(L3_TX_DIG_TM_81, TX_DIG_TM_81_31_8_RSVD, 24, 8)
7517    FIELD(L3_TX_DIG_TM_81, TX_RXDET_END_CH_THRESHOLD_7_0, 0, 8)
7518REG32(L3_TX_DIG_TM_82, 0xc148)
7519    FIELD(L3_TX_DIG_TM_82, TX_DIG_TM_82_31_8_RSVD, 24, 8)
7520    FIELD(L3_TX_DIG_TM_82, TX_RXDET_PROBE_THRESHOLD_7_0, 0, 8)
7521REG32(L3_TX_DIG_TM_83, 0xc14c)
7522    FIELD(L3_TX_DIG_TM_83, TX_DIG_TM_83_31_8_RSVD, 24, 8)
7523    FIELD(L3_TX_DIG_TM_83, DIG_BYP23_7_4_RSVD, 4, 4)
7524    FIELD(L3_TX_DIG_TM_83, TX_RXDET_PROBE_THRESHOLD_11_8, 0, 4)
7525REG32(L3_TX_DIG_TM_84, 0xc150)
7526    FIELD(L3_TX_DIG_TM_84, TX_DIG_TM_84_31_8_RSVD, 24, 8)
7527    FIELD(L3_TX_DIG_TM_84, TX_DIF_P, 7, 1)
7528    FIELD(L3_TX_DIG_TM_84, TX_DITHER_1P, 6, 1)
7529    FIELD(L3_TX_DIG_TM_84, TX_DITHER_1N, 5, 1)
7530    FIELD(L3_TX_DIG_TM_84, TX_DITHER_EN, 4, 1)
7531    FIELD(L3_TX_DIG_TM_84, DIG_BYP24_3_RSVD, 3, 1)
7532    FIELD(L3_TX_DIG_TM_84, TX_PHYDIRDY_SOC_MODE, 2, 1)
7533    FIELD(L3_TX_DIG_TM_84, DIG_BYP24_1_RSVD, 1, 1)
7534    FIELD(L3_TX_DIG_TM_84, TX_READ_SHADOW, 0, 1)
7535REG32(L3_TX_ANA_TM_85, 0xc154)
7536    FIELD(L3_TX_ANA_TM_85, TX_ANA_TM_85_31_8_RSVD, 24, 8)
7537    FIELD(L3_TX_ANA_TM_85, DIG_BYP25_7_6_RSVD, 6, 2)
7538    FIELD(L3_TX_ANA_TM_85, TX_HIBERN8_CTRL, 5, 1)
7539    FIELD(L3_TX_ANA_TM_85, TX_ALLOW_INLNCFG_FROM_TOP, 4, 1)
7540    FIELD(L3_TX_ANA_TM_85, DIG_BYP25_3_RSVD, 3, 1)
7541    FIELD(L3_TX_ANA_TM_85, TX_SEND_MSB_FIRST, 2, 1)
7542    FIELD(L3_TX_ANA_TM_85, DIG_BYP25_1_RSVD, 1, 1)
7543    FIELD(L3_TX_ANA_TM_85, TX_DIF_N, 0, 1)
7544REG32(L3_TX_ANA_TM_87, 0xc15c)
7545    FIELD(L3_TX_ANA_TM_87, TX_ANA_TM_87_31_8_RSVD, 24, 8)
7546    FIELD(L3_TX_ANA_TM_87, DIG_BYP27_7_4_RSVD, 4, 4)
7547    FIELD(L3_TX_ANA_TM_87, TX_SM_STATUS, 0, 4)
7548REG32(L3_TX_ANA_TM_88, 0xc160)
7549    FIELD(L3_TX_ANA_TM_88, TX_ANA_TM_88_31_8_RSVD, 24, 8)
7550    FIELD(L3_TX_ANA_TM_88, TX_COMP_PAT_HIGH_TIME_REGS, 0, 8)
7551REG32(L3_TX_ANA_TM_89, 0xc164)
7552    FIELD(L3_TX_ANA_TM_89, TX_ANA_TM_89_31_8_RSVD, 24, 8)
7553    FIELD(L3_TX_ANA_TM_89, DIG_BYP29_7_6_RSVD, 6, 2)
7554    FIELD(L3_TX_ANA_TM_89, TX_DATAPATH_CTRL_1_REGS, 5, 1)
7555    FIELD(L3_TX_ANA_TM_89, DIG_BYP29_4_3_RSVD, 3, 2)
7556    FIELD(L3_TX_ANA_TM_89, INITIAL_DISPARITY, 2, 1)
7557    FIELD(L3_TX_ANA_TM_89, SCRAMBLER_ENABLE, 1, 1)
7558    FIELD(L3_TX_ANA_TM_89, DIG_BYP29_0_RSVD, 0, 1)
7559REG32(L3_TX_ANA_TM_90, 0xc168)
7560    FIELD(L3_TX_ANA_TM_90, TX_ANA_TM_90_31_8_RSVD, 24, 8)
7561    FIELD(L3_TX_ANA_TM_90, DIG_BYP30_7_6_RSVD, 6, 2)
7562    FIELD(L3_TX_ANA_TM_90, TX_BYPASS_BCNT_LPBACK_REGS, 5, 1)
7563    FIELD(L3_TX_ANA_TM_90, DIG_BYP30_4_0_RSVD, 0, 5)
7564REG32(L3_TX_DIG_TM_91, 0xc16c)
7565    FIELD(L3_TX_DIG_TM_91, TX_DIG_TM_91_31_8_RSVD, 24, 8)
7566    FIELD(L3_TX_DIG_TM_91, TX_CFGCLK_FREQ, 0, 8)
7567REG32(L3_TX_DIG_TM_92, 0xc170)
7568    FIELD(L3_TX_DIG_TM_92, TX_DIG_TM_92_31_8_RSVD, 24, 8)
7569    FIELD(L3_TX_DIG_TM_92, TX_PHYDIRDY_PULL_UP_LATENCY, 0, 8)
7570REG32(L3_TX_ANA_TM_95, 0xc17c)
7571    FIELD(L3_TX_ANA_TM_95, TX_ANA_TM_95_31_8_RSVD, 24, 8)
7572    FIELD(L3_TX_ANA_TM_95, ANA_BYP63_7_6_RSVD, 6, 2)
7573    FIELD(L3_TX_ANA_TM_95, TX_TM_EN_PROG_SYNC_PATTERN, 5, 1)
7574    FIELD(L3_TX_ANA_TM_95, TX_EXTRA_HS_BURST_IN_LCC, 2, 3)
7575    FIELD(L3_TX_ANA_TM_95, ANA_BYP22_1_0_RSVD, 0, 2)
7576REG32(L3_TX_ANA_TM_96, 0xc180)
7577    FIELD(L3_TX_ANA_TM_96, TX_ANA_TM_96_31_8_RSVD, 24, 8)
7578    FIELD(L3_TX_ANA_TM_96, TX_TM_PROG_SYNC_PATTERN1, 0, 8)
7579REG32(L3_TX_ANA_TM_97, 0xc184)
7580    FIELD(L3_TX_ANA_TM_97, TX_ANA_TM_97_31_8_RSVD, 24, 8)
7581    FIELD(L3_TX_ANA_TM_97, TX_TM_PROG_SYNC_PATTERN2, 0, 8)
7582REG32(L3_TX_DIG_TM_98, 0xc188)
7583    FIELD(L3_TX_DIG_TM_98, TX_DIG_TM_98_31_8_RSVD, 24, 8)
7584    FIELD(L3_TX_DIG_TM_98, DIG_BYP33_7_6_RSVD, 6, 2)
7585    FIELD(L3_TX_DIG_TM_98, FORCE_RD_VALUE, 5, 1)
7586    FIELD(L3_TX_DIG_TM_98, FORCE_RD, 4, 1)
7587    FIELD(L3_TX_DIG_TM_98, TX_SER_ISO_CTRL_BAR, 3, 1)
7588    FIELD(L3_TX_DIG_TM_98, FORCE_TX_SER_ISO_CTRL_BAR, 2, 1)
7589    FIELD(L3_TX_DIG_TM_98, TX_ISO_CTRL_BAR, 1, 1)
7590    FIELD(L3_TX_DIG_TM_98, FORCE_TX_ISO_CTRL_BAR, 0, 1)
7591REG32(L3_TX_DIG_TM_99, 0xc18c)
7592    FIELD(L3_TX_DIG_TM_99, TX_DIG_TM_99_31_8_RSVD, 24, 8)
7593    FIELD(L3_TX_DIG_TM_99, TX_PIPE_SUPPLY_ENABLE_THRESHOLD, 0, 8)
7594REG32(L3_TX_DIG_TM_100, 0xc190)
7595    FIELD(L3_TX_DIG_TM_100, TX_DIG_TM_100_31_8_RSVD, 24, 8)
7596    FIELD(L3_TX_DIG_TM_100, TX_SERIALISER_SUPPLY_ENABLE_THRESHOLD, 0, 8)
7597REG32(L3_TX_DIG_TM_101, 0xc194)
7598    FIELD(L3_TX_DIG_TM_101, TX_DIG_TM_101_31_8_RSVD, 24, 8)
7599    FIELD(L3_TX_DIG_TM_101, TX_SERIALISER_ENABLE_THRESHOLD, 0, 8)
7600REG32(L3_TX_DIG_TM_102, 0xc198)
7601    FIELD(L3_TX_DIG_TM_102, TX_DIG_TM_102_31_8_RSVD, 24, 8)
7602    FIELD(L3_TX_DIG_TM_102, FORCE_TX_ANA_LL_EN, 7, 1)
7603    FIELD(L3_TX_DIG_TM_102, TX_ANA_LL_EN, 6, 1)
7604    FIELD(L3_TX_DIG_TM_102, FORCE_DELAY_CNT_THRESHOLD, 5, 1)
7605    FIELD(L3_TX_DIG_TM_102, FORCE_TX_MPHY_TRST_THRESHOLD, 4, 1)
7606    FIELD(L3_TX_DIG_TM_102, FORCE_TX_LDO_THRESHOLD, 3, 1)
7607    FIELD(L3_TX_DIG_TM_102, FORCE_TX_SERIALISER_ENABLE_THRESHOLD, 2, 1)
7608    FIELD(L3_TX_DIG_TM_102, FORCE_TX_SERIALISER_SUPPLY_ENABLE_THRESHOLD, 1, 1)
7609    FIELD(L3_TX_DIG_TM_102, FORCE_TX_PIPE_SUPPLY_ENABLE_THRESHOLD, 0, 1)
7610REG32(L3_TX_DIG_TM_103, 0xc19c)
7611    FIELD(L3_TX_DIG_TM_103, TX_DIG_TM_103_31_8_RSVD, 24, 8)
7612    FIELD(L3_TX_DIG_TM_103, FORCE_BG_EN, 7, 1)
7613    FIELD(L3_TX_DIG_TM_103, FORCE_CALIB_EN, 6, 1)
7614    FIELD(L3_TX_DIG_TM_103, FORCE_PLL_EN, 5, 1)
7615    FIELD(L3_TX_DIG_TM_103, FORCE_PSO, 4, 1)
7616    FIELD(L3_TX_DIG_TM_103, BG_EN, 3, 1)
7617    FIELD(L3_TX_DIG_TM_103, CALIB_EN, 2, 1)
7618    FIELD(L3_TX_DIG_TM_103, PLL_EN, 1, 1)
7619    FIELD(L3_TX_DIG_TM_103, PSO, 0, 1)
7620REG32(L3_TX_DIG_TM_104, 0xc1a0)
7621    FIELD(L3_TX_DIG_TM_104, TX_DIG_TM_104_31_8_RSVD, 24, 8)
7622    FIELD(L3_TX_DIG_TM_104, TX_LDO_THRESHOLD, 0, 8)
7623REG32(L3_TX_DIG_TM_105, 0xc1a4)
7624    FIELD(L3_TX_DIG_TM_105, TX_DIG_TM_105_31_8_RSVD, 24, 8)
7625    FIELD(L3_TX_DIG_TM_105, TX_MPHY_TRST_THRESHOLD, 0, 8)
7626REG32(L3_TX_DIG_TM_106, 0xc1a8)
7627    FIELD(L3_TX_DIG_TM_106, TX_DIG_TM_106_31_8_RSVD, 24, 8)
7628    FIELD(L3_TX_DIG_TM_106, DELAY_CNT_THRESHOLD, 0, 8)
7629REG32(L3_TX_DIG_TM_107, 0xc1ac)
7630    FIELD(L3_TX_DIG_TM_107, TX_DIG_TM_107_31_8_RSVD, 24, 8)
7631    FIELD(L3_TX_DIG_TM_107, DIG_BYP42_7_RSVD, 7, 1)
7632    FIELD(L3_TX_DIG_TM_107, FORCE_P3TOP0_PHYSTATUS_PULSE, 6, 1)
7633    FIELD(L3_TX_DIG_TM_107, ENABLE_HS_CLK_DIVISION, 5, 1)
7634    FIELD(L3_TX_DIG_TM_107, TESTDIGOUT_SEL, 1, 4)
7635    FIELD(L3_TX_DIG_TM_107, FORCE_TESTDIGOUT_SEL, 0, 1)
7636REG32(L3_TX_DIG_TM_108, 0xc1b0)
7637    FIELD(L3_TX_DIG_TM_108, TX_DIG_TM_108_31_8_RSVD, 24, 8)
7638    FIELD(L3_TX_DIG_TM_108, ANA_BYP43_7_RSVD, 7, 1)
7639    FIELD(L3_TX_DIG_TM_108, TX_EXT_DATA_DELAY, 3, 4)
7640    FIELD(L3_TX_DIG_TM_108, FORCE_TX_EXT_DATA_DELAY, 2, 1)
7641    FIELD(L3_TX_DIG_TM_108, FORCE_TX_DATA_DELAY, 1, 1)
7642    FIELD(L3_TX_DIG_TM_108, FORCE_UPHY_TXPMA_OPMODE, 0, 1)
7643REG32(L3_TX_DIG_TM_109, 0xc1b4)
7644    FIELD(L3_TX_DIG_TM_109, TX_DIG_TM_109_31_8_RSVD, 24, 8)
7645    FIELD(L3_TX_DIG_TM_109, UPHY_TXPMA_OPMODE, 0, 8)
7646REG32(L3_TX_DIG_TM_110, 0xc1b8)
7647    FIELD(L3_TX_DIG_TM_110, TX_DIG_TM_110_31_8_RSVD, 24, 8)
7648    FIELD(L3_TX_DIG_TM_110, TX_DATA_DELAY, 0, 8)
7649REG32(L3_TX_DIG_TM_111, 0xc1bc)
7650    FIELD(L3_TX_DIG_TM_111, TX_DIG_TM_111_31_8_RSVD, 24, 8)
7651    FIELD(L3_TX_DIG_TM_111, TX_DA_SPARE, 0, 8)
7652REG32(L3_TX_ANA_TM_112, 0xc1c0)
7653    FIELD(L3_TX_ANA_TM_112, TX_ANA_TM_112_31_8_RSVD, 24, 8)
7654    FIELD(L3_TX_ANA_TM_112, ANA_BYP25_7_6_RSVD, 6, 2)
7655    FIELD(L3_TX_ANA_TM_112, PIPE_TX_ENABLE_LFPS, 4, 2)
7656    FIELD(L3_TX_ANA_TM_112, FORCE_PIPE_TX_ENABLE_LFPS, 3, 1)
7657    FIELD(L3_TX_ANA_TM_112, PIPE_TX_ENABLE_IDLE_MODE, 1, 2)
7658    FIELD(L3_TX_ANA_TM_112, FORCE_PIPE_TX_ENABLE_IDLE_MODE, 0, 1)
7659REG32(L3_TX_ANA_TM_113, 0xc1c4)
7660    FIELD(L3_TX_ANA_TM_113, TX_ANA_TM_113_31_8_RSVD, 24, 8)
7661    FIELD(L3_TX_ANA_TM_113, MPHY_TX_DRIVERLDO_PROG, 0, 8)
7662REG32(L3_TX_ANA_TM_114, 0xc1c8)
7663    FIELD(L3_TX_ANA_TM_114, TX_ANA_TM_114_31_8_RSVD, 24, 8)
7664    FIELD(L3_TX_ANA_TM_114, ANA_BYP27_7_5_RSVD, 5, 3)
7665    FIELD(L3_TX_ANA_TM_114, FORCE_MPHY_TX_DRIVERLDO_PROG, 4, 1)
7666    FIELD(L3_TX_ANA_TM_114, MPHY_TX_DRIVERLDO_PROG, 0, 4)
7667REG32(L3_TX_ANA_TM_115, 0xc1cc)
7668    FIELD(L3_TX_ANA_TM_115, TX_ANA_TM_115_31_8_RSVD, 24, 8)
7669    FIELD(L3_TX_ANA_TM_115, ANA_BYP28_7_RSVD, 7, 1)
7670    FIELD(L3_TX_ANA_TM_115, PIPE_TX_GETLOCALPRESETCOEFFICIENTS, 6, 1)
7671    FIELD(L3_TX_ANA_TM_115, FORCE_PIPE_TX_GETLOCALPRESETCOEFFICIENTS, 5, 1)
7672    FIELD(L3_TX_ANA_TM_115, TX_PMADIG_DIGITAL_RESET_N, 4, 1)
7673    FIELD(L3_TX_ANA_TM_115, FORCE_TX_PMADIG_DIGITAL_RESET_N, 3, 1)
7674    FIELD(L3_TX_ANA_TM_115, TX_ANA_IF_RATE, 1, 2)
7675    FIELD(L3_TX_ANA_TM_115, FORCE_TX_ANA_IF_RATE, 0, 1)
7676REG32(L3_TX_ANA_TM_116, 0xc1d0)
7677    FIELD(L3_TX_ANA_TM_116, TX_ANA_TM_116_31_8_RSVD, 24, 8)
7678    FIELD(L3_TX_ANA_TM_116, ANA_BYP29_7_RSVD, 7, 1)
7679    FIELD(L3_TX_ANA_TM_116, PIPE_TX_LOCALPRESETINDEX, 3, 4)
7680    FIELD(L3_TX_ANA_TM_116, FORCE_PIPE_TX_LOCALPRESETINDEX, 2, 1)
7681    FIELD(L3_TX_ANA_TM_116, MPHY_TX_EN_LANE_LS_CLK, 1, 1)
7682    FIELD(L3_TX_ANA_TM_116, FORCE_MPHY_TX_EN_LANE_LS_CLK, 0, 1)
7683REG32(L3_TX_ANA_TM_117, 0xc1d4)
7684    FIELD(L3_TX_ANA_TM_117, TX_ANA_TM_117_31_8_RSVD, 24, 8)
7685    FIELD(L3_TX_ANA_TM_117, MULTILANE_BYP1_7_6_RSVD, 6, 2)
7686    FIELD(L3_TX_ANA_TM_117, TX_PCIE_4X_CFG_EN, 5, 1)
7687    FIELD(L3_TX_ANA_TM_117, FORCE_TX_PCIE_4X_CFG_EN, 4, 1)
7688    FIELD(L3_TX_ANA_TM_117, TX_PCIE_2X_CFG_EN, 3, 1)
7689    FIELD(L3_TX_ANA_TM_117, FORCE_TX_PCIE_2X_CFG_EN, 2, 1)
7690    FIELD(L3_TX_ANA_TM_117, TX_DP_MULTILANE_CFG_EN, 1, 1)
7691    FIELD(L3_TX_ANA_TM_117, FORCE_TX_DP_MULTILANE_CFG_EN, 0, 1)
7692REG32(L3_TX_ANA_TM_118, 0xc1d8)
7693    FIELD(L3_TX_ANA_TM_118, TX_ANA_TM_118_31_8_RSVD, 24, 8)
7694    FIELD(L3_TX_ANA_TM_118, ANA_BYP30_7_4_RSVD, 4, 4)
7695    FIELD(L3_TX_ANA_TM_118, FORCE_TX_DEEMPH_17_12, 3, 1)
7696    FIELD(L3_TX_ANA_TM_118, FORCE_TX_DEEMPH_11_6, 2, 1)
7697    FIELD(L3_TX_ANA_TM_118, FORCE_TX_DEEMPH_5_0, 1, 1)
7698    FIELD(L3_TX_ANA_TM_118, FORCE_TX_DEEMPH_17_0, 0, 1)
7699REG32(L3_TXPMA_TM_0, 0xc800)
7700    FIELD(L3_TXPMA_TM_0, TXPMA_TM_0_31_8_RSVD, 24, 8)
7701    FIELD(L3_TXPMA_TM_0, TM_TX_ENABLE_SUPPLY_MPHY, 7, 1)
7702    FIELD(L3_TXPMA_TM_0, TM_FORCE_TX_ENABLE_SUPPLY_MPHY, 6, 1)
7703    FIELD(L3_TXPMA_TM_0, TM_MPHY_TX_ENABLE_SUPPLY_LS_CLOCK, 5, 1)
7704    FIELD(L3_TXPMA_TM_0, TM_FORCE_MPHY_TX_ENABLE_SUPPLY_LS_CLOCK, 4, 1)
7705    FIELD(L3_TXPMA_TM_0, TM_MPHY_TX_ENABLE_SA_MODE, 3, 1)
7706    FIELD(L3_TXPMA_TM_0, TM_FORCE_MPHY_TX_ENABLE_SA_MODE, 2, 1)
7707    FIELD(L3_TXPMA_TM_0, TM_MPHY_TX_ENABLE_HS_NT, 1, 1)
7708    FIELD(L3_TXPMA_TM_0, TM_FORCE_MPHY_TX_ENABLE_HS_NT, 0, 1)
7709REG32(L3_TXPMA_TM_1, 0xc804)
7710    FIELD(L3_TXPMA_TM_1, TXPMA_TM_1_31_8_RSVD, 24, 8)
7711    FIELD(L3_TXPMA_TM_1, ANA_MPHY_BYP1_7_4_RSVD, 4, 4)
7712    FIELD(L3_TXPMA_TM_1, TM_MPHY_TX_HS_DITHER_VAL, 1, 3)
7713    FIELD(L3_TXPMA_TM_1, TM_FORCE_MPHY_TX_HS_DITHER_VAL, 0, 1)
7714REG32(L3_TXPMA_TM_2, 0xc808)
7715    FIELD(L3_TXPMA_TM_2, TXPMA_TM_2_31_8_RSVD, 24, 8)
7716    FIELD(L3_TXPMA_TM_2, TM_MPHY_TX_DRIVERLDO_PROG_6_0, 1, 7)
7717    FIELD(L3_TXPMA_TM_2, TM_FORCE_MPHY_TX_DRIVERLDO_PROG, 0, 1)
7718REG32(L3_TXPMA_TM_3, 0xc80c)
7719    FIELD(L3_TXPMA_TM_3, TXPMA_TM_3_31_8_RSVD, 24, 8)
7720    FIELD(L3_TXPMA_TM_3, ANA_MPHY_BYP3_7_5_RSVD, 5, 3)
7721    FIELD(L3_TXPMA_TM_3, TM_MPHY_TX_DRIVERLDO_PROG_11_7, 0, 5)
7722REG32(L3_TXPMA_TM_4, 0xc810)
7723    FIELD(L3_TXPMA_TM_4, TXPMA_TM_4_31_8_RSVD, 24, 8)
7724    FIELD(L3_TXPMA_TM_4, TM_PIPE_TX_TX_DATA_WIDTH, 5, 3)
7725    FIELD(L3_TXPMA_TM_4, TM_FORCE_PIPE_TX_TX_DATA_WIDTH, 4, 1)
7726    FIELD(L3_TXPMA_TM_4, TM_PIPE_TX_POWERDOWN_VCM_HOLD, 3, 1)
7727    FIELD(L3_TXPMA_TM_4, TM_FORCE_PIPE_TX_POWERDOWN_VCM_HOLD, 2, 1)
7728    FIELD(L3_TXPMA_TM_4, TM_PIPE_TX_ANABOOST_POWERDOWN, 1, 1)
7729    FIELD(L3_TXPMA_TM_4, ANA_PIPE_BYP0_0_RSVD, 0, 1)
7730REG32(L3_TXPMA_TM_5, 0xc814)
7731    FIELD(L3_TXPMA_TM_5, TXPMA_TM_5_31_8_RSVD, 24, 8)
7732    FIELD(L3_TXPMA_TM_5, ANA_BSCAN_BYP0_7_4_RSVD, 4, 4)
7733    FIELD(L3_TXPMA_TM_5, TM_TX_BSCAN_SEL, 3, 1)
7734    FIELD(L3_TXPMA_TM_5, TM_FORCE_TX_BSCAN_SEL, 2, 1)
7735    FIELD(L3_TXPMA_TM_5, TM_TX_BSCAN_DATA, 1, 1)
7736    FIELD(L3_TXPMA_TM_5, TM_FORCE_TX_BSCAN_DATA, 0, 1)
7737REG32(L3_TXPMA_TM_6, 0xc818)
7738    FIELD(L3_TXPMA_TM_6, TXPMA_TM_6_31_8_RSVD, 24, 8)
7739    FIELD(L3_TXPMA_TM_6, TM_TX_ENABLE_ISI_LPBK, 7, 1)
7740    FIELD(L3_TXPMA_TM_6, TM_FORCE_TX_ENABLE_ISI_LPBK, 6, 1)
7741    FIELD(L3_TXPMA_TM_6, TM_TX_ENABLE_SER_LPBK, 5, 1)
7742    FIELD(L3_TXPMA_TM_6, TM_FORCE_TX_ENABLE_SER_LPBK, 4, 1)
7743    FIELD(L3_TXPMA_TM_6, TM_TX_ENABLE_RX_LIN_LPBK, 3, 1)
7744    FIELD(L3_TXPMA_TM_6, TM_FORCE_TX_ENABLE_RX_LIN_LPBK, 2, 1)
7745    FIELD(L3_TXPMA_TM_6, TM_TX_ENABLE_RCRVD_DATA_LPBK, 1, 1)
7746    FIELD(L3_TXPMA_TM_6, TM_FORCE_TX_ENABLE_RCRVD_DATA_LPBK, 0, 1)
7747REG32(L3_TXPMA_TM_7, 0xc81c)
7748    FIELD(L3_TXPMA_TM_7, TXPMA_TM_7_31_8_RSVD, 24, 8)
7749    FIELD(L3_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_UPHY, 7, 1)
7750    FIELD(L3_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_UPHY, 6, 1)
7751    FIELD(L3_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_SERIALIZER, 5, 1)
7752    FIELD(L3_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_SERIALIZER, 4, 1)
7753    FIELD(L3_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_PIPE, 3, 1)
7754    FIELD(L3_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_PIPE, 2, 1)
7755    FIELD(L3_TXPMA_TM_7, TM_TX_ENABLE_SUPPLY_HSCLK, 1, 1)
7756    FIELD(L3_TXPMA_TM_7, TM_FORCE_TX_ENABLE_SUPPLY_HSCLK, 0, 1)
7757REG32(L3_TXPMA_TM_8, 0xc820)
7758    FIELD(L3_TXPMA_TM_8, TXPMA_TM_8_31_8_RSVD, 24, 8)
7759    FIELD(L3_TXPMA_TM_8, ANA_LS_LFPS_BYP0_7_2_RSVD, 2, 6)
7760    FIELD(L3_TXPMA_TM_8, TM_TX_LS_LFPS_DATA, 1, 1)
7761    FIELD(L3_TXPMA_TM_8, TM_FORCE_TX_LS_LFPS_DATA, 0, 1)
7762REG32(L3_TXPMA_TM_9, 0xc824)
7763    FIELD(L3_TXPMA_TM_9, TXPMA_TM_9_31_8_RSVD, 24, 8)
7764    FIELD(L3_TXPMA_TM_9, ANA_MISC0_7_RSVD, 7, 1)
7765    FIELD(L3_TXPMA_TM_9, TM_TX_SERIALIZER_MODE, 6, 1)
7766    FIELD(L3_TXPMA_TM_9, TM_FORCE_TX_SERIALIZER_MODE, 5, 1)
7767    FIELD(L3_TXPMA_TM_9, TM_TX_ENABLE_HSCLK_DIVISION, 3, 2)
7768    FIELD(L3_TXPMA_TM_9, TM_FORCE_TX_ENABLE_HSCLK_DIVISION, 2, 1)
7769    FIELD(L3_TXPMA_TM_9, TM_TX_DRIVER_POLARITY, 1, 1)
7770    FIELD(L3_TXPMA_TM_9, TM_FORCE_TX_DRIVER_POLARITY, 0, 1)
7771REG32(L3_TXPMA_TM_10, 0xc828)
7772    FIELD(L3_TXPMA_TM_10, TXPMA_TM_10_31_8_RSVD, 24, 8)
7773    FIELD(L3_TXPMA_TM_10, ANA_MISC1_7_6_RSVD, 6, 2)
7774    FIELD(L3_TXPMA_TM_10, TM_TX_ENABLE_LOWLEAKAGE, 5, 1)
7775    FIELD(L3_TXPMA_TM_10, TM_FORCE_TX_ENABLE_LOWLEAKAGE, 4, 1)
7776    FIELD(L3_TXPMA_TM_10, TM_TX_ENABLE_REF, 3, 1)
7777    FIELD(L3_TXPMA_TM_10, TM_FORCE_TX_ENABLE_REF, 2, 1)
7778    FIELD(L3_TXPMA_TM_10, TM_TX_ENABLE_LDO, 1, 1)
7779    FIELD(L3_TXPMA_TM_10, TM_FORCE_TX_ENABLE_LDO, 0, 1)
7780REG32(L3_TXPMA_TM_11, 0xc82c)
7781    FIELD(L3_TXPMA_TM_11, TXPMA_TM_11_31_8_RSVD, 24, 8)
7782    FIELD(L3_TXPMA_TM_11, ANA_VCM_BYP0_7_5_RSVD, 5, 3)
7783    FIELD(L3_TXPMA_TM_11, TM_TX_VCMHOLD_PROG, 1, 4)
7784    FIELD(L3_TXPMA_TM_11, TM_TX_VCMHOLD_OBSRV, 0, 1)
7785REG32(L3_TXPMA_TM_12, 0xc830)
7786    FIELD(L3_TXPMA_TM_12, TXPMA_TM_12_31_8_RSVD, 24, 8)
7787    FIELD(L3_TXPMA_TM_12, TM_TX_SER_POWERISLAND_OBSRV, 5, 3)
7788    FIELD(L3_TXPMA_TM_12, TM_TX_CLK_POWERISLAND_OBSRV, 1, 4)
7789    FIELD(L3_TXPMA_TM_12, ANA_PWR_ISLAND_BYP0_0_RSVD, 0, 1)
7790REG32(L3_TXPMA_TM_13, 0xc834)
7791    FIELD(L3_TXPMA_TM_13, TXPMA_TM_13_31_8_RSVD, 24, 8)
7792    FIELD(L3_TXPMA_TM_13, TM_TX_POWERISLAND_OBSRV, 0, 8)
7793REG32(L3_TXPMA_TM_14, 0xc838)
7794    FIELD(L3_TXPMA_TM_14, TXPMA_TM_14_31_8_RSVD, 24, 8)
7795    FIELD(L3_TXPMA_TM_14, ANA_MISC2_7_5_RSVD, 5, 3)
7796    FIELD(L3_TXPMA_TM_14, TM_TX_POWERISLAND_OBSRV, 3, 2)
7797    FIELD(L3_TXPMA_TM_14, PIPE_TM_TX_ANABOOST_POWER_OBSRV, 2, 1)
7798    FIELD(L3_TXPMA_TM_14, MPHY_TM_TX_ENABLE_DRIVERLDO_OBSRV, 1, 1)
7799    FIELD(L3_TXPMA_TM_14, MPHY_TM_TX_DRIVERLDO_REDC_SINKIQ, 0, 1)
7800REG32(L3_TXPMA_TM_15, 0xc83c)
7801    FIELD(L3_TXPMA_TM_15, TXPMA_TM_15_31_8_RSVD, 24, 8)
7802    FIELD(L3_TXPMA_TM_15, PIPE_TM_TX_ANABOOST_PROG_7_0, 0, 8)
7803REG32(L3_TXPMA_TM_16, 0xc840)
7804    FIELD(L3_TXPMA_TM_16, TXPMA_TM_16_31_8_RSVD, 24, 8)
7805    FIELD(L3_TXPMA_TM_16, PIPE_TM_TX_ANABOOST_PROG_15_8, 0, 8)
7806REG32(L3_TXPMA_TM_17, 0xc844)
7807    FIELD(L3_TXPMA_TM_17, TXPMA_TM_17_31_8_RSVD, 24, 8)
7808    FIELD(L3_TXPMA_TM_17, TM_TX_RSVD2, 0, 8)
7809REG32(L3_TXPMA_TM_18, 0xc848)
7810    FIELD(L3_TXPMA_TM_18, TXPMA_TM_18_31_8_RSVD, 24, 8)
7811    FIELD(L3_TXPMA_TM_18, TM_TX_ENABLE_VDDREF_CORE, 7, 1)
7812    FIELD(L3_TXPMA_TM_18, TM_FORCE_TX_ENABLE_VDDREF_CORE, 6, 1)
7813    FIELD(L3_TXPMA_TM_18, TM_TX_ENABLE_RBYRFB_CORE, 5, 1)
7814    FIELD(L3_TXPMA_TM_18, TM_FORCE_TX_ENABLE_RBYRFB_CORE, 4, 1)
7815    FIELD(L3_TXPMA_TM_18, TM_TX_ENABLE_BGREF_CORE, 3, 1)
7816    FIELD(L3_TXPMA_TM_18, TM_FORCE_TX_ENABLE_BGREF_CORE, 2, 1)
7817    FIELD(L3_TXPMA_TM_18, TM_TX_ENABLE_BGFB_CORE, 1, 1)
7818    FIELD(L3_TXPMA_TM_18, TM_FORCE_TX_ENABLE_BGFB_CORE, 0, 1)
7819REG32(L3_TXPMA_TM_19, 0xc84c)
7820    FIELD(L3_TXPMA_TM_19, TXPMA_TM_19_31_8_RSVD, 24, 8)
7821    FIELD(L3_TXPMA_TM_19, ANA_SATA_BYP0_RSVD, 6, 2)
7822    FIELD(L3_TXPMA_TM_19, TM_ZDIF_TX_SATA_OFFSET, 0, 6)
7823REG32(L3_TXPMA_TM_20, 0xc850)
7824    FIELD(L3_TXPMA_TM_20, TXPMA_TM_20_31_8_RSVD, 24, 8)
7825    FIELD(L3_TXPMA_TM_20, TM_TX_ELEC_IDLE_DELAY_ENTRY, 0, 8)
7826REG32(L3_TXPMA_TM_21, 0xc854)
7827    FIELD(L3_TXPMA_TM_21, TXPMA_TM_21_31_8_RSVD, 24, 8)
7828    FIELD(L3_TXPMA_TM_21, TM_TX_ELEC_IDLE_DELAY_EXIT, 0, 8)
7829REG32(L3_TXPMA_TM_22, 0xc858)
7830    FIELD(L3_TXPMA_TM_22, TXPMA_TM_22_31_8_RSVD, 24, 8)
7831    FIELD(L3_TXPMA_TM_22, TM_TX_ENABLE_LFPS_DELAY_ENTRY, 0, 8)
7832REG32(L3_TXPMA_TM_23, 0xc85c)
7833    FIELD(L3_TXPMA_TM_23, TXPMA_TM_23_31_8_RSVD, 24, 8)
7834    FIELD(L3_TXPMA_TM_23, TM_TX_ENABLE_LFPS_DELAY_EXIT, 0, 8)
7835REG32(L3_TXPMA_TM_24, 0xc860)
7836    FIELD(L3_TXPMA_TM_24, TXPMA_TM_24_31_8_RSVD, 24, 8)
7837    FIELD(L3_TXPMA_TM_24, ANA_MISC6_7_RSVD, 7, 1)
7838    FIELD(L3_TXPMA_TM_24, TM_TX_EN_ANA_SUBLP_MODE, 6, 1)
7839    FIELD(L3_TXPMA_TM_24, TM_FORCE_TX_EN_ANA_SUBLP_MODE, 5, 1)
7840    FIELD(L3_TXPMA_TM_24, TM_TX_EN_DIG_SUBLP_MODE, 4, 1)
7841    FIELD(L3_TXPMA_TM_24, TM_FORCE_TX_EN_DIG_SUBLP_MODE, 3, 1)
7842    FIELD(L3_TXPMA_TM_24, TM_TX_DP_LVLDB0_OVRRD, 2, 1)
7843    FIELD(L3_TXPMA_TM_24, TM_FORCE_TX_DP_LVLDB0_OVRRD, 1, 1)
7844    FIELD(L3_TXPMA_TM_24, TM_TX_CLOCK_STOP_REQ, 0, 1)
7845REG32(L3_TXPMA_TM_25, 0xc864)
7846    FIELD(L3_TXPMA_TM_25, TXPMA_TM_25_31_8_RSVD, 24, 8)
7847    FIELD(L3_TXPMA_TM_25, ANA_MISC6_7_6_RSVD, 6, 2)
7848    FIELD(L3_TXPMA_TM_25, TM_TX_WRRD_SYNC_SUP_OBSRV_PLL, 5, 1)
7849    FIELD(L3_TXPMA_TM_25, TM_TX_WRRD_SYNC_SUP_OBSRV_RX, 4, 1)
7850    FIELD(L3_TXPMA_TM_25, TM_TX_LANE_LNG, 3, 1)
7851    FIELD(L3_TXPMA_TM_25, TM_FORCE_TX_LANE_LNG, 2, 1)
7852    FIELD(L3_TXPMA_TM_25, TM_TX_LANE_MASTER, 1, 1)
7853    FIELD(L3_TXPMA_TM_25, TM_FORCE_TX_LANE_MASTER, 0, 1)
7854REG32(L3_TXPMA_TM_26, 0xc868)
7855    FIELD(L3_TXPMA_TM_26, TXPMA_TM_26_31_8_RSVD, 24, 8)
7856    FIELD(L3_TXPMA_TM_26, TM_TXPMD_APB_RESET_DELAY, 0, 8)
7857REG32(L3_TXPMA_TM_27, 0xc86c)
7858    FIELD(L3_TXPMA_TM_27, TXPMA_TM_27_31_8_RSVD, 24, 8)
7859    FIELD(L3_TXPMA_TM_27, TM_BSCAN_MODE_EN, 7, 1)
7860    FIELD(L3_TXPMA_TM_27, TM_FORCE_BSCAN_MODE_EN, 6, 1)
7861    FIELD(L3_TXPMA_TM_27, TM_PIPE_TX_FAST_EST_COMMON_MODE, 5, 1)
7862    FIELD(L3_TXPMA_TM_27, TM_FORCE_PIPE_TX_FAST_EST_COMMON_MODE, 4, 1)
7863    FIELD(L3_TXPMA_TM_27, TM_TX_PIPE_TX_ENABLE_LFPS, 3, 1)
7864    FIELD(L3_TXPMA_TM_27, TM_FORCE_TX_PIPE_TX_ENABLE_LFPS, 2, 1)
7865    FIELD(L3_TXPMA_TM_27, TM_TX_PIPE_TX_ENABLE_IDLE_MODE, 1, 1)
7866    FIELD(L3_TXPMA_TM_27, TM_FORCE_TX_PIPE_TX_ENABLE_IDLE_MODE, 0, 1)
7867REG32(L3_TXPMA_ST_0, 0xcb00)
7868    FIELD(L3_TXPMA_ST_0, TXPMA_ST_0_31_8_RSVD, 24, 8)
7869    FIELD(L3_TXPMA_ST_0, TX_PHY_MODE, 4, 4)
7870    FIELD(L3_TXPMA_ST_0, TX_PHY_GEAR, 0, 4)
7871REG32(L3_TXPMA_ST_1, 0xcb04)
7872    FIELD(L3_TXPMA_ST_1, TXPMA_ST_1_31_8_RSVD, 24, 8)
7873    FIELD(L3_TXPMA_ST_1, TX_ENABLE_HSCLK_DIVISION, 6, 2)
7874    FIELD(L3_TXPMA_ST_1, PIPE_TX_TRISTATE, 5, 1)
7875    FIELD(L3_TXPMA_ST_1, TX_ENABLE_SUPPLY_SERIALIZER, 4, 1)
7876    FIELD(L3_TXPMA_ST_1, TX_ENABLE_SUPPLY_HSCLK, 3, 1)
7877    FIELD(L3_TXPMA_ST_1, TX_ENABLE_SUPPLY_MPHY, 2, 1)
7878    FIELD(L3_TXPMA_ST_1, TX_ENABLE_SUPPLY_PIPE, 1, 1)
7879    FIELD(L3_TXPMA_ST_1, TX_ENABLE_SUPPLY_UPHY, 0, 1)
7880REG32(L3_TXPMA_ST_2, 0xcb08)
7881    FIELD(L3_TXPMA_ST_2, TXPMA_ST_2_31_8_RSVD, 24, 8)
7882    FIELD(L3_TXPMA_ST_2, ANA_ST2_7_5_SPARE, 5, 3)
7883    FIELD(L3_TXPMA_ST_2, PIPE_TX_ENABLE_RXDET, 4, 1)
7884    FIELD(L3_TXPMA_ST_2, PIPE_TX_ENABLE_IDLE_MODE, 2, 2)
7885    FIELD(L3_TXPMA_ST_2, PIPE_TX_ENABLE_LFPS, 0, 2)
7886REG32(L3_TXPMA_ST_3, 0xcb0c)
7887    FIELD(L3_TXPMA_ST_3, TXPMA_ST_3_31_8_RSVD, 24, 8)
7888    FIELD(L3_TXPMA_ST_3, ANA_ST3_7_6_SPARE, 6, 2)
7889    FIELD(L3_TXPMA_ST_3, TX_LSEG_DN_RESCAL_CODE, 0, 6)
7890REG32(L3_TXPMA_ST_4, 0xcb10)
7891    FIELD(L3_TXPMA_ST_4, TXPMA_ST_4_31_8_RSVD, 24, 8)
7892    FIELD(L3_TXPMA_ST_4, ANA_ST4_7_6_SPARE, 6, 2)
7893    FIELD(L3_TXPMA_ST_4, TX_USEG_DP_RESCAL_CODE, 0, 6)
7894REG32(L3_TXPMA_ST_5, 0xcb14)
7895    FIELD(L3_TXPMA_ST_5, TXPMA_ST_5_31_8_RSVD, 24, 8)
7896    FIELD(L3_TXPMA_ST_5, ANA_ST5_7_6_SPARE, 6, 2)
7897    FIELD(L3_TXPMA_ST_5, PIPE_TX_LOCALFS, 0, 6)
7898REG32(L3_TXPMA_ST_6, 0xcb18)
7899    FIELD(L3_TXPMA_ST_6, TXPMA_ST_6_31_8_RSVD, 24, 8)
7900    FIELD(L3_TXPMA_ST_6, ANA_ST6_7_SPARE, 7, 1)
7901    FIELD(L3_TXPMA_ST_6, PIPE_TX_LOCALTXCOEFFICIENTSVALID, 6, 1)
7902    FIELD(L3_TXPMA_ST_6, PIPE_TX_LOCALLF, 0, 6)
7903REG32(L3_TXPMA_ST_7, 0xcb1c)
7904    FIELD(L3_TXPMA_ST_7, TXPMA_ST_7_31_8_RSVD, 24, 8)
7905    FIELD(L3_TXPMA_ST_7, PIPE_TX_LOCALTXPRESETCOEFFICIENTS_7_0, 0, 8)
7906REG32(L3_TXPMA_ST_8, 0xcb20)
7907    FIELD(L3_TXPMA_ST_8, TXPMA_ST_8_31_8_RSVD, 24, 8)
7908    FIELD(L3_TXPMA_ST_8, PIPE_TX_LOCALTXPRESETCOEFFICIENTS_15_8, 0, 8)
7909REG32(L3_TXPMA_ST_9, 0xcb24)
7910    FIELD(L3_TXPMA_ST_9, TXPMA_ST_9_31_8_RSVD, 24, 8)
7911    FIELD(L3_TXPMA_ST_9, ANA_ST9_7_2_SPARE, 2, 6)
7912    FIELD(L3_TXPMA_ST_9, PIPE_TX_LOCALTXPRESETCOEFFICIENTS_17_16, 0, 2)
7913REG32(L3_TXPMD_TM_0, 0xcc00)
7914    FIELD(L3_TXPMD_TM_0, TXPMD_TM_0_31_8_RSVD, 24, 8)
7915    FIELD(L3_TXPMD_TM_0, PIPE_TM_TX_USEG_POST_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
7916    FIELD(L3_TXPMD_TM_0, PIPE_TM_TX_USEG_POST_DISABLE_ENDPOS, 0, 5)
7917REG32(L3_TXPMD_TM_1, 0xcc04)
7918    FIELD(L3_TXPMD_TM_1, TXPMD_TM_1_31_8_RSVD, 24, 8)
7919    FIELD(L3_TXPMD_TM_1, PIPE_TM_TX_USEG_POST_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
7920    FIELD(L3_TXPMD_TM_1, PIPE_TM_TX_USEG_POST_DISABLE_STARTPOS, 0, 5)
7921REG32(L3_TXPMD_TM_2, 0xcc08)
7922    FIELD(L3_TXPMD_TM_2, TXPMD_TM_2_31_8_RSVD, 24, 8)
7923    FIELD(L3_TXPMD_TM_2, PIPE_TM_TX_USEG_POST_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
7924    FIELD(L3_TXPMD_TM_2, PIPE_TM_TX_USEG_POST_EMPHASIS_ENDPOS, 0, 5)
7925REG32(L3_TXPMD_TM_3, 0xcc0c)
7926    FIELD(L3_TXPMD_TM_3, TXPMD_TM_3_31_8_RSVD, 24, 8)
7927    FIELD(L3_TXPMD_TM_3, PIPE_TM_TX_USEG_POST_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
7928    FIELD(L3_TXPMD_TM_3, PIPE_TM_TX_USEG_POST_EMPHASIS_STARTPOS, 0, 5)
7929REG32(L3_TXPMD_TM_4, 0xcc10)
7930    FIELD(L3_TXPMD_TM_4, TXPMD_TM_4_31_8_RSVD, 24, 8)
7931    FIELD(L3_TXPMD_TM_4, PIPE_TM_TX_USEG_POST_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
7932    FIELD(L3_TXPMD_TM_4, PIPE_TM_TX_USEG_POST_MAINSEL_ENDPOS, 0, 5)
7933REG32(L3_TXPMD_TM_5, 0xcc14)
7934    FIELD(L3_TXPMD_TM_5, TXPMD_TM_5_31_8_RSVD, 24, 8)
7935    FIELD(L3_TXPMD_TM_5, PIPE_TM_TX_USEG_POST_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
7936    FIELD(L3_TXPMD_TM_5, PIPE_TM_TX_USEG_POST_MAINSEL_STARTPOS, 0, 5)
7937REG32(L3_TXPMD_TM_6, 0xcc18)
7938    FIELD(L3_TXPMD_TM_6, TXPMD_TM_6_31_8_RSVD, 24, 8)
7939    FIELD(L3_TXPMD_TM_6, PIPE_TM_TX_USEG_POST_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
7940    FIELD(L3_TXPMD_TM_6, PIPE_TM_TX_USEG_POST_MARGIN_ENDPOS, 0, 5)
7941REG32(L3_TXPMD_TM_7, 0xcc1c)
7942    FIELD(L3_TXPMD_TM_7, TXPMD_TM_7_31_8_RSVD, 24, 8)
7943    FIELD(L3_TXPMD_TM_7, PIPE_TM_TX_USEG_POST_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
7944    FIELD(L3_TXPMD_TM_7, PIPE_TM_TX_USEG_POST_MARGIN_STARTPOS, 0, 5)
7945REG32(L3_TXPMD_TM_8, 0xcc20)
7946    FIELD(L3_TXPMD_TM_8, TXPMD_TM_8_31_8_RSVD, 24, 8)
7947    FIELD(L3_TXPMD_TM_8, PIPE_TM_TX_USEG_PRE_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
7948    FIELD(L3_TXPMD_TM_8, PIPE_TM_TX_USEG_PRE_DISABLE_ENDPOS, 0, 5)
7949REG32(L3_TXPMD_TM_9, 0xcc24)
7950    FIELD(L3_TXPMD_TM_9, TXPMD_TM_9_31_8_RSVD, 24, 8)
7951    FIELD(L3_TXPMD_TM_9, PIPE_TM_TX_USEG_PRE_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
7952    FIELD(L3_TXPMD_TM_9, PIPE_TM_TX_USEG_PRE_DISABLE_STARTPOS, 0, 5)
7953REG32(L3_TXPMD_TM_10, 0xcc28)
7954    FIELD(L3_TXPMD_TM_10, TXPMD_TM_10_31_8_RSVD, 24, 8)
7955    FIELD(L3_TXPMD_TM_10, PIPE_TM_TX_USEG_PRE_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
7956    FIELD(L3_TXPMD_TM_10, PIPE_TM_TX_USEG_PRE_EMPHASIS_ENDPOS, 0, 5)
7957REG32(L3_TXPMD_TM_11, 0xcc2c)
7958    FIELD(L3_TXPMD_TM_11, TXPMD_TM_11_31_8_RSVD, 24, 8)
7959    FIELD(L3_TXPMD_TM_11, PIPE_TM_TX_USEG_PRE_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
7960    FIELD(L3_TXPMD_TM_11, PIPE_TM_TX_USEG_PRE_EMPHASIS_STARTPOS, 0, 5)
7961REG32(L3_TXPMD_TM_12, 0xcc30)
7962    FIELD(L3_TXPMD_TM_12, TXPMD_TM_12_31_8_RSVD, 24, 8)
7963    FIELD(L3_TXPMD_TM_12, PIPE_TM_TX_USEG_PRE_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
7964    FIELD(L3_TXPMD_TM_12, PIPE_TM_TX_USEG_PRE_MAINSEL_ENDPOS, 0, 5)
7965REG32(L3_TXPMD_TM_13, 0xcc34)
7966    FIELD(L3_TXPMD_TM_13, TXPMD_TM_13_31_8_RSVD, 24, 8)
7967    FIELD(L3_TXPMD_TM_13, PIPE_TM_TX_USEG_PRE_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
7968    FIELD(L3_TXPMD_TM_13, PIPE_TM_TX_USEG_PRE_MAINSEL_STARTPOS, 0, 5)
7969REG32(L3_TXPMD_TM_14, 0xcc38)
7970    FIELD(L3_TXPMD_TM_14, TXPMD_TM_14_31_8_RSVD, 24, 8)
7971    FIELD(L3_TXPMD_TM_14, PIPE_TM_TX_USEG_PRE_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
7972    FIELD(L3_TXPMD_TM_14, PIPE_TM_TX_USEG_PRE_MARGIN_ENDPOS, 0, 5)
7973REG32(L3_TXPMD_TM_15, 0xcc3c)
7974    FIELD(L3_TXPMD_TM_15, TXPMD_TM_15_31_8_RSVD, 24, 8)
7975    FIELD(L3_TXPMD_TM_15, PIPE_TM_TX_USEG_PRE_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
7976    FIELD(L3_TXPMD_TM_15, PIPE_TM_TX_USEG_PRE_MARGIN_STARTPOS, 0, 5)
7977REG32(L3_TXPMD_TM_16, 0xcc40)
7978    FIELD(L3_TXPMD_TM_16, TXPMD_TM_16_31_8_RSVD, 24, 8)
7979    FIELD(L3_TXPMD_TM_16, PIPE_TM_TX_LSEG_POST_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
7980    FIELD(L3_TXPMD_TM_16, PIPE_TM_TX_LSEG_POST_DISABLE_ENDPOS, 0, 5)
7981REG32(L3_TXPMD_TM_17, 0xcc44)
7982    FIELD(L3_TXPMD_TM_17, TXPMD_TM_17_31_8_RSVD, 24, 8)
7983    FIELD(L3_TXPMD_TM_17, PIPE_TM_TX_LSEG_POST_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
7984    FIELD(L3_TXPMD_TM_17, PIPE_TM_TX_LSEG_POST_DISABLE_STARTPOS, 0, 5)
7985REG32(L3_TXPMD_TM_18, 0xcc48)
7986    FIELD(L3_TXPMD_TM_18, TXPMD_TM_18_31_8_RSVD, 24, 8)
7987    FIELD(L3_TXPMD_TM_18, PIPE_TM_TX_LSEG_POST_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
7988    FIELD(L3_TXPMD_TM_18, PIPE_TM_TX_LSEG_POST_EMPHASIS_ENDPOS, 0, 5)
7989REG32(L3_TXPMD_TM_19, 0xcc4c)
7990    FIELD(L3_TXPMD_TM_19, TXPMD_TM_19_31_8_RSVD, 24, 8)
7991    FIELD(L3_TXPMD_TM_19, PIPE_TM_TX_LSEG_POST_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
7992    FIELD(L3_TXPMD_TM_19, PIPE_TM_TX_LSEG_POST_EMPHASIS_STARTPOS, 0, 5)
7993REG32(L3_TXPMD_TM_20, 0xcc50)
7994    FIELD(L3_TXPMD_TM_20, TXPMD_TM_20_31_8_RSVD, 24, 8)
7995    FIELD(L3_TXPMD_TM_20, PIPE_TM_TX_LSEG_POST_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
7996    FIELD(L3_TXPMD_TM_20, PIPE_TM_TX_LSEG_POST_MAINSEL_ENDPOS, 0, 5)
7997REG32(L3_TXPMD_TM_21, 0xcc54)
7998    FIELD(L3_TXPMD_TM_21, TXPMD_TM_21_31_8_RSVD, 24, 8)
7999    FIELD(L3_TXPMD_TM_21, PIPE_TM_TX_LSEG_POST_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
8000    FIELD(L3_TXPMD_TM_21, PIPE_TM_TX_LSEG_POST_MAINSEL_STARTPOS, 0, 5)

8001REG32(L3_TXPMD_TM_22, 0xcc58)
8002    FIELD(L3_TXPMD_TM_22, TXPMD_TM_22_31_8_RSVD, 24, 8)
8003    FIELD(L3_TXPMD_TM_22, PIPE_TM_TX_LSEG_POST_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
8004    FIELD(L3_TXPMD_TM_22, PIPE_TM_TX_LSEG_POST_MARGIN_ENDPOS, 0, 5)
8005REG32(L3_TXPMD_TM_23, 0xcc5c)
8006    FIELD(L3_TXPMD_TM_23, TXPMD_TM_23_31_8_RSVD, 24, 8)
8007    FIELD(L3_TXPMD_TM_23, PIPE_TM_TX_LSEG_POST_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
8008    FIELD(L3_TXPMD_TM_23, PIPE_TM_TX_LSEG_POST_MARGIN_STARTPOS, 0, 5)
8009REG32(L3_TXPMD_TM_24, 0xcc60)
8010    FIELD(L3_TXPMD_TM_24, TXPMD_TM_24_31_8_RSVD, 24, 8)
8011    FIELD(L3_TXPMD_TM_24, PIPE_TM_TX_LSEG_PRE_DISABLE_ENDPOS_7_5_RSVD, 5, 3)
8012    FIELD(L3_TXPMD_TM_24, PIPE_TM_TX_LSEG_PRE_DISABLE_ENDPOS, 0, 5)
8013REG32(L3_TXPMD_TM_25, 0xcc64)
8014    FIELD(L3_TXPMD_TM_25, TXPMD_TM_25_31_8_RSVD, 24, 8)
8015    FIELD(L3_TXPMD_TM_25, PIPE_TM_TX_LSEG_PRE_DISABLE_STARTPOS_7_5_RSVD, 5, 3)
8016    FIELD(L3_TXPMD_TM_25, PIPE_TM_TX_LSEG_PRE_DISABLE_STARTPOS, 0, 5)
8017REG32(L3_TXPMD_TM_26, 0xcc68)
8018    FIELD(L3_TXPMD_TM_26, TXPMD_TM_26_31_8_RSVD, 24, 8)
8019    FIELD(L3_TXPMD_TM_26, PIPE_TM_TX_LSEG_PRE_EMPHASIS_ENDPOS_7_5_RSVD, 5, 3)
8020    FIELD(L3_TXPMD_TM_26, PIPE_TM_TX_LSEG_PRE_EMPHASIS_ENDPOS, 0, 5)
8021REG32(L3_TXPMD_TM_27, 0xcc6c)
8022    FIELD(L3_TXPMD_TM_27, TXPMD_TM_27_31_8_RSVD, 24, 8)
8023    FIELD(L3_TXPMD_TM_27, PIPE_TM_TX_LSEG_PRE_EMPHASIS_STARTPOS_7_5_RSVD, 5, 3)
8024    FIELD(L3_TXPMD_TM_27, PIPE_TM_TX_LSEG_PRE_EMPHASIS_STARTPOS, 0, 5)
8025REG32(L3_TXPMD_TM_28, 0xcc70)
8026    FIELD(L3_TXPMD_TM_28, TXPMD_TM_28_31_8_RSVD, 24, 8)
8027    FIELD(L3_TXPMD_TM_28, PIPE_TM_TX_LSEG_PRE_MAINSEL_ENDPOS_7_5_RSVD, 5, 3)
8028    FIELD(L3_TXPMD_TM_28, PIPE_TM_TX_LSEG_PRE_MAINSEL_ENDPOS, 0, 5)
8029REG32(L3_TXPMD_TM_29, 0xcc74)
8030    FIELD(L3_TXPMD_TM_29, TXPMD_TM_29_31_8_RSVD, 24, 8)
8031    FIELD(L3_TXPMD_TM_29, PIPE_TM_TX_LSEG_PRE_MAINSEL_STARTPOS_7_5_RSVD, 5, 3)
8032    FIELD(L3_TXPMD_TM_29, PIPE_TM_TX_LSEG_PRE_MAINSEL_STARTPOS, 0, 5)
8033REG32(L3_TXPMD_TM_30, 0xcc78)
8034    FIELD(L3_TXPMD_TM_30, TXPMD_TM_30_31_8_RSVD, 24, 8)
8035    FIELD(L3_TXPMD_TM_30, PIPE_TM_TX_LSEG_PRE_MARGIN_ENDPOS_7_5_RSVD, 5, 3)
8036    FIELD(L3_TXPMD_TM_30, PIPE_TM_TX_LSEG_PRE_MARGIN_ENDPOS, 0, 5)
8037REG32(L3_TXPMD_TM_31, 0xcc7c)
8038    FIELD(L3_TXPMD_TM_31, TXPMD_TM_31_31_8_RSVD, 24, 8)
8039    FIELD(L3_TXPMD_TM_31, PIPE_TM_TX_LSEG_PRE_MARGIN_STARTPOS_7_5_RSVD, 5, 3)
8040    FIELD(L3_TXPMD_TM_31, PIPE_TM_TX_LSEG_PRE_MARGIN_STARTPOS, 0, 5)
8041REG32(L3_TXPMD_TM_32, 0xcc80)
8042    FIELD(L3_TXPMD_TM_32, TXPMD_TM_32_31_8_RSVD, 24, 8)
8043    FIELD(L3_TXPMD_TM_32, PIPE_TM_TX_PRE_FS_DIVISION_COEF_7_0, 0, 8)
8044REG32(L3_TXPMD_TM_33, 0xcc84)
8045    FIELD(L3_TXPMD_TM_33, TXPMD_TM_33_31_8_RSVD, 24, 8)
8046    FIELD(L3_TXPMD_TM_33, PIPE_TM_TX_PRE_FS_DIVISION_COEF_15_8, 0, 8)
8047REG32(L3_TXPMD_TM_34, 0xcc88)
8048    FIELD(L3_TXPMD_TM_34, TXPMD_TM_34_31_8_RSVD, 24, 8)
8049    FIELD(L3_TXPMD_TM_34, PIPE_TM_TX_MAIN_FS_DIVISION_COEF_7_0, 0, 8)
8050REG32(L3_TXPMD_TM_35, 0xcc8c)
8051    FIELD(L3_TXPMD_TM_35, TXPMD_TM_35_31_8_RSVD, 24, 8)
8052    FIELD(L3_TXPMD_TM_35, PIPE_TM_TX_MAIN_FS_DIVISION_COEF_15_8, 0, 8)
8053REG32(L3_TXPMD_TM_36, 0xcc90)
8054    FIELD(L3_TXPMD_TM_36, TXPMD_TM_36_31_8_RSVD, 24, 8)
8055    FIELD(L3_TXPMD_TM_36, PIPE_TM_TX_POST_FS_DIVISION_COEF_7_0, 0, 8)
8056REG32(L3_TXPMD_TM_37, 0xcc94)
8057    FIELD(L3_TXPMD_TM_37, TXPMD_TM_37_31_8_RSVD, 24, 8)
8058    FIELD(L3_TXPMD_TM_37, PIPE_TM_TX_POST_FS_DIVISION_COEF_15_8, 0, 8)
8059REG32(L3_TXPMD_TM_38, 0xcc98)
8060    FIELD(L3_TXPMD_TM_38, TXPMD_TM_38_31_8_RSVD, 24, 8)
8061    FIELD(L3_TXPMD_TM_38, ANA_MISC0_7_RSVD, 7, 1)
8062    FIELD(L3_TXPMD_TM_38, PIPE_TM_TX_ENABLE_SWNW_CNTRL_BYP, 6, 1)
8063    FIELD(L3_TXPMD_TM_38, PIPE_TM_TX_ENABLE_TRISTATE_BYP, 5, 1)
8064    FIELD(L3_TXPMD_TM_38, PIPE_TM_TX_TRISTATE, 4, 1)
8065    FIELD(L3_TXPMD_TM_38, TM_TX_DRIVERLDO_RXDET_BYP, 3, 1)
8066    FIELD(L3_TXPMD_TM_38, TM_TX_DRIVERLDO_IDLE_BYP, 2, 1)
8067    FIELD(L3_TXPMD_TM_38, TM_TX_DRIVERLDO_EN_RXDET_BYP, 1, 1)
8068    FIELD(L3_TXPMD_TM_38, TM_TX_DRIVERLDO_EN_IDLE_BYP, 0, 1)
8069REG32(L3_TXPMD_TM_39, 0xcc9c)
8070    FIELD(L3_TXPMD_TM_39, TXPMD_TM_39_31_8_RSVD, 24, 8)
8071    FIELD(L3_TXPMD_TM_39, ANA_MPHY_BYP0_7_3_RSVD, 3, 5)
8072    FIELD(L3_TXPMD_TM_39, MPHY_TM_TX_OVRD_DEEMPH_TRIM, 2, 1)
8073    FIELD(L3_TXPMD_TM_39, MPHY_TM_TX_ENABLE_DEEMPH, 1, 1)
8074    FIELD(L3_TXPMD_TM_39, MPHY_TM_TX_OVRD_ENABLE_DEEMPH, 0, 1)
8075REG32(L3_TXPMD_TM_40, 0xcca0)
8076    FIELD(L3_TXPMD_TM_40, TXPMD_TM_40_31_8_RSVD, 24, 8)
8077    FIELD(L3_TXPMD_TM_40, MPHY_TM_TX_DEEMPH_TRIM_7_0, 0, 8)
8078REG32(L3_TXPMD_TM_41, 0xcca4)
8079    FIELD(L3_TXPMD_TM_41, TXPMD_TM_41_31_8_RSVD, 24, 8)
8080    FIELD(L3_TXPMD_TM_41, MPHY_TM_TX_DEEMPH_TRIM_15_8, 0, 8)
8081REG32(L3_TXPMD_TM_42, 0xcca8)
8082    FIELD(L3_TXPMD_TM_42, TXPMD_TM_42_31_8_RSVD, 24, 8)
8083    FIELD(L3_TXPMD_TM_42, ANA_MPHY_BYP3_7_5_RSVD, 5, 3)
8084    FIELD(L3_TXPMD_TM_42, MPHY_TM_TX_OVRD_LS_DATA, 1, 4)
8085    FIELD(L3_TXPMD_TM_42, MPHY_TM_TX_ENABLE_OVRD_LS_DATA, 0, 1)
8086REG32(L3_TXPMD_TM_43, 0xccac)
8087    FIELD(L3_TXPMD_TM_43, TXPMD_TM_43_31_8_RSVD, 24, 8)
8088    FIELD(L3_TXPMD_TM_43, ANA_MPHY_BYP4_7_4_RSVD, 4, 4)
8089    FIELD(L3_TXPMD_TM_43, MPHY_TM_TX_OVRD_LS_DATA_BAR, 0, 4)
8090REG32(L3_TXPMD_TM_44, 0xccb0)
8091    FIELD(L3_TXPMD_TM_44, TXPMD_TM_44_31_8_RSVD, 24, 8)
8092    FIELD(L3_TXPMD_TM_44, ANA_PIPE_BYP38_7_6_RSVD, 6, 2)
8093    FIELD(L3_TXPMD_TM_44, PIPE_TM_TX_EN_PRE_LFPS_PATH, 5, 1)
8094    FIELD(L3_TXPMD_TM_44, PIPE_TM_TX_OVRD_EN_PRE_LFPS_PATH, 4, 1)
8095    FIELD(L3_TXPMD_TM_44, PIPE_TM_TX_EN_POST_LFPS_PATH, 3, 1)
8096    FIELD(L3_TXPMD_TM_44, PIPE_TM_TX_OVRD_EN_POST_LFPS_PATH, 2, 1)
8097    FIELD(L3_TXPMD_TM_44, PIPE_TM_TX_EN_MAIN_LFPS_PATH, 1, 1)
8098    FIELD(L3_TXPMD_TM_44, PIPE_TM_TX_OVRD_EN_MAIN_LFPS_PATH, 0, 1)
8099REG32(L3_TXPMD_TM_45, 0xccb4)
8100    FIELD(L3_TXPMD_TM_45, TXPMD_TM_45_31_8_RSVD, 24, 8)
8101    FIELD(L3_TXPMD_TM_45, ANA_DP_BYP0_7_6_RSVD, 6, 2)
8102    FIELD(L3_TXPMD_TM_45, DP_TM_TX_DP_ENABLE_POST2_PATH, 5, 1)
8103    FIELD(L3_TXPMD_TM_45, DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH, 4, 1)
8104    FIELD(L3_TXPMD_TM_45, DP_TM_TX_DP_ENABLE_POST1_PATH, 3, 1)
8105    FIELD(L3_TXPMD_TM_45, DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH, 2, 1)
8106    FIELD(L3_TXPMD_TM_45, DP_TM_TX_DP_ENABLE_MAIN_PATH, 1, 1)
8107    FIELD(L3_TXPMD_TM_45, DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH, 0, 1)
8108REG32(L3_TXPMD_TM_46, 0xccb8)
8109    FIELD(L3_TXPMD_TM_46, TXPMD_TM_46_31_8_RSVD, 24, 8)
8110    FIELD(L3_TXPMD_TM_46, ANA_PIPE_BYP39_7_6_RSVD, 6, 2)
8111    FIELD(L3_TXPMD_TM_46, PIPE_TM_TX_PIPE_ENABLE_PRE_PATH, 5, 1)
8112    FIELD(L3_TXPMD_TM_46, PIPE_TM_TX_OVRD_PIPE_ENABLE_PRE_PATH, 4, 1)
8113    FIELD(L3_TXPMD_TM_46, PIPE_TM_TX_PIPE_ENABLE_POST_PATH, 3, 1)
8114    FIELD(L3_TXPMD_TM_46, PIPE_TM_TX_OVRD_PIPE_ENABLE_POST_PATH, 2, 1)
8115    FIELD(L3_TXPMD_TM_46, PIPE_TM_TX_PIPE_ENABLE_MAIN_PATH, 1, 1)
8116    FIELD(L3_TXPMD_TM_46, PIPE_TM_TX_OVRD_PIPE_ENABLE_MAIN_PATH, 0, 1)
8117REG32(L3_TXPMD_TM_47, 0xccbc)
8118    FIELD(L3_TXPMD_TM_47, TXPMD_TM_47_31_8_RSVD, 24, 8)
8119    FIELD(L3_TXPMD_TM_47, TM_TX_RSVD1, 0, 8)
8120REG32(L3_TXPMD_TM_48, 0xccc0)
8121    FIELD(L3_TXPMD_TM_48, TXPMD_TM_48_31_8_RSVD, 24, 8)
8122    FIELD(L3_TXPMD_TM_48, ANA_MISC2_7_6_RSVD, 6, 2)
8123    FIELD(L3_TXPMD_TM_48, TM_FORCE_RESULTANT_MARGINING_FACTOR, 5, 1)
8124    FIELD(L3_TXPMD_TM_48, TM_RESULTANT_MARGINING_FACTOR, 0, 5)
8125REG32(L3_TM_ANA_BYP_1, 0xd004)
8126    FIELD(L3_TM_ANA_BYP_1, TM_ANA_BYP_1_31_8_RSVD, 24, 8)
8127    FIELD(L3_TM_ANA_BYP_1, MPHY_PWM_DES_PDZ, 7, 1)
8128    FIELD(L3_TM_ANA_BYP_1, FORCE_MPHY_PWM_DES_PDZ, 6, 1)
8129    FIELD(L3_TM_ANA_BYP_1, MPHY_PWMB_SYS_ENABLE, 5, 1)
8130    FIELD(L3_TM_ANA_BYP_1, FORCE_MPHY_PWMB_SYS_ENABLE, 4, 1)
8131    FIELD(L3_TM_ANA_BYP_1, MPHY_PSO_SQUELCH, 3, 1)
8132    FIELD(L3_TM_ANA_BYP_1, FORCE_MPHY_PSO_SQUELCH, 2, 1)
8133    FIELD(L3_TM_ANA_BYP_1, MPHY_PSO_LSRX, 1, 1)
8134    FIELD(L3_TM_ANA_BYP_1, FORCE_MPHY_PSO_LSRX, 0, 1)
8135REG32(L3_TM_ANA_BYP_2, 0xd008)
8136    FIELD(L3_TM_ANA_BYP_2, TM_ANA_BYP_2_31_8_RSVD, 24, 8)
8137    FIELD(L3_TM_ANA_BYP_2, MPHY_PWM_LSPREAMP_PD, 7, 1)
8138    FIELD(L3_TM_ANA_BYP_2, FORCE_MPHY_PWM_LSPREAMP_PD, 6, 1)
8139    FIELD(L3_TM_ANA_BYP_2, MPHY_PWM_GEAR_SEL, 3, 3)
8140    FIELD(L3_TM_ANA_BYP_2, FORCE_MPHY_PWM_GEAR_SEL, 2, 1)
8141    FIELD(L3_TM_ANA_BYP_2, MPHY_PWM_DET_PD, 1, 1)
8142    FIELD(L3_TM_ANA_BYP_2, FORCE_MPHY_PWM_DET_PD, 0, 1)
8143REG32(L3_TM_ANA_BYP_3, 0xd00c)
8144    FIELD(L3_TM_ANA_BYP_3, TM_ANA_BYP_3_31_8_RSVD, 24, 8)
8145    FIELD(L3_TM_ANA_BYP_3, MPHY_RX_MASK_BURST_START, 7, 1)
8146    FIELD(L3_TM_ANA_BYP_3, FORCE_MPHY_RX_MASK_BURST_START, 6, 1)
8147    FIELD(L3_TM_ANA_BYP_3, MPHY_RX_GATE_SYMBOL_CLK, 5, 1)
8148    FIELD(L3_TM_ANA_BYP_3, FORCE_MPHY_RX_GATE_SYMBOL_CLK, 4, 1)
8149    FIELD(L3_TM_ANA_BYP_3, MPHY_PWM_PREAMP_BIAS_PD, 3, 1)
8150    FIELD(L3_TM_ANA_BYP_3, FORCE_MPHY_PWM_PREAMP_BIAS_PD, 2, 1)
8151    FIELD(L3_TM_ANA_BYP_3, MPHY_PWM_LSPREAMP_STANDBYSLEEPSTALL, 1, 1)
8152    FIELD(L3_TM_ANA_BYP_3, FORCE_MPHY_PWM_LSPREAMP_STANDBYSLEEPSTAL, 0, 1)
8153REG32(L3_TM_ANA_BYP_4, 0xd010)
8154    FIELD(L3_TM_ANA_BYP_4, TM_ANA_BYP_4_31_8_RSVD, 24, 8)
8155    FIELD(L3_TM_ANA_BYP_4, HSRX_RSTB, 7, 1)
8156    FIELD(L3_TM_ANA_BYP_4, FORCE_HSRX_RSTB, 6, 1)
8157    FIELD(L3_TM_ANA_BYP_4, MPHY_RX_TERM_ENABLE, 5, 1)
8158    FIELD(L3_TM_ANA_BYP_4, FORCE_MPHY_RX_TERM_ENABLE, 4, 1)
8159    FIELD(L3_TM_ANA_BYP_4, MPHY_RX_MUX_TYP1B_TYP2, 3, 1)
8160    FIELD(L3_TM_ANA_BYP_4, FORCE_MPHY_RX_MUX_TYP1B_TYP2, 2, 1)
8161    FIELD(L3_TM_ANA_BYP_4, MPHY_RX_MUX_HSB_LS, 1, 1)
8162    FIELD(L3_TM_ANA_BYP_4, FORCE_MPHY_RX_MUX_HSB_LS, 0, 1)
8163REG32(L3_TM_ANA_BYP_5, 0xd014)
8164    FIELD(L3_TM_ANA_BYP_5, TM_ANA_BYP_5_31_8_RSVD, 24, 8)
8165    FIELD(L3_TM_ANA_BYP_5, MPHY_SQ_SWAP_POLARITY, 5, 1)
8166    FIELD(L3_TM_ANA_BYP_5, FORCE_MPHY_SQ_SWAP_POLARITY, 4, 1)
8167    FIELD(L3_TM_ANA_BYP_5, MPHY_SQ_PD, 3, 1)
8168    FIELD(L3_TM_ANA_BYP_5, FORCE_MPHY_SQ_PD, 2, 1)
8169    FIELD(L3_TM_ANA_BYP_5, MPHY_SQ_DETECTOR_PD, 1, 1)
8170    FIELD(L3_TM_ANA_BYP_5, FORCE_MPHY_SQ_DETECTOR_PD, 0, 1)
8171REG32(L3_TM_ANA_BYP_7, 0xd018)
8172    FIELD(L3_TM_ANA_BYP_7, TM_ANA_BYP_7_31_8_RSVD, 24, 8)
8173    FIELD(L3_TM_ANA_BYP_7, PIPE_RXEQTRAINING, 7, 1)
8174    FIELD(L3_TM_ANA_BYP_7, FORCE_PIPE_RXEQTRAINING, 6, 1)
8175    FIELD(L3_TM_ANA_BYP_7, PIPE_RX_TERM_ENABLE, 5, 1)
8176    FIELD(L3_TM_ANA_BYP_7, FORCE_PIPE_RX_TERM_ENABLE, 4, 1)
8177REG32(L3_TM_ANA_BYP_8, 0xd01c)
8178    FIELD(L3_TM_ANA_BYP_8, TM_ANA_BYP_8_31_8_RSVD, 24, 8)
8179    FIELD(L3_TM_ANA_BYP_8, UPHY_BIASGEN_IRCONST_IO_MIRROR_ENABLE, 7, 1)
8180    FIELD(L3_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_IRCONST_IO_MIRROR_ENABLE, 6, 1)
8181    FIELD(L3_TM_ANA_BYP_8, UPHY_BIASGEN_IRCONST_CORE_MIRROR_ENABLE, 5, 1)
8182    FIELD(L3_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_IRCONST_CORE_MIRROR_ENABLE, 4, 1)
8183    FIELD(L3_TM_ANA_BYP_8, UPHY_BIASGEN_ICONST_IO_MIRROR_ENABLE, 3, 1)
8184    FIELD(L3_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_ICONST_IO_MIRROR_ENABLE, 2, 1)
8185    FIELD(L3_TM_ANA_BYP_8, UPHY_BIASGEN_ICONST_CORE_MIRROR_ENABLE, 1, 1)
8186    FIELD(L3_TM_ANA_BYP_8, FORCE_UPHY_BIASGEN_ICONST_CORE_MIRROR_ENABLE, 0, 1)
8187REG32(L3_TM_ANA_BYP_9, 0xd020)
8188    FIELD(L3_TM_ANA_BYP_9, TM_ANA_BYP_9_31_8_RSVD, 24, 8)
8189    FIELD(L3_TM_ANA_BYP_9, UPHY_RECLPBK_CLK_DATAZ_ENABLE_CORE, 7, 1)
8190    FIELD(L3_TM_ANA_BYP_9, FORCE_UPHY_RECLPBK_CLK_DATAZ_ENABLE_CORE, 6, 1)
8191    FIELD(L3_TM_ANA_BYP_9, UPHY_PSO_SAMP_LPBK, 5, 1)
8192    FIELD(L3_TM_ANA_BYP_9, FORCE_UPHY_PSO_SAMP_LPBK, 4, 1)
8193    FIELD(L3_TM_ANA_BYP_9, UPHY_EQ_LPBK_ENABLE_CORE, 3, 1)
8194    FIELD(L3_TM_ANA_BYP_9, FORCE_UPHY_EQ_LPBK_ENABLE_CORE, 2, 1)
8195    FIELD(L3_TM_ANA_BYP_9, UPHY_EQ_AC_DCZ_COUPLED_CORE, 1, 1)
8196    FIELD(L3_TM_ANA_BYP_9, FORCE_UPHY_EQ_AC_DCZ_COUPLED_CORE, 0, 1)
8197REG32(L3_TM_ANA_BYP_10, 0xd024)
8198    FIELD(L3_TM_ANA_BYP_10, TM_ANA_BYP_10_31_8_RSVD, 24, 8)
8199    FIELD(L3_TM_ANA_BYP_10, UPHY_LPBK_CLK_DATA_SEL, 5, 1)
8200    FIELD(L3_TM_ANA_BYP_10, UPHY_LPBK_CENTRE_EDGEZ_ENABLE_CORE, 4, 1)
8201    FIELD(L3_TM_ANA_BYP_10, UPHY_HSRX_LPBK_SEL, 1, 3)
8202    FIELD(L3_TM_ANA_BYP_10, FORCE_UPHY_HSRX_LPBK_SEL, 0, 1)
8203REG32(L3_TM_ANA_BYP_11, 0xd028)
8204    FIELD(L3_TM_ANA_BYP_11, TM_ANA_BYP_11_31_8_RSVD, 24, 8)
8205    FIELD(L3_TM_ANA_BYP_11, UPHY_PD_PI_DIV_PATH, 5, 1)
8206    FIELD(L3_TM_ANA_BYP_11, UPHY_PSO_CLK_LANE, 4, 1)
8207    FIELD(L3_TM_ANA_BYP_11, FORCE_UPHY_PSO_CLK_LANE, 3, 1)
8208    FIELD(L3_TM_ANA_BYP_11, UPHY_HSCLK_DIVISION_FACTOR, 1, 2)
8209    FIELD(L3_TM_ANA_BYP_11, FORCE_UPHY_HSCLK_DIVISION_FACTOR, 0, 1)
8210REG32(L3_TM_ANA_BYP_12, 0xd02c)
8211    FIELD(L3_TM_ANA_BYP_12, TM_ANA_BYP_12_31_8_RSVD, 24, 8)
8212    FIELD(L3_TM_ANA_BYP_12, UPHY_PSO_HSRXDIG, 7, 1)
8213    FIELD(L3_TM_ANA_BYP_12, FORCE_UPHY_PSO_HSRXDIG, 6, 1)
8214    FIELD(L3_TM_ANA_BYP_12, UPHY_PDN_HS_DES, 5, 1)
8215    FIELD(L3_TM_ANA_BYP_12, FORCE_UPHY_PDN_HS_DES, 4, 1)
8216    FIELD(L3_TM_ANA_BYP_12, UPHY_RST_GF_MUX, 3, 1)
8217    FIELD(L3_TM_ANA_BYP_12, FORCE_UPHY_RST_GF_MUX, 2, 1)
8218    FIELD(L3_TM_ANA_BYP_12, UPHY_ENABLE_CDR, 1, 1)
8219    FIELD(L3_TM_ANA_BYP_12, FORCE_UPHY_ENABLE_CDR, 0, 1)
8220REG32(L3_TM_ANA_BYP_13, 0xd030)
8221    FIELD(L3_TM_ANA_BYP_13, TM_ANA_BYP_13_31_8_RSVD, 24, 8)
8222    FIELD(L3_TM_ANA_BYP_13, UPHY_PSO_SAMP_FLOPS, 1, 1)
8223    FIELD(L3_TM_ANA_BYP_13, FORCE_UPHY_PSO_SAMP_FLOPS, 0, 1)
8224REG32(L3_TM_ANA_BYP_14, 0xd034)
8225    FIELD(L3_TM_ANA_BYP_14, TM_ANA_BYP_14_31_8_RSVD, 24, 8)
8226    FIELD(L3_TM_ANA_BYP_14, UPHY_PSO_EPI, 7, 1)
8227    FIELD(L3_TM_ANA_BYP_14, FORCE_UPHY_PSO_EPI, 6, 1)
8228    FIELD(L3_TM_ANA_BYP_14, UPHY_PD_SAMP_C2C_ECLK, 5, 1)
8229    FIELD(L3_TM_ANA_BYP_14, FORCE_UPHY_PD_SAMP_C2C_ECLK, 4, 1)
8230    FIELD(L3_TM_ANA_BYP_14, UPHY_PSO_IQPI, 1, 1)
8231    FIELD(L3_TM_ANA_BYP_14, FORCE_UPHY_PSO_IQPI, 0, 1)
8232REG32(L3_TM_ANA_BYP_15, 0xd038)
8233    FIELD(L3_TM_ANA_BYP_15, TM_ANA_BYP_15_31_8_RSVD, 24, 8)
8234    FIELD(L3_TM_ANA_BYP_15, UPHY_ENABLE_LOW_LEAKAGE, 7, 1)
8235    FIELD(L3_TM_ANA_BYP_15, FORCE_UPHY_ENABLE_LOW_LEAKAGE, 6, 1)
8236    FIELD(L3_TM_ANA_BYP_15, UPHY_PD_SAMP_C2C, 5, 1)
8237    FIELD(L3_TM_ANA_BYP_15, FORCE_UPHY_PD_SAMP_C2C, 4, 1)
8238    FIELD(L3_TM_ANA_BYP_15, UPHY_PSO_CORE_EQ, 3, 1)
8239    FIELD(L3_TM_ANA_BYP_15, FORCE_UPHY_PSO_CORE_EQ, 2, 1)
8240    FIELD(L3_TM_ANA_BYP_15, UPHY_PSO_IO_EQ, 1, 1)
8241    FIELD(L3_TM_ANA_BYP_15, FORCE_UPHY_PSO_IO_EQ, 0, 1)
8242REG32(L3_TM_ANA_BYP_16, 0xd03c)
8243    FIELD(L3_TM_ANA_BYP_16, TM_ANA_BYP_16_31_8_RSVD, 24, 8)
8244    FIELD(L3_TM_ANA_BYP_16, UPHY_PSO_SIGDET, 7, 1)
8245    FIELD(L3_TM_ANA_BYP_16, FORCE_UPHY_PSO_SIGDET, 6, 1)
8246    FIELD(L3_TM_ANA_BYP_16, UPHY_RX_LANE_POLARITY_SWAP, 5, 1)
8247    FIELD(L3_TM_ANA_BYP_16, FORCE_UPHY_RX_LANE_POLARITY_SWAP, 4, 1)
8248    FIELD(L3_TM_ANA_BYP_16, UPHY_RUN_CALIB, 3, 1)
8249    FIELD(L3_TM_ANA_BYP_16, FORCE_UPHY_RUN_CALIB, 2, 1)
8250    FIELD(L3_TM_ANA_BYP_16, UPHY_RESTORE_CALCODE, 1, 1)
8251    FIELD(L3_TM_ANA_BYP_16, FORCE_UPHY_RESTORE_CALCODE, 0, 1)
8252REG32(L3_TM_ANA_BYP_17, 0xd040)
8253    FIELD(L3_TM_ANA_BYP_17, TM_ANA_BYP_17_31_8_RSVD, 24, 8)
8254    FIELD(L3_TM_ANA_BYP_17, UPHY_STARTLOOP_PLL, 6, 1)
8255    FIELD(L3_TM_ANA_BYP_17, FORCE_UPHY_STARTLOOP_PLL, 5, 1)
8256    FIELD(L3_TM_ANA_BYP_17, UPHY_RX_RESCALIB_CODE, 1, 4)
8257    FIELD(L3_TM_ANA_BYP_17, FORCE_UPHY_RX_RESCALIB_CODE, 0, 1)
8258REG32(L3_TM_ANA_BYP_18, 0xd044)
8259    FIELD(L3_TM_ANA_BYP_18, TM_ANA_BYP_18_31_8_RSVD, 24, 8)
8260    FIELD(L3_TM_ANA_BYP_18, FORCE_UPHY_RESTORE_CALCODE_DATA, 3, 1)
8261    FIELD(L3_TM_ANA_BYP_18, FORCE_UPHY_RX_PMA_OPMODE, 2, 1)
8262    FIELD(L3_TM_ANA_BYP_18, UPHY_PSO_LFPSBCN, 1, 1)
8263    FIELD(L3_TM_ANA_BYP_18, FORCE_UPHY_PSO_LFPSBCN, 0, 1)
8264REG32(L3_TM_ANA_BYP_20, 0xd048)
8265    FIELD(L3_TM_ANA_BYP_20, TM_ANA_BYP_20_31_8_RSVD, 24, 8)
8266    FIELD(L3_TM_ANA_BYP_20, UPHY_RX_PMA_OPMODE, 0, 8)
8267REG32(L3_TM_ANA_BYP_21, 0xd04c)
8268    FIELD(L3_TM_ANA_BYP_21, TM_ANA_BYP_21_31_8_RSVD, 24, 8)
8269    FIELD(L3_TM_ANA_BYP_21, UPHY_RESTORE_CALCODE_DATA, 0, 8)
8270REG32(L3_TM_ANA_BYP_22, 0xd050)
8271    FIELD(L3_TM_ANA_BYP_22, TM_ANA_BYP_22_31_8_RSVD, 24, 8)
8272    FIELD(L3_TM_ANA_BYP_22, ISO_HSRX_CTRL_BAR, 7, 1)
8273    FIELD(L3_TM_ANA_BYP_22, FORCE_ISO_HSRX_CTRL_BAR, 6, 1)
8274    FIELD(L3_TM_ANA_BYP_22, HSRX_CLOCK_STOP_REQ, 5, 1)
8275    FIELD(L3_TM_ANA_BYP_22, FORCE_HSRX_CLOCK_STOP_REQ, 4, 1)
8276    FIELD(L3_TM_ANA_BYP_22, UPHY_SBRX_RUN_CALIB, 3, 1)
8277    FIELD(L3_TM_ANA_BYP_22, FORCE_UPHY_SBRX_RUN_CALIB, 2, 1)
8278    FIELD(L3_TM_ANA_BYP_22, RXPMA_RSTB, 1, 1)
8279    FIELD(L3_TM_ANA_BYP_22, FORCE_RXPMA_RSTB, 0, 1)
8280REG32(L3_TM_ANA_BYP_23, 0xd054)
8281    FIELD(L3_TM_ANA_BYP_23, TM_ANA_BYP_23_31_8_RSVD, 24, 8)
8282    FIELD(L3_TM_ANA_BYP_23, ISO_SIGDET_CTRL_BAR, 7, 1)
8283    FIELD(L3_TM_ANA_BYP_23, FORCE_ISO_SIGDET_CTRL_BAR, 6, 1)
8284    FIELD(L3_TM_ANA_BYP_23, ISO_LFPS_CTRL_BAR, 5, 1)
8285    FIELD(L3_TM_ANA_BYP_23, FORCE_ISO_LFPS_CTRL_BAR, 4, 1)
8286    FIELD(L3_TM_ANA_BYP_23, ISO_MPHY_LSRX_CTRL_BAR, 3, 1)
8287    FIELD(L3_TM_ANA_BYP_23, FORCE_ISO_MPHY_LSRX_CTRL_BAR, 2, 1)
8288    FIELD(L3_TM_ANA_BYP_23, ISO_MPHY_SQUELCH_CTRL_BAR, 1, 1)
8289    FIELD(L3_TM_ANA_BYP_23, FORCE_ISO_MPHY_SQUELCH_CTRL_BAR, 0, 1)
8290REG32(L3_TM_DIG_1, 0xd058)
8291    FIELD(L3_TM_DIG_1, TM_DIG_1_31_8_RSVD, 24, 8)
8292    FIELD(L3_TM_DIG_1, EN_TXRX_DIFGEAR, 7, 1)
8293    FIELD(L3_TM_DIG_1, MPHY_HS_TERM_PT_SEL, 6, 1)
8294    FIELD(L3_TM_DIG_1, TX_ALLOW_INLNCFG_FROM_TOP, 5, 1)
8295    FIELD(L3_TM_DIG_1, BYPASS_MARKER_DETECTOR, 4, 1)
8296    FIELD(L3_TM_DIG_1, BYPASS_EXIT_VAL, 0, 4)
8297REG32(L3_TM_DIG_2, 0xd05c)
8298    FIELD(L3_TM_DIG_2, TM_DIG_2_31_8_RSVD, 24, 8)
8299    FIELD(L3_TM_DIG_2, MPHY_SYM_STATE, 1, 5)
8300    FIELD(L3_TM_DIG_2, FORCE_MPHY_SYM_STATE, 0, 1)
8301REG32(L3_TM_DIG_3, 0xd060)
8302    FIELD(L3_TM_DIG_3, TM_DIG_3_31_8_RSVD, 24, 8)
8303    FIELD(L3_TM_DIG_3, MPHY_SQUELCH_DETECT, 7, 1)
8304    FIELD(L3_TM_DIG_3, FORCE_MPHY_SQUELCH_DETECT, 6, 1)
8305    FIELD(L3_TM_DIG_3, MPHY_CFG_STATE, 1, 5)
8306    FIELD(L3_TM_DIG_3, FORCE_MPHY_CFG_STATE, 0, 1)
8307REG32(L3_TM_DIG_4, 0xd064)
8308    FIELD(L3_TM_DIG_4, TM_DIG_4_31_8_RSVD, 24, 8)
8309    FIELD(L3_TM_DIG_4, STATUS_REG_VAL, 4, 4)
8310    FIELD(L3_TM_DIG_4, READ_SHADOW, 3, 1)
8311REG32(L3_TM_DIG_5, 0xd068)
8312    FIELD(L3_TM_DIG_5, TM_DIG_5_31_8_RSVD, 24, 8)
8313    FIELD(L3_TM_DIG_5, SYMBOL_CLK_ALWAYS_ON_N, 2, 1)
8314    FIELD(L3_TM_DIG_5, BYPASS_DIFN_DETECT, 1, 1)
8315    FIELD(L3_TM_DIG_5, HIBERN8_CTRL, 0, 1)
8316REG32(L3_TM_DIG_6, 0xd06c)
8317    FIELD(L3_TM_DIG_6, TM_DIG_6_31_8_RSVD, 24, 8)
8318    FIELD(L3_TM_DIG_6, FORCE_BYPASS_ON_ERR, 6, 1)
8319    FIELD(L3_TM_DIG_6, SUPPRESS_ERR, 5, 1)
8320    FIELD(L3_TM_DIG_6, BYPASS_OHC, 4, 1)
8321    FIELD(L3_TM_DIG_6, BYPASS_DECODER, 3, 1)
8322    FIELD(L3_TM_DIG_6, FORCE_BYPASS_DEC, 2, 1)
8323    FIELD(L3_TM_DIG_6, BYPASS_DESCRAM, 1, 1)
8324    FIELD(L3_TM_DIG_6, FORCE_BYPASS_DESCRAM, 0, 1)
8325REG32(L3_TM_DIG_7, 0xd070)
8326    FIELD(L3_TM_DIG_7, TM_DIG_7_31_8_RSVD, 24, 8)
8327    FIELD(L3_TM_DIG_7, BYPASS_ON_ERR_CHAR, 0, 8)
8328REG32(L3_TM_DIG_8, 0xd074)
8329    FIELD(L3_TM_DIG_8, TM_DIG_8_31_8_RSVD, 24, 8)
8330    FIELD(L3_TM_DIG_8, EYESURF_ENABLE, 4, 1)
8331    FIELD(L3_TM_DIG_8, USE_EB_IN_MPHY, 3, 1)
8332    FIELD(L3_TM_DIG_8, BYPASS_EB, 2, 1)
8333    FIELD(L3_TM_DIG_8, EB_MODE, 1, 1)
8334    FIELD(L3_TM_DIG_8, FORCE_EB_MODE, 0, 1)
8335REG32(L3_TM_DIG_9, 0xd078)
8336    FIELD(L3_TM_DIG_9, TM_DIG_9_31_8_RSVD, 24, 8)
8337    FIELD(L3_TM_DIG_9, FLIP_ENDIAN, 3, 1)
8338    FIELD(L3_TM_DIG_9, DEC_ERR_CNT_THRESHOLD, 0, 3)
8339REG32(L3_TM_DIG_10, 0xd07c)
8340    FIELD(L3_TM_DIG_10, TM_DIG_10_31_8_RSVD, 24, 8)
8341    FIELD(L3_TM_DIG_10, CDR_BIT_LOCK_TIME, 0, 4)
8342REG32(L3_TM_DIG_11, 0xd080)
8343    FIELD(L3_TM_DIG_11, TM_DIG_11_31_8_RSVD, 24, 8)
8344    FIELD(L3_TM_DIG_11, BYPASS_CDR_ERR_MASK, 7, 1)
8345    FIELD(L3_TM_DIG_11, SYMB_ERR_SEL, 5, 2)
8346    FIELD(L3_TM_DIG_11, SYMB_ERR, 4, 1)
8347REG32(L3_TM_DIG_12, 0xd084)
8348    FIELD(L3_TM_DIG_12, TM_DIG_12_31_8_RSVD, 24, 8)
8349    FIELD(L3_TM_DIG_12, FLIP_ENDIAN_EB_DATA_OUT, 5, 1)
8350    FIELD(L3_TM_DIG_12, FLIP_ENDIAN_EB_DATA_IN, 4, 1)
8351    FIELD(L3_TM_DIG_12, OVERFLOW_BYP, 3, 1)
8352    FIELD(L3_TM_DIG_12, UNDERFLOW_BYP, 2, 1)
8353    FIELD(L3_TM_DIG_12, OVERFLOW_BYP_VAL, 1, 1)
8354    FIELD(L3_TM_DIG_12, UNDERFLOW_BYP_VAL, 0, 1)
8355REG32(L3_TM_DIG_13, 0xd088)
8356    FIELD(L3_TM_DIG_13, TM_DIG_13_31_8_RSVD, 24, 8)
8357    FIELD(L3_TM_DIG_13, OMC_PRESENTN, 6, 1)
8358    FIELD(L3_TM_DIG_13, CFG_CLK_FREQ, 0, 6)
8359REG32(L3_TM_DIG_14, 0xd08c)
8360    FIELD(L3_TM_DIG_14, TM_DIG_14_31_8_RSVD, 24, 8)
8361    FIELD(L3_TM_DIG_14, LFPS_OUTPUT_SEL, 6, 2)
8362    FIELD(L3_TM_DIG_14, LFPS_STRETCH, 4, 2)
8363REG32(L3_TM_DIG_15, 0xd090)
8364    FIELD(L3_TM_DIG_15, TM_DIG_15_31_8_RSVD, 24, 8)
8365    FIELD(L3_TM_DIG_15, FORCE_LFPS_FILTER_THRESH, 5, 1)
8366    FIELD(L3_TM_DIG_15, LFPS_FILTER_THRESH, 0, 5)
8367REG32(L3_TM_DIG_16, 0xd094)
8368    FIELD(L3_TM_DIG_16, TM_DIG_16_31_8_RSVD, 24, 8)
8369    FIELD(L3_TM_DIG_16, TESTDIGOUT_SEL, 1, 4)
8370    FIELD(L3_TM_DIG_16, FORCE_TESTDIGOUT_SEL, 0, 1)
8371REG32(L3_TM_DIG_17, 0xd098)
8372    FIELD(L3_TM_DIG_17, TM_DIG_17_31_8_RSVD, 24, 8)
8373    FIELD(L3_TM_DIG_17, FORCE_SATA_RX_VALID_CNT, 4, 1)
8374    FIELD(L3_TM_DIG_17, SATA_RX_VALID_CNT, 0, 4)
8375REG32(L3_TM_DIG_18, 0xd09c)
8376    FIELD(L3_TM_DIG_18, TM_DIG_18_31_8_RSVD, 24, 8)
8377    FIELD(L3_TM_DIG_18, CLK_DIST_SETTLE_TIME, 4, 4)
8378    FIELD(L3_TM_DIG_18, BIASGEN_SETTLE_TIME, 0, 4)
8379REG32(L3_TM_DIG_19, 0xd0a0)
8380    FIELD(L3_TM_DIG_19, TM_DIG_19_31_8_RSVD, 24, 8)
8381    FIELD(L3_TM_DIG_19, HSRX_ANA_SETTLE_TIME, 4, 4)
8382    FIELD(L3_TM_DIG_19, SBRX_ANA_SETTLE_TIME, 0, 4)
8383REG32(L3_TM_DIG_20, 0xd0a4)
8384    FIELD(L3_TM_DIG_20, TM_DIG_20_31_8_RSVD, 24, 8)
8385    FIELD(L3_TM_DIG_20, HSRX_COOLING_TIME, 3, 4)
8386    FIELD(L3_TM_DIG_20, FORCE_RX_CAL, 2, 1)
8387    FIELD(L3_TM_DIG_20, BYPASS_HSRX_CAL, 1, 1)
8388    FIELD(L3_TM_DIG_20, BYPASS_SBRX_CAL, 0, 1)
8389REG32(L3_TM_DIG_21, 0xd0a8)
8390    FIELD(L3_TM_DIG_21, TM_DIG_21_31_8_RSVD, 24, 8)
8391    FIELD(L3_TM_DIG_21, COMMA_LOCATION_RST, 4, 1)
8392    FIELD(L3_TM_DIG_21, SSC_WAIT_CNT, 2, 2)
8393    FIELD(L3_TM_DIG_21, COMMA_PRE_LOCK_THRESH, 0, 2)
8394REG32(L3_TM_DIG_22, 0xd0ac)
8395    FIELD(L3_TM_DIG_22, TM_DIG_22_31_8_RSVD, 24, 8)
8396    FIELD(L3_TM_DIG_22, DIS_DEFAULT_CDR_GATE_LOGIC, 5, 1)
8397    FIELD(L3_TM_DIG_22, INV_POL_SIGDET_HIGH, 4, 1)
8398    FIELD(L3_TM_DIG_22, INV_POL_SIGDET_LOW, 3, 1)
8399    FIELD(L3_TM_DIG_22, SIGDET_LFPS_BAR_EN, 2, 1)
8400    FIELD(L3_TM_DIG_22, OBSRV_SIGDET_OUTPUT, 1, 1)
8401    FIELD(L3_TM_DIG_22, RX_SIGDET_EN, 0, 1)
8402REG32(L3_TM_DIG_23, 0xd0b0)
8403    FIELD(L3_TM_DIG_23, TM_DIG_23_31_8_RSVD, 24, 8)
8404    FIELD(L3_TM_DIG_23, DELAY_TIMER_LOAD_VAL_HIGH_1, 6, 2)
8405    FIELD(L3_TM_DIG_23, FORCE_RX_SIGDET_SEL, 5, 1)
8406    FIELD(L3_TM_DIG_23, RX_SIGDET_SEL_VAL, 4, 1)
8407    FIELD(L3_TM_DIG_23, FORCE_RX_SIG_DET_FILT_FUNC_SEL, 3, 1)
8408    FIELD(L3_TM_DIG_23, RX_SIG_DET_FILT_FUNC_SEL, 0, 3)
8409REG32(L3_TM_DIG_24, 0xd0b4)
8410    FIELD(L3_TM_DIG_24, TM_DIG_24_31_8_RSVD, 24, 8)
8411    FIELD(L3_TM_DIG_24, FILTER_TIMER_LOAD_VAL_HIGH_1, 6, 2)
8412    FIELD(L3_TM_DIG_24, MIN_TIMER_LOAD_VAL_HIGH_1, 4, 2)
8413    FIELD(L3_TM_DIG_24, FILTER_TIMER_LOAD_VAL_LOW_1, 2, 2)
8414    FIELD(L3_TM_DIG_24, MIN_TIMER_LOAD_VAL_LOW_1, 0, 2)
8415REG32(L3_TM_DIG_25, 0xd0b8)
8416    FIELD(L3_TM_DIG_25, TM_DIG_25_31_8_RSVD, 24, 8)
8417    FIELD(L3_TM_DIG_25, FILTER_TIMER_LOAD_VAL_HIGH_0, 0, 8)
8418REG32(L3_TM_DIG_26, 0xd0bc)
8419    FIELD(L3_TM_DIG_26, TM_DIG_26_31_8_RSVD, 24, 8)
8420    FIELD(L3_TM_DIG_26, DELAY_TIMER_LOAD_VAL_HIGH_0, 0, 8)
8421REG32(L3_TM_DIG_27, 0xd0c0)
8422    FIELD(L3_TM_DIG_27, TM_DIG_27_31_8_RSVD, 24, 8)
8423    FIELD(L3_TM_DIG_27, MIN_TIMER_LOAD_VAL_HIGH_0, 0, 8)
8424REG32(L3_TM_DIG_28, 0xd0c4)
8425    FIELD(L3_TM_DIG_28, TM_DIG_28_31_8_RSVD, 24, 8)
8426    FIELD(L3_TM_DIG_28, FILTER_TIMER_LOAD_VAL_LOW_0, 0, 8)
8427REG32(L3_TM_DIG_29, 0xd0c8)
8428    FIELD(L3_TM_DIG_29, TM_DIG_29_31_8_RSVD, 24, 8)
8429    FIELD(L3_TM_DIG_29, MIN_TIMER_LOAD_VAL_LOW_0, 0, 8)
8430REG32(L3_TM_AUX_0, 0xd0cc)
8431    FIELD(L3_TM_AUX_0, TM_AUX_0_31_8_RSVD, 24, 8)
8432    FIELD(L3_TM_AUX_0, BIT_0, 7, 1)
8433    FIELD(L3_TM_AUX_0, BIT_1, 6, 1)
8434    FIELD(L3_TM_AUX_0, BIT_2, 5, 1)
8435    FIELD(L3_TM_AUX_0, BIT_3, 4, 1)
8436    FIELD(L3_TM_AUX_0, BIT_4, 3, 1)
8437    FIELD(L3_TM_AUX_0, BIT_5, 2, 1)
8438    FIELD(L3_TM_AUX_0, BIT_6, 1, 1)
8439    FIELD(L3_TM_AUX_0, BIT_7, 0, 1)
8440REG32(L3_TM_AUX_1, 0xd0d0)
8441    FIELD(L3_TM_AUX_1, TM_AUX_1_31_8_RSVD, 24, 8)
8442    FIELD(L3_TM_AUX_1, BIT_0, 7, 1)
8443    FIELD(L3_TM_AUX_1, BIT_1, 6, 1)
8444    FIELD(L3_TM_AUX_1, BIT_2, 5, 1)
8445    FIELD(L3_TM_AUX_1, BIT_3, 4, 1)
8446    FIELD(L3_TM_AUX_1, BIT_4, 3, 1)
8447    FIELD(L3_TM_AUX_1, BIT_5, 2, 1)
8448    FIELD(L3_TM_AUX_1, BIT_6, 1, 1)
8449    FIELD(L3_TM_AUX_1, BIT_7, 0, 1)
8450REG32(L3_TM_AUX_2, 0xd0d4)
8451    FIELD(L3_TM_AUX_2, TM_AUX_2_31_8_RSVD, 24, 8)
8452    FIELD(L3_TM_AUX_2, BIT_0, 7, 1)
8453    FIELD(L3_TM_AUX_2, BIT_1, 6, 1)
8454    FIELD(L3_TM_AUX_2, BIT_2, 5, 1)
8455    FIELD(L3_TM_AUX_2, BIT_3, 4, 1)
8456    FIELD(L3_TM_AUX_2, BIT_4, 3, 1)
8457    FIELD(L3_TM_AUX_2, BIT_5, 2, 1)
8458    FIELD(L3_TM_AUX_2, BIT_6, 1, 1)
8459    FIELD(L3_TM_AUX_2, BIT_7, 0, 1)
8460REG32(L3_TM_AUX_3, 0xd0d8)
8461    FIELD(L3_TM_AUX_3, TM_AUX_3_31_8_RSVD, 24, 8)
8462    FIELD(L3_TM_AUX_3, BIT_0, 7, 1)
8463    FIELD(L3_TM_AUX_3, BIT_1, 6, 1)
8464    FIELD(L3_TM_AUX_3, BIT_2, 5, 1)
8465    FIELD(L3_TM_AUX_3, BIT_3, 4, 1)
8466    FIELD(L3_TM_AUX_3, BIT_4, 3, 1)
8467    FIELD(L3_TM_AUX_3, BIT_5, 2, 1)
8468    FIELD(L3_TM_AUX_3, BIT_6, 1, 1)
8469    FIELD(L3_TM_AUX_3, BIT_7, 0, 1)
8470REG32(L3_TM_AUX_4, 0xd0dc)
8471    FIELD(L3_TM_AUX_4, TM_AUX_4_31_8_RSVD, 24, 8)
8472    FIELD(L3_TM_AUX_4, BIT_0, 7, 1)
8473    FIELD(L3_TM_AUX_4, BIT_1, 6, 1)
8474    FIELD(L3_TM_AUX_4, BIT_2, 5, 1)
8475    FIELD(L3_TM_AUX_4, BIT_3, 4, 1)
8476    FIELD(L3_TM_AUX_4, BIT_4, 3, 1)
8477    FIELD(L3_TM_AUX_4, BIT_5, 2, 1)
8478    FIELD(L3_TM_AUX_4, BIT_6, 1, 1)
8479    FIELD(L3_TM_AUX_4, BIT_7, 0, 1)
8480REG32(L3_TM_DIG_30, 0xd0e0)
8481    FIELD(L3_TM_DIG_30, TM_DIG_30_31_8_RSVD, 24, 8)
8482    FIELD(L3_TM_DIG_30, SD_LD_BAR_FILTER_TIME_VAL_1, 4, 2)
8483    FIELD(L3_TM_DIG_30, SD_LD_BAR_DLY_TIME_VAL_1, 2, 2)
8484    FIELD(L3_TM_DIG_30, SD_LD_BAR_MIN_TIMER_VAL_1, 0, 2)
8485REG32(L3_TM_DIG_31, 0xd0e4)
8486    FIELD(L3_TM_DIG_31, TM_DIG_31_31_8_RSVD, 24, 8)
8487    FIELD(L3_TM_DIG_31, SD_LD_BAR_FILTER_TIME_VAL_0, 0, 8)
8488REG32(L3_TM_DIG_32, 0xd0e8)
8489    FIELD(L3_TM_DIG_32, TM_DIG_32_31_8_RSVD, 24, 8)
8490    FIELD(L3_TM_DIG_32, SD_LD_BAR_DLY_TIME_VAL_0, 0, 8)
8491REG32(L3_TM_DIG_33, 0xd0ec)
8492    FIELD(L3_TM_DIG_33, TM_DIG_33_31_8_RSVD, 24, 8)
8493    FIELD(L3_TM_DIG_33, SD_LD_BAR_MIN_TIMER_VAL_0, 0, 8)
8494REG32(L3_TM_DIG_34, 0xd0f0)
8495    FIELD(L3_TM_DIG_34, TM_DIG_34_31_8_RSVD, 24, 8)
8496    FIELD(L3_TM_DIG_34, SATA_JUNK_DATA_TIMEOUT_VAL, 0, 6)
8497REG32(L3_TM_DIG_35, 0xd0f4)
8498    FIELD(L3_TM_DIG_35, TM_DIG_35_31_8_RSVD, 24, 8)
8499    FIELD(L3_TM_DIG_35, SATA_CDR_LOCK_WAIT_TIMEOUT_VAL, 0, 6)
8500REG32(L3_TM_DIG_36, 0xd0f8)
8501    FIELD(L3_TM_DIG_36, TM_DIG_36_31_8_RSVD, 24, 8)
8502    FIELD(L3_TM_DIG_36, COM_DET_THRESH_VAL_0, 0, 8)
8503REG32(L3_TM_DIG_37, 0xd0fc)
8504    FIELD(L3_TM_DIG_37, TM_DIG_37_31_8_RSVD, 24, 8)
8505    FIELD(L3_TM_DIG_37, FORCE_COM_DETECT_THRESH, 4, 1)
8506    FIELD(L3_TM_DIG_37, COM_DET_THRESH_VAL_1, 0, 4)
8507REG32(L3_TM_LFPS_1, 0xd800)
8508    FIELD(L3_TM_LFPS_1, TM_LFPS_1_31_8_RSVD, 24, 8)
8509    FIELD(L3_TM_LFPS_1, PROG_REFP, 4, 4)
8510    FIELD(L3_TM_LFPS_1, PROG_REFM, 0, 4)
8511REG32(L3_TM_LFPS_2, 0xd804)
8512    FIELD(L3_TM_LFPS_2, TM_LFPS_2_31_8_RSVD, 24, 8)
8513    FIELD(L3_TM_LFPS_2, PROG_VCM, 4, 3)
8514    FIELD(L3_TM_LFPS_2, PROG_FILTER_CAP, 0, 4)
8515REG32(L3_TM_LFPS_3, 0xd808)
8516    FIELD(L3_TM_LFPS_3, TM_LFPS_3_31_8_RSVD, 24, 8)
8517    FIELD(L3_TM_LFPS_3, PROG_C2, 5, 3)
8518    FIELD(L3_TM_LFPS_3, PROG_C1, 2, 3)
8519    FIELD(L3_TM_LFPS_3, PROG_PADINTF, 0, 2)
8520REG32(L3_TM_LFPS_4, 0xd80c)
8521    FIELD(L3_TM_LFPS_4, TM_LFPS_4_31_8_RSVD, 24, 8)
8522    FIELD(L3_TM_LFPS_4, TESTBIT, 0, 6)
8523REG32(L3_TM_RXPMA_1, 0xd810)
8524    FIELD(L3_TM_RXPMA_1, TM_RXPMA_1_31_8_RSVD, 24, 8)
8525    FIELD(L3_TM_RXPMA_1, UPHY_TESTBIT, 0, 8)
8526REG32(L3_TM_BSCAN_1, 0xd814)
8527    FIELD(L3_TM_BSCAN_1, TM_BSCAN_1_31_8_RSVD, 24, 8)
8528    FIELD(L3_TM_BSCAN_1, BSCAN_LPF_RES, 0, 3)
8529REG32(L3_TM_MPHY_SQ_1, 0xd818)
8530    FIELD(L3_TM_MPHY_SQ_1, TM_MPHY_SQ_1_31_8_RSVD, 24, 8)
8531    FIELD(L3_TM_MPHY_SQ_1, TB_REDUCE_OFFSET, 4, 1)
8532    FIELD(L3_TM_MPHY_SQ_1, TB_INCREASE_OFFSET, 3, 1)
8533    FIELD(L3_TM_MPHY_SQ_1, TB_DRIVE_RES_SEL, 1, 2)
8534    FIELD(L3_TM_MPHY_SQ_1, TB_BYPASS_HYST, 0, 1)
8535REG32(L3_TM_LSRX_1, 0xd81c)
8536    FIELD(L3_TM_LSRX_1, TM_LSRX_1_31_8_RSVD, 24, 8)
8537    FIELD(L3_TM_LSRX_1, LSRX_TESTBITS_0, 0, 8)
8538REG32(L3_TM_LSRX_2, 0xd820)
8539    FIELD(L3_TM_LSRX_2, TM_LSRX_2_31_8_RSVD, 24, 8)
8540    FIELD(L3_TM_LSRX_2, LSRX_TESTBITS_1, 0, 6)
8541REG32(L3_TM_SIGDET_1, 0xd824)
8542    FIELD(L3_TM_SIGDET_1, TM_SIGDET_1_31_8_RSVD, 24, 8)
8543    FIELD(L3_TM_SIGDET_1, BIASTRIM, 4, 3)
8544    FIELD(L3_TM_SIGDET_1, RELIABPROT, 2, 2)
8545    FIELD(L3_TM_SIGDET_1, STRESSPORT, 0, 2)
8546REG32(L3_TM_SIGDET_2, 0xd828)
8547    FIELD(L3_TM_SIGDET_2, TM_SIGDET_2_31_8_RSVD, 24, 8)
8548    FIELD(L3_TM_SIGDET_2, VSENSETRIM, 0, 8)
8549REG32(L3_TM_DFT_1, 0xd82c)
8550    FIELD(L3_TM_DFT_1, TM_DFT_1_31_8_RSVD, 24, 8)
8551    FIELD(L3_TM_DFT_1, LFPS_DFT_SEL_P, 4, 4)
8552    FIELD(L3_TM_DFT_1, LFPS_DFT_ENABLE, 3, 1)
8553REG32(L3_TM_DFT_2, 0xd830)
8554    FIELD(L3_TM_DFT_2, TM_DFT_2_31_8_RSVD, 24, 8)
8555    FIELD(L3_TM_DFT_2, SIGDET_DFT_SEL_P, 0, 3)
8556REG32(L3_TM_DFT_3, 0xd834)
8557    FIELD(L3_TM_DFT_3, TM_DFT_3_31_8_RSVD, 24, 8)
8558    FIELD(L3_TM_DFT_3, BSCAN_DFT_ENABLE, 4, 1)
8559    FIELD(L3_TM_DFT_3, BSCAN_DFT_SEL_P, 0, 4)
8560REG32(L3_TM_DFT_4, 0xd838)
8561    FIELD(L3_TM_DFT_4, TM_DFT_4_31_8_RSVD, 24, 8)
8562    FIELD(L3_TM_DFT_4, IQPI_DFT_ENABLE, 1, 1)
8563    FIELD(L3_TM_DFT_4, EPI_DFT_ENABLE, 0, 1)
8564REG32(L3_TM_DFT_5, 0xd83c)
8565    FIELD(L3_TM_DFT_5, TM_DFT_5_31_8_RSVD, 24, 8)
8566    FIELD(L3_TM_DFT_5, IQPI_DFT_SEL, 0, 8)
8567REG32(L3_TM_DFT_6, 0xd840)
8568    FIELD(L3_TM_DFT_6, TM_DFT_6_31_8_RSVD, 24, 8)
8569    FIELD(L3_TM_DFT_6, EPI_DFT_SEL, 0, 8)
8570REG32(L3_TM_DFT_7, 0xd844)
8571    FIELD(L3_TM_DFT_7, TM_DFT_7_31_8_RSVD, 24, 8)
8572    FIELD(L3_TM_DFT_7, EQ_DFT_ENABLE, 4, 1)
8573    FIELD(L3_TM_DFT_7, EQ_DFT_SEL_P, 0, 4)
8574REG32(L3_TM_DFT_8, 0xd848)
8575    FIELD(L3_TM_DFT_8, TM_DFT_8_31_8_RSVD, 24, 8)
8576    FIELD(L3_TM_DFT_8, LSRX_DFT_ENABLE, 4, 1)
8577    FIELD(L3_TM_DFT_8, LSRX_DFT_SEL_P, 0, 4)
8578REG32(L3_TM_DFT_9, 0xd84c)
8579    FIELD(L3_TM_DFT_9, TM_DFT_9_31_8_RSVD, 24, 8)
8580    FIELD(L3_TM_DFT_9, SAMP_DFT_SEL_P_0, 0, 8)
8581REG32(L3_TM_DFT_10, 0xd850)
8582    FIELD(L3_TM_DFT_10, TM_DFT_10_31_8_RSVD, 24, 8)
8583    FIELD(L3_TM_DFT_10, CLKLANE_DFT_SEL, 2, 2)
8584    FIELD(L3_TM_DFT_10, SAMP_DFT_SEL_P_1, 0, 2)
8585REG32(L3_TM_BG_1, 0xd854)
8586    FIELD(L3_TM_BG_1, TM_BG_1_31_8_RSVD, 24, 8)
8587    FIELD(L3_TM_BG_1, BIASGEN_CURRENT_PROG_0, 0, 8)
8588REG32(L3_TM_BG_2, 0xd858)
8589    FIELD(L3_TM_BG_2, TM_BG_2_31_8_RSVD, 24, 8)
8590    FIELD(L3_TM_BG_2, BIASGEN_CURRENT_PROG_1, 0, 8)
8591REG32(L3_TM_BG_3, 0xd85c)
8592    FIELD(L3_TM_BG_3, TM_BG_3_31_8_RSVD, 24, 8)
8593    FIELD(L3_TM_BG_3, BIASGEN_CURRENT_PROG_2, 0, 8)
8594REG32(L3_TM_BG_4, 0xd860)
8595    FIELD(L3_TM_BG_4, TM_BG_4_31_8_RSVD, 24, 8)
8596    FIELD(L3_TM_BG_4, BIASGEN_CURRENT_PROG_3, 0, 8)
8597REG32(L3_TM_BG_5, 0xd864)
8598    FIELD(L3_TM_BG_5, TM_BG_5_31_8_RSVD, 24, 8)
8599    FIELD(L3_TM_BG_5, BIASGEN_CURRENT_PROG_4, 0, 8)
8600REG32(L3_TM_BG_6, 0xd868)
8601    FIELD(L3_TM_BG_6, TM_BG_6_31_8_RSVD, 24, 8)
8602    FIELD(L3_TM_BG_6, BIASGEN_CURRENT_PROG_5, 0, 8)
8603REG32(L3_TM_BG_7, 0xd86c)
8604    FIELD(L3_TM_BG_7, TM_BG_7_31_8_RSVD, 24, 8)
8605    FIELD(L3_TM_BG_7, BIASGEN_CURRENT_PROG_6, 0, 8)
8606REG32(L3_TM_BG_8, 0xd870)
8607    FIELD(L3_TM_BG_8, TM_BG_8_31_8_RSVD, 24, 8)
8608    FIELD(L3_TM_BG_8, BIASGEN_CURRENT_PROG_7, 0, 8)
8609REG32(L3_TM_BG_9, 0xd874)
8610    FIELD(L3_TM_BG_9, TM_BG_9_31_8_RSVD, 24, 8)
8611    FIELD(L3_TM_BG_9, BIASGEN_CURRENT_PROG_8, 0, 8)
8612REG32(L3_TM_BG_10, 0xd878)
8613    FIELD(L3_TM_BG_10, TM_BG_10_31_8_RSVD, 24, 8)
8614    FIELD(L3_TM_BG_10, BIASGEN_CURRENT_PROG_9, 0, 8)
8615REG32(L3_TM_SD0, 0xd87c)
8616    FIELD(L3_TM_SD0, TM_SD0_31_8_RSVD, 24, 8)
8617    FIELD(L3_TM_SD0, SD_CAL_OVERRIDE_CODE, 2, 6)
8618    FIELD(L3_TM_SD0, SD_CAL_OVERRIDE_EN, 1, 1)
8619    FIELD(L3_TM_SD0, SD_CAL_DIR, 0, 1)
8620REG32(L3_TM_SD1, 0xd880)
8621    FIELD(L3_TM_SD1, TM_SD1_31_8_RSVD, 24, 8)
8622    FIELD(L3_TM_SD1, SD_BYPASS_ANA_CAL_EN_VAL, 7, 1)
8623    FIELD(L3_TM_SD1, SD_BYPASS_ANA_CAL_EN, 6, 1)
8624    FIELD(L3_TM_SD1, SD_CAL_CODE_START, 0, 6)
8625REG32(L3_TM_SD2, 0xd884)
8626    FIELD(L3_TM_SD2, TM_SD2_31_8_RSVD, 24, 8)
8627    FIELD(L3_TM_SD2, SD_CAL_FORCE_CAL, 7, 1)
8628    FIELD(L3_TM_SD2, SD_CAL_CODE_TUNE_BYP, 6, 1)
8629    FIELD(L3_TM_SD2, SD_CAL_CODE_TUNE, 0, 6)
8630REG32(L3_TM_SD3, 0xd888)
8631    FIELD(L3_TM_SD3, TM_SD3_31_8_RSVD, 24, 8)
8632    FIELD(L3_TM_SD3, SD_CAL_ITER_WAIT_0, 0, 8)
8633REG32(L3_TM_SD4, 0xd88c)
8634    FIELD(L3_TM_SD4, TM_SD4_31_8_RSVD, 24, 8)
8635    FIELD(L3_TM_SD4, SD_CAL_ITER_WAIT_BYPASS, 4, 1)
8636    FIELD(L3_TM_SD4, SD_CAL_ITER_WAIT_1, 0, 4)
8637REG32(L3_TM_SD5, 0xd890)
8638    FIELD(L3_TM_SD5, TM_SD5_31_8_RSVD, 24, 8)
8639    FIELD(L3_TM_SD5, SD_CAL_INIT_WAIT_0, 0, 8)
8640REG32(L3_TM_SD6, 0xd894)
8641    FIELD(L3_TM_SD6, TM_SD6_31_8_RSVD, 24, 8)
8642    FIELD(L3_TM_SD6, SD_CAL_INIT_WAIT_BYPASS, 4, 1)
8643    FIELD(L3_TM_SD6, SD_CAL_INIT_WAIT_1, 0, 4)
8644REG32(L3_TM_MISC1, 0xd898)
8645    FIELD(L3_TM_MISC1, TM_MISC1_31_8_RSVD, 24, 8)
8646    FIELD(L3_TM_MISC1, HSRX_POLARITY_FLIP, 7, 1)
8647    FIELD(L3_TM_MISC1, RXTERM_BIAS_PROG, 3, 4)
8648    FIELD(L3_TM_MISC1, LSRX_OR_SYS_POLARITY_FLIP, 2, 1)
8649    FIELD(L3_TM_MISC1, FORCE_SATAG1_DCC_MODE, 1, 1)
8650    FIELD(L3_TM_MISC1, SATAG1_DCC_MODE_VAL, 0, 1)
8651REG32(L3_TM_MISC2, 0xd89c)
8652    FIELD(L3_TM_MISC2, TM_MISC2_31_8_RSVD, 24, 8)
8653    FIELD(L3_TM_MISC2, ILL_CAL_BYPASS_COUNTS, 7, 1)
8654    FIELD(L3_TM_MISC2, PWR_SEQ_SAMP_CAL_ALWAYS, 6, 1)
8655    FIELD(L3_TM_MISC2, PWR_SEQ_BYP_CAL_DONE, 5, 1)
8656    FIELD(L3_TM_MISC2, PWR_SEQ_BYP_CAL_DONE_VAL, 4, 1)
8657    FIELD(L3_TM_MISC2, SAMP_BYPASS_CAL_TO_EQ, 3, 1)
8658    FIELD(L3_TM_MISC2, SAMP_BYPASS_CAL_TO_EQ_VAL, 2, 1)
8659    FIELD(L3_TM_MISC2, UNUSED, 0, 2)
8660REG32(L3_TM_EYE_SURF0, 0xd8a0)
8661    FIELD(L3_TM_EYE_SURF0, TM_EYE_SURF0_31_8_RSVD, 24, 8)
8662    FIELD(L3_TM_EYE_SURF0, UNUSED, 7, 1)
8663    FIELD(L3_TM_EYE_SURF0, EYE_SURF_RUN, 6, 1)
8664    FIELD(L3_TM_EYE_SURF0, COORD_EW_DIR, 5, 1)
8665    FIELD(L3_TM_EYE_SURF0, COORD_EW_OFFSET, 0, 5)
8666REG32(L3_TM_EYE_SURF1, 0xd8a4)
8667    FIELD(L3_TM_EYE_SURF1, TM_EYE_SURF1_31_8_RSVD, 24, 8)
8668    FIELD(L3_TM_EYE_SURF1, COORD_NS_DIR, 7, 1)
8669    FIELD(L3_TM_EYE_SURF1, COORD_NS_OFFSET, 0, 7)
8670REG32(L3_TM_EYE_SURF2, 0xd8a8)
8671    FIELD(L3_TM_EYE_SURF2, TM_EYE_SURF2_31_8_RSVD, 24, 8)
8672    FIELD(L3_TM_EYE_SURF2, TIMER_DELAY_TIME0, 0, 8)
8673REG32(L3_TM_EYE_SURF3, 0xd8ac)
8674    FIELD(L3_TM_EYE_SURF3, TM_EYE_SURF3_31_8_RSVD, 24, 8)
8675    FIELD(L3_TM_EYE_SURF3, TIMER_DELAY_TIME1, 0, 8)
8676REG32(L3_TM_EYE_SURF4, 0xd8b0)
8677    FIELD(L3_TM_EYE_SURF4, TM_EYE_SURF4_31_8_RSVD, 24, 8)
8678    FIELD(L3_TM_EYE_SURF4, TIMER_DELAY_TIME2, 0, 8)
8679REG32(L3_TM_EYE_SURF5, 0xd8b4)
8680    FIELD(L3_TM_EYE_SURF5, TM_EYE_SURF5_31_8_RSVD, 24, 8)
8681    FIELD(L3_TM_EYE_SURF5, TIMER_DELAY_TIME3, 0, 8)
8682REG32(L3_TM_EYE_SURF6, 0xd8b8)
8683    FIELD(L3_TM_EYE_SURF6, TM_EYE_SURF6_31_8_RSVD, 24, 8)
8684    FIELD(L3_TM_EYE_SURF6, TIMER_TEST_TIME0, 0, 8)
8685REG32(L3_TM_EYE_SURF7, 0xd8bc)
8686    FIELD(L3_TM_EYE_SURF7, TM_EYE_SURF7_31_8_RSVD, 24, 8)
8687    FIELD(L3_TM_EYE_SURF7, TIMER_TEST_TIME1, 0, 8)
8688REG32(L3_TM_EYE_SURF8, 0xd8c0)
8689    FIELD(L3_TM_EYE_SURF8, TM_EYE_SURF8_31_8_RSVD, 24, 8)
8690    FIELD(L3_TM_EYE_SURF8, TIMER_TEST_TIME2, 0, 8)
8691REG32(L3_TM_EYE_SURF9, 0xd8c4)
8692    FIELD(L3_TM_EYE_SURF9, TM_EYE_SURF9_31_8_RSVD, 24, 8)
8693    FIELD(L3_TM_EYE_SURF9, TIMER_TEST_TIME3, 0, 8)
8694REG32(L3_TM_SPARE, 0xd8c8)
8695    FIELD(L3_TM_SPARE, TM_SPARE_31_8_RSVD, 24, 8)
8696    FIELD(L3_TM_SPARE, RXDA_SPARE_PORT, 0, 8)
8697REG32(L3_TM_ANA_EQ1, 0xd8cc)
8698    FIELD(L3_TM_ANA_EQ1, TM_ANA_EQ1_31_8_RSVD, 24, 8)
8699    FIELD(L3_TM_ANA_EQ1, UNUSED, 5, 3)
8700    FIELD(L3_TM_ANA_EQ1, EQ_INPUT_CM_PROG, 2, 3)
8701    FIELD(L3_TM_ANA_EQ1, EQ_PADINTF_HQ_PROG, 0, 2)
8702REG32(L3_TM_ANA_E_PI0, 0xd8d0)
8703    FIELD(L3_TM_ANA_E_PI0, TM_ANA_E_PI0_31_8_RSVD, 24, 8)
8704    FIELD(L3_TM_ANA_E_PI0, EPI_BIASTRIM, 5, 3)
8705    FIELD(L3_TM_ANA_E_PI0, UNUSED, 0, 5)
8706REG32(L3_TM_ANA_IQ_PI0, 0xd8d4)
8707    FIELD(L3_TM_ANA_IQ_PI0, TM_ANA_IQ_PI0_31_8_RSVD, 24, 8)
8708    FIELD(L3_TM_ANA_IQ_PI0, IQPI_BIASTRIM, 5, 3)
8709    FIELD(L3_TM_ANA_IQ_PI0, UNUSED, 0, 5)
8710REG32(L3_TM_ANA_MISC0, 0xd8d8)
8711    FIELD(L3_TM_ANA_MISC0, TM_ANA_MISC0_31_8_RSVD, 24, 8)
8712    FIELD(L3_TM_ANA_MISC0, EPI_CALIB_EN, 7, 1)
8713    FIELD(L3_TM_ANA_MISC0, IQPI_CALIB_EN, 6, 1)
8714    FIELD(L3_TM_ANA_MISC0, UNUSED, 0, 6)
8715REG32(L3_TM_SAMP_CODE_IQ_PH0, 0xd8dc)
8716    FIELD(L3_TM_SAMP_CODE_IQ_PH0, TM_SAMP_CODE_IQ_PH0_31_8_RSVD, 24, 8)
8717    FIELD(L3_TM_SAMP_CODE_IQ_PH0, UNUSED, 7, 1)
8718    FIELD(L3_TM_SAMP_CODE_IQ_PH0, SAMP_CALIB_BYP, 6, 1)
8719    FIELD(L3_TM_SAMP_CODE_IQ_PH0, IQ_PH0_SAMP_CODE, 0, 6)
8720REG32(L3_TM_SAMP_CODE_IQ_PH90, 0xd8e0)
8721    FIELD(L3_TM_SAMP_CODE_IQ_PH90, TM_SAMP_CODE_IQ_PH90_31_8_RSVD, 24, 8)
8722    FIELD(L3_TM_SAMP_CODE_IQ_PH90, CALIB_SWEEP_DIR, 6, 2)
8723    FIELD(L3_TM_SAMP_CODE_IQ_PH90, IQ_PH90_SAMP_CODE, 0, 6)
8724REG32(L3_TM_SAMP_CODE_IQ_PH180, 0xd8e4)
8725    FIELD(L3_TM_SAMP_CODE_IQ_PH180, TM_SAMP_CODE_IQ_PH180_31_8_RSVD, 24, 8)
8726    FIELD(L3_TM_SAMP_CODE_IQ_PH180, UNUSED, 6, 2)
8727    FIELD(L3_TM_SAMP_CODE_IQ_PH180, IQ_PH180_SAMP_CODE, 0, 6)
8728REG32(L3_TM_SAMP_CODE_IQ_PH270, 0xd8e8)
8729    FIELD(L3_TM_SAMP_CODE_IQ_PH270, TM_SAMP_CODE_IQ_PH270_31_8_RSVD, 24, 8)
8730    FIELD(L3_TM_SAMP_CODE_IQ_PH270, HSRX_DBG_BUS_SEL, 6, 2)
8731    FIELD(L3_TM_SAMP_CODE_IQ_PH270, IQ_PH270_SAMP_CODE, 0, 6)
8732REG32(L3_TM_SAMP_CODE_E_PH0, 0xd8ec)
8733    FIELD(L3_TM_SAMP_CODE_E_PH0, TM_SAMP_CODE_E_PH0_31_8_RSVD, 24, 8)
8734    FIELD(L3_TM_SAMP_CODE_E_PH0, UNUSED, 6, 2)
8735    FIELD(L3_TM_SAMP_CODE_E_PH0, E_PH90_SAMP_CODE, 0, 6)
8736REG32(L3_TM_SAMP_CODE_E_PH180, 0xd8f0)
8737    FIELD(L3_TM_SAMP_CODE_E_PH180, TM_SAMP_CODE_E_PH180_31_8_RSVD, 24, 8)
8738    FIELD(L3_TM_SAMP_CODE_E_PH180, UNUSED, 6, 2)
8739    FIELD(L3_TM_SAMP_CODE_E_PH180, E_PH270_SAMP_CODE, 0, 6)
8740REG32(L3_TM_IQ_ILL0, 0xd8f4)
8741    FIELD(L3_TM_IQ_ILL0, TM_IQ_ILL0_31_8_RSVD, 24, 8)
8742    FIELD(L3_TM_IQ_ILL0, ILL_BYPASS_IQ_CAL_EN, 7, 1)
8743    FIELD(L3_TM_IQ_ILL0, IQ_ILL_PLOADTRIM_BYP_VAL, 2, 5)
8744    FIELD(L3_TM_IQ_ILL0, IQ_ILL_PLOADTRIM_BYP, 1, 1)
8745    FIELD(L3_TM_IQ_ILL0, ILL_BYPASS_IQ_CODES, 0, 1)
8746REG32(L3_TM_IQ_ILL1, 0xd8f8)
8747    FIELD(L3_TM_IQ_ILL1, TM_IQ_ILL1_31_8_RSVD, 24, 8)
8748    FIELD(L3_TM_IQ_ILL1, ILL_BYPASS_IQ_CALCODE_F0, 0, 8)
8749REG32(L3_TM_IQ_ILL2, 0xd8fc)
8750    FIELD(L3_TM_IQ_ILL2, TM_IQ_ILL2_31_8_RSVD, 24, 8)
8751    FIELD(L3_TM_IQ_ILL2, ILL_BYPASS_IQ_CALCODE_F1, 0, 8)
8752REG32(L3_TM_IQ_ILL3, 0xd900)
8753    FIELD(L3_TM_IQ_ILL3, TM_IQ_ILL3_31_8_RSVD, 24, 8)
8754    FIELD(L3_TM_IQ_ILL3, ILL_BYPASS_IQ_CALCODE_F2, 0, 8)
8755REG32(L3_TM_IQ_ILL4, 0xd904)
8756    FIELD(L3_TM_IQ_ILL4, TM_IQ_ILL4_31_8_RSVD, 24, 8)
8757    FIELD(L3_TM_IQ_ILL4, ILL_BYPASS_IQ_CALCODE_F3, 0, 8)
8758REG32(L3_TM_IQ_ILL5, 0xd908)
8759    FIELD(L3_TM_IQ_ILL5, TM_IQ_ILL5_31_8_RSVD, 24, 8)
8760    FIELD(L3_TM_IQ_ILL5, ILL_BYPASS_IQ_CALCODE_F4, 0, 8)
8761REG32(L3_TM_IQ_ILL6, 0xd90c)
8762    FIELD(L3_TM_IQ_ILL6, TM_IQ_ILL6_31_8_RSVD, 24, 8)
8763    FIELD(L3_TM_IQ_ILL6, ILL_BYPASS_IQ_CALCODE_F5, 0, 8)
8764REG32(L3_TM_IQ_ILL7, 0xd910)
8765    FIELD(L3_TM_IQ_ILL7, TM_IQ_ILL7_31_8_RSVD, 24, 8)
8766    FIELD(L3_TM_IQ_ILL7, ILL_BYPASS_IQ_CNSTGMTRIM_VAL, 0, 8)
8767REG32(L3_TM_IQ_ILL8, 0xd914)
8768    FIELD(L3_TM_IQ_ILL8, TM_IQ_ILL8_31_8_RSVD, 24, 8)
8769    FIELD(L3_TM_IQ_ILL8, ILL_BYPASS_IQ_POLYTRIM_VAL, 0, 8)
8770REG32(L3_TM_IQ_ILL9, 0xd918)
8771    FIELD(L3_TM_IQ_ILL9, TM_IQ_ILL9_31_8_RSVD, 24, 8)
8772    FIELD(L3_TM_IQ_ILL9, UNUSED, 4, 4)
8773    FIELD(L3_TM_IQ_ILL9, ILL_BYPASS_IQ_LFEN, 3, 1)
8774    FIELD(L3_TM_IQ_ILL9, ILL_BYPASS_IQ_LFEN_VAL, 2, 1)
8775    FIELD(L3_TM_IQ_ILL9, ILL_BYPASS_IQ_CNSTGMTRIM, 1, 1)
8776    FIELD(L3_TM_IQ_ILL9, ILL_BYPASS_IQ_POLYTIM, 0, 1)
8777REG32(L3_TM_IQ_ILL10, 0xd91c)
8778    FIELD(L3_TM_IQ_ILL10, TM_IQ_ILL10_31_8_RSVD, 24, 8)
8779    FIELD(L3_TM_IQ_ILL10, UNUSED, 6, 2)
8780    FIELD(L3_TM_IQ_ILL10, IQPI_CALCTRIM, 4, 2)
8781    FIELD(L3_TM_IQ_ILL10, IQPI_REPLICATRIM, 0, 4)
8782REG32(L3_TM_E_ILL0, 0xd920)
8783    FIELD(L3_TM_E_ILL0, TM_E_ILL0_31_8_RSVD, 24, 8)
8784    FIELD(L3_TM_E_ILL0, E_ILL_CALIB_CTRL, 7, 1)
8785    FIELD(L3_TM_E_ILL0, E_ILL_PLOADTRIM_BYP_VAL, 2, 5)
8786    FIELD(L3_TM_E_ILL0, E_ILL_PLOADTRIM_BYP, 1, 1)
8787    FIELD(L3_TM_E_ILL0, E_ILL_CALIB_BYP, 0, 1)
8788REG32(L3_TM_E_ILL1, 0xd924)
8789    FIELD(L3_TM_E_ILL1, TM_E_ILL1_31_8_RSVD, 24, 8)
8790    FIELD(L3_TM_E_ILL1, ILL_BYPASS_E_CALCODE_F0, 0, 8)
8791REG32(L3_TM_E_ILL2, 0xd928)
8792    FIELD(L3_TM_E_ILL2, TM_E_ILL2_31_8_RSVD, 24, 8)
8793    FIELD(L3_TM_E_ILL2, ILL_BYPASS_E_CALCODE_F1, 0, 8)
8794REG32(L3_TM_E_ILL3, 0xd92c)
8795    FIELD(L3_TM_E_ILL3, TM_E_ILL3_31_8_RSVD, 24, 8)
8796    FIELD(L3_TM_E_ILL3, ILL_BYPASS_E_CALCODE_F2, 0, 8)
8797REG32(L3_TM_E_ILL4, 0xd930)
8798    FIELD(L3_TM_E_ILL4, TM_E_ILL4_31_8_RSVD, 24, 8)
8799    FIELD(L3_TM_E_ILL4, ILL_BYPASS_E_CALCODE_F3, 0, 8)
8800REG32(L3_TM_E_ILL5, 0xd934)
8801    FIELD(L3_TM_E_ILL5, TM_E_ILL5_31_8_RSVD, 24, 8)
8802    FIELD(L3_TM_E_ILL5, ILL_BYPASS_E_CALCODE_F4, 0, 8)
8803REG32(L3_TM_E_ILL6, 0xd938)
8804    FIELD(L3_TM_E_ILL6, TM_E_ILL6_31_8_RSVD, 24, 8)
8805    FIELD(L3_TM_E_ILL6, ILL_BYPASS_E_CALCODE_F5, 0, 8)
8806REG32(L3_TM_E_ILL7, 0xd93c)
8807    FIELD(L3_TM_E_ILL7, TM_E_ILL7_31_8_RSVD, 24, 8)
8808    FIELD(L3_TM_E_ILL7, ILL_BYPASS_E_CNSTGMTRIM_VAL, 0, 8)
8809REG32(L3_TM_E_ILL8, 0xd940)
8810    FIELD(L3_TM_E_ILL8, TM_E_ILL8_31_8_RSVD, 24, 8)
8811    FIELD(L3_TM_E_ILL8, ILL_BYPASS_E_POLYTRIM_VAL, 0, 8)
8812REG32(L3_TM_E_ILL9, 0xd944)
8813    FIELD(L3_TM_E_ILL9, TM_E_ILL9_31_8_RSVD, 24, 8)
8814    FIELD(L3_TM_E_ILL9, UNUSED, 4, 4)
8815    FIELD(L3_TM_E_ILL9, ILL_BYPASS_E_LFEN, 3, 1)
8816    FIELD(L3_TM_E_ILL9, ILL_BYPASS_E_LFEN_VAL, 2, 1)
8817    FIELD(L3_TM_E_ILL9, ILL_BYPASS_E_CNSTGMTRIM, 1, 1)
8818    FIELD(L3_TM_E_ILL9, ILL_BYPASS_E_POLYTIM, 0, 1)
8819REG32(L3_TM_E_ILL10, 0xd948)
8820    FIELD(L3_TM_E_ILL10, TM_E_ILL10_31_8_RSVD, 24, 8)
8821    FIELD(L3_TM_E_ILL10, UNUSED, 6, 2)
8822    FIELD(L3_TM_E_ILL10, EPI_CALCTRIM, 4, 2)
8823    FIELD(L3_TM_E_ILL10, EPI_REPLICATRIM, 0, 4)
8824REG32(L3_TM_EQ0, 0xd94c)
8825    FIELD(L3_TM_EQ0, TM_EQ0_31_8_RSVD, 24, 8)
8826    FIELD(L3_TM_EQ0, EQ_STG1_RL_PROG_MSB, 7, 1)
8827    FIELD(L3_TM_EQ0, EQ_STG1_CTRL_BYP, 6, 1)
8828    FIELD(L3_TM_EQ0, EQ_STG2_CTRL_BYP, 5, 1)
8829    FIELD(L3_TM_EQ0, EQ_ADAPTATION_FORCE, 4, 1)
8830    FIELD(L3_TM_EQ0, EQ_ADAPTATION_FORCE_VAL, 3, 1)
8831    FIELD(L3_TM_EQ0, EQ_ISOURCE_EN_VAL, 0, 3)
8832REG32(L3_TM_EQ1, 0xd950)
8833    FIELD(L3_TM_EQ1, TM_EQ1_31_8_RSVD, 24, 8)
8834    FIELD(L3_TM_EQ1, EQ_STG1_PREAMP_MODE_VAL, 7, 1)
8835    FIELD(L3_TM_EQ1, EQ_STG1_RL_PROG, 5, 2)
8836    FIELD(L3_TM_EQ1, EQ_STG2_CM_PROG, 3, 2)
8837    FIELD(L3_TM_EQ1, EQ_STG2_PREAMP_MODE_VAL, 2, 1)
8838    FIELD(L3_TM_EQ1, EQ_STG2_RL_PROG, 0, 2)
8839REG32(L3_TM_EQ2, 0xd954)
8840    FIELD(L3_TM_EQ2, TM_EQ2_31_8_RSVD, 24, 8)
8841    FIELD(L3_TM_EQ2, UNUSED, 7, 1)
8842    FIELD(L3_TM_EQ2, EQ_EN_BACKGND_ADAPT, 6, 1)
8843    FIELD(L3_TM_EQ2, EQ_COUNT_STRAYS, 5, 1)
8844    FIELD(L3_TM_EQ2, EQ_WINDOW_SIZE, 3, 2)
8845    FIELD(L3_TM_EQ2, EQ_MAJ_THRESH, 1, 2)
8846    FIELD(L3_TM_EQ2, EQ_BIAS_CTRL_BYP, 0, 1)
8847REG32(L3_TM_EQ3, 0xd958)
8848    FIELD(L3_TM_EQ3, TM_EQ3_31_8_RSVD, 24, 8)
8849    FIELD(L3_TM_EQ3, UNUSED, 5, 3)
8850    FIELD(L3_TM_EQ3, EQ_BYPASS_ISINK_ENZ_VAL, 0, 5)
8851REG32(L3_TM_EQ4, 0xd95c)
8852    FIELD(L3_TM_EQ4, TM_EQ4_31_8_RSVD, 24, 8)
8853    FIELD(L3_TM_EQ4, UNUSED, 5, 3)
8854    FIELD(L3_TM_EQ4, BYPASS_EQ_C_STG1, 4, 1)
8855    FIELD(L3_TM_EQ4, BYPASS_EQ_C_VAL_STG1, 0, 4)
8856REG32(L3_TM_EQ5, 0xd960)
8857    FIELD(L3_TM_EQ5, TM_EQ5_31_8_RSVD, 24, 8)
8858    FIELD(L3_TM_EQ5, UNUSED, 6, 2)
8859    FIELD(L3_TM_EQ5, BYPASS_EQ_R_STG1, 5, 1)
8860    FIELD(L3_TM_EQ5, BYPASS_EQ_R_VAL_STG1, 0, 5)
8861REG32(L3_TM_EQ6, 0xd964)
8862    FIELD(L3_TM_EQ6, TM_EQ6_31_8_RSVD, 24, 8)
8863    FIELD(L3_TM_EQ6, UNUSED, 5, 3)
8864    FIELD(L3_TM_EQ6, BYPASS_EQ_C_STG2, 4, 1)
8865    FIELD(L3_TM_EQ6, BYPASS_EQ_C_VAL_STG2, 0, 4)
8866REG32(L3_TM_EQ7, 0xd968)
8867    FIELD(L3_TM_EQ7, TM_EQ7_31_8_RSVD, 24, 8)
8868    FIELD(L3_TM_EQ7, UNUSED, 6, 2)
8869    FIELD(L3_TM_EQ7, BYPASS_EQ_R_STG2, 5, 1)
8870    FIELD(L3_TM_EQ7, BYPASS_EQ_R_VAL_STG2, 0, 5)
8871REG32(L3_TM_EQ8, 0xd96c)
8872    FIELD(L3_TM_EQ8, TM_EQ8_31_8_RSVD, 24, 8)
8873    FIELD(L3_TM_EQ8, EQ_BYPASS_CALIB, 7, 1)
8874    FIELD(L3_TM_EQ8, EQ_SWEEP, 5, 2)
8875    FIELD(L3_TM_EQ8, SEL_SAMP, 2, 3)
8876    FIELD(L3_TM_EQ8, BYPASS_EQ_CAL, 1, 1)
8877    FIELD(L3_TM_EQ8, BYPASS_EQ_CAL_VAL, 0, 1)
8878REG32(L3_TM_EQ9, 0xd970)
8879    FIELD(L3_TM_EQ9, TM_EQ9_31_8_RSVD, 24, 8)
8880    FIELD(L3_TM_EQ9, UNUSED, 7, 1)
8881    FIELD(L3_TM_EQ9, EQ_BYPASS_CALIB_CODE, 0, 7)
8882REG32(L3_TM_EQ10, 0xd974)
8883    FIELD(L3_TM_EQ10, TM_EQ10_31_8_RSVD, 24, 8)
8884    FIELD(L3_TM_EQ10, UNUSED, 7, 1)
8885    FIELD(L3_TM_EQ10, OFFSET_COEF_SCALER, 4, 3)
8886    FIELD(L3_TM_EQ10, DIAG_OUTPUT_SEL, 0, 4)
8887REG32(L3_TM_EQ11, 0xd978)
8888    FIELD(L3_TM_EQ11, TM_EQ11_31_8_RSVD, 24, 8)
8889    FIELD(L3_TM_EQ11, EQ_CALIB_CLK_DIV_FORCE, 7, 1)
8890    FIELD(L3_TM_EQ11, EDGE_IS_FIRST, 6, 1)
8891    FIELD(L3_TM_EQ11, FORCE_EQ_OFFS_ON, 5, 1)
8892    FIELD(L3_TM_EQ11, FORCE_EQ_OFFS_OFF, 4, 1)
8893    FIELD(L3_TM_EQ11, EQ_OFFS_WITH_ADAPT, 3, 1)
8894    FIELD(L3_TM_EQ11, OFFSET_VOTER_OVERRIDE_EN, 2, 1)
8895    FIELD(L3_TM_EQ11, OFFSET_VOTER_OVERRIDE_NEG, 1, 1)
8896    FIELD(L3_TM_EQ11, OFFSET_VOTER_OVERRIDE_POS, 0, 1)
8897REG32(L3_TM_ILL7, 0xd97c)
8898    FIELD(L3_TM_ILL7, TM_ILL7_31_8_RSVD, 24, 8)
8899    FIELD(L3_TM_ILL7, ILL_CAL_INIT_WAIT, 0, 8)
8900REG32(L3_TM_ILL8, 0xd980)
8901    FIELD(L3_TM_ILL8, TM_ILL8_31_8_RSVD, 24, 8)
8902    FIELD(L3_TM_ILL8, ILL_CAL_ITER_WAIT, 0, 8)
8903REG32(L3_TM_ILL9, 0xd984)
8904    FIELD(L3_TM_ILL9, TM_ILL9_31_8_RSVD, 24, 8)
8905    FIELD(L3_TM_ILL9, ILL_CAL_BYPASS_CAP_START, 7, 1)
8906    FIELD(L3_TM_ILL9, ILL_CAL_CAP_START_VAL, 0, 7)
8907REG32(L3_TM_ILL10, 0xd988)
8908    FIELD(L3_TM_ILL10, TM_ILL10_31_8_RSVD, 24, 8)
8909    FIELD(L3_TM_ILL10, G3A_USB3_PCIEG2_PLL_CTR_11_8_BYP_VAL, 4, 4)
8910    FIELD(L3_TM_ILL10, G3B_PLL_CTR_11_8_BYP_VAL, 0, 4)
8911REG32(L3_TM_ILL11, 0xd98c)
8912    FIELD(L3_TM_ILL11, TM_ILL11_31_8_RSVD, 24, 8)
8913    FIELD(L3_TM_ILL11, G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL, 4, 4)
8914    FIELD(L3_TM_ILL11, G2B_PLL_CTR_11_8_BYP_VAL, 0, 4)
8915REG32(L3_TM_ILL12, 0xd990)
8916    FIELD(L3_TM_ILL12, TM_ILL12_31_8_RSVD, 24, 8)
8917    FIELD(L3_TM_ILL12, G1A_PLL_CTR_BYP_VAL, 0, 8)
8918REG32(L3_TM_ILL13, 0xd994)
8919    FIELD(L3_TM_ILL13, TM_ILL13_31_8_RSVD, 24, 8)
8920    FIELD(L3_TM_ILL13, ILL_CAL_IDLE_VAL_REFCNT, 0, 3)
8921REG32(L3_TM_ILL14, 0xd998)
8922    FIELD(L3_TM_ILL14, TM_ILL14_31_8_RSVD, 24, 8)
8923    FIELD(L3_TM_ILL14, ILL_CALIB_WAIT, 4, 4)
8924    FIELD(L3_TM_ILL14, ILL_CHG_WAIT, 0, 4)
8925REG32(L3_TM_FRZ_FSM0, 0xd99c)
8926    FIELD(L3_TM_FRZ_FSM0, TM_FRZ_FSM0_31_8_RSVD, 24, 8)
8927    FIELD(L3_TM_FRZ_FSM0, FREEZE_HSRX_PWR_SEQ_FSM, 0, 8)
8928REG32(L3_TM_FRZ_FSM1, 0xd9a0)
8929    FIELD(L3_TM_FRZ_FSM1, TM_FRZ_FSM1_31_8_RSVD, 24, 8)
8930    FIELD(L3_TM_FRZ_FSM1, UNUSED, 6, 2)
8931    FIELD(L3_TM_FRZ_FSM1, FREEZE_ILL_CALIB_FSM, 0, 6)
8932REG32(L3_TM_RST_DLY, 0xd9a4)
8933    FIELD(L3_TM_RST_DLY, TM_RST_DLY_31_8_RSVD, 24, 8)
8934    FIELD(L3_TM_RST_DLY, APB_RST_DLY, 0, 8)
8935REG32(L3_TM_ILL15, 0xd9a8)
8936    FIELD(L3_TM_ILL15, TM_ILL15_31_8_RSVD, 24, 8)
8937    FIELD(L3_TM_ILL15, ILL_CAL_REF_CTR_MSB_REG1, 0, 8)
8938REG32(L3_TM_MISC3, 0xd9ac)
8939    FIELD(L3_TM_MISC3, TM_MISC3_31_8_RSVD, 24, 8)
8940    FIELD(L3_TM_MISC3, AUX0_BIT_7, 7, 1)
8941    FIELD(L3_TM_MISC3, AUX0_BIT_6, 6, 1)
8942    FIELD(L3_TM_MISC3, AUX0_BIT_5, 5, 1)
8943    FIELD(L3_TM_MISC3, DBG_BUS_SEL, 2, 3)
8944    FIELD(L3_TM_MISC3, CDR_EN_FPL, 1, 1)
8945    FIELD(L3_TM_MISC3, CDR_EN_FFL, 0, 1)
8946REG32(L3_TM_EQ_OFFS1, 0xd9b0)
8947    FIELD(L3_TM_EQ_OFFS1, TM_EQ_OFFS1_31_8_RSVD, 24, 8)
8948    FIELD(L3_TM_EQ_OFFS1, EQ_OFFSET_CORR_BYP, 1, 7)
8949    FIELD(L3_TM_EQ_OFFS1, AUX1_BIT_7, 0, 1)
8950REG32(L3_TM_SAMP0, 0xd9b4)
8951    FIELD(L3_TM_SAMP0, TM_SAMP0_31_8_RSVD, 24, 8)
8952    FIELD(L3_TM_SAMP0, SAMP_CALIB_CLK_DIV_FACTOR, 1, 7)
8953    FIELD(L3_TM_SAMP0, SAMP_CALIB_CLK_DIV_FORCE, 0, 1)
8954REG32(L3_TM_EQ12, 0xd9b8)
8955    FIELD(L3_TM_EQ12, TM_EQ12_31_8_RSVD, 24, 8)
8956    FIELD(L3_TM_EQ12, EQ_CALIB_CLK_DIV_FACTOR, 0, 8)
8957REG32(L3_TM_MISC4, 0xd9bc)
8958    FIELD(L3_TM_MISC4, TM_MISC4_31_8_RSVD, 24, 8)
8959    FIELD(L3_TM_MISC4, PSO_CLK_LANE_FRM_PCS, 2, 1)
8960    FIELD(L3_TM_MISC4, BSCAN_MODE_VAL, 1, 1)
8961    FIELD(L3_TM_MISC4, BSCAN_FORCE_MODE, 0, 1)
8962REG32(L3_TM_SAMP_STATUS0, 0xda80)
8963    FIELD(L3_TM_SAMP_STATUS0, TM_SAMP_STATUS0_31_8_RSVD, 24, 8)
8964    FIELD(L3_TM_SAMP_STATUS0, IQ_SAMP_PH0_CALIB_CODE, 0, 6)
8965REG32(L3_TM_SAMP_STATUS1, 0xda84)
8966    FIELD(L3_TM_SAMP_STATUS1, TM_SAMP_STATUS1_31_8_RSVD, 24, 8)
8967    FIELD(L3_TM_SAMP_STATUS1, IQ_SAMP_PH90_CALIB_CODE, 0, 6)
8968REG32(L3_TM_SAMP_STATUS2, 0xda88)
8969    FIELD(L3_TM_SAMP_STATUS2, TM_SAMP_STATUS2_31_8_RSVD, 24, 8)
8970    FIELD(L3_TM_SAMP_STATUS2, IQ_SAMP_PH180_CALIB_CODE, 0, 6)
8971REG32(L3_TM_SAMP_STATUS3, 0xda8c)
8972    FIELD(L3_TM_SAMP_STATUS3, TM_SAMP_STATUS3_31_8_RSVD, 24, 8)
8973    FIELD(L3_TM_SAMP_STATUS3, IQ_SAMP_PH270_CALIB_CODE, 0, 6)
8974REG32(L3_TM_SAMP_STATUS4, 0xda90)
8975    FIELD(L3_TM_SAMP_STATUS4, TM_SAMP_STATUS4_31_8_RSVD, 24, 8)
8976    FIELD(L3_TM_SAMP_STATUS4, E_SAMP_PH0_CALIB_CODE, 0, 6)
8977REG32(L3_TM_SAMP_STATUS5, 0xda94)
8978    FIELD(L3_TM_SAMP_STATUS5, TM_SAMP_STATUS5_31_8_RSVD, 24, 8)
8979    FIELD(L3_TM_SAMP_STATUS5, E_SAMP_PH180_CALIB_CODE, 0, 6)
8980REG32(L3_TM_ILL_STATUS0, 0xda98)
8981    FIELD(L3_TM_ILL_STATUS0, TM_ILL_STATUS0_31_8_RSVD, 24, 8)
8982    FIELD(L3_TM_ILL_STATUS0, IQ_F0_CALCODE_CALIB_VAL, 0, 7)
8983REG32(L3_TM_ILL_STATUS1, 0xda9c)
8984    FIELD(L3_TM_ILL_STATUS1, TM_ILL_STATUS1_31_8_RSVD, 24, 8)
8985    FIELD(L3_TM_ILL_STATUS1, IQ_F1_CALCODE_CALIB_VAL, 0, 7)
8986REG32(L3_TM_ILL_STATUS2, 0xdaa0)
8987    FIELD(L3_TM_ILL_STATUS2, TM_ILL_STATUS2_31_8_RSVD, 24, 8)
8988    FIELD(L3_TM_ILL_STATUS2, IQ_F2_CALCODE_CALIB_VAL, 0, 7)
8989REG32(L3_TM_ILL_STATUS3, 0xdaa4)
8990    FIELD(L3_TM_ILL_STATUS3, TM_ILL_STATUS3_31_8_RSVD, 24, 8)
8991    FIELD(L3_TM_ILL_STATUS3, IQ_F3_CALCODE_CALIB_VAL, 0, 7)
8992REG32(L3_TM_ILL_STATUS4, 0xdaa8)
8993    FIELD(L3_TM_ILL_STATUS4, TM_ILL_STATUS4_31_8_RSVD, 24, 8)
8994    FIELD(L3_TM_ILL_STATUS4, IQ_F4_CALCODE_CALIB_VAL, 0, 7)
8995REG32(L3_TM_ILL_STATUS5, 0xdaac)
8996    FIELD(L3_TM_ILL_STATUS5, TM_ILL_STATUS5_31_8_RSVD, 24, 8)
8997    FIELD(L3_TM_ILL_STATUS5, IQ_F5_CALCODE_CALIB_VAL, 0, 7)
8998REG32(L3_TM_ILL_STATUS6, 0xdab0)
8999    FIELD(L3_TM_ILL_STATUS6, TM_ILL_STATUS6_31_8_RSVD, 24, 8)
9000    FIELD(L3_TM_ILL_STATUS6, E_F0_CALCODE_CALIB_VAL, 0, 7)

9001REG32(L3_TM_ILL_STATUS7, 0xdab4)
9002    FIELD(L3_TM_ILL_STATUS7, TM_ILL_STATUS7_31_8_RSVD, 24, 8)
9003    FIELD(L3_TM_ILL_STATUS7, E_F1_CALCODE_CALIB_VAL, 0, 7)
9004REG32(L3_TM_ILL_STATUS8, 0xdab8)
9005    FIELD(L3_TM_ILL_STATUS8, TM_ILL_STATUS8_31_8_RSVD, 24, 8)
9006    FIELD(L3_TM_ILL_STATUS8, E_F2_CALCODE_CALIB_VAL, 0, 7)
9007REG32(L3_TM_ILL_STATUS9, 0xdabc)
9008    FIELD(L3_TM_ILL_STATUS9, TM_ILL_STATUS9_31_8_RSVD, 24, 8)
9009    FIELD(L3_TM_ILL_STATUS9, E_F3_CALCODE_CALIB_VAL, 0, 7)
9010REG32(L3_TM_ILL_STATUS10, 0xdac0)
9011    FIELD(L3_TM_ILL_STATUS10, TM_ILL_STATUS10_31_8_RSVD, 24, 8)
9012    FIELD(L3_TM_ILL_STATUS10, E_F4_CALCODE_CALIB_VAL, 0, 7)
9013REG32(L3_TM_ILL_STATUS11, 0xdac4)
9014    FIELD(L3_TM_ILL_STATUS11, TM_ILL_STATUS11_31_8_RSVD, 24, 8)
9015    FIELD(L3_TM_ILL_STATUS11, E_F5_CALCODE_CALIB_VAL, 0, 7)
9016REG32(L3_TM_MISC_ST_0, 0xdac8)
9017    FIELD(L3_TM_MISC_ST_0, TM_MISC_ST_0_31_8_RSVD, 24, 8)
9018    FIELD(L3_TM_MISC_ST_0, EYE_SURF_DONE, 5, 1)
9019    FIELD(L3_TM_MISC_ST_0, SD_CAL_DONE, 4, 1)
9020    FIELD(L3_TM_MISC_ST_0, SAMP_CAL_DONE, 3, 1)
9021    FIELD(L3_TM_MISC_ST_0, ILL_CAL_DONE, 2, 1)
9022    FIELD(L3_TM_MISC_ST_0, EQ_CAL_DONE, 1, 1)
9023    FIELD(L3_TM_MISC_ST_0, EQ_VALID_ADAPT_CODE, 0, 1)
9024REG32(L3_TM_SD_ST_0, 0xdacc)
9025    FIELD(L3_TM_SD_ST_0, TM_SD_ST_0_31_8_RSVD, 24, 8)
9026    FIELD(L3_TM_SD_ST_0, SD_CAL_CODE, 0, 6)
9027REG32(L3_TM_EYESURF_ST0, 0xdad0)
9028    FIELD(L3_TM_EYESURF_ST0, TM_EYESURF_ST0_31_8_RSVD, 24, 8)
9029    FIELD(L3_TM_EYESURF_ST0, ERROR_COUNT0, 0, 8)
9030REG32(L3_TM_EYESURF_ST1, 0xdad4)
9031    FIELD(L3_TM_EYESURF_ST1, TM_EYESURF_ST1_31_8_RSVD, 24, 8)
9032    FIELD(L3_TM_EYESURF_ST1, ERROR_COUNT1, 0, 8)
9033REG32(L3_TM_EQ_ST0, 0xdad8)
9034    FIELD(L3_TM_EQ_ST0, TM_EQ_ST0_31_8_RSVD, 24, 8)
9035    FIELD(L3_TM_EQ_ST0, EQ_ADAPT_CODE0, 0, 8)
9036REG32(L3_TM_EQ_ST1, 0xdadc)
9037    FIELD(L3_TM_EQ_ST1, TM_EQ_ST1_31_8_RSVD, 24, 8)
9038    FIELD(L3_TM_EQ_ST1, EQ_ADAPT_CODE1, 0, 8)
9039REG32(L3_TM_EQ_ST2, 0xdae0)
9040    FIELD(L3_TM_EQ_ST2, TM_EQ_ST2_31_8_RSVD, 24, 8)
9041    FIELD(L3_TM_EQ_ST2, EQ_CALIB_CODE, 0, 7)
9042REG32(L3_TM_RXPMA_ST1, 0xdae4)
9043    FIELD(L3_TM_RXPMA_ST1, TM_RXPMA_ST1_31_8_RSVD, 24, 8)
9044    FIELD(L3_TM_RXPMA_ST1, HSRX_OPMODE_STATUS, 0, 8)
9045REG32(L3_TM_CDR0, 0xdc00)
9046    FIELD(L3_TM_CDR0, TM_CDR0_31_8_RSVD, 24, 8)
9047    FIELD(L3_TM_CDR0, FAST_PHASE_LOCK_FORCE, 7, 1)
9048    FIELD(L3_TM_CDR0, UNUSED, 5, 2)
9049    FIELD(L3_TM_CDR0, CDR_LOOP_CTRL, 2, 3)
9050    FIELD(L3_TM_CDR0, SECOND_ORDER_LOOP_DIS, 1, 1)
9051    FIELD(L3_TM_CDR0, FIRST_ORDER_LOOP_DIS, 0, 1)
9052REG32(L3_TM_CDR1, 0xdc04)
9053    FIELD(L3_TM_CDR1, TM_CDR1_31_8_RSVD, 24, 8)
9054    FIELD(L3_TM_CDR1, RESET_DELAY_2OL, 0, 8)
9055REG32(L3_TM_CDR2, 0xdc08)
9056    FIELD(L3_TM_CDR2, TM_CDR2_31_8_RSVD, 24, 8)
9057    FIELD(L3_TM_CDR2, CLK_SEL_2OL, 6, 2)
9058    FIELD(L3_TM_CDR2, INTEGRATOR_THRESH_2OL, 0, 6)
9059REG32(L3_TM_CDR3, 0xdc0c)
9060    FIELD(L3_TM_CDR3, TM_CDR3_31_8_RSVD, 24, 8)
9061    FIELD(L3_TM_CDR3, UNUSED, 7, 1)
9062    FIELD(L3_TM_CDR3, SIGNAL_THRESH_1OL, 0, 7)
9063REG32(L3_TM_CDR4, 0xdc10)
9064    FIELD(L3_TM_CDR4, TM_CDR4_31_8_RSVD, 24, 8)
9065    FIELD(L3_TM_CDR4, UNUSED, 7, 1)
9066    FIELD(L3_TM_CDR4, SIGNAL_THRESH_2OL, 0, 7)
9067REG32(L3_TM_CDR5, 0xdc14)
9068    FIELD(L3_TM_CDR5, TM_CDR5_31_8_RSVD, 24, 8)
9069    FIELD(L3_TM_CDR5, FPHL_FSM_ACC_CYCLES, 5, 3)
9070    FIELD(L3_TM_CDR5, FFL_PH0_INT_GAIN, 0, 5)
9071REG32(L3_TM_CDR6, 0xdc18)
9072    FIELD(L3_TM_CDR6, TM_CDR6_31_8_RSVD, 24, 8)
9073    FIELD(L3_TM_CDR6, FPHL_FSM_DELAY_CYCLES, 5, 3)
9074    FIELD(L3_TM_CDR6, FFL_PH1_INT_GAIN, 0, 5)
9075REG32(L3_TM_CDR7, 0xdc1c)
9076    FIELD(L3_TM_CDR7, TM_CDR7_31_8_RSVD, 24, 8)
9077    FIELD(L3_TM_CDR7, FPHL_FSM_TRIGGER1_WAIT_CYCLES, 5, 3)
9078    FIELD(L3_TM_CDR7, FFL_PH2_INT_GAIN, 0, 5)
9079REG32(L3_TM_CDR8, 0xdc20)
9080    FIELD(L3_TM_CDR8, TM_CDR8_31_8_RSVD, 24, 8)
9081    FIELD(L3_TM_CDR8, FPHL_FSM_TRIGGER2_WAIT_CYCLES, 5, 3)
9082    FIELD(L3_TM_CDR8, FFL_PH3_INT_GAIN, 0, 5)
9083REG32(L3_TM_CDR9, 0xdc24)
9084    FIELD(L3_TM_CDR9, TM_CDR9_31_8_RSVD, 24, 8)
9085    FIELD(L3_TM_CDR9, FPHL_FSM_TRIGGER3_WAIT_CYCLES, 5, 3)
9086    FIELD(L3_TM_CDR9, FFL_PH4_INT_GAIN, 0, 5)
9087REG32(L3_TM_CDR10, 0xdc28)
9088    FIELD(L3_TM_CDR10, TM_CDR10_31_8_RSVD, 24, 8)
9089    FIELD(L3_TM_CDR10, FFL_TIME_PER_PHASE_10_8, 5, 3)
9090    FIELD(L3_TM_CDR10, FFL_PH5_INT_GAIN, 0, 5)
9091REG32(L3_TM_CDR11, 0xdc2c)
9092    FIELD(L3_TM_CDR11, TM_CDR11_31_8_RSVD, 24, 8)
9093    FIELD(L3_TM_CDR11, UNUSED, 5, 3)
9094    FIELD(L3_TM_CDR11, FFL_PH6_INT_GAIN, 0, 5)
9095REG32(L3_TM_CDR12, 0xdc30)
9096    FIELD(L3_TM_CDR12, TM_CDR12_31_8_RSVD, 24, 8)
9097    FIELD(L3_TM_CDR12, CDRLF_RESET_ON_EN_CDR, 7, 1)
9098    FIELD(L3_TM_CDR12, CDRLF_RESET_ON_INT_MAX_2OL, 6, 1)
9099    FIELD(L3_TM_CDR12, CDRLF_RESET_ON_MODE_CHG, 5, 1)
9100    FIELD(L3_TM_CDR12, FFL_PH7_INT_GAIN, 0, 5)
9101REG32(L3_TM_CDR13, 0xdc34)
9102    FIELD(L3_TM_CDR13, TM_CDR13_31_8_RSVD, 24, 8)
9103    FIELD(L3_TM_CDR13, FFL_TIME_PER_PHASE_7_0, 0, 8)
9104REG32(L3_TM_CDR14, 0xdc38)
9105    FIELD(L3_TM_CDR14, TM_CDR14_31_8_RSVD, 24, 8)
9106    FIELD(L3_TM_CDR14, FFL_PH3_POST_INT_GAIN, 6, 2)
9107    FIELD(L3_TM_CDR14, FFL_PH2_POST_INT_GAIN, 4, 2)
9108    FIELD(L3_TM_CDR14, FFL_PH1_POST_INT_GAIN, 2, 2)
9109    FIELD(L3_TM_CDR14, FFL_PH0_POST_INT_GAIN, 0, 2)
9110REG32(L3_TM_CDR15, 0xdc3c)
9111    FIELD(L3_TM_CDR15, TM_CDR15_31_8_RSVD, 24, 8)
9112    FIELD(L3_TM_CDR15, FFL_PH7_POST_INT_GAIN, 6, 2)
9113    FIELD(L3_TM_CDR15, FFL_PH6_POST_INT_GAIN, 4, 2)
9114    FIELD(L3_TM_CDR15, FFL_PH5_POST_INT_GAIN, 2, 2)
9115    FIELD(L3_TM_CDR15, FFL_PH4_POST_INT_GAIN, 0, 2)
9116REG32(L3_TM_CDR16, 0xdc40)
9117    FIELD(L3_TM_CDR16, TM_CDR16_31_8_RSVD, 24, 8)
9118    FIELD(L3_TM_CDR16, UNUSED, 5, 3)
9119    FIELD(L3_TM_CDR16, FFL_PH0_PROP_GAIN, 0, 5)
9120REG32(L3_TM_CDR17, 0xdc44)
9121    FIELD(L3_TM_CDR17, TM_CDR17_31_8_RSVD, 24, 8)
9122    FIELD(L3_TM_CDR17, UNUSED, 5, 3)
9123    FIELD(L3_TM_CDR17, FFL_PH1_PROP_GAIN, 0, 5)
9124REG32(L3_TM_CDR18, 0xdc48)
9125    FIELD(L3_TM_CDR18, TM_CDR18_31_8_RSVD, 24, 8)
9126    FIELD(L3_TM_CDR18, UNUSED, 5, 3)
9127    FIELD(L3_TM_CDR18, FFL_PH2_PROP_GAIN, 0, 5)
9128REG32(L3_TM_CDR19, 0xdc4c)
9129    FIELD(L3_TM_CDR19, TM_CDR19_31_8_RSVD, 24, 8)
9130    FIELD(L3_TM_CDR19, UNUSED, 5, 3)
9131    FIELD(L3_TM_CDR19, FFL_PH3_PROP_GAIN, 0, 5)
9132REG32(L3_TM_CDR20, 0xdc50)
9133    FIELD(L3_TM_CDR20, TM_CDR20_31_8_RSVD, 24, 8)
9134    FIELD(L3_TM_CDR20, UNUSED, 5, 3)
9135    FIELD(L3_TM_CDR20, FFL_PH4_PROP_GAIN, 0, 5)
9136REG32(L3_TM_CDR21, 0xdc54)
9137    FIELD(L3_TM_CDR21, TM_CDR21_31_8_RSVD, 24, 8)
9138    FIELD(L3_TM_CDR21, UNUSED, 5, 3)
9139    FIELD(L3_TM_CDR21, FFL_PH5_PROP_GAIN, 0, 5)
9140REG32(L3_TM_CDR22, 0xdc58)
9141    FIELD(L3_TM_CDR22, TM_CDR22_31_8_RSVD, 24, 8)
9142    FIELD(L3_TM_CDR22, UNUSED, 5, 3)
9143    FIELD(L3_TM_CDR22, FFL_PH6_PROP_GAIN, 0, 5)
9144REG32(L3_TM_CDR23, 0xdc5c)
9145    FIELD(L3_TM_CDR23, TM_CDR23_31_8_RSVD, 24, 8)
9146    FIELD(L3_TM_CDR23, UNUSED, 7, 1)
9147    FIELD(L3_TM_CDR23, PHASE_LAG_LEAD_RESPONSE, 5, 2)
9148    FIELD(L3_TM_CDR23, FFL_PH7_PROP_GAIN, 0, 5)
9149REG32(L3_TM_MISC0, 0xdc60)
9150    FIELD(L3_TM_MISC0, TM_MISC0_31_8_RSVD, 24, 8)
9151    FIELD(L3_TM_MISC0, UNUSED, 2, 6)
9152    FIELD(L3_TM_MISC0, DBG0_SEL, 0, 2)
9153REG32(L3_TM_HSRX_ST0, 0xdc64)
9154    FIELD(L3_TM_HSRX_ST0, TM_HSRX_ST0_31_8_RSVD, 24, 8)
9155    FIELD(L3_TM_HSRX_ST0, FAST_LOCK_STATUS, 0, 1)
9156REG32(L3_TM_PLL_LS_CLOCK, 0xe000)
9157    FIELD(L3_TM_PLL_LS_CLOCK, TM_PLL_LS_CLOCK_31_8_RSVD, 24, 8)
9158    FIELD(L3_TM_PLL_LS_CLOCK, TM_PLL_LS_CLOCK, 0, 8)
9159REG32(L3_TM_PLL_LOOP_FILT, 0xe004)
9160    FIELD(L3_TM_PLL_LOOP_FILT, TM_PLL_LOOP_FILT_31_8_RSVD, 24, 8)
9161    FIELD(L3_TM_PLL_LOOP_FILT, TM_FORCE_RES_SW_ON, 7, 1)
9162    FIELD(L3_TM_PLL_LOOP_FILT, TM_MPHY_USB3_R2_HIGH_RES_SW_ON, 6, 1)
9163    FIELD(L3_TM_PLL_LOOP_FILT, TM_MPHY_USB3_R2_LOW_RES_SW_ON, 5, 1)
9164    FIELD(L3_TM_PLL_LOOP_FILT, TM_PCIE_R1_DEFAULT_RES_SW_ON, 4, 1)
9165    FIELD(L3_TM_PLL_LOOP_FILT, TM_PCIE_R1_HIGH_RES_SW_ON, 3, 1)
9166    FIELD(L3_TM_PLL_LOOP_FILT, TM_PCIE_R1_LOW_RES_SW_ON, 2, 1)
9167    FIELD(L3_TM_PLL_LOOP_FILT, TM_BYPASS_SEC_LOOP_FILTER, 1, 1)
9168    FIELD(L3_TM_PLL_LOOP_FILT, TM_SEC_LOOP, 0, 1)
9169REG32(L3_TM_PLL_DIG2, 0xe008)
9170    FIELD(L3_TM_PLL_DIG2, TM_PLL_DIG2_31_8_RSVD, 24, 8)
9171    FIELD(L3_TM_PLL_DIG2, TM_FBDIV_0_LSB, 7, 1)
9172    FIELD(L3_TM_PLL_DIG2, TM_PLL_HS_CLOCK_0, 0, 7)
9173REG32(L3_TM_PLL_FBDIV, 0xe00c)
9174    FIELD(L3_TM_PLL_FBDIV, TM_PLL_FBDIV_31_8_RSVD, 24, 8)
9175    FIELD(L3_TM_PLL_FBDIV, TM_FBDIV_1, 0, 8)
9176REG32(L3_TM_PLL_DIG4, 0xe010)
9177    FIELD(L3_TM_PLL_DIG4, TM_PLL_DIG4_31_8_RSVD, 24, 8)
9178    FIELD(L3_TM_PLL_DIG4, TM_VCO_CLOCK_PULDN, 7, 1)
9179    FIELD(L3_TM_PLL_DIG4, TM_FORCE_ANA_COARSEDONE, 6, 1)
9180    FIELD(L3_TM_PLL_DIG4, TM_ANA_COARSEDONE, 5, 1)
9181    FIELD(L3_TM_PLL_DIG4, TM_FORCE_COARSE_DONE_INT, 4, 1)
9182    FIELD(L3_TM_PLL_DIG4, TM_COARSE_DONE_INT, 3, 1)
9183    FIELD(L3_TM_PLL_DIG4, TM_FORCE_FBDIV, 2, 1)
9184    FIELD(L3_TM_PLL_DIG4, TM_FBDIV_2, 0, 2)
9185REG32(L3_TM_PLL_DIG5, 0xe014)
9186    FIELD(L3_TM_PLL_DIG5, TM_PLL_DIG5_31_8_RSVD, 24, 8)
9187    FIELD(L3_TM_PLL_DIG5, TM_PD_6GHZ_LOWNOISE_RING, 7, 1)
9188    FIELD(L3_TM_PLL_DIG5, TM_PD_6GHZ_RING, 6, 1)
9189    FIELD(L3_TM_PLL_DIG5, TM_COARSE_PROG, 1, 5)
9190    FIELD(L3_TM_PLL_DIG5, TM_FORCE_VCO_CLOCK_PULDN, 0, 1)
9191REG32(L3_TM_PLL_DIG6, 0xe018)
9192    FIELD(L3_TM_PLL_DIG6, TM_PLL_DIG6_31_8_RSVD, 24, 8)
9193    FIELD(L3_TM_PLL_DIG6, TM_CONFG_CHNG_CYCLES_0_LSB, 7, 1)
9194    FIELD(L3_TM_PLL_DIG6, TM_VCO_SETTLE_CYCLES, 5, 2)
9195    FIELD(L3_TM_PLL_DIG6, TM_INITIAL_WAIT_CYCLES, 3, 2)
9196    FIELD(L3_TM_PLL_DIG6, TM_FORCE_COARSE_PROG_PD_RING, 2, 1)
9197    FIELD(L3_TM_PLL_DIG6, TM_PD_1P5GHZ_RING, 1, 1)
9198    FIELD(L3_TM_PLL_DIG6, TM_PD_3GHZ_RING, 0, 1)
9199REG32(L3_TM_PLL_DIG7, 0xe01c)
9200    FIELD(L3_TM_PLL_DIG7, TM_PLL_DIG7_31_8_RSVD, 24, 8)
9201    FIELD(L3_TM_PLL_DIG7, TM_CPUMP_CODE_0_LSB, 7, 1)
9202    FIELD(L3_TM_PLL_DIG7, TM_FORCE_ANA_START_LOOP, 6, 1)
9203    FIELD(L3_TM_PLL_DIG7, TM_ANA_START_LOOP, 5, 1)
9204    FIELD(L3_TM_PLL_DIG7, TM_PLL_LOCK_CYCLES, 3, 2)
9205    FIELD(L3_TM_PLL_DIG7, TM_STAND_BY_SETTLE_CYCLES, 1, 2)
9206    FIELD(L3_TM_PLL_DIG7, TM_CONFG_CHNG_CYCLES_1_MSB, 0, 1)
9207REG32(L3_TM_PLL_CPUMP_CODE_1, 0xe020)
9208    FIELD(L3_TM_PLL_CPUMP_CODE_1, TM_PLL_CPUMP_CODE_1_31_8_RSVD, 24, 8)
9209    FIELD(L3_TM_PLL_CPUMP_CODE_1, TM_CPUMP_CODE_1, 0, 8)
9210REG32(L3_TM_PLL_DIG9, 0xe024)
9211    FIELD(L3_TM_PLL_DIG9, TM_PLL_DIG9_31_8_RSVD, 24, 8)
9212    FIELD(L3_TM_PLL_DIG9, TM_PLL_RSVD, 6, 2)
9213    FIELD(L3_TM_PLL_DIG9, TM_FB_BY2_BYPASS, 5, 1)
9214    FIELD(L3_TM_PLL_DIG9, TM_FORCE_CP_CODE, 4, 1)
9215    FIELD(L3_TM_PLL_DIG9, TM_CPUMP_CODE_2_MSB, 0, 4)
9216REG32(L3_TM_PLL_COARSE_CODE_LSB, 0xe028)
9217    FIELD(L3_TM_PLL_COARSE_CODE_LSB, TM_PLL_COARSE_CODE_LSB_31_8_RSVD, 24, 8)
9218    FIELD(L3_TM_PLL_COARSE_CODE_LSB, TM_COARSE_CODE_LSB, 0, 8)
9219REG32(L3_TM_PLL_DIG11, 0xe02c)
9220    FIELD(L3_TM_PLL_DIG11, TM_PLL_DIG11_31_8_RSVD, 24, 8)
9221    FIELD(L3_TM_PLL_DIG11, TM_CONST_NDAC_CNTRL, 4, 4)
9222    FIELD(L3_TM_PLL_DIG11, TM_FORCE_COARSE_CODE, 3, 1)
9223    FIELD(L3_TM_PLL_DIG11, TM_COARSE_CODE_MSB, 0, 3)
9224REG32(L3_TM_PLL_DIG12, 0xe030)
9225    FIELD(L3_TM_PLL_DIG12, TM_PLL_DIG12_31_8_RSVD, 24, 8)
9226    FIELD(L3_TM_PLL_DIG12, TM_FORCE_PTAT_NDAC_CNTRL, 7, 1)
9227    FIELD(L3_TM_PLL_DIG12, TM_PTAT_NDAC_CNTRL, 1, 6)
9228    FIELD(L3_TM_PLL_DIG12, TM_FORCE_CONST_NDAC_CNTRL, 0, 1)
9229REG32(L3_TM_PLL_CONST_PMOS, 0xe034)
9230    FIELD(L3_TM_PLL_CONST_PMOS, TM_PLL_CONST_PMOS_31_8_RSVD, 24, 8)
9231    FIELD(L3_TM_PLL_CONST_PMOS, TM_CONST_PMOS_CNTRL, 0, 8)
9232REG32(L3_TM_PLL_DIG14, 0xe038)
9233    FIELD(L3_TM_PLL_DIG14, TM_PLL_DIG14_31_8_RSVD, 24, 8)
9234    FIELD(L3_TM_PLL_DIG14, TM_COARSE_CODE_AFTER_V2I_0_LSB, 1, 7)
9235    FIELD(L3_TM_PLL_DIG14, TM_FORCE_CONST_PMOS_CNTRL, 0, 1)
9236REG32(L3_TM_PLL_DIG15, 0xe03c)
9237    FIELD(L3_TM_PLL_DIG15, TM_PLL_DIG15_31_8_RSVD, 24, 8)
9238    FIELD(L3_TM_PLL_DIG15, TM_V2I_CODE_0_LSB, 5, 3)
9239    FIELD(L3_TM_PLL_DIG15, TM_FORCE_COARSE_CODE_AFTER_V2I, 4, 1)
9240    FIELD(L3_TM_PLL_DIG15, TM_COARSE_CODE_AFTER_V2I_1_MSB, 0, 4)
9241REG32(L3_TM_PLL_DIG16, 0xe040)
9242    FIELD(L3_TM_PLL_DIG16, TM_PLL_DIG16_31_8_RSVD, 24, 8)
9243    FIELD(L3_TM_PLL_DIG16, TM_FORCE_PLL_LOCK, 7, 1)
9244    FIELD(L3_TM_PLL_DIG16, TM_PLL_LOCK, 6, 1)
9245    FIELD(L3_TM_PLL_DIG16, TM_FORCE_SS_NO_STEPS_STEP_SIZE, 5, 1)
9246    FIELD(L3_TM_PLL_DIG16, TM_PLL_RSVD, 4, 1)
9247    FIELD(L3_TM_PLL_DIG16, TM_FORCE_V2I_CODE, 3, 1)
9248    FIELD(L3_TM_PLL_DIG16, TM_V2I_CODE_1_MSB, 0, 3)
9249REG32(L3_TM_PLL_DIG17, 0xe044)
9250    FIELD(L3_TM_PLL_DIG17, TM_PLL_DIG17_31_8_RSVD, 24, 8)
9251    FIELD(L3_TM_PLL_DIG17, TM_FB_CLK, 6, 2)
9252    FIELD(L3_TM_PLL_DIG17, TM_MODE_DEPTH, 3, 3)
9253    FIELD(L3_TM_PLL_DIG17, TM_MODE_RATE, 0, 3)
9254REG32(L3_TM_PLL_DIG18, 0xe048)
9255    FIELD(L3_TM_PLL_DIG18, TM_PLL_DIG18_31_8_RSVD, 24, 8)
9256    FIELD(L3_TM_PLL_DIG18, TM_PLL_LOCK_PULDN, 7, 1)
9257    FIELD(L3_TM_PLL_DIG18, TM_STEP_SIZE_CNTRL, 5, 2)
9258    FIELD(L3_TM_PLL_DIG18, TM_SD_GSHIFT, 3, 2)
9259    FIELD(L3_TM_PLL_DIG18, TM_SD_DITHER, 1, 2)
9260    FIELD(L3_TM_PLL_DIG18, TM_PLL_LOCK_INT, 0, 1)
9261REG32(L3_TM_PLL_DIG19, 0xe04c)
9262    FIELD(L3_TM_PLL_DIG19, TM_PLL_DIG19_31_8_RSVD, 24, 8)
9263    FIELD(L3_TM_PLL_DIG19, TM_FORCE_EN_CLOCK_HS_DIV_2, 7, 1)
9264    FIELD(L3_TM_PLL_DIG19, TM_EN_CLOCK_HS_DIV_2, 6, 1)
9265    FIELD(L3_TM_PLL_DIG19, TM_PLL_HS_CLOCK_1, 3, 3)
9266    FIELD(L3_TM_PLL_DIG19, TM_PD_PFD, 2, 1)
9267    FIELD(L3_TM_PLL_DIG19, TM_FORCE_PD_PFD, 1, 1)
9268    FIELD(L3_TM_PLL_DIG19, TM_SELECT_PCI_2P5, 0, 1)
9269REG32(L3_TM_PLL_DIG20, 0xe050)
9270    FIELD(L3_TM_PLL_DIG20, TM_PLL_DIG20_31_8_RSVD, 24, 8)
9271    FIELD(L3_TM_PLL_DIG20, TM_PLL_HALF_FULL_RATE, 7, 1)
9272    FIELD(L3_TM_PLL_DIG20, TM_PLL_RSVD, 6, 1)
9273    FIELD(L3_TM_PLL_DIG20, TM_V2I_PROG, 1, 5)
9274    FIELD(L3_TM_PLL_DIG20, TM_FORCE_V2I_PROG, 0, 1)
9275REG32(L3_TM_PLL_DIG21, 0xe054)
9276    FIELD(L3_TM_PLL_DIG21, TM_PLL_DIG21_31_8_RSVD, 24, 8)
9277    FIELD(L3_TM_PLL_DIG21, TM_FORCE_EN_PLL_LDO_0P9_REF, 7, 1)
9278    FIELD(L3_TM_PLL_DIG21, ANA_TM_EN_PLL_0P9_FORCE_SW, 6, 1)
9279    FIELD(L3_TM_PLL_DIG21, TM_PLL_PD_OPDIV_SYM, 5, 1)
9280    FIELD(L3_TM_PLL_DIG21, TM_FORCE_PLL_PD_OPDIV_SYM, 4, 1)
9281    FIELD(L3_TM_PLL_DIG21, TM_PLL_RSVD_1, 3, 1)
9282    FIELD(L3_TM_PLL_DIG21, TM_PLL_RSVD_2, 2, 1)
9283    FIELD(L3_TM_PLL_DIG21, TM_PLL_EN, 1, 1)
9284    FIELD(L3_TM_PLL_DIG21, TM_FORCE_PLL_EN, 0, 1)
9285REG32(L3_TM_PLL_DIG22, 0xe058)
9286    FIELD(L3_TM_PLL_DIG22, TM_PLL_DIG22_31_8_RSVD, 24, 8)
9287    FIELD(L3_TM_PLL_DIG22, TM_PLL_RSVD, 7, 1)
9288    FIELD(L3_TM_PLL_DIG22, TM_EN_PLL_LDO_0P9_REF_CP, 6, 1)
9289    FIELD(L3_TM_PLL_DIG22, TM_FORCE_EN_PLL_LDO_0P9_REF_CP, 5, 1)
9290    FIELD(L3_TM_PLL_DIG22, TM_FORCE_COARSE_START, 4, 1)
9291    FIELD(L3_TM_PLL_DIG22, TM_FORCE_PD_PLL_LDO_1P4, 3, 1)
9292    FIELD(L3_TM_PLL_DIG22, TM_FORCE_ANA_EN_LL_DELAYED, 2, 1)
9293    FIELD(L3_TM_PLL_DIG22, TM_FORCE_ANA_EN_LL, 1, 1)
9294    FIELD(L3_TM_PLL_DIG22, TM_EN_PLL_LDO_0P9_REF, 0, 1)
9295REG32(L3_TM_PLL_DIG23, 0xe05c)
9296    FIELD(L3_TM_PLL_DIG23, TM_PLL_DIG23_31_8_RSVD, 24, 8)
9297    FIELD(L3_TM_PLL_DIG23, BF_7, 7, 1)
9298    FIELD(L3_TM_PLL_DIG23, PLL_TM_VCO_LDO_BYPASS, 6, 1)
9299    FIELD(L3_TM_PLL_DIG23, TM_ANA_EN_LL_DELAYED, 5, 1)
9300    FIELD(L3_TM_PLL_DIG23, TM_ANA_EN_LL, 4, 1)
9301    FIELD(L3_TM_PLL_DIG23, TM_ANA_PD_PLL, 3, 1)
9302    FIELD(L3_TM_PLL_DIG23, TM_FORCE_PLL_PD, 2, 1)
9303    FIELD(L3_TM_PLL_DIG23, TM_ANA_COARSE_START, 1, 1)
9304    FIELD(L3_TM_PLL_DIG23, TM_PD_PLL_LDO_1P4, 0, 1)
9305REG32(L3_TM_PLL_DIG24, 0xe060)
9306    FIELD(L3_TM_PLL_DIG24, TM_PLL_DIG24_31_8_RSVD, 24, 8)
9307    FIELD(L3_TM_PLL_DIG24, TM_PLL_RSVD, 7, 1)
9308    FIELD(L3_TM_PLL_DIG24, PLL_TM_VCO_LDO, 1, 6)
9309    FIELD(L3_TM_PLL_DIG24, PLL_TM_VCO_LDO_BYPASS_WITH_SEQUENCE, 0, 1)
9310REG32(L3_TM_PLL_DIG25, 0xe064)
9311    FIELD(L3_TM_PLL_DIG25, TM_PLL_DIG25_31_8_RSVD, 24, 8)
9312    FIELD(L3_TM_PLL_DIG25, TM_FORCE_RST_N_HSRIPPLE, 7, 1)
9313    FIELD(L3_TM_PLL_DIG25, TM_RST_N_HSRIPPLE, 6, 1)
9314    FIELD(L3_TM_PLL_DIG25, TM_PLL_ATB_CNTRL, 1, 5)
9315    FIELD(L3_TM_PLL_DIG25, TM_PLL_OBSERVE_PTAT_10U, 0, 1)
9316REG32(L3_TM_PLL_DIG26, 0xe068)
9317    FIELD(L3_TM_PLL_DIG26, TM_PLL_DIG26_31_8_RSVD, 24, 8)
9318    FIELD(L3_TM_PLL_DIG26, TM_PLL_RSVD, 7, 1)
9319    FIELD(L3_TM_PLL_DIG26, TM_PD_PLL_PTAT, 6, 1)
9320    FIELD(L3_TM_PLL_DIG26, TM_FORCE_PD_PLL_PTAT, 5, 1)
9321    FIELD(L3_TM_PLL_DIG26, TM_USB3_R2_HIGH_RES_SW_ON, 4, 1)
9322    FIELD(L3_TM_PLL_DIG26, TM_PLL_SEL_VCO_DIV2_LOOP_OUT, 3, 1)
9323    FIELD(L3_TM_PLL_DIG26, TM_PLL_SEL_VCO_DIRECT_LOOP_OUT, 2, 1)
9324    FIELD(L3_TM_PLL_DIG26, TM_PLL_SEL_VCO_HISPEED_DIV2_LOOP_OUT, 1, 1)
9325    FIELD(L3_TM_PLL_DIG26, TM_FORCE_LOOP_PATH, 0, 1)
9326REG32(L3_TM_PLL_CLK_DIST_NTRIM_LSB, 0xe06c)
9327    FIELD(L3_TM_PLL_CLK_DIST_NTRIM_LSB, TM_PLL_CLK_DIST_NTRIM_LSB_31_8_RSVD, 24, 8)
9328    FIELD(L3_TM_PLL_CLK_DIST_NTRIM_LSB, TM_CLKDIST_BIAS_NTRIM_LSB, 0, 8)
9329REG32(L3_TM_PLL_CLK_DIST_PTRIM_LSB, 0xe070)
9330    FIELD(L3_TM_PLL_CLK_DIST_PTRIM_LSB, TM_PLL_CLK_DIST_PTRIM_LSB_31_8_RSVD, 24, 8)
9331    FIELD(L3_TM_PLL_CLK_DIST_PTRIM_LSB, TM_CLKDIST_BIAS_PTRIM_LSB, 0, 8)
9332REG32(L3_TM_PLL_DIG_29, 0xe074)
9333    FIELD(L3_TM_PLL_DIG_29, TM_PLL_DIG_29_31_8_RSVD, 24, 8)
9334    FIELD(L3_TM_PLL_DIG_29, TM_CLKDIST_OBSRV_MRSTBUF_SUP, 7, 1)
9335    FIELD(L3_TM_PLL_DIG_29, TM_CLKDIST_OBSRV_LRSTBUF_SUP, 6, 1)
9336    FIELD(L3_TM_PLL_DIG_29, TM_CLKDIST_ENABLE_RST_RPTR, 5, 1)
9337    FIELD(L3_TM_PLL_DIG_29, TM_FORCE_CLKDIST_ENABLE_RST_RPTR, 4, 1)
9338    FIELD(L3_TM_PLL_DIG_29, TM_CLKDIST_ENABLE_CLK_RPTR, 3, 1)
9339    FIELD(L3_TM_PLL_DIG_29, TM_FORCE_CLKDIST_ENABLE_CLK_RPTR, 2, 1)
9340    FIELD(L3_TM_PLL_DIG_29, TM_CLKDIST_BIAS_PTRIM_MSB, 1, 1)
9341    FIELD(L3_TM_PLL_DIG_29, TM_CLKDIST_BIAS_NTRIM_MSB, 0, 1)
9342REG32(L3_TM_PLL_DIG_30, 0xe078)
9343    FIELD(L3_TM_PLL_DIG_30, TM_PLL_DIG_30_31_8_RSVD, 24, 8)
9344    FIELD(L3_TM_PLL_DIG_30, TM_CLKDIST_ENABLE_BIAS, 7, 1)
9345    FIELD(L3_TM_PLL_DIG_30, TM_FORCE_CLKDIST_ENABLE_BIAS, 6, 1)
9346    FIELD(L3_TM_PLL_DIG_30, TM_CLKDIST_ENABLE_CMN_BIAS, 5, 1)
9347    FIELD(L3_TM_PLL_DIG_30, TM_FORCE_CLKDIST_ENABLE_CMN_BIAS, 4, 1)
9348    FIELD(L3_TM_PLL_DIG_30, TM_CLKDIST_SUP_OBSRV, 3, 1)
9349    FIELD(L3_TM_PLL_DIG_30, TM_CLKDIST_OBSRV_RSTMUX_SUP, 2, 1)
9350    FIELD(L3_TM_PLL_DIG_30, TM_CLKDIST_OBSRV_RPTR_RSTBUF_SUP, 1, 1)
9351    FIELD(L3_TM_PLL_DIG_30, TM_CLKDIST_OBSRV_MUS_SUP, 0, 1)
9352REG32(L3_TM_PLL_DIG_31, 0xe07c)
9353    FIELD(L3_TM_PLL_DIG_31, TM_PLL_DIG_31_31_8_RSVD, 24, 8)
9354    FIELD(L3_TM_PLL_DIG_31, TM_CLKDIST_ENABLE_MASTER_CLK_DRIVE, 7, 1)
9355    FIELD(L3_TM_PLL_DIG_31, TM_FORCE_CLKDIST_ENABLE_MASTER_CLK_DRIVE, 6, 1)
9356    FIELD(L3_TM_PLL_DIG_31, TM_CLKDIST_ENABLE_LANE_RST_DRIVE, 5, 1)
9357    FIELD(L3_TM_PLL_DIG_31, TM_FORCE_CLKDIST_ENABLE_LANE_RST_DRIVE, 4, 1)
9358    FIELD(L3_TM_PLL_DIG_31, TM_CLKDIST_ENABLE_LANE_CLK_DRIVE, 3, 1)
9359    FIELD(L3_TM_PLL_DIG_31, TM_FORCE_CLKDIST_ENABLE_LANE_CLK_DRIVE, 2, 1)
9360    FIELD(L3_TM_PLL_DIG_31, TM_CLKDIST_BIAS_RATE_SEL, 1, 1)
9361    FIELD(L3_TM_PLL_DIG_31, TM_FORCE_CLKDIST_BIAS_RATE_SEL, 0, 1)
9362REG32(L3_TM_PLL_DIG_32, 0xe080)
9363    FIELD(L3_TM_PLL_DIG_32, TM_PLL_DIG_32_31_8_RSVD, 24, 8)
9364    FIELD(L3_TM_PLL_DIG_32, TM_CLKDIST_MUX_XVCR_CLK_EN, 7, 1)
9365    FIELD(L3_TM_PLL_DIG_32, TM_FORCE_CLKDIST_MUX_XVCR_CLK_EN, 6, 1)
9366    FIELD(L3_TM_PLL_DIG_32, TM_FORCE_LOAD_FBDIV, 5, 1)
9367    FIELD(L3_TM_PLL_DIG_32, TM_LOAD_FBDIV, 4, 1)
9368    FIELD(L3_TM_PLL_DIG_32, TM_FORCE_RST_FDBK_DIV, 3, 1)
9369    FIELD(L3_TM_PLL_DIG_32, TM_RST_FDBK_DIV, 2, 1)
9370    FIELD(L3_TM_PLL_DIG_32, TM_CLKDIST_ENABLE_MASTER_RST_DRIVE, 1, 1)
9371    FIELD(L3_TM_PLL_DIG_32, TM_FORCE_CLKDIST_ENABLE_MASTER_RST_DRIVE, 0, 1)
9372REG32(L3_TM_PLL_DIG_33, 0xe084)
9373    FIELD(L3_TM_PLL_DIG_33, TM_PLL_DIG_33_31_8_RSVD, 24, 8)
9374    FIELD(L3_TM_PLL_DIG_33, TM_FORCE_TX_CLK_RST_REL, 7, 1)
9375    FIELD(L3_TM_PLL_DIG_33, TM_TX_CLK_RST_REL, 6, 1)
9376    FIELD(L3_TM_PLL_DIG_33, TM_CLKDIST_MUX_XCVR_MASTER_RST_EN, 5, 1)
9377    FIELD(L3_TM_PLL_DIG_33, TM_FORCE_CLKDIST_MUX_XCVR_MASTER_RST_EN, 4, 1)
9378    FIELD(L3_TM_PLL_DIG_33, TM_CLKDIST_MUX_MASTER_CLK_SEL, 3, 1)
9379    FIELD(L3_TM_PLL_DIG_33, TM_FORCE_CLKDIST_MUX_MASTER_CLK_SEL, 2, 1)
9380    FIELD(L3_TM_PLL_DIG_33, TM_CLKDIST_MUX_LOCAL_CLK_SEL, 1, 1)
9381    FIELD(L3_TM_PLL_DIG_33, TM_FORCE_CLKDIST_MUX_LOCAL_CLK_SEL, 0, 1)
9382REG32(L3_TM_PLL_DIG_34, 0xe088)
9383    FIELD(L3_TM_PLL_DIG_34, TM_PLL_DIG_34_31_8_RSVD, 24, 8)
9384    FIELD(L3_TM_PLL_DIG_34, TM_PLL_RSVD, 7, 1)
9385    FIELD(L3_TM_PLL_DIG_34, TM_FBDIV_3_MSB, 2, 5)
9386    FIELD(L3_TM_PLL_DIG_34, TM_SEL_VCO_OUT, 1, 1)
9387    FIELD(L3_TM_PLL_DIG_34, TM_FORCE_SEL_VCO_OUT, 0, 1)
9388REG32(L3_TM_PLL_DIG_35, 0xe08c)
9389    FIELD(L3_TM_PLL_DIG_35, TM_PLL_DIG_35_31_8_RSVD, 24, 8)
9390    FIELD(L3_TM_PLL_DIG_35, TM_CLKDIST_BIAS_SPARE, 6, 2)
9391    FIELD(L3_TM_PLL_DIG_35, TM_CLKDIST_DRVR_SPARE, 4, 2)
9392    FIELD(L3_TM_PLL_DIG_35, TM_CLKDIST_MUX_SPARE, 2, 2)
9393    FIELD(L3_TM_PLL_DIG_35, TM_CLKDIST_RPTR_SPARE, 0, 2)
9394REG32(L3_TM_PLL_DIG_36, 0xe090)
9395    FIELD(L3_TM_PLL_DIG_36, TM_PLL_DIG_36_31_8_RSVD, 24, 8)
9396    FIELD(L3_TM_PLL_DIG_36, CLKDIST_BIAS_SPARE, 6, 2)
9397    FIELD(L3_TM_PLL_DIG_36, CLKDIST_DRVR_SPARE, 4, 2)
9398    FIELD(L3_TM_PLL_DIG_36, CLKDIST_MUX_SPARE, 2, 2)
9399    FIELD(L3_TM_PLL_DIG_36, CLKDIST_RPTR_SPARE, 0, 2)
9400REG32(L3_TM_PLL_DIG_37, 0xe094)
9401    FIELD(L3_TM_PLL_DIG_37, TM_PLL_DIG_37_31_8_RSVD, 24, 8)
9402    FIELD(L3_TM_PLL_DIG_37, TM_COARSE_CODE_SAT_VALUE_LSB, 5, 3)
9403    FIELD(L3_TM_PLL_DIG_37, TM_ENABLE_COARSE_SATURATION, 4, 1)
9404    FIELD(L3_TM_PLL_DIG_37, W_SPARE_OUTPUTS, 2, 2)
9405    FIELD(L3_TM_PLL_DIG_37, TM_FORCE_EN_IP_DIV_BYPASS, 1, 1)
9406    FIELD(L3_TM_PLL_DIG_37, TM_EN_IP_DIV_BYPASS, 0, 1)
9407REG32(L3_TM_PLL_COARSE_CODE_SAT_MSB, 0xe098)
9408    FIELD(L3_TM_PLL_COARSE_CODE_SAT_MSB, TM_PLL_COARSE_CODE_SAT_MSB_31_8_RSVD, 24, 8)
9409    FIELD(L3_TM_PLL_COARSE_CODE_SAT_MSB, TM_COARSE_CODE_SAT_VALUE_MSB, 0, 8)
9410REG32(L3_MPHY_CFG_HIB8, 0xe300)
9411    FIELD(L3_MPHY_CFG_HIB8, MPHY_CFG_HIB8_31_8_RSVD, 24, 8)
9412    FIELD(L3_MPHY_CFG_HIB8, MPHY_HIBERN8_RSVD, 1, 7)
9413    FIELD(L3_MPHY_CFG_HIB8, MPHY_HIBERN8, 0, 1)
9414REG32(L3_MPHY_CFG_MODE, 0xe304)
9415    FIELD(L3_MPHY_CFG_MODE, MPHY_CFG_MODE_31_8_RSVD, 24, 8)
9416    FIELD(L3_MPHY_CFG_MODE, MPHY_HS_LS_MODE_RSVD, 2, 6)
9417    FIELD(L3_MPHY_CFG_MODE, MPHY_HS_LS_MODE, 0, 2)
9418REG32(L3_MPHY_CFG_HS_GEAR, 0xe308)
9419    FIELD(L3_MPHY_CFG_HS_GEAR, MPHY_CFG_HS_GEAR_31_8_RSVD, 24, 8)
9420    FIELD(L3_MPHY_CFG_HS_GEAR, MPHY_HS_GEAR_RSVD, 2, 6)
9421    FIELD(L3_MPHY_CFG_HS_GEAR, MPHY_HS_GEAR, 0, 2)
9422REG32(L3_MPHY_CFG_HS_RATE, 0xe30c)
9423    FIELD(L3_MPHY_CFG_HS_RATE, MPHY_CFG_HS_RATE_31_8_RSVD, 24, 8)
9424    FIELD(L3_MPHY_CFG_HS_RATE, MPHY_RATE_RSVD, 1, 7)
9425    FIELD(L3_MPHY_CFG_HS_RATE, MPHY_RATE, 0, 1)
9426REG32(L3_MPHY_CFG_PWM, 0xe310)
9427    FIELD(L3_MPHY_CFG_PWM, MPHY_CFG_PWM_31_8_RSVD, 24, 8)
9428    FIELD(L3_MPHY_CFG_PWM, MPHY_PWM_GEAR_RSVD, 3, 5)
9429    FIELD(L3_MPHY_CFG_PWM, MPHY_PWM_GEAR, 0, 3)
9430REG32(L3_PLL_OPDIV_LS, 0xe314)
9431    FIELD(L3_PLL_OPDIV_LS, PLL_OPDIV_LS_31_8_RSVD, 24, 8)
9432    FIELD(L3_PLL_OPDIV_LS, TM_SEL_OPDIV_FOR_REFCLK, 7, 1)
9433    FIELD(L3_PLL_OPDIV_LS, ANA_OPDIV_LS, 0, 7)
9434REG32(L3_MPHY_CFG_UPDT, 0xe318)
9435    FIELD(L3_MPHY_CFG_UPDT, MPHY_CFG_UPDT_31_8_RSVD, 24, 8)
9436    FIELD(L3_MPHY_CFG_UPDT, MPHY_CFGUPDT_RSVD, 1, 7)
9437    FIELD(L3_MPHY_CFG_UPDT, MPHY_CFGUPDT, 0, 1)
9438REG32(L3_PLL_TM_DIV_CNTRLS, 0xe31c)
9439    FIELD(L3_PLL_TM_DIV_CNTRLS, PLL_TM_DIV_CNTRLS_31_8_RSVD, 24, 8)
9440    FIELD(L3_PLL_TM_DIV_CNTRLS, TM_FORCE_PD_OPDIV_LS, 7, 1)
9441    FIELD(L3_PLL_TM_DIV_CNTRLS, TM_PD_OPDIV_LS, 6, 1)
9442    FIELD(L3_PLL_TM_DIV_CNTRLS, PLL_TM_DIV_CNTRLS_RSVD, 5, 1)
9443    FIELD(L3_PLL_TM_DIV_CNTRLS, TM_BYPASS_OPDIV_LS_MOD, 4, 1)
9444    FIELD(L3_PLL_TM_DIV_CNTRLS, TM_FORCE_PLL_PD_HS, 3, 1)
9445    FIELD(L3_PLL_TM_DIV_CNTRLS, TM_PLL_PD_HS, 2, 1)
9446    FIELD(L3_PLL_TM_DIV_CNTRLS, SEL_IP_MUX_CONTROL, 1, 1)
9447    FIELD(L3_PLL_TM_DIV_CNTRLS, TM_SWAP_OP_MUX_CONTROL, 0, 1)
9448REG32(L3_PLL_FBDIV_G1A_LSB, 0xe320)
9449    FIELD(L3_PLL_FBDIV_G1A_LSB, PLL_FBDIV_G1A_LSB_31_8_RSVD, 24, 8)
9450    FIELD(L3_PLL_FBDIV_G1A_LSB, FBDIV_G1A_LSB, 0, 8)
9451REG32(L3_PLL_FBDIV_G1B_LSB, 0xe324)
9452    FIELD(L3_PLL_FBDIV_G1B_LSB, PLL_FBDIV_G1B_LSB_31_8_RSVD, 24, 8)
9453    FIELD(L3_PLL_FBDIV_G1B_LSB, FBDIV_G1B_LSB, 0, 8)
9454REG32(L3_PLL_FBDIV_G2A_LSB, 0xe328)
9455    FIELD(L3_PLL_FBDIV_G2A_LSB, PLL_FBDIV_G2A_LSB_31_8_RSVD, 24, 8)
9456    FIELD(L3_PLL_FBDIV_G2A_LSB, FBDIV_G2A_LSB, 0, 8)
9457REG32(L3_PLL_FBDIV_G2B_LSB, 0xe32c)
9458    FIELD(L3_PLL_FBDIV_G2B_LSB, PLL_FBDIV_G2B_LSB_31_8_RSVD, 24, 8)
9459    FIELD(L3_PLL_FBDIV_G2B_LSB, FBDIV_G2B_LSB, 0, 8)
9460REG32(L3_PLL_FBDIV_G3A_LSB, 0xe330)
9461    FIELD(L3_PLL_FBDIV_G3A_LSB, PLL_FBDIV_G3A_LSB_31_8_RSVD, 24, 8)
9462    FIELD(L3_PLL_FBDIV_G3A_LSB, FBDIV_G3A_LSB, 0, 8)
9463REG32(L3_PLL_FBDIV_G3B_LSB, 0xe334)
9464    FIELD(L3_PLL_FBDIV_G3B_LSB, PLL_FBDIV_G3B_LSB_31_8_RSVD, 24, 8)
9465    FIELD(L3_PLL_FBDIV_G3B_LSB, FBDIV_G3B_LSB, 0, 8)
9466REG32(L3_PLL_FBDIV_G1A_MSB, 0xe338)
9467    FIELD(L3_PLL_FBDIV_G1A_MSB, PLL_FBDIV_G1A_MSB_31_8_RSVD, 24, 8)
9468    FIELD(L3_PLL_FBDIV_G1A_MSB, FBDIV_G1A_MSB, 0, 8)
9469REG32(L3_PLL_FBDIV_G1B_MSB, 0xe33c)
9470    FIELD(L3_PLL_FBDIV_G1B_MSB, PLL_FBDIV_G1B_MSB_31_8_RSVD, 24, 8)
9471    FIELD(L3_PLL_FBDIV_G1B_MSB, FBDIV_G1B_MSB, 0, 8)
9472REG32(L3_PLL_FBDIV_G2A_MSB, 0xe340)
9473    FIELD(L3_PLL_FBDIV_G2A_MSB, PLL_FBDIV_G2A_MSB_31_8_RSVD, 24, 8)
9474    FIELD(L3_PLL_FBDIV_G2A_MSB, FBDIV_G2A_MSB, 0, 8)
9475REG32(L3_PLL_FBDIV_G2B_MSB, 0xe344)
9476    FIELD(L3_PLL_FBDIV_G2B_MSB, PLL_FBDIV_G2B_MSB_31_8_RSVD, 24, 8)
9477    FIELD(L3_PLL_FBDIV_G2B_MSB, FBDIV_G2B_MSB, 0, 8)
9478REG32(L3_PLL_FBDIV_G3A_MSB, 0xe348)
9479    FIELD(L3_PLL_FBDIV_G3A_MSB, PLL_FBDIV_G3A_MSB_31_8_RSVD, 24, 8)
9480    FIELD(L3_PLL_FBDIV_G3A_MSB, FBDIV_G3A_MSB, 0, 8)
9481REG32(L3_PLL_FBDIV_G3B_MSB, 0xe34c)
9482    FIELD(L3_PLL_FBDIV_G3B_MSB, PLL_FBDIV_G3B_MSB_31_8_RSVD, 24, 8)
9483    FIELD(L3_PLL_FBDIV_G3B_MSB, FBDIV_G3B_MSB, 0, 8)
9484REG32(L3_PLL_IPDIV, 0xe350)
9485    FIELD(L3_PLL_IPDIV, PLL_IPDIV_31_8_RSVD, 24, 8)
9486    FIELD(L3_PLL_IPDIV, PLL_IPDIV, 0, 8)
9487REG32(L3_PLL_FBDIV_FRAC_0_LSB, 0xe354)
9488    FIELD(L3_PLL_FBDIV_FRAC_0_LSB, PLL_FBDIV_FRAC_0_LSB_31_8_RSVD, 24, 8)
9489    FIELD(L3_PLL_FBDIV_FRAC_0_LSB, FBDIV_FRAC_0_LSB, 0, 8)
9490REG32(L3_PLL_FBDIV_FRAC_1, 0xe358)
9491    FIELD(L3_PLL_FBDIV_FRAC_1, PLL_FBDIV_FRAC_1_31_8_RSVD, 24, 8)
9492    FIELD(L3_PLL_FBDIV_FRAC_1, FBDIV_FRAC_1, 0, 8)
9493REG32(L3_PLL_FBDIV_FRAC_2, 0xe35c)
9494    FIELD(L3_PLL_FBDIV_FRAC_2, PLL_FBDIV_FRAC_2_31_8_RSVD, 24, 8)
9495    FIELD(L3_PLL_FBDIV_FRAC_2, FBDIV_FRAC_2, 0, 8)
9496REG32(L3_PLL_FBDIV_FRAC_3_MSB, 0xe360)
9497    FIELD(L3_PLL_FBDIV_FRAC_3_MSB, PLL_FBDIV_FRAC_3_MSB_31_8_RSVD, 24, 8)
9498    FIELD(L3_PLL_FBDIV_FRAC_3_MSB, PLL_FBDIV_FRAC_3_MSV_RSVD, 7, 1)
9499    FIELD(L3_PLL_FBDIV_FRAC_3_MSB, TM_FORCE_EN_FRAC, 6, 1)
9500    FIELD(L3_PLL_FBDIV_FRAC_3_MSB, TM_EN_FRAC, 5, 1)
9501    FIELD(L3_PLL_FBDIV_FRAC_3_MSB, FBDIV_FRAC_3_MSB_RSVD, 3, 2)
9502    FIELD(L3_PLL_FBDIV_FRAC_3_MSB, FBDIV_FRAC_3_MSB, 0, 3)
9503REG32(L3_PLL_PWR_SEQ_WAIT_TIME, 0xe364)
9504    FIELD(L3_PLL_PWR_SEQ_WAIT_TIME, PLL_PWR_SEQ_WAIT_TIME_31_8_RSVD, 24, 8)
9505    FIELD(L3_PLL_PWR_SEQ_WAIT_TIME, TM_PLL_SETTLING, 6, 2)
9506    FIELD(L3_PLL_PWR_SEQ_WAIT_TIME, TM_PLL_BIAS_SETTLING, 4, 2)
9507    FIELD(L3_PLL_PWR_SEQ_WAIT_TIME, TM_LDO_SETTLING, 2, 2)
9508    FIELD(L3_PLL_PWR_SEQ_WAIT_TIME, TM_LDO_RELIABILITY, 0, 2)
9509REG32(L3_PLL_SS_STEPS_0_LSB, 0xe368)
9510    FIELD(L3_PLL_SS_STEPS_0_LSB, PLL_SS_STEPS_0_LSB_31_8_RSVD, 24, 8)
9511    FIELD(L3_PLL_SS_STEPS_0_LSB, SS_NUM_OF_STEPS_0_LSB, 0, 8)
9512REG32(L3_PLL_SS_STEPS_1_MSB, 0xe36c)
9513    FIELD(L3_PLL_SS_STEPS_1_MSB, PLL_SS_STEPS_1_MSB_31_8_RSVD, 24, 8)
9514    FIELD(L3_PLL_SS_STEPS_1_MSB, SS_NUM_OF_STEPS_1_MSB_RSVD, 3, 5)
9515    FIELD(L3_PLL_SS_STEPS_1_MSB, SS_NUM_OF_STEPS_1_MSB, 0, 3)
9516REG32(L3_PLL_SS_STEP_SIZE_0_LSB, 0xe370)
9517    FIELD(L3_PLL_SS_STEP_SIZE_0_LSB, PLL_SS_STEP_SIZE_0_LSB_31_8_RSVD, 24, 8)
9518    FIELD(L3_PLL_SS_STEP_SIZE_0_LSB, SS_STEP_SIZE_0_LSB, 0, 8)
9519REG32(L3_PLL_SS_STEP_SIZE_1, 0xe374)
9520    FIELD(L3_PLL_SS_STEP_SIZE_1, PLL_SS_STEP_SIZE_1_31_8_RSVD, 24, 8)
9521    FIELD(L3_PLL_SS_STEP_SIZE_1, SS_STEP_SIZE_1, 0, 8)
9522REG32(L3_PLL_SS_STEP_SIZE_2, 0xe378)
9523    FIELD(L3_PLL_SS_STEP_SIZE_2, PLL_SS_STEP_SIZE_2_31_8_RSVD, 24, 8)
9524    FIELD(L3_PLL_SS_STEP_SIZE_2, SS_STEP_SIZE_2, 0, 8)
9525REG32(L3_PLL_SS_STEP_SIZE_3_MSB, 0xe37c)
9526    FIELD(L3_PLL_SS_STEP_SIZE_3_MSB, PLL_SS_STEP_SIZE_3_MSB_31_8_RSVD, 24, 8)
9527    FIELD(L3_PLL_SS_STEP_SIZE_3_MSB, TM_FORCE_EN_SS, 7, 1)
9528    FIELD(L3_PLL_SS_STEP_SIZE_3_MSB, TM_EN_SS, 6, 1)
9529    FIELD(L3_PLL_SS_STEP_SIZE_3_MSB, FORCE_SS_NUM_OF_STEPS, 5, 1)
9530    FIELD(L3_PLL_SS_STEP_SIZE_3_MSB, FORCE_SS_STEP_SIZE, 4, 1)
9531    FIELD(L3_PLL_SS_STEP_SIZE_3_MSB, SS_SPREAD_TYPE, 2, 2)
9532    FIELD(L3_PLL_SS_STEP_SIZE_3_MSB, SS_STEP_SIZE_3_MSB, 0, 2)
9533REG32(L3_TM_MASK_CFG_UPDT, 0xe380)
9534    FIELD(L3_TM_MASK_CFG_UPDT, TM_MASK_CFG_UPDT_31_8_RSVD, 24, 8)
9535    FIELD(L3_TM_MASK_CFG_UPDT, TM_MASK_CFG_UPDT_RSVD, 7, 1)
9536    FIELD(L3_TM_MASK_CFG_UPDT, HIBERN8_MASK_CFG_UPDT, 6, 1)
9537    FIELD(L3_TM_MASK_CFG_UPDT, HS_MODE_MASK_CFG_UPDT, 5, 1)
9538    FIELD(L3_TM_MASK_CFG_UPDT, LS_MODE_MASK_CFG_UPDT, 4, 1)
9539    FIELD(L3_TM_MASK_CFG_UPDT, OPDIV_LS_MASK_CFG_UPDT, 3, 1)
9540    FIELD(L3_TM_MASK_CFG_UPDT, PWM_GEAR_MASK_CFG_UPDT, 2, 1)
9541    FIELD(L3_TM_MASK_CFG_UPDT, HS_GEAR_MASK_CFG_UPDT, 1, 1)
9542    FIELD(L3_TM_MASK_CFG_UPDT, HS_RATE_MASK_CFG_UPDT, 0, 1)
9543REG32(L3_PLL_TM_FORCE_DIV, 0xe384)
9544    FIELD(L3_PLL_TM_FORCE_DIV, PLL_TM_FORCE_DIV_31_8_RSVD, 24, 8)
9545    FIELD(L3_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_FRAC, 7, 1)
9546    FIELD(L3_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G3B, 6, 1)
9547    FIELD(L3_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G3A, 5, 1)
9548    FIELD(L3_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G2B, 4, 1)
9549    FIELD(L3_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G2A, 3, 1)
9550    FIELD(L3_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G1B, 2, 1)
9551    FIELD(L3_PLL_TM_FORCE_DIV, TM_FORCE_FBDIV_G1A, 1, 1)
9552    FIELD(L3_PLL_TM_FORCE_DIV, TM_FORCE_IPDIV, 0, 1)
9553REG32(L3_PLL_TM_COARSE_CODE_1_LSB, 0xe388)
9554    FIELD(L3_PLL_TM_COARSE_CODE_1_LSB, PLL_TM_COARSE_CODE_1_LSB_31_8_RSVD, 24, 8)
9555    FIELD(L3_PLL_TM_COARSE_CODE_1_LSB, TM_COARSE_CODE_1_LSB, 0, 8)
9556REG32(L3_PLL_TM_COARSE_CODE_2_LSB, 0xe38c)
9557    FIELD(L3_PLL_TM_COARSE_CODE_2_LSB, PLL_TM_COARSE_CODE_2_LSB_31_8_RSVD, 24, 8)
9558    FIELD(L3_PLL_TM_COARSE_CODE_2_LSB, TM_COARSE_CODE_2_LSB, 0, 8)
9559REG32(L3_PLL_TM_COARSE_CODE_3_LSB, 0xe390)
9560    FIELD(L3_PLL_TM_COARSE_CODE_3_LSB, PLL_TM_COARSE_CODE_3_LSB_31_8_RSVD, 24, 8)
9561    FIELD(L3_PLL_TM_COARSE_CODE_3_LSB, TM_COARSE_CODE_3_LSB, 0, 8)
9562REG32(L3_PLL_TM_COARSE_CODE_4_LSB, 0xe394)
9563    FIELD(L3_PLL_TM_COARSE_CODE_4_LSB, PLL_TM_COARSE_CODE_4_LSB_31_8_RSVD, 24, 8)
9564    FIELD(L3_PLL_TM_COARSE_CODE_4_LSB, TM_COARSE_CODE_4_LSB, 0, 8)
9565REG32(L3_PLL_TM_COARSE_CODE_5_LSB, 0xe398)
9566    FIELD(L3_PLL_TM_COARSE_CODE_5_LSB, PLL_TM_COARSE_CODE_5_LSB_31_8_RSVD, 24, 8)
9567    FIELD(L3_PLL_TM_COARSE_CODE_5_LSB, TM_COARSE_CODE_5_LSB, 0, 8)
9568REG32(L3_PLL_TM_COARSE_CODE_6_LSB, 0xe39c)
9569    FIELD(L3_PLL_TM_COARSE_CODE_6_LSB, PLL_TM_COARSE_CODE_6_LSB_31_8_RSVD, 24, 8)
9570    FIELD(L3_PLL_TM_COARSE_CODE_6_LSB, TM_COARSE_CODE_6_LSB, 0, 8)
9571REG32(L3_PLL_TM_COARSE_CODE_1_2_MSB, 0xe3a0)
9572    FIELD(L3_PLL_TM_COARSE_CODE_1_2_MSB, PLL_TM_COARSE_CODE_1_2_MSB_31_8_RSVD, 24, 8)
9573    FIELD(L3_PLL_TM_COARSE_CODE_1_2_MSB, TM_COARSE_CODE_G1_AB_MSB_RSVD, 6, 2)
9574    FIELD(L3_PLL_TM_COARSE_CODE_1_2_MSB, TM_COARSE_CODE_2_MSB, 3, 3)
9575    FIELD(L3_PLL_TM_COARSE_CODE_1_2_MSB, TM_COARSE_CODE_1_MSB, 0, 3)
9576REG32(L3_PLL_TM_COARSE_CODE_3_4_MSB, 0xe3a4)
9577    FIELD(L3_PLL_TM_COARSE_CODE_3_4_MSB, PLL_TM_COARSE_CODE_3_4_MSB_31_8_RSVD, 24, 8)
9578    FIELD(L3_PLL_TM_COARSE_CODE_3_4_MSB, TM_COARSE_CODE_G2_AB_MSB_RSVD, 6, 2)
9579    FIELD(L3_PLL_TM_COARSE_CODE_3_4_MSB, TM_COARSE_CODE_4_MSB, 3, 3)
9580    FIELD(L3_PLL_TM_COARSE_CODE_3_4_MSB, TM_COARSE_CODE_3_MSB, 0, 3)
9581REG32(L3_PLL_TM_COARSE_CODE_5_6_MSB, 0xe3a8)
9582    FIELD(L3_PLL_TM_COARSE_CODE_5_6_MSB, PLL_TM_COARSE_CODE_5_6_MSB_31_8_RSVD, 24, 8)
9583    FIELD(L3_PLL_TM_COARSE_CODE_5_6_MSB, TM_COARSE_CODE_G3_AB_MSB_RSVD, 6, 2)
9584    FIELD(L3_PLL_TM_COARSE_CODE_5_6_MSB, TM_COARSE_CODE_6_MSB, 3, 3)
9585    FIELD(L3_PLL_TM_COARSE_CODE_5_6_MSB, TM_COARSE_CODE_5_MSB, 0, 3)
9586REG32(L3_PLL_TM_SHARED_0, 0xe3ac)
9587    FIELD(L3_PLL_TM_SHARED_0, PLL_TM_SHARED_0_31_8_RSVD, 24, 8)
9588    FIELD(L3_PLL_TM_SHARED_0, TM_FORCE_EXTSIGNAL_FOR_HIBERN8, 7, 1)
9589    FIELD(L3_PLL_TM_SHARED_0, TM_FORCE_REGBIT_FOR_HIBERN8, 6, 1)
9590    FIELD(L3_PLL_TM_SHARED_0, TM_FORCE_PLL_STANDBY, 5, 1)
9591    FIELD(L3_PLL_TM_SHARED_0, TM_PLL_STANDBY, 4, 1)
9592    FIELD(L3_PLL_TM_SHARED_0, TM_SLOWN_FAST_BRING_UP_ALWAYS, 3, 1)
9593    FIELD(L3_PLL_TM_SHARED_0, EN_TM_FOR_BRING_UP_SCHEME, 2, 1)
9594    FIELD(L3_PLL_TM_SHARED_0, SELECT_HS_FB_DIVIDER, 1, 1)
9595    FIELD(L3_PLL_TM_SHARED_0, TM_BYPASS_COARSE_SEARCH, 0, 1)
9596REG32(L3_PLL_TM_FRAC_OFFSET_0, 0xe3b0)
9597    FIELD(L3_PLL_TM_FRAC_OFFSET_0, PLL_TM_FRAC_OFFSET_0_31_8_RSVD, 24, 8)
9598    FIELD(L3_PLL_TM_FRAC_OFFSET_0, TM_FRAC_OFFSET_LSB_0, 0, 8)
9599REG32(L3_PLL_TM_FRAC_OFFSET_1, 0xe3b4)
9600    FIELD(L3_PLL_TM_FRAC_OFFSET_1, PLL_TM_FRAC_OFFSET_1_31_8_RSVD, 24, 8)
9601    FIELD(L3_PLL_TM_FRAC_OFFSET_1, TM_FRAC_OFFSET_1, 0, 8)
9602REG32(L3_PLL_TM_FRAC_OFFSET_2, 0xe3b8)
9603    FIELD(L3_PLL_TM_FRAC_OFFSET_2, PLL_TM_FRAC_OFFSET_2_31_8_RSVD, 24, 8)
9604    FIELD(L3_PLL_TM_FRAC_OFFSET_2, TM_PLL_RSVD, 2, 6)
9605    FIELD(L3_PLL_TM_FRAC_OFFSET_2, TM_FORCE_FBDIV_FRAC_OFFSET, 1, 1)
9606    FIELD(L3_PLL_TM_FRAC_OFFSET_2, TM_FRAC_OFFSET_MSB_2, 0, 1)
9607REG32(L3_PLL_STATUS_READ_0, 0xe3e0)
9608    FIELD(L3_PLL_STATUS_READ_0, PLL_STATUS_READ_0_31_8_RSVD, 24, 8)
9609    FIELD(L3_PLL_STATUS_READ_0, PLL_COARSE_CODE_LSB_STATUS_READ, 0, 8)
9610REG32(L3_PLL_STATUS_READ_1, 0xe3e4)
9611    FIELD(L3_PLL_STATUS_READ_1, PLL_STATUS_READ_1_31_8_RSVD, 24, 8)
9612    FIELD(L3_PLL_STATUS_READ_1, PLL_STATUS_READ_1_RSVD, 6, 2)
9613    FIELD(L3_PLL_STATUS_READ_1, PLL_START_LOOP_STATUS_READ, 5, 1)
9614    FIELD(L3_PLL_STATUS_READ_1, PLL_LOCK_STATUS_READ, 4, 1)
9615    FIELD(L3_PLL_STATUS_READ_1, PLL_COARSE_DONE_STATUS_READ, 3, 1)
9616    FIELD(L3_PLL_STATUS_READ_1, PLL_COARSE_CODE_MSB_STATUS_READ, 0, 3)
9617REG32(L3_TM_CALIB_DIG0, 0xec00)
9618    FIELD(L3_TM_CALIB_DIG0, TM_CALIB_DIG0_31_8_RSVD, 24, 8)
9619    FIELD(L3_TM_CALIB_DIG0, TM_CALIB_DIG0_7_6_RSVD, 6, 2)
9620    FIELD(L3_TM_CALIB_DIG0, ICONST_CNTRL, 5, 1)
9621    FIELD(L3_TM_CALIB_DIG0, ICONST_BYP, 4, 1)
9622    FIELD(L3_TM_CALIB_DIG0, CALIB_RSTN_CNTRL, 2, 2)
9623    FIELD(L3_TM_CALIB_DIG0, TM_CALIB_DIG0_0_1_RSVD, 0, 2)
9624REG32(L3_TM_CALIB_DIG1, 0xec04)
9625    FIELD(L3_TM_CALIB_DIG1, TM_CALIB_DIG1_31_8_RSVD, 24, 8)
9626    FIELD(L3_TM_CALIB_DIG1, TM_CALIB_DIG1_4_7_RSVD, 4, 4)
9627    FIELD(L3_TM_CALIB_DIG1, FORCE_CALIB_EN_LL, 3, 1)
9628    FIELD(L3_TM_CALIB_DIG1, TM_CALIB_DIG1_1_2_RSVD, 1, 2)
9629    FIELD(L3_TM_CALIB_DIG1, CALIB_EN_LL_CNTRL, 0, 1)
9630REG32(L3_TM_CALIB_DIG2, 0xec08)
9631    FIELD(L3_TM_CALIB_DIG2, TM_CALIB_DIG2_31_8_RSVD, 24, 8)
9632    FIELD(L3_TM_CALIB_DIG2, CALIB_ICONST0, 0, 8)
9633REG32(L3_TM_CALIB_DIG3, 0xec0c)
9634    FIELD(L3_TM_CALIB_DIG3, TM_CALIB_DIG3_31_8_RSVD, 24, 8)
9635    FIELD(L3_TM_CALIB_DIG3, CALIB_ICONST1, 0, 8)
9636REG32(L3_TM_CALIB_DIG4, 0xec10)
9637    FIELD(L3_TM_CALIB_DIG4, TM_CALIB_DIG4_31_8_RSVD, 24, 8)
9638    FIELD(L3_TM_CALIB_DIG4, CALIB_ICONST2, 0, 8)
9639REG32(L3_TM_CALIB_DIG5, 0xec14)
9640    FIELD(L3_TM_CALIB_DIG5, TM_CALIB_DIG5_31_8_RSVD, 24, 8)
9641    FIELD(L3_TM_CALIB_DIG5, CALIB_ICONST3, 0, 8)
9642REG32(L3_TM_CALIB_DIG6, 0xec18)
9643    FIELD(L3_TM_CALIB_DIG6, TM_CALIB_DIG6_31_8_RSVD, 24, 8)
9644    FIELD(L3_TM_CALIB_DIG6, CALIB_ICONST4, 0, 8)
9645REG32(L3_TM_CALIB_DIG7, 0xec1c)
9646    FIELD(L3_TM_CALIB_DIG7, TM_CALIB_DIG7_31_8_RSVD, 24, 8)
9647    FIELD(L3_TM_CALIB_DIG7, CALIB_ICONST5, 0, 8)
9648REG32(L3_TM_CALIB_DIG8, 0xec20)
9649    FIELD(L3_TM_CALIB_DIG8, TM_CALIB_DIG8_31_8_RSVD, 24, 8)
9650    FIELD(L3_TM_CALIB_DIG8, CALIB_ICONST6, 0, 8)
9651REG32(L3_TM_CALIB_DIG9, 0xec24)
9652    FIELD(L3_TM_CALIB_DIG9, TM_CALIB_DIG9_31_8_RSVD, 24, 8)
9653    FIELD(L3_TM_CALIB_DIG9, CALIB_ICONST7, 0, 8)
9654REG32(L3_TM_CALIB_DIG10, 0xec28)
9655    FIELD(L3_TM_CALIB_DIG10, TM_CALIB_DIG10_31_8_RSVD, 24, 8)
9656    FIELD(L3_TM_CALIB_DIG10, CALIB_ICONST8, 0, 8)
9657REG32(L3_TM_CALIB_DIG11, 0xec2c)
9658    FIELD(L3_TM_CALIB_DIG11, TM_CALIB_DIG11_31_8_RSVD, 24, 8)
9659    FIELD(L3_TM_CALIB_DIG11, CALIB_ICONST9, 0, 8)
9660REG32(L3_TM_CALIB_DIG12, 0xec30)
9661    FIELD(L3_TM_CALIB_DIG12, TM_CALIB_DIG12_31_8_RSVD, 24, 8)
9662    FIELD(L3_TM_CALIB_DIG12, CALIB_ICONST10_7_RSVD, 7, 1)
9663    FIELD(L3_TM_CALIB_DIG12, CALIB_ICONST_10, 0, 7)
9664REG32(L3_TM_CALIB_DIG13, 0xec34)
9665    FIELD(L3_TM_CALIB_DIG13, TM_CALIB_DIG13_31_8_RSVD, 24, 8)
9666    FIELD(L3_TM_CALIB_DIG13, TM_CALIB_DIG13_6_7_RSVD, 6, 2)
9667    FIELD(L3_TM_CALIB_DIG13, TM_OR_FP_ICAL_CODE, 5, 1)
9668    FIELD(L3_TM_CALIB_DIG13, FP_ICAL_CODE_OR, 0, 5)
9669REG32(L3_TM_CALIB_DIG14, 0xec38)
9670    FIELD(L3_TM_CALIB_DIG14, TM_CALIB_DIG14_31_8_RSVD, 24, 8)
9671    FIELD(L3_TM_CALIB_DIG14, ICAL_CODE_OR_0, 7, 1)
9672    FIELD(L3_TM_CALIB_DIG14, TM_OR_ICAL_CODE, 6, 1)
9673    FIELD(L3_TM_CALIB_DIG14, FORCE_EN_ICAL, 5, 1)
9674    FIELD(L3_TM_CALIB_DIG14, TM_OR_EN_ICAL, 4, 1)
9675    FIELD(L3_TM_CALIB_DIG14, FORCE_EN_CALIB, 3, 1)
9676    FIELD(L3_TM_CALIB_DIG14, TM_OR_EN_CALIB, 2, 1)
9677    FIELD(L3_TM_CALIB_DIG14, FORCE_CALIB_DONE, 1, 1)
9678    FIELD(L3_TM_CALIB_DIG14, TM_OR_CALIB_DONE, 0, 1)
9679REG32(L3_TM_CALIB_DIG15, 0xec3c)
9680    FIELD(L3_TM_CALIB_DIG15, TM_CALIB_DIG15_31_8_RSVD, 24, 8)
9681    FIELD(L3_TM_CALIB_DIG15, RX_CODE_OR_0, 7, 1)
9682    FIELD(L3_TM_CALIB_DIG15, TM_OR_RX_CODE, 6, 1)
9683    FIELD(L3_TM_CALIB_DIG15, FORCE_EN_RX, 5, 1)
9684    FIELD(L3_TM_CALIB_DIG15, TM_OR_EN_RX, 4, 1)
9685    FIELD(L3_TM_CALIB_DIG15, ICAL_CODE_OR_4, 3, 1)
9686    FIELD(L3_TM_CALIB_DIG15, ICAL_CODE_OR_3, 2, 1)
9687    FIELD(L3_TM_CALIB_DIG15, ICAL_CODE_OR_2, 1, 1)
9688    FIELD(L3_TM_CALIB_DIG15, ICAL_CODE_OR_1, 0, 1)
9689REG32(L3_TM_CALIB_DIG16, 0xec40)
9690    FIELD(L3_TM_CALIB_DIG16, TM_CALIB_DIG16_31_8_RSVD, 24, 8)
9691    FIELD(L3_TM_CALIB_DIG16, MPHY_CODE_OR_1, 7, 1)
9692    FIELD(L3_TM_CALIB_DIG16, MPHY_CODE_OR_0, 6, 1)
9693    FIELD(L3_TM_CALIB_DIG16, TM_OR_MPHY_CODE, 5, 1)
9694    FIELD(L3_TM_CALIB_DIG16, FORCE_EN_MPHY, 4, 1)
9695    FIELD(L3_TM_CALIB_DIG16, TM_OR_EN_MPHY, 3, 1)
9696    FIELD(L3_TM_CALIB_DIG16, RX_CODE_OR_3, 2, 1)
9697    FIELD(L3_TM_CALIB_DIG16, RX_CODE_OR_2, 1, 1)
9698    FIELD(L3_TM_CALIB_DIG16, RX_CODE_OR_1, 0, 1)
9699REG32(L3_TM_CALIB_DIG17, 0xec44)
9700    FIELD(L3_TM_CALIB_DIG17, TM_CALIB_DIG17_31_8_RSVD, 24, 8)
9701    FIELD(L3_TM_CALIB_DIG17, USB2_CODE_OR_2, 7, 1)
9702    FIELD(L3_TM_CALIB_DIG17, USB2_CODE_OR_1, 6, 1)
9703    FIELD(L3_TM_CALIB_DIG17, USB2_CODE_OR_0, 5, 1)
9704    FIELD(L3_TM_CALIB_DIG17, TM_OR_USB2_CODE, 4, 1)
9705    FIELD(L3_TM_CALIB_DIG17, FORCE_EN_USB2, 3, 1)
9706    FIELD(L3_TM_CALIB_DIG17, TM_OR_EN_USB2, 2, 1)
9707    FIELD(L3_TM_CALIB_DIG17, MPHY_CODE_OR_3, 1, 1)
9708    FIELD(L3_TM_CALIB_DIG17, MPHY_CODE_OR_2, 0, 1)
9709REG32(L3_TM_CALIB_DIG18, 0xec48)
9710    FIELD(L3_TM_CALIB_DIG18, TM_CALIB_DIG18_31_8_RSVD, 24, 8)
9711    FIELD(L3_TM_CALIB_DIG18, PIPE_NSW_CODE_OR_2, 7, 1)
9712    FIELD(L3_TM_CALIB_DIG18, PIPE_NSW_CODE_OR_1, 6, 1)
9713    FIELD(L3_TM_CALIB_DIG18, PIPE_NSW_CODE_OR_0, 5, 1)
9714    FIELD(L3_TM_CALIB_DIG18, TM_OR_PIPE_NSW_CODE, 4, 1)
9715    FIELD(L3_TM_CALIB_DIG18, FORCE_EN_PIPE_NSW, 3, 1)
9716    FIELD(L3_TM_CALIB_DIG18, TM_OR_EN_PIPE_NSW, 2, 1)
9717    FIELD(L3_TM_CALIB_DIG18, USB2_CODE_OR_4, 1, 1)
9718    FIELD(L3_TM_CALIB_DIG18, USB2_CODE_OR_3, 0, 1)
9719REG32(L3_TM_CALIB_DIG19, 0xec4c)
9720    FIELD(L3_TM_CALIB_DIG19, TM_CALIB_DIG19_31_8_RSVD, 24, 8)
9721    FIELD(L3_TM_CALIB_DIG19, PIPE_PSW_CODE_OR_1, 7, 1)
9722    FIELD(L3_TM_CALIB_DIG19, PIPE_PSW_CODE_OR_0, 6, 1)
9723    FIELD(L3_TM_CALIB_DIG19, TM_OR_PIPE_PSW_CODE, 5, 1)
9724    FIELD(L3_TM_CALIB_DIG19, FORCE_EN_PIPE_PSW, 4, 1)
9725    FIELD(L3_TM_CALIB_DIG19, TM_OR_EN_PIPE_PSW, 3, 1)
9726    FIELD(L3_TM_CALIB_DIG19, PIPE_NSW_CODE_OR_5, 2, 1)
9727    FIELD(L3_TM_CALIB_DIG19, PIPE_NSW_CODE_OR_4, 1, 1)
9728    FIELD(L3_TM_CALIB_DIG19, PIPE_NSW_CODE_OR_3, 0, 1)
9729REG32(L3_TM_CALIB_DIG20, 0xec50)
9730    FIELD(L3_TM_CALIB_DIG20, TM_CALIB_DIG20_31_8_RSVD, 24, 8)
9731    FIELD(L3_TM_CALIB_DIG20, CALIB_MODE, 6, 2)
9732    FIELD(L3_TM_CALIB_DIG20, PIPE_PSW_CODE_OR_5, 3, 1)
9733    FIELD(L3_TM_CALIB_DIG20, PIPE_PSW_CODE_OR_4, 2, 1)
9734    FIELD(L3_TM_CALIB_DIG20, PIPE_PSW_CODE_OR_3, 1, 1)
9735    FIELD(L3_TM_CALIB_DIG20, PIPE_PSW_CODE_OR_2, 0, 1)
9736REG32(L3_TM_CALIB_DIG21, 0xec54)
9737    FIELD(L3_TM_CALIB_DIG21, TM_CALIB_DIG21_31_8_RSVD, 24, 8)
9738    FIELD(L3_TM_CALIB_DIG21, TM_CALIB_ANA, 3, 5)
9739    FIELD(L3_TM_CALIB_DIG21, TM_CALIB_DIG22_2_RSVD, 2, 1)
9740    FIELD(L3_TM_CALIB_DIG21, FORCE_ICALIB_DONE, 1, 1)
9741    FIELD(L3_TM_CALIB_DIG21, TM_OR_ICALIB_DONE, 0, 1)
9742REG32(L3_TM_CALIB_DIG22, 0xec58)
9743    FIELD(L3_TM_CALIB_DIG22, TM_CALIB_DIG22_31_8_RSVD, 24, 8)
9744    FIELD(L3_TM_CALIB_DIG22, TM_CALIB_DIG22_5_7_RSVD, 7, 1)
9745    FIELD(L3_TM_CALIB_DIG22, EN_FP_ICAL, 6, 1)
9746    FIELD(L3_TM_CALIB_DIG22, BYPASS_FP_ICAL, 5, 1)
9747    FIELD(L3_TM_CALIB_DIG22, TM_CALIB_OBSRV_INTNODES, 0, 5)
9748REG32(L3_TM_SLICER2_CTRL, 0xec5c)
9749    FIELD(L3_TM_SLICER2_CTRL, TM_SLICER2_CTRL_31_8_RSVD, 24, 8)
9750    FIELD(L3_TM_SLICER2_CTRL, SLICER2_TM_CONTROL_7_RSVD, 7, 1)
9751    FIELD(L3_TM_SLICER2_CTRL, SLICER2_TM_SELPLLOUT_TESTOUT, 6, 1)
9752    FIELD(L3_TM_SLICER2_CTRL, SLICER2_TM_SELDIGOUT_TESTOUT, 5, 1)
9753    FIELD(L3_TM_SLICER2_CTRL, SLICER2_TM_OBSERVE_SUP, 4, 1)
9754    FIELD(L3_TM_SLICER2_CTRL, SLICER2_TM_OBSERVE_DIGSUP, 3, 1)
9755    FIELD(L3_TM_SLICER2_CTRL, SLICER2_TM_OBSERVE_DIFSUP, 2, 1)
9756    FIELD(L3_TM_SLICER2_CTRL, SLICER2_TM_ENABLE_SINGLE_ENDED, 1, 1)
9757    FIELD(L3_TM_SLICER2_CTRL, REFCLKN23_TM_OBSERVE_SUP, 0, 1)
9758REG32(L3_TM_SLICER23_BIAS_PROG0, 0xec60)
9759    FIELD(L3_TM_SLICER23_BIAS_PROG0, TM_SLICER23_BIAS_PROG0_31_8_RSVD, 24, 8)
9760    FIELD(L3_TM_SLICER23_BIAS_PROG0, SLICER23_TM_BIAS_PROG0, 0, 8)
9761REG32(L3_TM_SLICER23_BIAS_PROG1, 0xec64)
9762    FIELD(L3_TM_SLICER23_BIAS_PROG1, TM_SLICER23_BIAS_PROG1_31_8_RSVD, 24, 8)
9763    FIELD(L3_TM_SLICER23_BIAS_PROG1, SLICER23_TM_BIAS_PROG1_4_7_RSVD, 4, 4)
9764    FIELD(L3_TM_SLICER23_BIAS_PROG1, SLICER23_TM_BIAS_PROG1, 0, 4)
9765REG32(L3_TM_SLICER3_CTRL, 0xec68)
9766    FIELD(L3_TM_SLICER3_CTRL, TM_SLICER3_CTRL_31_8_RSVD, 24, 8)
9767    FIELD(L3_TM_SLICER3_CTRL, SLICER3_TM_CONTROL1_7_RSVD, 7, 1)
9768    FIELD(L3_TM_SLICER3_CTRL, SLICER3_TM_SELPLLOUT_TESTOUT, 6, 1)
9769    FIELD(L3_TM_SLICER3_CTRL, SLICER3_TM_SELDIGOUT_TESTOUT, 5, 1)
9770    FIELD(L3_TM_SLICER3_CTRL, SLICER3_TM_OBSERVE_SUP, 4, 1)
9771    FIELD(L3_TM_SLICER3_CTRL, SLICER3_TM_OBSERVE_DIGSUP, 3, 1)
9772    FIELD(L3_TM_SLICER3_CTRL, SLICER3_TM_OBSERVE_DIFSUP, 2, 1)
9773    FIELD(L3_TM_SLICER3_CTRL, SLICER3_TM_ENABLE_SINGLE_ENDED, 1, 1)
9774    FIELD(L3_TM_SLICER3_CTRL, SLICER3_TM_CONTROL1_0_RSVD, 0, 1)
9775REG32(L3_CAL_SLICER_SPARE, 0xeca0)
9776    FIELD(L3_CAL_SLICER_SPARE, CAL_SLICER_SPARE_31_8_RSVD, 24, 8)
9777    FIELD(L3_CAL_SLICER_SPARE, CAL_SLICER_SPARE_RESERVED, 6, 2)
9778    FIELD(L3_CAL_SLICER_SPARE, SLICER3_DA_SPARE, 4, 2)
9779    FIELD(L3_CAL_SLICER_SPARE, SLICER2_DA_SPARE, 2, 2)
9780    FIELD(L3_CAL_SLICER_SPARE, CAL_DA_SPARE, 0, 2)
9781REG32(L3_SLICER2_ENABLE, 0xef00)
9782    FIELD(L3_SLICER2_ENABLE, SLICER2_ENABLE_31_8_RSVD, 24, 8)
9783    FIELD(L3_SLICER2_ENABLE, REFCLK23_SUP_EN, 7, 1)
9784    FIELD(L3_SLICER2_ENABLE, SLICER2_ENABLE_TERM, 6, 1)
9785    FIELD(L3_SLICER2_ENABLE, SLICER2_ENABLE_TC_CNTRL, 4, 2)
9786    FIELD(L3_SLICER2_ENABLE, SLICER2_ENABLE_DIVIDER_4TEST, 3, 1)
9787    FIELD(L3_SLICER2_ENABLE, SLICER2_ENABLE_CLK_OUT, 2, 1)
9788    FIELD(L3_SLICER2_ENABLE, SLICER2_ENABLE_BGBIAS, 1, 1)
9789    FIELD(L3_SLICER2_ENABLE, SLICER2_ENABLE, 0, 1)
9790REG32(L3_SLICER3_ENABLE, 0xef04)
9791    FIELD(L3_SLICER3_ENABLE, SLICER3_ENABLE_31_8_RSVD, 24, 8)
9792    FIELD(L3_SLICER3_ENABLE, SLICER23_PD_BIAS, 7, 1)
9793    FIELD(L3_SLICER3_ENABLE, SLICER3_ENABLE_TERM, 6, 1)
9794    FIELD(L3_SLICER3_ENABLE, SLICER3_ENABLE_TC_CNTRL, 4, 2)
9795    FIELD(L3_SLICER3_ENABLE, SLICER3_ENABLE_DIVIDER_4TEST, 3, 1)
9796    FIELD(L3_SLICER3_ENABLE, SLICER3_ENABLE_CLK_OUT, 2, 1)
9797    FIELD(L3_SLICER3_ENABLE, SLICER3_ENABLE_BGBIAS, 1, 1)
9798    FIELD(L3_SLICER3_ENABLE, SLICER3_ENABLE, 0, 1)
9799REG32(L3_SLICER2_BYPASS, 0xef08)
9800    FIELD(L3_SLICER2_BYPASS, SLICER2_BYPASS_31_8_RSVD, 24, 8)
9801    FIELD(L3_SLICER2_BYPASS, SLICER2_BYPASS_7_RSVD, 7, 1)
9802    FIELD(L3_SLICER2_BYPASS, SLICER2_ENABLE_TERM_BYPASS, 6, 1)
9803    FIELD(L3_SLICER2_BYPASS, SLICER2_ENABLE_TC_CNTRL_BYPASS, 5, 1)
9804    FIELD(L3_SLICER2_BYPASS, SLICER2_ENABLE_CLK_OUT_BYPASS, 2, 1)
9805    FIELD(L3_SLICER2_BYPASS, SLICER2_ENABLE_BGBIAS_BYPASS, 1, 1)
9806    FIELD(L3_SLICER2_BYPASS, SLICER2_ENABLE_BYPASS, 0, 1)
9807REG32(L3_SLICER3_BYPASS, 0xef0c)
9808    FIELD(L3_SLICER3_BYPASS, SLICER3_BYPASS_31_8_RSVD, 24, 8)
9809    FIELD(L3_SLICER3_BYPASS, SLICER23_PD_BIAS_BYPASS, 7, 1)
9810    FIELD(L3_SLICER3_BYPASS, SLICER3_ENABLE_TERM_BYPASS, 6, 1)
9811    FIELD(L3_SLICER3_BYPASS, SLICER3_ENABLE_TC_CNTRL_BYPASS, 5, 1)
9812    FIELD(L3_SLICER3_BYPASS, SLICER3_ENABLE_CLK_OUT_BYPASS, 2, 1)
9813    FIELD(L3_SLICER3_BYPASS, SLICER3_ENABLE_BGBIAS_BYPASS, 1, 1)
9814    FIELD(L3_SLICER3_BYPASS, SLICER3_ENABLE_BYPASS, 0, 1)
9815REG32(L3_TM_BRINGUP_CONTROL, 0xef10)
9816    FIELD(L3_TM_BRINGUP_CONTROL, TM_BRINGUP_CONTROL_31_8_RSVD, 24, 8)
9817    FIELD(L3_TM_BRINGUP_CONTROL, TM_BRING_UP_CONTROL_2_7_RSVD, 2, 6)
9818    FIELD(L3_TM_BRINGUP_CONTROL, TM_SLOW_FAST_BRING_UP_ALWAYS, 1, 1)
9819    FIELD(L3_TM_BRINGUP_CONTROL, TM_BRING_UP_CONTROL_1_RSVD, 0, 1)
9820REG32(L3_CALIB_DONE_STATUS, 0xef14)
9821    FIELD(L3_CALIB_DONE_STATUS, CALIB_DONE_STATUS_31_8_RSVD, 24, 8)
9822    FIELD(L3_CALIB_DONE_STATUS, CALIB_DONE_STATUS_2_7_RSVD, 2, 6)
9823    FIELD(L3_CALIB_DONE_STATUS, CALIB_DONE_STATUS, 1, 1)
9824    FIELD(L3_CALIB_DONE_STATUS, CALIB_COMP_OUT_STATUS, 0, 1)
9825REG32(L3_CALIB_PIPE_PSW_CODE_STATUS, 0xef18)
9826    FIELD(L3_CALIB_PIPE_PSW_CODE_STATUS, CALIB_PIPE_PSW_CODE_STATUS_31_8_RSVD, 24, 8)
9827    FIELD(L3_CALIB_PIPE_PSW_CODE_STATUS, CALIB_PIPE_PSW_CODE_STATUS_6_7_RSVD, 6, 2)
9828    FIELD(L3_CALIB_PIPE_PSW_CODE_STATUS, PIPE_PSW_CALIB_CODE_STATUS, 0, 6)
9829REG32(L3_CALIB_PIPE_NSW_CODE_STATUS, 0xef1c)
9830    FIELD(L3_CALIB_PIPE_NSW_CODE_STATUS, CALIB_PIPE_NSW_CODE_STATUS_31_8_RSVD, 24, 8)
9831    FIELD(L3_CALIB_PIPE_NSW_CODE_STATUS, CALIB_PIPE_PSW_CODE_STATUS_6_7_RSVD, 6, 2)
9832    FIELD(L3_CALIB_PIPE_NSW_CODE_STATUS, PIPE_NSW_CALIB_CODE_STATUS, 0, 6)
9833REG32(L3_CALIB_MPHY_TX_CODE_STATUS, 0xef20)
9834    FIELD(L3_CALIB_MPHY_TX_CODE_STATUS, CALIB_MPHY_TX_CODE_STATUS_31_8_RSVD, 24, 8)
9835    FIELD(L3_CALIB_MPHY_TX_CODE_STATUS, CALIB_MPHY_TX_CODE_STATUS_4_7_RSVD, 4, 4)
9836    FIELD(L3_CALIB_MPHY_TX_CODE_STATUS, MPHY_TX_CALIB_CODE_STATUS, 0, 4)
9837REG32(L3_CALIB_ICAL_CODE_STATUS, 0xef24)
9838    FIELD(L3_CALIB_ICAL_CODE_STATUS, CALIB_ICAL_CODE_STATUS_31_8_RSVD, 24, 8)
9839    FIELD(L3_CALIB_ICAL_CODE_STATUS, I_CALIB_CODE_STATUS_5_7_RSVD, 5, 3)
9840    FIELD(L3_CALIB_ICAL_CODE_STATUS, I_CALIB_CODE_STATUS, 0, 5)
9841REG32(L3_CALIB_RX_CODE_STATUS, 0xef28)
9842    FIELD(L3_CALIB_RX_CODE_STATUS, CALIB_RX_CODE_STATUS_31_8_RSVD, 24, 8)
9843    FIELD(L3_CALIB_RX_CODE_STATUS, CALIB_RX_CODE_STATUS_4_7_RSVD, 4, 4)
9844    FIELD(L3_CALIB_RX_CODE_STATUS, I_CALIB_CODE_STATUS, 0, 4)
9845REG32(L3_CALIB_USB2_TX_CODE_STATUS, 0xef2c)
9846    FIELD(L3_CALIB_USB2_TX_CODE_STATUS, CALIB_USB2_TX_CODE_STATUS_31_8_RSVD, 24, 8)
9847    FIELD(L3_CALIB_USB2_TX_CODE_STATUS, USB2_TX_CALIB_CODE_STATUS_5_7_RSVD, 5, 3)
9848    FIELD(L3_CALIB_USB2_TX_CODE_STATUS, USB2_TX_CALIB_CODE_STATUS, 0, 5)
9849REG32(L3_CAL_ISO_CTRL, 0xef30)
9850    FIELD(L3_CAL_ISO_CTRL, CAL_ISO_CTRL_31_8_RSVD, 24, 8)
9851    FIELD(L3_CAL_ISO_CTRL, CAL_SIO_CONTROL_RSVD, 2, 6)
9852    FIELD(L3_CAL_ISO_CTRL, CAL_ISO_CTRL_BAR, 1, 1)
9853    FIELD(L3_CAL_ISO_CTRL, FORCE_CAL_ISO_CTRL_BAR, 0, 1)
9854REG32(L3_UPHY_GLOBAL_CTRL, 0xf000)
9855    FIELD(L3_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_31_8_RSVD, 24, 8)
9856    FIELD(L3_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_7_RSVD, 7, 1)
9857    FIELD(L3_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_6_RSVD, 6, 1)
9858    FIELD(L3_UPHY_GLOBAL_CTRL, UPHY_GLOBAL_CTRL_5_RSVD, 5, 1)
9859    FIELD(L3_UPHY_GLOBAL_CTRL, PCLK_SELECT, 4, 1)
9860    FIELD(L3_UPHY_GLOBAL_CTRL, MPHY_G3_BIST_ENABLE, 3, 1)
9861    FIELD(L3_UPHY_GLOBAL_CTRL, MULTI_RATE_ENABLE, 2, 1)
9862    FIELD(L3_UPHY_GLOBAL_CTRL, MPHY_GEAR_SELECT, 0, 2)
9863REG32(L3_BIST_CTRL_1, 0xf004)
9864    FIELD(L3_BIST_CTRL_1, BIST_CTRL_1_31_8_RSVD, 24, 8)
9865    FIELD(L3_BIST_CTRL_1, REPETITIVE_PATTERN_ENABLE, 7, 1)
9866    FIELD(L3_BIST_CTRL_1, PRBS_PATTERNS, 5, 2)
9867    FIELD(L3_BIST_CTRL_1, BIST_PATTERN_SELECT, 2, 3)
9868    FIELD(L3_BIST_CTRL_1, BIST_INFINITE_MODE_ENABLE, 1, 1)
9869    FIELD(L3_BIST_CTRL_1, BIST_ENABLE, 0, 1)
9870REG32(L3_BIST_CTRL_2, 0xf008)
9871    FIELD(L3_BIST_CTRL_2, BIST_CTRL_2_31_8_RSVD, 24, 8)
9872    FIELD(L3_BIST_CTRL_2, BIST_CTRL_2_7_3_RSVD, 3, 5)
9873    FIELD(L3_BIST_CTRL_2, BIST_TRAINIG_SEQUENCE_SELECT, 1, 2)
9874    FIELD(L3_BIST_CTRL_2, BIST_ERROR_INJECTION_ENABLE, 0, 1)
9875REG32(L3_BIST_RUN_LEN_L, 0xf00c)
9876    FIELD(L3_BIST_RUN_LEN_L, BIST_RUN_LEN_L_31_8_RSVD, 24, 8)
9877    FIELD(L3_BIST_RUN_LEN_L, BIST_RUN_LEN_L, 0, 8)
9878REG32(L3_BIST_ERR_INJ_POINT_L, 0xf010)
9879    FIELD(L3_BIST_ERR_INJ_POINT_L, BIST_ERR_INJ_POINT_L_31_8_RSVD, 24, 8)
9880    FIELD(L3_BIST_ERR_INJ_POINT_L, BIST_ERROR_INJ_POINT_L, 0, 8)
9881REG32(L3_BIST_RUNLEN_ERR_INJ_H, 0xf014)
9882    FIELD(L3_BIST_RUNLEN_ERR_INJ_H, BIST_RUNLEN_ERR_INJ_H_31_8_RSVD, 24, 8)
9883    FIELD(L3_BIST_RUNLEN_ERR_INJ_H, BIST_RUN_LEN_H, 4, 4)
9884    FIELD(L3_BIST_RUNLEN_ERR_INJ_H, BIST_ERROR_INJ_POINT_H, 0, 4)
9885REG32(L3_BIST_IDLE_TIME, 0xf018)
9886    FIELD(L3_BIST_IDLE_TIME, BIST_IDLE_TIME_31_8_RSVD, 24, 8)
9887    FIELD(L3_BIST_IDLE_TIME, BIST_IDLE_TIME, 0, 8)
9888REG32(L3_BIST_MARKER_L, 0xf01c)
9889    FIELD(L3_BIST_MARKER_L, BIST_MARKER_L_31_8_RSVD, 24, 8)
9890    FIELD(L3_BIST_MARKER_L, BIST_MARKER_L, 0, 8)
9891REG32(L3_BIST_IDLE_CHAR_L, 0xf020)
9892    FIELD(L3_BIST_IDLE_CHAR_L, BIST_IDLE_CHAR_L_31_8_RSVD, 24, 8)
9893    FIELD(L3_BIST_IDLE_CHAR_L, BIST_IDLE_CHAR_L, 0, 8)
9894REG32(L3_BIST_MARKER_IDLE_H, 0xf024)
9895    FIELD(L3_BIST_MARKER_IDLE_H, BIST_MARKER_IDLE_H_31_8_RSVD, 24, 8)
9896    FIELD(L3_BIST_MARKER_IDLE_H, BIST_MARKER_IDLE_RESERVED_7, 6, 2)
9897    FIELD(L3_BIST_MARKER_IDLE_H, BIST_MARKER_H, 4, 2)
9898    FIELD(L3_BIST_MARKER_IDLE_H, BIST_MARKER_IDLE_RESERVED_3, 2, 2)
9899    FIELD(L3_BIST_MARKER_IDLE_H, BIST_IDLE_CHAR_H, 0, 2)
9900REG32(L3_BIST_LOW_PULSE_TIME, 0xf028)
9901    FIELD(L3_BIST_LOW_PULSE_TIME, BIST_LOW_PULSE_TIME_31_8_RSVD, 24, 8)
9902    FIELD(L3_BIST_LOW_PULSE_TIME, BIST_LOW_PULSE_TIME, 0, 8)
9903REG32(L3_BIST_TOTAL_PULSE_TIME, 0xf02c)
9904    FIELD(L3_BIST_TOTAL_PULSE_TIME, BIST_TOTAL_PULSE_TIME_31_8_RSVD, 24, 8)
9905    FIELD(L3_BIST_TOTAL_PULSE_TIME, BIST_TOTAL_PULSE_TIME, 0, 8)
9906REG32(L3_BIST_TEST_PAT_1, 0xf030)
9907    FIELD(L3_BIST_TEST_PAT_1, BIST_TEST_PAT_1_31_8_RSVD, 24, 8)
9908    FIELD(L3_BIST_TEST_PAT_1, BIST_TEST_PAT_1_L, 0, 8)
9909REG32(L3_BIST_TEST_PAT_2, 0xf034)
9910    FIELD(L3_BIST_TEST_PAT_2, BIST_TEST_PAT_2_31_8_RSVD, 24, 8)
9911    FIELD(L3_BIST_TEST_PAT_2, BIST_TEST_PAT_2_L, 0, 8)
9912REG32(L3_BIST_TEST_PAT_3, 0xf038)
9913    FIELD(L3_BIST_TEST_PAT_3, BIST_TEST_PAT_3_31_8_RSVD, 24, 8)
9914    FIELD(L3_BIST_TEST_PAT_3, BIST_TEST_PAT_3_L, 0, 8)
9915REG32(L3_BIST_TEST_PAT_4, 0xf03c)
9916    FIELD(L3_BIST_TEST_PAT_4, BIST_TEST_PAT_4_31_8_RSVD, 24, 8)
9917    FIELD(L3_BIST_TEST_PAT_4, BIST_TEST_PAT_4_L, 0, 8)
9918REG32(L3_BIST_TEST_PAT_MSBS, 0xf040)
9919    FIELD(L3_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_MSBS_31_8_RSVD, 24, 8)
9920    FIELD(L3_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_4_H, 6, 2)
9921    FIELD(L3_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_3_H, 4, 2)
9922    FIELD(L3_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_2_H, 2, 2)
9923    FIELD(L3_BIST_TEST_PAT_MSBS, BIST_TEST_PAT_1_H, 0, 2)
9924REG32(L3_BIST_PKT_NUM, 0xf044)
9925    FIELD(L3_BIST_PKT_NUM, BIST_PKT_NUM_31_8_RSVD, 24, 8)
9926    FIELD(L3_BIST_PKT_NUM, BIST_PKT_NUM, 0, 8)
9927REG32(L3_BIST_FRM_IDLE_TIME, 0xf048)
9928    FIELD(L3_BIST_FRM_IDLE_TIME, BIST_FRM_IDLE_TIME_31_8_RSVD, 24, 8)
9929    FIELD(L3_BIST_FRM_IDLE_TIME, BIST_FRM_IDLE_TIME, 0, 8)
9930REG32(L3_BIST_PKT_CTR_L, 0xf04c)
9931    FIELD(L3_BIST_PKT_CTR_L, BIST_PKT_CTR_L_31_8_RSVD, 24, 8)
9932    FIELD(L3_BIST_PKT_CTR_L, BIST_PKT_CTR_L, 0, 8)
9933REG32(L3_BIST_PKT_CTR_H, 0xf050)
9934    FIELD(L3_BIST_PKT_CTR_H, BIST_PKT_CTR_H_31_8_RSVD, 24, 8)
9935    FIELD(L3_BIST_PKT_CTR_H, BIST_PKT_CTR_H, 0, 8)
9936REG32(L3_BIST_ERR_CTR_L, 0xf054)
9937    FIELD(L3_BIST_ERR_CTR_L, BIST_ERR_CTR_L_31_8_RSVD, 24, 8)
9938    FIELD(L3_BIST_ERR_CTR_L, BIST_ERR_CTR_L, 0, 8)
9939REG32(L3_BIST_ERR_CTR_H, 0xf058)
9940    FIELD(L3_BIST_ERR_CTR_H, BIST_ERR_CTR_H_31_8_RSVD, 24, 8)
9941    FIELD(L3_BIST_ERR_CTR_H, BIST_ERR_CTR_H, 0, 8)
9942REG32(L3_CLK_DIV_CNT, 0xf05c)
9943    FIELD(L3_CLK_DIV_CNT, CLK_DIV_CNT_31_8_RSVD, 24, 8)
9944    FIELD(L3_CLK_DIV_CNT, REF_CLK_BYPASS_GT_50MHZ, 7, 1)
9945    FIELD(L3_CLK_DIV_CNT, SLOW_CNT_REG, 0, 7)
9946REG32(L3_DATA_BUS_WID, 0xf060)
9947    FIELD(L3_DATA_BUS_WID, DATA_BUS_WID_31_8_RSVD, 24, 8)
9948    FIELD(L3_DATA_BUS_WID, RATE_CHANGE_BYPASS, 7, 1)
9949    FIELD(L3_DATA_BUS_WID, PCLK_RATIO_BY_4, 6, 1)
9950    FIELD(L3_DATA_BUS_WID, PCLK_RATIO_BY_2, 5, 1)
9951    FIELD(L3_DATA_BUS_WID, RATE_CHANGE_DELAY_SEL, 4, 1)
9952    FIELD(L3_DATA_BUS_WID, RATE_CHANGE_DELAY_COUNT, 0, 4)
9953REG32(L3_ANADIG_BYPASS, 0xf064)
9954    FIELD(L3_ANADIG_BYPASS, ANADIG_BYPASS_31_8_RSVD, 24, 8)
9955    FIELD(L3_ANADIG_BYPASS, ANA_DIG_COUNTER_SELECT, 7, 1)
9956    FIELD(L3_ANADIG_BYPASS, ANADIG_COUNT, 0, 7)
9957REG32(L3_BIST_FILLER_OUT, 0xf068)
9958    FIELD(L3_BIST_FILLER_OUT, BIST_FILLER_OUT_31_8_RSVD, 24, 8)
9959    FIELD(L3_BIST_FILLER_OUT, BIST_FILLER_OUT_RESERVED, 2, 6)
9960    FIELD(L3_BIST_FILLER_OUT, BIST_FILLER_OUT_ENABLE, 1, 1)
9961    FIELD(L3_BIST_FILLER_OUT, BIST_TX_RX_LOOPBACK_ENABLE, 0, 1)
9962REG32(L3_BIST_FORCE_MK_RST, 0xf06c)
9963    FIELD(L3_BIST_FORCE_MK_RST, BIST_FORCE_MK_RST_31_8_RSVD, 24, 8)
9964    FIELD(L3_BIST_FORCE_MK_RST, BIST_FORCE_RESET, 1, 1)
9965    FIELD(L3_BIST_FORCE_MK_RST, BIST_ENABLE_MK_FROM_REG, 0, 1)
9966REG32(L3_SPARE_IN, 0xf070)
9967    FIELD(L3_SPARE_IN, SPARE_IN_31_8_RSVD, 24, 8)
9968    FIELD(L3_SPARE_IN, SPARE_IN, 0, 8)
9969REG32(L3_SPARE_OUT, 0xf074)
9970    FIELD(L3_SPARE_OUT, SPARE_OUT_31_8_RSVD, 24, 8)
9971    FIELD(L3_SPARE_OUT, SPARE_OUT, 0, 8)
9972REG32(PLL_REF_SEL0, 0x10000)
9973    FIELD(PLL_REF_SEL0, PLL_REF_SEL0_31_8_RSVD, 24, 8)
9974    FIELD(PLL_REF_SEL0, PLL_REF_SEL0_7_RSVD, 7, 1)
9975    FIELD(PLL_REF_SEL0, PLL_REF_SEL0_6_RSVD, 6, 1)
9976    FIELD(PLL_REF_SEL0, PLL_REF_SEL0_5_RSVD, 5, 1)
9977    FIELD(PLL_REF_SEL0, PLLREFSEL0, 0, 5)
9978REG32(PLL_REF_SEL1, 0x10004)
9979    FIELD(PLL_REF_SEL1, PLL_REF_SEL1_31_8_RSVD, 24, 8)
9980    FIELD(PLL_REF_SEL1, PLL_REF_SEL0_7_RSVD, 7, 1)
9981    FIELD(PLL_REF_SEL1, PLL_REF_SEL0_6_RSVD, 6, 1)
9982    FIELD(PLL_REF_SEL1, PLL_REF_SEL0_5_RSVD, 5, 1)
9983    FIELD(PLL_REF_SEL1, PLLREFSEL1, 0, 5)
9984REG32(PLL_REF_SEL2, 0x10008)
9985    FIELD(PLL_REF_SEL2, PLL_REF_SEL2_31_8_RSVD, 24, 8)
9986    FIELD(PLL_REF_SEL2, PLL_REF_SEL0_7_RSVD, 7, 1)
9987    FIELD(PLL_REF_SEL2, PLL_REF_SEL0_6_RSVD, 6, 1)
9988    FIELD(PLL_REF_SEL2, PLL_REF_SEL0_5_RSVD, 5, 1)
9989    FIELD(PLL_REF_SEL2, PLLREFSEL2, 0, 5)
9990REG32(PLL_REF_SEL3, 0x1000c)
9991    FIELD(PLL_REF_SEL3, PLL_REF_SEL3_31_8_RSVD, 24, 8)
9992    FIELD(PLL_REF_SEL3, PLL_REF_SEL0_7_RSVD, 7, 1)
9993    FIELD(PLL_REF_SEL3, PLL_REF_SEL0_6_RSVD, 6, 1)
9994    FIELD(PLL_REF_SEL3, PLL_REF_SEL0_5_RSVD, 5, 1)
9995    FIELD(PLL_REF_SEL3, PLLREFSEL3, 0, 5)
9996REG32(ICM_CFG0, 0x10010)
9997    FIELD(ICM_CFG0, ICM_CFG0_31_8_RSVD, 24, 8)
9998    FIELD(ICM_CFG0, ICM_CFG0_7_RSVD, 7, 1)
9999    FIELD(ICM_CFG0, L1_ICM_CFG, 4, 3)
10000    FIELD(ICM_CFG0, ICM_CFG0_3_RSVD, 3, 1)

10001    FIELD(ICM_CFG0, L0_ICM_CFG, 0, 3)
10002REG32(ICM_CFG1, 0x10014)
10003    FIELD(ICM_CFG1, ICM_CFG1_31_8_RSVD, 24, 8)
10004    FIELD(ICM_CFG1, ICM_CFG1_7_RSVD, 7, 1)
10005    FIELD(ICM_CFG1, L3_ICM_CFG, 4, 3)
10006    FIELD(ICM_CFG1, ICM_CFG1_3_RSVD, 3, 1)
10007    FIELD(ICM_CFG1, L2_ICM_CFG, 0, 3)
10008REG32(TM_CMN_RST, 0x10018)
10009    FIELD(TM_CMN_RST, TM_CMN_RST_31_8_RSVD, 24, 8)
10010    FIELD(TM_CMN_RST, TM_CMN_RST_7_2_RSVD, 2, 6)
10011    FIELD(TM_CMN_RST, CMN_RESETN, 1, 1)
10012    FIELD(TM_CMN_RST, CMN_RESETN_TM_EN, 0, 1)
10013REG32(PCIE_DYNDESKEW_PAT0, 0x1001c)
10014    FIELD(PCIE_DYNDESKEW_PAT0, PCIE_DYNDESKEW_PAT0_31_8_RSVD, 24, 8)
10015    FIELD(PCIE_DYNDESKEW_PAT0, PCIE_DYN_DESKEW_PAT0, 0, 8)
10016REG32(PCIE_DYNDESKEW_PAT1, 0x10020)
10017    FIELD(PCIE_DYNDESKEW_PAT1, PCIE_DYNDESKEW_PAT1_31_8_RSVD, 24, 8)
10018    FIELD(PCIE_DYNDESKEW_PAT1, PCIE_DYN_DESKEW_PAT1, 0, 8)
10019REG32(LANE_RPTR_CTRL, 0x10024)
10020    FIELD(LANE_RPTR_CTRL, LANE_RPTR_CTRL_31_8_RSVD, 24, 8)
10021    FIELD(LANE_RPTR_CTRL, LANE_RPTR_CTRL_7_1_RSVD, 1, 7)
10022    FIELD(LANE_RPTR_CTRL, LANE_RPTR_ON, 0, 1)
10023REG32(BGCAL_REF_SEL, 0x10028)
10024    FIELD(BGCAL_REF_SEL, BGCAL_REF_SEL_31_8_RSVD, 24, 8)
10025    FIELD(BGCAL_REF_SEL, BGCAL_REF_SEL_7_RSVD, 7, 1)
10026    FIELD(BGCAL_REF_SEL, BGCAL_REF_SEL_6_RSVD, 6, 1)
10027    FIELD(BGCAL_REF_SEL, BGCAL_REF_SEL_5_RSVD, 5, 1)
10028    FIELD(BGCAL_REF_SEL, BGCAL_REFSEL, 0, 5)
10029REG32(PCIE_RXSTAT_CTRL, 0x1002c)
10030    FIELD(PCIE_RXSTAT_CTRL, PCIE_RXSTAT_CTRL_31_8_RSVD, 24, 8)
10031    FIELD(PCIE_RXSTAT_CTRL, PCIE_RXSTAT_CTRL_7_1_RSVD, 1, 7)
10032    FIELD(PCIE_RXSTAT_CTRL, PCIE_RXSTAT_PIPELN_DIS_TM, 0, 1)
10033REG32(PLLLOCK2PCIEPHYRDY_CNT, 0x10034)
10034    FIELD(PLLLOCK2PCIEPHYRDY_CNT, PLLLOCK2PCIEPHYRDY_CNT_31_8_RSVD, 24, 8)
10035    FIELD(PLLLOCK2PCIEPHYRDY_CNT, PLLLOCK2PCIEPHYRDY_CNT, 0, 8)
10036REG32(LPBK_CTRL0, 0x10038)
10037    FIELD(LPBK_CTRL0, LPBK_CTRL0_31_8_RSVD, 24, 8)
10038    FIELD(LPBK_CTRL0, LPBK_CTRL0_7_RSVD, 7, 1)
10039    FIELD(LPBK_CTRL0, L1_LPBK_SEL, 4, 3)
10040    FIELD(LPBK_CTRL0, LPBK_CTRL0_3_RSVD, 3, 1)
10041    FIELD(LPBK_CTRL0, L0_LPBK_SEL, 0, 3)
10042REG32(LPBK_CTRL1, 0x1003c)
10043    FIELD(LPBK_CTRL1, LPBK_CTRL1_31_8_RSVD, 24, 8)
10044    FIELD(LPBK_CTRL1, LPBK_CTRL1_7_RSVD, 7, 1)
10045    FIELD(LPBK_CTRL1, L3_LPBK_SEL, 4, 3)
10046    FIELD(LPBK_CTRL1, LPBK_CTRL1_3_RSVD, 3, 1)
10047    FIELD(LPBK_CTRL1, L2_LPBK_SEL, 0, 3)
10048REG32(TX_PROT_BUS_WIDTH, 0x10040)
10049    FIELD(TX_PROT_BUS_WIDTH, TX_PROT_BUS_WIDTH_31_8_RSVD, 24, 8)
10050    FIELD(TX_PROT_BUS_WIDTH, L3_TX_PROT_BUSWIDTH, 6, 2)
10051    FIELD(TX_PROT_BUS_WIDTH, L2_TX_PROT_BUSWIDTH, 4, 2)
10052    FIELD(TX_PROT_BUS_WIDTH, L1_TX_PROT_BUSWIDTH, 2, 2)
10053    FIELD(TX_PROT_BUS_WIDTH, L0_TX_PROT_BUSWIDTH, 0, 2)
10054REG32(RX_PROT_BUS_WIDTH, 0x10044)
10055    FIELD(RX_PROT_BUS_WIDTH, RX_PROT_BUS_WIDTH_31_8_RSVD, 24, 8)
10056    FIELD(RX_PROT_BUS_WIDTH, L3_RX_PROT_BUSWIDTH, 6, 2)
10057    FIELD(RX_PROT_BUS_WIDTH, L2_RX_PROT_BUSWIDTH, 4, 2)
10058    FIELD(RX_PROT_BUS_WIDTH, L1_RX_PROT_BUSWIDTH, 2, 2)
10059    FIELD(RX_PROT_BUS_WIDTH, L0_RX_PROT_BUSWIDTH, 0, 2)
10060REG32(RMMI_RST_CTRL, 0x10048)
10061    FIELD(RMMI_RST_CTRL, RMMI_RST_CTRL_31_8_RSVD, 24, 8)
10062    FIELD(RMMI_RST_CTRL, L3_RX_RESET, 7, 1)
10063    FIELD(RMMI_RST_CTRL, L2_RX_RESET, 6, 1)
10064    FIELD(RMMI_RST_CTRL, L1_RX_RESET, 5, 1)
10065    FIELD(RMMI_RST_CTRL, L0_RX_RESET, 4, 1)
10066    FIELD(RMMI_RST_CTRL, L3_TX_RESET, 3, 1)
10067    FIELD(RMMI_RST_CTRL, L2_TX_RESET, 2, 1)
10068    FIELD(RMMI_RST_CTRL, L1_TX_RESET, 1, 1)
10069    FIELD(RMMI_RST_CTRL, L0_TX_RESET, 0, 1)
10070REG32(TM_RX_COUPLING_CTRL, 0x1004c)
10071    FIELD(TM_RX_COUPLING_CTRL, TM_RX_COUPLING_CTRL_31_8_RSVD, 24, 8)
10072    FIELD(TM_RX_COUPLING_CTRL, L3_RX_COUPLING_TM_EN, 7, 1)
10073    FIELD(TM_RX_COUPLING_CTRL, L3_RX_COUPLING, 6, 1)
10074    FIELD(TM_RX_COUPLING_CTRL, L2_RX_COUPLING_TM_EN, 5, 1)
10075    FIELD(TM_RX_COUPLING_CTRL, L2_RX_COUPLING, 4, 1)
10076    FIELD(TM_RX_COUPLING_CTRL, L1_RX_COUPLING_TM_EN, 3, 1)
10077    FIELD(TM_RX_COUPLING_CTRL, L1_RX_COUPLING, 2, 1)
10078    FIELD(TM_RX_COUPLING_CTRL, L0_RX_COUPLING_TM_EN, 1, 1)
10079    FIELD(TM_RX_COUPLING_CTRL, L0_RX_COUPLING, 0, 1)
10080REG32(TM_PCIE_DESKEW_CTRL, 0x10050)
10081    FIELD(TM_PCIE_DESKEW_CTRL, TM_PCIE_DESKEW_CTRL_31_8_RSVD, 24, 8)
10082    FIELD(TM_PCIE_DESKEW_CTRL, EN_DESKEW_RATE_CHANGE_TM, 7, 1)
10083    FIELD(TM_PCIE_DESKEW_CTRL, LINK_DOWN_RESET, 6, 1)
10084    FIELD(TM_PCIE_DESKEW_CTRL, PCIE_DESKEW_BYP, 5, 1)
10085    FIELD(TM_PCIE_DESKEW_CTRL, PCIE_DYN_DESKEW_BYP, 4, 1)
10086    FIELD(TM_PCIE_DESKEW_CTRL, PCIE_RX_DATA_PATH_EN_TM_EN, 3, 1)
10087    FIELD(TM_PCIE_DESKEW_CTRL, PCIE_RX_DATA_PATH_EN_TM, 2, 1)
10088    FIELD(TM_PCIE_DESKEW_CTRL, PCIE_DESKEW_TM_EN, 1, 1)
10089    FIELD(TM_PCIE_DESKEW_CTRL, PCIE_DESKEW_EN, 0, 1)
10090REG32(TM_PCIE_LANEMAP, 0x10054)
10091    FIELD(TM_PCIE_LANEMAP, TM_PCIE_LANEMAP_31_8_RSVD, 24, 8)
10092    FIELD(TM_PCIE_LANEMAP, TM_PCIE_LANEMAP_TM_7_5_RSVD, 5, 3)
10093    FIELD(TM_PCIE_LANEMAP, PCIE_LANEMAP_TM_EN, 4, 1)
10094    FIELD(TM_PCIE_LANEMAP, PCIE_LANEMAP_TM, 0, 4)
10095REG32(RX_DETECT_CTRL, 0x10058)
10096    FIELD(RX_DETECT_CTRL, RX_DETECT_CTRL_31_8_RSVD, 24, 8)
10097    FIELD(RX_DETECT_CTRL, L3_TXDETRX_RC_OFF, 7, 1)
10098    FIELD(RX_DETECT_CTRL, L3_TXDETRX_RC_OFF_TM_EN, 6, 1)
10099    FIELD(RX_DETECT_CTRL, L2_TXDETRX_RC_OFF, 5, 1)
10100    FIELD(RX_DETECT_CTRL, L2_TXDETRX_RC_OFF_TM_EN, 4, 1)
10101    FIELD(RX_DETECT_CTRL, L1_TXDETRX_RC_OFF, 3, 1)
10102    FIELD(RX_DETECT_CTRL, L1_TXDETRX_RC_OFF_TM_EN, 2, 1)
10103    FIELD(RX_DETECT_CTRL, L0_TXDETRX_RC_OFF, 1, 1)
10104    FIELD(RX_DETECT_CTRL, L0_TXDETRX_RC_OFF_TM_EN, 0, 1)
10105REG32(DESKEW_ST0, 0x1005c)
10106    FIELD(DESKEW_ST0, DESKEW_ST0_31_8_RSVD, 24, 8)
10107    FIELD(DESKEW_ST0, IDLE_SEQ_DETD, 4, 4)
10108    FIELD(DESKEW_ST0, IDLE_SEQ_4_DETD, 0, 4)
10109REG32(DESKEW_ST1, 0x10060)
10110    FIELD(DESKEW_ST1, DESKEW_ST1_31_8_RSVD, 24, 8)
10111    FIELD(DESKEW_ST1, DESKEW_ST1_7_6_RSVD, 6, 2)
10112    FIELD(DESKEW_ST1, DESKEW_DONE, 5, 1)
10113    FIELD(DESKEW_ST1, DESKEW_IN_PROGRESS, 4, 1)
10114    FIELD(DESKEW_ST1, PCIE_LANE_MAP, 0, 4)
10115REG32(AFE_RX0_CTRL, 0x10064)
10116    FIELD(AFE_RX0_CTRL, AFE_RX0_CTRL_31_8_RSVD, 24, 8)
10117    FIELD(AFE_RX0_CTRL, AFE_RX0_CTRL_7_5_RSVD, 5, 3)
10118    FIELD(AFE_RX0_CTRL, PSO_IO_EQ, 4, 1)
10119    FIELD(AFE_RX0_CTRL, PSO_CORE_EQ, 3, 1)
10120    FIELD(AFE_RX0_CTRL, PSO_EQ_TM, 2, 1)
10121    FIELD(AFE_RX0_CTRL, AFE_RX0_MPHY_PWM_SYS_REFCLK, 1, 1)
10122    FIELD(AFE_RX0_CTRL, AFE_RX0_MPHY_MASK_BURST_START, 0, 1)
10123REG32(AFE_RX1_CTRL, 0x10068)
10124    FIELD(AFE_RX1_CTRL, AFE_RX1_CTRL_31_8_RSVD, 24, 8)
10125    FIELD(AFE_RX1_CTRL, AFE_RX1_CTRL_7_5_RSVD, 5, 3)
10126    FIELD(AFE_RX1_CTRL, PSO_IO_EQ, 4, 1)
10127    FIELD(AFE_RX1_CTRL, PSO_CORE_EQ, 3, 1)
10128    FIELD(AFE_RX1_CTRL, PSO_EQ_TM, 2, 1)
10129    FIELD(AFE_RX1_CTRL, AFE_RX1_MPHY_PWM_SYS_REFCLK, 1, 1)
10130    FIELD(AFE_RX1_CTRL, AFE_RX1_MPHY_MASK_BURST_START, 0, 1)
10131REG32(AFE_RX2_CTRL, 0x1006c)
10132    FIELD(AFE_RX2_CTRL, AFE_RX2_CTRL_31_8_RSVD, 24, 8)
10133    FIELD(AFE_RX2_CTRL, AFE_RX2_CTRL_7_5_RSVD, 5, 3)
10134    FIELD(AFE_RX2_CTRL, PSO_IO_EQ, 4, 1)
10135    FIELD(AFE_RX2_CTRL, PSO_CORE_EQ, 3, 1)
10136    FIELD(AFE_RX2_CTRL, PSO_EQ_TM, 2, 1)
10137    FIELD(AFE_RX2_CTRL, AFE_RX2_MPHY_PWM_SYS_REFCLK, 1, 1)
10138    FIELD(AFE_RX2_CTRL, AFE_RX2_MPHY_MASK_BURST_START, 0, 1)
10139REG32(AFE_RX3_CTRL, 0x10070)
10140    FIELD(AFE_RX3_CTRL, AFE_RX3_CTRL_31_8_RSVD, 24, 8)
10141    FIELD(AFE_RX3_CTRL, AFE_RX3_CTRL_7_5_RSVD, 5, 3)
10142    FIELD(AFE_RX3_CTRL, PSO_IO_EQ, 4, 1)
10143    FIELD(AFE_RX3_CTRL, PSO_CORE_EQ, 3, 1)
10144    FIELD(AFE_RX3_CTRL, PSO_EQ_TM, 2, 1)
10145    FIELD(AFE_RX3_CTRL, AFE_RX3_MPHY_PWM_SYS_REFCLK, 1, 1)
10146    FIELD(AFE_RX3_CTRL, AFE_RX3_MPHY_MASK_BURST_START, 0, 1)
10147REG32(SPARE_IN0, 0x10074)
10148    FIELD(SPARE_IN0, SPARE_IN0_31_8_RSVD, 24, 8)
10149    FIELD(SPARE_IN0, SPARE_IN, 0, 8)
10150REG32(SPARE_OUT0, 0x10078)
10151    FIELD(SPARE_OUT0, SPARE_OUT0_31_8_RSVD, 24, 8)
10152    FIELD(SPARE_OUT0, SPARE_OUT, 0, 8)
10153REG32(SPARE_IN1, 0x1007c)
10154    FIELD(SPARE_IN1, SPARE_IN1_31_8_RSVD, 24, 8)
10155    FIELD(SPARE_IN1, SPARE_IN, 0, 8)
10156REG32(SPARE_OUT1, 0x10080)
10157    FIELD(SPARE_OUT1, SPARE_OUT1_31_8_RSVD, 24, 8)
10158    FIELD(SPARE_OUT1, SPARE_OUT, 0, 8)
10159REG32(SPARE_IN2, 0x10084)
10160    FIELD(SPARE_IN2, SPARE_IN2_31_8_RSVD, 24, 8)
10161    FIELD(SPARE_IN2, SPARE_IN, 0, 8)
10162REG32(SPARE_OUT2, 0x10088)
10163    FIELD(SPARE_OUT2, SPARE_OUT2_31_8_RSVD, 24, 8)
10164    FIELD(SPARE_OUT2, SPARE_OUT, 0, 8)
10165REG32(SPARE_IN3, 0x1008c)
10166    FIELD(SPARE_IN3, SPARE_IN3_31_8_RSVD, 24, 8)
10167    FIELD(SPARE_IN3, SPARE_IN, 0, 8)
10168REG32(SPARE_OUT3, 0x10090)
10169    FIELD(SPARE_OUT3, SPARE_OUT3_31_8_RSVD, 24, 8)
10170    FIELD(SPARE_OUT3, SPARE_OUT, 0, 8)
10171REG32(SGMII_CDET_CTRL, 0x10094)
10172    FIELD(SGMII_CDET_CTRL, SGMII_CDET_CTRL_31_8_RSVD, 24, 8)
10173    FIELD(SGMII_CDET_CTRL, L3_EN_CDET_TM_EN, 7, 1)
10174    FIELD(SGMII_CDET_CTRL, L3_EN_CDET, 6, 1)
10175    FIELD(SGMII_CDET_CTRL, L2_EN_CDET_TM_EN, 5, 1)
10176    FIELD(SGMII_CDET_CTRL, L2_EN_CDET, 4, 1)
10177    FIELD(SGMII_CDET_CTRL, L1_EN_CDET_TM_EN, 3, 1)
10178    FIELD(SGMII_CDET_CTRL, L1_EN_CDET, 2, 1)
10179    FIELD(SGMII_CDET_CTRL, L0_EN_CDET_TM_EN, 1, 1)
10180    FIELD(SGMII_CDET_CTRL, L0_EN_CDET, 0, 1)
10181REG32(UPHY_SPARE0, 0x10098)
10182    FIELD(UPHY_SPARE0, UPHY_SPARE0_31_8_RSVD, 24, 8)
10183    FIELD(UPHY_SPARE0, SPARE, 0, 8)
10184REG32(UPHY_SPARE1, 0x1009c)
10185    FIELD(UPHY_SPARE1, UPHY_SPARE1_31_8_RSVD, 24, 8)
10186    FIELD(UPHY_SPARE1, SPARE, 0, 8)
10187REG32(UPHY_SPARE2, 0x100a0)
10188    FIELD(UPHY_SPARE2, UPHY_SPARE2_31_8_RSVD, 24, 8)
10189    FIELD(UPHY_SPARE2, SPARE, 0, 8)
10190REG32(UPHY_SPARE3, 0x100a4)
10191    FIELD(UPHY_SPARE3, UPHY_SPARE3_31_8_RSVD, 24, 8)
10192    FIELD(UPHY_SPARE3, SPARE, 0, 8)
10193REG32(CIRRUS_SPARE_OUT0, 0x100a8)
10194    FIELD(CIRRUS_SPARE_OUT0, CIRRUS_SPARE_OUT0_31_8_RSVD, 24, 8)
10195    FIELD(CIRRUS_SPARE_OUT0, SPARE, 0, 8)
10196REG32(CIRRUS_SPARE_OUT1, 0x100ac)
10197    FIELD(CIRRUS_SPARE_OUT1, CIRRUS_SPARE_OUT1_31_8_RSVD, 24, 8)
10198    FIELD(CIRRUS_SPARE_OUT1, SPARE, 0, 8)
10199REG32(CIRRUS_SPARE_OUT2, 0x100b0)
10200    FIELD(CIRRUS_SPARE_OUT2, CIRRUS_SPARE_OUT2_31_8_RSVD, 24, 8)
10201    FIELD(CIRRUS_SPARE_OUT2, SPARE, 0, 8)
10202REG32(CIRRUS_SPARE_OUT3, 0x100b4)
10203    FIELD(CIRRUS_SPARE_OUT3, CIRRUS_SPARE_OUT3_31_8_RSVD, 24, 8)
10204    FIELD(CIRRUS_SPARE_OUT3, SPARE, 0, 8)
10205REG32(CIRRUS_SPARE_IN0, 0x100b8)
10206    FIELD(CIRRUS_SPARE_IN0, CIRRUS_SPARE_IN0_31_8_RSVD, 24, 8)
10207    FIELD(CIRRUS_SPARE_IN0, SPARE, 0, 8)
10208REG32(CIRRUS_SPARE_IN1, 0x100bc)
10209    FIELD(CIRRUS_SPARE_IN1, CIRRUS_SPARE_IN1_31_8_RSVD, 24, 8)
10210    FIELD(CIRRUS_SPARE_IN1, SPARE, 0, 8)
10211REG32(CIRRUS_SPARE_IN2, 0x100c0)
10212    FIELD(CIRRUS_SPARE_IN2, CIRRUS_SPARE_IN2_31_8_RSVD, 24, 8)
10213    FIELD(CIRRUS_SPARE_IN2, SPARE, 0, 8)
10214REG32(CIRRUS_SPARE_IN3, 0x100c4)
10215    FIELD(CIRRUS_SPARE_IN3, CIRRUS_SPARE_IN3_31_8_RSVD, 24, 8)
10216    FIELD(CIRRUS_SPARE_IN3, SPARE, 0, 8)
10217REG32(AFE_EQ_PSO_DELAY, 0x100c8)
10218    FIELD(AFE_EQ_PSO_DELAY, AFE_EQ_PSO_DELAY_31_8_RSVD, 24, 8)
10219    FIELD(AFE_EQ_PSO_DELAY, RSVD_7, 7, 1)
10220    FIELD(AFE_EQ_PSO_DELAY, DEASSERT_DELAY, 4, 3)
10221    FIELD(AFE_EQ_PSO_DELAY, RSVD_3, 3, 1)
10222    FIELD(AFE_EQ_PSO_DELAY, ASSERT_DELAY, 0, 3)
10223REG32(USB_TXFIFO0_CTRL, 0x10210)
10224    FIELD(USB_TXFIFO0_CTRL, USB_TXFIFO0_CTRL_31_8_RSVD, 24, 8)
10225    FIELD(USB_TXFIFO0_CTRL, USB0_TXFIFO_BYP, 7, 1)
10226    FIELD(USB_TXFIFO0_CTRL, USB_TXFIFO0_CTRL_6_RSVD, 6, 1)
10227    FIELD(USB_TXFIFO0_CTRL, USB0_TXFIFO_ALMOST_EMPTY_VAL, 0, 6)
10228REG32(USB_TXFIFO1_CTRL, 0x10214)
10229    FIELD(USB_TXFIFO1_CTRL, USB_TXFIFO1_CTRL_31_8_RSVD, 24, 8)
10230    FIELD(USB_TXFIFO1_CTRL, USB1_TXFIFO_BYP, 7, 1)
10231    FIELD(USB_TXFIFO1_CTRL, USB_TXFIFO1_CTRL_6_RSVD, 6, 1)
10232    FIELD(USB_TXFIFO1_CTRL, USB1_TXFIFO_ALMOST_EMPTY_VAL, 0, 6)
10233REG32(DP_TXFIFO0_CTRL, 0x10218)
10234    FIELD(DP_TXFIFO0_CTRL, DP_TXFIFO0_CTRL_31_8_RSVD, 24, 8)
10235    FIELD(DP_TXFIFO0_CTRL, DP0_TXFIFO_BYP, 7, 1)
10236    FIELD(DP_TXFIFO0_CTRL, DP_TXFIFO0_CTRL_6_RSVD, 6, 1)
10237    FIELD(DP_TXFIFO0_CTRL, DP0_TXFIFO_ALMOST_EMPTY_VAL, 0, 6)
10238REG32(DP_TXFIFO1_CTRL, 0x1021c)
10239    FIELD(DP_TXFIFO1_CTRL, DP_TXFIFO1_CTRL_31_8_RSVD, 24, 8)
10240    FIELD(DP_TXFIFO1_CTRL, DP1_TXFIFO_BYP, 7, 1)
10241    FIELD(DP_TXFIFO1_CTRL, DP_TXFIFO1_CTRL_6_RSVD, 6, 1)
10242    FIELD(DP_TXFIFO1_CTRL, DP1_TXFIFO_ALMOST_EMPTY_VAL, 0, 6)
10243
10244#define SERDES_R_MAX (R_DP_TXFIFO1_CTRL + 1)
10245
10246typedef struct SERDES {
10247    SysBusDevice parent_obj;
10248    MemoryRegion iomem;
10249
10250    uint32_t regs[SERDES_R_MAX];
10251    RegisterInfo regs_info[SERDES_R_MAX];
10252    const char *prefix;
10253} SERDES;
10254
10255static RegisterAccessInfo serdes_regs_info[] = {
10256    {   .name = "L0_TX_ANA_TM_0",  .addr = A_L0_TX_ANA_TM_0,
10257        .reset = 0x28,
10258        .ro = 0xffffffc3,
10259    },{ .name = "L0_TX_ANA_TM_3",  .addr = A_L0_TX_ANA_TM_3,
10260        .ro = 0xffffff00,
10261    },{ .name = "L0_TX_ANA_TM_4",  .addr = A_L0_TX_ANA_TM_4,
10262        .ro = 0xffffff80,
10263    },{ .name = "L0_TX_ANA_TM_5",  .addr = A_L0_TX_ANA_TM_5,
10264        .ro = 0xffffff80,
10265    },{ .name = "L0_TX_ANA_TM_9",  .addr = A_L0_TX_ANA_TM_9,
10266        .reset = 0x3f,
10267        .ro = 0xffffff00,
10268    },{ .name = "L0_TX_ANA_TM_10",  .addr = A_L0_TX_ANA_TM_10,
10269        .reset = 0x30,
10270        .ro = 0xffffff00,
10271    },{ .name = "L0_TX_ANA_TM_13",  .addr = A_L0_TX_ANA_TM_13,
10272        .reset = 0x2,
10273        .ro = 0xfffffff0,
10274    },{ .name = "L0_TX_ANA_TM_14",  .addr = A_L0_TX_ANA_TM_14,
10275        .ro = 0xffffffcf,
10276    },{ .name = "L0_TX_ANA_TM_15",  .addr = A_L0_TX_ANA_TM_15,
10277        .ro = 0xffffff00,
10278    },{ .name = "L0_TX_ANA_TM_16",  .addr = A_L0_TX_ANA_TM_16,
10279        .ro = 0xfffffff0,
10280    },{ .name = "L0_TX_ANA_TM_18",  .addr = A_L0_TX_ANA_TM_18,
10281        .reset = 0x2,
10282        .ro = 0xffffff00,
10283    },{ .name = "L0_TX_ANA_TM_19",  .addr = A_L0_TX_ANA_TM_19,
10284        .ro = 0xffffff00,
10285    },{ .name = "L0_TX_ANA_TM_20",  .addr = A_L0_TX_ANA_TM_20,
10286        .ro = 0xffffffe0,
10287    },{ .name = "L0_TX_ANA_TM_21",  .addr = A_L0_TX_ANA_TM_21,
10288        .ro = 0xffffffc0,
10289    },{ .name = "L0_TX_DIG_TM_61",  .addr = A_L0_TX_DIG_TM_61,
10290        .ro = 0xffffff34,
10291    },{ .name = "L0_TX_DIG_TM_62",  .addr = A_L0_TX_DIG_TM_62,
10292        .ro = 0xffffff00,
10293    },{ .name = "L0_TX_DIG_TM_65",  .addr = A_L0_TX_DIG_TM_65,
10294        .ro = 0xffffff01,
10295    },{ .name = "L0_TX_DIG_TM_67",  .addr = A_L0_TX_DIG_TM_67,
10296        .ro = 0xffffff00,
10297    },{ .name = "L0_TX_DIG_TM_68",  .addr = A_L0_TX_DIG_TM_68,
10298        .ro = 0xffffff00,
10299    },{ .name = "L0_TX_DIG_TM_69",  .addr = A_L0_TX_DIG_TM_69,
10300        .ro = 0xffffff00,
10301    },{ .name = "L0_TX_DIG_TM_76",  .addr = A_L0_TX_DIG_TM_76,
10302        .ro = 0xffffff00,
10303    },{ .name = "L0_TX_DIG_TM_77",  .addr = A_L0_TX_DIG_TM_77,
10304        .ro = 0xffffff00,
10305    },{ .name = "L0_TX_DIG_TM_78",  .addr = A_L0_TX_DIG_TM_78,
10306        .ro = 0xffffff00,
10307    },{ .name = "L0_TX_DIG_TM_79",  .addr = A_L0_TX_DIG_TM_79,
10308        .ro = 0xffffff00,
10309    },{ .name = "L0_TX_DIG_TM_80",  .addr = A_L0_TX_DIG_TM_80,
10310        .ro = 0xffffff00,
10311    },{ .name = "L0_TX_DIG_TM_81",  .addr = A_L0_TX_DIG_TM_81,
10312        .ro = 0xffffff00,
10313    },{ .name = "L0_TX_DIG_TM_82",  .addr = A_L0_TX_DIG_TM_82,
10314        .ro = 0xffffff00,
10315    },{ .name = "L0_TX_DIG_TM_83",  .addr = A_L0_TX_DIG_TM_83,
10316        .ro = 0xfffffff0,
10317    },{ .name = "L0_TX_DIG_TM_84",  .addr = A_L0_TX_DIG_TM_84,
10318        .ro = 0xffffff0a,
10319    },{ .name = "L0_TX_ANA_TM_85",  .addr = A_L0_TX_ANA_TM_85,
10320        .ro = 0xffffffca,
10321    },{ .name = "L0_TX_ANA_TM_87",  .addr = A_L0_TX_ANA_TM_87,
10322        .ro = 0xfffffff0,
10323    },{ .name = "L0_TX_ANA_TM_88",  .addr = A_L0_TX_ANA_TM_88,
10324        .reset = 0x96,
10325        .ro = 0xffffff00,
10326    },{ .name = "L0_TX_ANA_TM_89",  .addr = A_L0_TX_ANA_TM_89,
10327        .ro = 0xffffffd9,
10328    },{ .name = "L0_TX_ANA_TM_90",  .addr = A_L0_TX_ANA_TM_90,
10329        .ro = 0xffffffdf,
10330    },{ .name = "L0_TX_DIG_TM_91",  .addr = A_L0_TX_DIG_TM_91,
10331        .reset = 0x1a,
10332        .ro = 0xffffff00,
10333    },{ .name = "L0_TX_DIG_TM_92",  .addr = A_L0_TX_DIG_TM_92,
10334        .reset = 0xa,
10335        .ro = 0xffffff00,
10336    },{ .name = "L0_TX_ANA_TM_95",  .addr = A_L0_TX_ANA_TM_95,
10337        .ro = 0xffffffc3,
10338    },{ .name = "L0_TX_ANA_TM_96",  .addr = A_L0_TX_ANA_TM_96,
10339        .ro = 0xffffff00,
10340    },{ .name = "L0_TX_ANA_TM_97",  .addr = A_L0_TX_ANA_TM_97,
10341        .ro = 0xffffff00,
10342    },{ .name = "L0_TX_DIG_TM_98",  .addr = A_L0_TX_DIG_TM_98,
10343        .ro = 0xffffffc0,
10344    },{ .name = "L0_TX_DIG_TM_99",  .addr = A_L0_TX_DIG_TM_99,
10345        .ro = 0xffffff00,
10346    },{ .name = "L0_TX_DIG_TM_100",  .addr = A_L0_TX_DIG_TM_100,
10347        .ro = 0xffffff00,
10348    },{ .name = "L0_TX_DIG_TM_101",  .addr = A_L0_TX_DIG_TM_101,
10349        .ro = 0xffffff00,
10350    },{ .name = "L0_TX_DIG_TM_102",  .addr = A_L0_TX_DIG_TM_102,
10351        .ro = 0xffffff00,
10352    },{ .name = "L0_TX_DIG_TM_103",  .addr = A_L0_TX_DIG_TM_103,
10353        .ro = 0xffffff00,
10354    },{ .name = "L0_TX_DIG_TM_104",  .addr = A_L0_TX_DIG_TM_104,
10355        .ro = 0xffffff00,
10356    },{ .name = "L0_TX_DIG_TM_105",  .addr = A_L0_TX_DIG_TM_105,
10357        .ro = 0xffffff00,
10358    },{ .name = "L0_TX_DIG_TM_106",  .addr = A_L0_TX_DIG_TM_106,
10359        .ro = 0xffffff00,
10360    },{ .name = "L0_TX_DIG_TM_107",  .addr = A_L0_TX_DIG_TM_107,
10361        .ro = 0xffffff80,
10362    },{ .name = "L0_TX_DIG_TM_108",  .addr = A_L0_TX_DIG_TM_108,
10363        .ro = 0xffffff80,
10364    },{ .name = "L0_TX_DIG_TM_109",  .addr = A_L0_TX_DIG_TM_109,
10365        .ro = 0xffffff00,
10366    },{ .name = "L0_TX_DIG_TM_110",  .addr = A_L0_TX_DIG_TM_110,
10367        .reset = 0x9,
10368        .ro = 0xffffff00,
10369    },{ .name = "L0_TX_DIG_TM_111",  .addr = A_L0_TX_DIG_TM_111,
10370        .ro = 0xffffff00,
10371    },{ .name = "L0_TX_ANA_TM_112",  .addr = A_L0_TX_ANA_TM_112,
10372        .ro = 0xffffffc0,
10373    },{ .name = "L0_TX_ANA_TM_113",  .addr = A_L0_TX_ANA_TM_113,
10374        .ro = 0xffffff00,
10375    },{ .name = "L0_TX_ANA_TM_114",  .addr = A_L0_TX_ANA_TM_114,
10376        .ro = 0xffffffe0,
10377    },{ .name = "L0_TX_ANA_TM_115",  .addr = A_L0_TX_ANA_TM_115,
10378        .ro = 0xffffff80,
10379    },{ .name = "L0_TX_ANA_TM_116",  .addr = A_L0_TX_ANA_TM_116,
10380        .ro = 0xffffff80,
10381    },{ .name = "L0_TX_ANA_TM_117",  .addr = A_L0_TX_ANA_TM_117,
10382        .ro = 0xffffffc0,
10383    },{ .name = "L0_TX_ANA_TM_118",  .addr = A_L0_TX_ANA_TM_118,
10384        .ro = 0xfffffff0,
10385    },{ .name = "L0_TXPMA_TM_0",  .addr = A_L0_TXPMA_TM_0,
10386        .ro = 0xffffff00,
10387    },{ .name = "L0_TXPMA_TM_1",  .addr = A_L0_TXPMA_TM_1,
10388        .ro = 0xfffffff0,
10389    },{ .name = "L0_TXPMA_TM_2",  .addr = A_L0_TXPMA_TM_2,
10390        .ro = 0xffffff00,
10391    },{ .name = "L0_TXPMA_TM_3",  .addr = A_L0_TXPMA_TM_3,
10392        .ro = 0xffffffe0,
10393    },{ .name = "L0_TXPMA_TM_4",  .addr = A_L0_TXPMA_TM_4,
10394        .reset = 0x2,
10395        .ro = 0xffffff01,
10396    },{ .name = "L0_TXPMA_TM_5",  .addr = A_L0_TXPMA_TM_5,
10397        .ro = 0xfffffff0,
10398    },{ .name = "L0_TXPMA_TM_6",  .addr = A_L0_TXPMA_TM_6,
10399        .ro = 0xffffff00,
10400    },{ .name = "L0_TXPMA_TM_7",  .addr = A_L0_TXPMA_TM_7,
10401        .ro = 0xffffff00,
10402    },{ .name = "L0_TXPMA_TM_8",  .addr = A_L0_TXPMA_TM_8,
10403        .ro = 0xfffffffc,
10404    },{ .name = "L0_TXPMA_TM_9",  .addr = A_L0_TXPMA_TM_9,
10405        .ro = 0xffffff80,
10406    },{ .name = "L0_TXPMA_TM_10",  .addr = A_L0_TXPMA_TM_10,
10407        .ro = 0xffffffc0,
10408    },{ .name = "L0_TXPMA_TM_11",  .addr = A_L0_TXPMA_TM_11,
10409        .ro = 0xffffffe0,
10410    },{ .name = "L0_TXPMA_TM_12",  .addr = A_L0_TXPMA_TM_12,
10411        .ro = 0xffffff01,
10412    },{ .name = "L0_TXPMA_TM_13",  .addr = A_L0_TXPMA_TM_13,
10413        .ro = 0xffffff00,
10414    },{ .name = "L0_TXPMA_TM_14",  .addr = A_L0_TXPMA_TM_14,
10415        .ro = 0xffffffe0,
10416    },{ .name = "L0_TXPMA_TM_15",  .addr = A_L0_TXPMA_TM_15,
10417        .ro = 0xffffff00,
10418    },{ .name = "L0_TXPMA_TM_16",  .addr = A_L0_TXPMA_TM_16,
10419        .ro = 0xffffff00,
10420    },{ .name = "L0_TXPMA_TM_17",  .addr = A_L0_TXPMA_TM_17,
10421        .ro = 0xffffff00,
10422    },{ .name = "L0_TXPMA_TM_18",  .addr = A_L0_TXPMA_TM_18,
10423        .reset = 0xf,
10424        .ro = 0xffffff00,
10425    },{ .name = "L0_TXPMA_TM_19",  .addr = A_L0_TXPMA_TM_19,
10426        .reset = 0x3,
10427        .ro = 0xffffffc0,
10428    },{ .name = "L0_TXPMA_TM_20",  .addr = A_L0_TXPMA_TM_20,
10429        .reset = 0x6,
10430        .ro = 0xffffff00,
10431    },{ .name = "L0_TXPMA_TM_21",  .addr = A_L0_TXPMA_TM_21,
10432        .reset = 0x3,
10433        .ro = 0xffffff00,
10434    },{ .name = "L0_TXPMA_TM_22",  .addr = A_L0_TXPMA_TM_22,
10435        .reset = 0x6,
10436        .ro = 0xffffff00,
10437    },{ .name = "L0_TXPMA_TM_23",  .addr = A_L0_TXPMA_TM_23,
10438        .reset = 0x3,
10439        .ro = 0xffffff00,
10440    },{ .name = "L0_TXPMA_TM_24",  .addr = A_L0_TXPMA_TM_24,
10441        .ro = 0xffffff80,
10442    },{ .name = "L0_TXPMA_TM_25",  .addr = A_L0_TXPMA_TM_25,
10443        .ro = 0xffffffc0,
10444    },{ .name = "L0_TXPMA_TM_26",  .addr = A_L0_TXPMA_TM_26,
10445        .reset = 0x64,
10446        .ro = 0xffffff00,
10447    },{ .name = "L0_TXPMA_TM_27",  .addr = A_L0_TXPMA_TM_27,
10448        .ro = 0xffffff00,
10449    },{ .name = "L0_TXPMA_ST_0",  .addr = A_L0_TXPMA_ST_0,
10450        .reset = 0x1,
10451        .ro = 0xffffffff,
10452    },{ .name = "L0_TXPMA_ST_1",  .addr = A_L0_TXPMA_ST_1,
10453        .reset = 0x1,
10454        .ro = 0xffffffff,
10455    },{ .name = "L0_TXPMA_ST_2",  .addr = A_L0_TXPMA_ST_2,
10456        .reset = 0x4,
10457        .ro = 0xffffffff,
10458    },{ .name = "L0_TXPMA_ST_3",  .addr = A_L0_TXPMA_ST_3,
10459        .reset = 0x20,
10460        .ro = 0xffffffff,
10461    },{ .name = "L0_TXPMA_ST_4",  .addr = A_L0_TXPMA_ST_4,
10462        .reset = 0x20,
10463        .ro = 0xffffffff,
10464    },{ .name = "L0_TXPMA_ST_5",  .addr = A_L0_TXPMA_ST_5,
10465        .reset = 0x20,
10466        .ro = 0xffffffff,
10467    },{ .name = "L0_TXPMA_ST_6",  .addr = A_L0_TXPMA_ST_6,
10468        .reset = 0xb,
10469        .ro = 0xffffffff,
10470    },{ .name = "L0_TXPMA_ST_7",  .addr = A_L0_TXPMA_ST_7,
10471        .ro = 0xffffffff,
10472    },{ .name = "L0_TXPMA_ST_8",  .addr = A_L0_TXPMA_ST_8,
10473        .ro = 0xffffffff,
10474    },{ .name = "L0_TXPMA_ST_9",  .addr = A_L0_TXPMA_ST_9,
10475        .ro = 0xffffffff,
10476    },{ .name = "L0_TXPMD_TM_0",  .addr = A_L0_TXPMD_TM_0,
10477        .ro = 0xffffffe0,
10478    },{ .name = "L0_TXPMD_TM_1",  .addr = A_L0_TXPMD_TM_1,
10479        .ro = 0xffffffe0,
10480    },{ .name = "L0_TXPMD_TM_2",  .addr = A_L0_TXPMD_TM_2,
10481        .ro = 0xffffffe0,
10482    },{ .name = "L0_TXPMD_TM_3",  .addr = A_L0_TXPMD_TM_3,
10483        .ro = 0xffffffe0,
10484    },{ .name = "L0_TXPMD_TM_4",  .addr = A_L0_TXPMD_TM_4,
10485        .ro = 0xffffffe0,
10486    },{ .name = "L0_TXPMD_TM_5",  .addr = A_L0_TXPMD_TM_5,
10487        .ro = 0xffffffe0,
10488    },{ .name = "L0_TXPMD_TM_6",  .addr = A_L0_TXPMD_TM_6,
10489        .ro = 0xffffffe0,
10490    },{ .name = "L0_TXPMD_TM_7",  .addr = A_L0_TXPMD_TM_7,
10491        .ro = 0xffffffe0,
10492    },{ .name = "L0_TXPMD_TM_8",  .addr = A_L0_TXPMD_TM_8,
10493        .ro = 0xffffffe0,
10494    },{ .name = "L0_TXPMD_TM_9",  .addr = A_L0_TXPMD_TM_9,
10495        .ro = 0xffffffe0,
10496    },{ .name = "L0_TXPMD_TM_10",  .addr = A_L0_TXPMD_TM_10,
10497        .ro = 0xffffffe0,
10498    },{ .name = "L0_TXPMD_TM_11",  .addr = A_L0_TXPMD_TM_11,
10499        .ro = 0xffffffe0,
10500    },{ .name = "L0_TXPMD_TM_12",  .addr = A_L0_TXPMD_TM_12,
10501        .ro = 0xffffffe0,
10502    },{ .name = "L0_TXPMD_TM_13",  .addr = A_L0_TXPMD_TM_13,
10503        .ro = 0xffffffe0,
10504    },{ .name = "L0_TXPMD_TM_14",  .addr = A_L0_TXPMD_TM_14,
10505        .ro = 0xffffffe0,
10506    },{ .name = "L0_TXPMD_TM_15",  .addr = A_L0_TXPMD_TM_15,
10507        .ro = 0xffffffe0,
10508    },{ .name = "L0_TXPMD_TM_16",  .addr = A_L0_TXPMD_TM_16,
10509        .ro = 0xffffffe0,
10510    },{ .name = "L0_TXPMD_TM_17",  .addr = A_L0_TXPMD_TM_17,
10511        .ro = 0xffffffe0,
10512    },{ .name = "L0_TXPMD_TM_18",  .addr = A_L0_TXPMD_TM_18,
10513        .ro = 0xffffffe0,
10514    },{ .name = "L0_TXPMD_TM_19",  .addr = A_L0_TXPMD_TM_19,
10515        .ro = 0xffffffe0,
10516    },{ .name = "L0_TXPMD_TM_20",  .addr = A_L0_TXPMD_TM_20,
10517        .ro = 0xffffffe0,
10518    },{ .name = "L0_TXPMD_TM_21",  .addr = A_L0_TXPMD_TM_21,
10519        .ro = 0xffffffe0,
10520    },{ .name = "L0_TXPMD_TM_22",  .addr = A_L0_TXPMD_TM_22,
10521        .ro = 0xffffffe0,
10522    },{ .name = "L0_TXPMD_TM_23",  .addr = A_L0_TXPMD_TM_23,
10523        .ro = 0xffffffe0,
10524    },{ .name = "L0_TXPMD_TM_24",  .addr = A_L0_TXPMD_TM_24,
10525        .ro = 0xffffffe0,
10526    },{ .name = "L0_TXPMD_TM_25",  .addr = A_L0_TXPMD_TM_25,
10527        .ro = 0xffffffe0,
10528    },{ .name = "L0_TXPMD_TM_26",  .addr = A_L0_TXPMD_TM_26,
10529        .ro = 0xffffffe0,
10530    },{ .name = "L0_TXPMD_TM_27",  .addr = A_L0_TXPMD_TM_27,
10531        .ro = 0xffffffe0,
10532    },{ .name = "L0_TXPMD_TM_28",  .addr = A_L0_TXPMD_TM_28,
10533        .ro = 0xffffffe0,
10534    },{ .name = "L0_TXPMD_TM_29",  .addr = A_L0_TXPMD_TM_29,
10535        .ro = 0xffffffe0,
10536    },{ .name = "L0_TXPMD_TM_30",  .addr = A_L0_TXPMD_TM_30,
10537        .ro = 0xffffffe0,
10538    },{ .name = "L0_TXPMD_TM_31",  .addr = A_L0_TXPMD_TM_31,
10539        .ro = 0xffffffe0,
10540    },{ .name = "L0_TXPMD_TM_32",  .addr = A_L0_TXPMD_TM_32,
10541        .ro = 0xffffff00,
10542    },{ .name = "L0_TXPMD_TM_33",  .addr = A_L0_TXPMD_TM_33,
10543        .ro = 0xffffff00,
10544    },{ .name = "L0_TXPMD_TM_34",  .addr = A_L0_TXPMD_TM_34,
10545        .ro = 0xffffff00,
10546    },{ .name = "L0_TXPMD_TM_35",  .addr = A_L0_TXPMD_TM_35,
10547        .ro = 0xffffff00,
10548    },{ .name = "L0_TXPMD_TM_36",  .addr = A_L0_TXPMD_TM_36,
10549        .ro = 0xffffff00,
10550    },{ .name = "L0_TXPMD_TM_37",  .addr = A_L0_TXPMD_TM_37,
10551        .ro = 0xffffff00,
10552    },{ .name = "L0_TXPMD_TM_38",  .addr = A_L0_TXPMD_TM_38,
10553        .ro = 0xffffff80,
10554    },{ .name = "L0_TXPMD_TM_39",  .addr = A_L0_TXPMD_TM_39,
10555        .ro = 0xfffffff8,
10556    },{ .name = "L0_TXPMD_TM_40",  .addr = A_L0_TXPMD_TM_40,
10557        .ro = 0xffffff00,
10558    },{ .name = "L0_TXPMD_TM_41",  .addr = A_L0_TXPMD_TM_41,
10559        .ro = 0xffffff00,
10560    },{ .name = "L0_TXPMD_TM_42",  .addr = A_L0_TXPMD_TM_42,
10561        .ro = 0xffffffe0,
10562    },{ .name = "L0_TXPMD_TM_43",  .addr = A_L0_TXPMD_TM_43,
10563        .ro = 0xfffffff0,
10564    },{ .name = "L0_TXPMD_TM_44",  .addr = A_L0_TXPMD_TM_44,
10565        .ro = 0xffffffc0,
10566    },{ .name = "L0_TXPMD_TM_45",  .addr = A_L0_TXPMD_TM_45,
10567        .ro = 0xffffffc0,
10568    },{ .name = "L0_TXPMD_TM_46",  .addr = A_L0_TXPMD_TM_46,
10569        .ro = 0xffffffc0,
10570    },{ .name = "L0_TXPMD_TM_47",  .addr = A_L0_TXPMD_TM_47,
10571        .ro = 0xffffff00,
10572    },{ .name = "L0_TXPMD_TM_48",  .addr = A_L0_TXPMD_TM_48,
10573        .ro = 0xffffffc0,
10574    },{ .name = "L0_TM_ANA_BYP_1",  .addr = A_L0_TM_ANA_BYP_1,
10575        .ro = 0xffffff00,
10576    },{ .name = "L0_TM_ANA_BYP_2",  .addr = A_L0_TM_ANA_BYP_2,
10577        .ro = 0xffffff00,
10578    },{ .name = "L0_TM_ANA_BYP_3",  .addr = A_L0_TM_ANA_BYP_3,
10579        .ro = 0xffffff00,
10580    },{ .name = "L0_TM_ANA_BYP_4",  .addr = A_L0_TM_ANA_BYP_4,
10581        .ro = 0xffffff00,
10582    },{ .name = "L0_TM_ANA_BYP_5",  .addr = A_L0_TM_ANA_BYP_5,
10583        .rsvd = 0xc0,
10584        .ro = 0xffffffc0,
10585    },{ .name = "L0_TM_ANA_BYP_7",  .addr = A_L0_TM_ANA_BYP_7,
10586        .rsvd = 0xf,
10587        .ro = 0xffffff0f,
10588    },{ .name = "L0_TM_ANA_BYP_8",  .addr = A_L0_TM_ANA_BYP_8,
10589        .ro = 0xffffff00,
10590    },{ .name = "L0_TM_ANA_BYP_9",  .addr = A_L0_TM_ANA_BYP_9,
10591        .ro = 0xffffff00,
10592    },{ .name = "L0_TM_ANA_BYP_10",  .addr = A_L0_TM_ANA_BYP_10,
10593        .rsvd = 0xc0,
10594        .ro = 0xffffffc0,
10595    },{ .name = "L0_TM_ANA_BYP_11",  .addr = A_L0_TM_ANA_BYP_11,
10596        .rsvd = 0xc0,
10597        .ro = 0xffffffc0,
10598    },{ .name = "L0_TM_ANA_BYP_12",  .addr = A_L0_TM_ANA_BYP_12,
10599        .ro = 0xffffff00,
10600    },{ .name = "L0_TM_ANA_BYP_13",  .addr = A_L0_TM_ANA_BYP_13,
10601        .rsvd = 0xfc,
10602        .ro = 0xfffffffc,
10603    },{ .name = "L0_TM_ANA_BYP_14",  .addr = A_L0_TM_ANA_BYP_14,
10604        .rsvd = 0xc,
10605        .ro = 0xffffff0c,
10606    },{ .name = "L0_TM_ANA_BYP_15",  .addr = A_L0_TM_ANA_BYP_15,
10607        .ro = 0xffffff00,
10608    },{ .name = "L0_TM_ANA_BYP_16",  .addr = A_L0_TM_ANA_BYP_16,
10609        .ro = 0xffffff00,
10610    },{ .name = "L0_TM_ANA_BYP_17",  .addr = A_L0_TM_ANA_BYP_17,
10611        .rsvd = 0x80,
10612        .ro = 0xffffff80,
10613    },{ .name = "L0_TM_ANA_BYP_18",  .addr = A_L0_TM_ANA_BYP_18,
10614        .rsvd = 0xf0,
10615        .ro = 0xfffffff0,
10616    },{ .name = "L0_TM_ANA_BYP_20",  .addr = A_L0_TM_ANA_BYP_20,
10617        .ro = 0xffffff00,
10618    },{ .name = "L0_TM_ANA_BYP_21",  .addr = A_L0_TM_ANA_BYP_21,
10619        .ro = 0xffffff00,
10620    },{ .name = "L0_TM_ANA_BYP_22",  .addr = A_L0_TM_ANA_BYP_22,
10621        .ro = 0xffffff00,
10622    },{ .name = "L0_TM_ANA_BYP_23",  .addr = A_L0_TM_ANA_BYP_23,
10623        .ro = 0xffffff00,
10624    },{ .name = "L0_TM_DIG_1",  .addr = A_L0_TM_DIG_1,
10625        .reset = 0x40,
10626        .ro = 0xffffff00,
10627    },{ .name = "L0_TM_DIG_2",  .addr = A_L0_TM_DIG_2,
10628        .rsvd = 0xc0,
10629        .ro = 0xffffffc0,
10630    },{ .name = "L0_TM_DIG_3",  .addr = A_L0_TM_DIG_3,
10631        .ro = 0xffffff00,
10632    },{ .name = "L0_TM_DIG_4",  .addr = A_L0_TM_DIG_4,
10633        .rsvd = 0x7,
10634        .ro = 0xffffff07,
10635    },{ .name = "L0_TM_DIG_5",  .addr = A_L0_TM_DIG_5,
10636        .rsvd = 0xf8,
10637        .ro = 0xfffffff8,
10638    },{ .name = "L0_TM_DIG_6",  .addr = A_L0_TM_DIG_6,
10639        .rsvd = 0x80,
10640        .ro = 0xffffff80,
10641    },{ .name = "L0_TM_DIG_7",  .addr = A_L0_TM_DIG_7,
10642        .ro = 0xffffff00,
10643    },{ .name = "L0_TM_DIG_8",  .addr = A_L0_TM_DIG_8,
10644        .rsvd = 0xe0,
10645        .ro = 0xffffffe0,
10646    },{ .name = "L0_TM_DIG_9",  .addr = A_L0_TM_DIG_9,
10647        .rsvd = 0xf0,
10648        .ro = 0xfffffff0,
10649    },{ .name = "L0_TM_DIG_10",  .addr = A_L0_TM_DIG_10,
10650        .reset = 0x1,
10651        .rsvd = 0xf0,
10652        .ro = 0xfffffff0,
10653    },{ .name = "L0_TM_DIG_11",  .addr = A_L0_TM_DIG_11,
10654        .rsvd = 0xf,
10655        .ro = 0xffffff0f,
10656    },{ .name = "L0_TM_DIG_12",  .addr = A_L0_TM_DIG_12,
10657        .rsvd = 0xc0,
10658        .ro = 0xffffffc0,
10659    },{ .name = "L0_TM_DIG_13",  .addr = A_L0_TM_DIG_13,
10660        .reset = 0x1a,
10661        .rsvd = 0x80,
10662        .ro = 0xffffff80,
10663    },{ .name = "L0_TM_DIG_14",  .addr = A_L0_TM_DIG_14,
10664        .rsvd = 0xf,
10665        .ro = 0xffffff0f,
10666    },{ .name = "L0_TM_DIG_15",  .addr = A_L0_TM_DIG_15,
10667        .reset = 0xd,
10668        .rsvd = 0xc0,
10669        .ro = 0xffffffc0,
10670    },{ .name = "L0_TM_DIG_16",  .addr = A_L0_TM_DIG_16,
10671        .rsvd = 0xe0,
10672        .ro = 0xffffffe0,
10673    },{ .name = "L0_TM_DIG_17",  .addr = A_L0_TM_DIG_17,
10674        .rsvd = 0xe0,
10675        .ro = 0xffffffe0,
10676    },{ .name = "L0_TM_DIG_18",  .addr = A_L0_TM_DIG_18,
10677        .reset = 0x2a,
10678        .ro = 0xffffff00,
10679    },{ .name = "L0_TM_DIG_19",  .addr = A_L0_TM_DIG_19,
10680        .reset = 0x36,
10681        .ro = 0xffffff00,
10682    },{ .name = "L0_TM_DIG_20",  .addr = A_L0_TM_DIG_20,
10683        .reset = 0x10,
10684        .rsvd = 0x80,
10685        .ro = 0xffffff80,
10686    },{ .name = "L0_TM_DIG_21",  .addr = A_L0_TM_DIG_21,
10687        .rsvd = 0xe0,
10688        .ro = 0xffffffe0,
10689    },{ .name = "L0_TM_DIG_22",  .addr = A_L0_TM_DIG_22,
10690        .rsvd = 0xc0,
10691        .ro = 0xffffffc0,
10692    },{ .name = "L0_TM_DIG_23",  .addr = A_L0_TM_DIG_23,
10693        .reset = 0x5,
10694        .ro = 0xffffff00,
10695    },{ .name = "L0_TM_DIG_24",  .addr = A_L0_TM_DIG_24,
10696        .ro = 0xffffff00,
10697    },{ .name = "L0_TM_DIG_25",  .addr = A_L0_TM_DIG_25,
10698        .ro = 0xffffff00,
10699    },{ .name = "L0_TM_DIG_26",  .addr = A_L0_TM_DIG_26,
10700        .ro = 0xffffff00,
10701    },{ .name = "L0_TM_DIG_27",  .addr = A_L0_TM_DIG_27,
10702        .ro = 0xffffff00,
10703    },{ .name = "L0_TM_DIG_28",  .addr = A_L0_TM_DIG_28,
10704        .ro = 0xffffff00,
10705    },{ .name = "L0_TM_DIG_29",  .addr = A_L0_TM_DIG_29,
10706        .ro = 0xffffff00,
10707    },{ .name = "L0_TM_AUX_0",  .addr = A_L0_TM_AUX_0,
10708        .ro = 0xffffff00,
10709    },{ .name = "L0_TM_AUX_1",  .addr = A_L0_TM_AUX_1,
10710        .ro = 0xffffff00,
10711    },{ .name = "L0_TM_AUX_2",  .addr = A_L0_TM_AUX_2,
10712        .ro = 0xffffff00,
10713    },{ .name = "L0_TM_AUX_3",  .addr = A_L0_TM_AUX_3,
10714        .ro = 0xffffff00,
10715    },{ .name = "L0_TM_AUX_4",  .addr = A_L0_TM_AUX_4,
10716        .ro = 0xffffff00,
10717    },{ .name = "L0_TM_DIG_30",  .addr = A_L0_TM_DIG_30,
10718        .rsvd = 0xc0,
10719        .ro = 0xffffffc0,
10720    },{ .name = "L0_TM_DIG_31",  .addr = A_L0_TM_DIG_31,
10721        .reset = 0xfa,
10722        .ro = 0xffffff00,
10723    },{ .name = "L0_TM_DIG_32",  .addr = A_L0_TM_DIG_32,
10724        .reset = 0xfa,
10725        .ro = 0xffffff00,
10726    },{ .name = "L0_TM_DIG_33",  .addr = A_L0_TM_DIG_33,
10727        .ro = 0xffffff00,
10728    },{ .name = "L0_TM_DIG_34",  .addr = A_L0_TM_DIG_34,
10729        .reset = 0x1e,
10730        .rsvd = 0xc0,
10731        .ro = 0xffffffc0,
10732    },{ .name = "L0_TM_DIG_35",  .addr = A_L0_TM_DIG_35,
10733        .reset = 0x18,
10734        .rsvd = 0xc0,
10735        .ro = 0xffffffc0,
10736    },{ .name = "L0_TM_DIG_36",  .addr = A_L0_TM_DIG_36,
10737        .ro = 0xffffff00,
10738    },{ .name = "L0_TM_DIG_37",  .addr = A_L0_TM_DIG_37,
10739        .rsvd = 0xe0,
10740        .ro = 0xffffffe0,
10741    },{ .name = "L0_TM_LFPS_1",  .addr = A_L0_TM_LFPS_1,
10742        .reset = 0x88,
10743        .ro = 0xffffff00,
10744    },{ .name = "L0_TM_LFPS_2",  .addr = A_L0_TM_LFPS_2,
10745        .reset = 0x34,
10746        .rsvd = 0x80,
10747        .ro = 0xffffff80,
10748    },{ .name = "L0_TM_LFPS_3",  .addr = A_L0_TM_LFPS_3,
10749        .reset = 0x6c,
10750        .ro = 0xffffff00,
10751    },{ .name = "L0_TM_LFPS_4",  .addr = A_L0_TM_LFPS_4,
10752        .rsvd = 0xc0,
10753        .ro = 0xffffffc0,
10754    },{ .name = "L0_TM_RXPMA_1",  .addr = A_L0_TM_RXPMA_1,
10755        .ro = 0xffffff00,
10756    },{ .name = "L0_TM_BSCAN_1",  .addr = A_L0_TM_BSCAN_1,
10757        .rsvd = 0xf8,
10758        .ro = 0xfffffff8,
10759    },{ .name = "L0_TM_MPHY_SQ_1",  .addr = A_L0_TM_MPHY_SQ_1,
10760        .reset = 0x1,
10761        .rsvd = 0xe0,
10762        .ro = 0xffffffe0,
10763    },{ .name = "L0_TM_LSRX_1",  .addr = A_L0_TM_LSRX_1,
10764        .ro = 0xffffff00,
10765    },{ .name = "L0_TM_LSRX_2",  .addr = A_L0_TM_LSRX_2,
10766        .rsvd = 0xc0,
10767        .ro = 0xffffffc0,
10768    },{ .name = "L0_TM_SIGDET_1",  .addr = A_L0_TM_SIGDET_1,
10769        .reset = 0x34,
10770        .rsvd = 0x80,
10771        .ro = 0xffffff80,
10772    },{ .name = "L0_TM_SIGDET_2",  .addr = A_L0_TM_SIGDET_2,
10773        .reset = 0xf,
10774        .ro = 0xffffff00,
10775    },{ .name = "L0_TM_DFT_1",  .addr = A_L0_TM_DFT_1,
10776        .rsvd = 0x7,
10777        .ro = 0xffffff07,
10778    },{ .name = "L0_TM_DFT_2",  .addr = A_L0_TM_DFT_2,
10779        .rsvd = 0xf8,
10780        .ro = 0xfffffff8,
10781    },{ .name = "L0_TM_DFT_3",  .addr = A_L0_TM_DFT_3,
10782        .rsvd = 0xe0,
10783        .ro = 0xffffffe0,
10784    },{ .name = "L0_TM_DFT_4",  .addr = A_L0_TM_DFT_4,
10785        .rsvd = 0xfc,
10786        .ro = 0xfffffffc,
10787    },{ .name = "L0_TM_DFT_5",  .addr = A_L0_TM_DFT_5,
10788        .ro = 0xffffff00,
10789    },{ .name = "L0_TM_DFT_6",  .addr = A_L0_TM_DFT_6,
10790        .ro = 0xffffff00,
10791    },{ .name = "L0_TM_DFT_7",  .addr = A_L0_TM_DFT_7,
10792        .rsvd = 0xe0,
10793        .ro = 0xffffffe0,
10794    },{ .name = "L0_TM_DFT_8",  .addr = A_L0_TM_DFT_8,
10795        .rsvd = 0xe0,
10796        .ro = 0xffffffe0,
10797    },{ .name = "L0_TM_DFT_9",  .addr = A_L0_TM_DFT_9,
10798        .ro = 0xffffff00,
10799    },{ .name = "L0_TM_DFT_10",  .addr = A_L0_TM_DFT_10,
10800        .rsvd = 0xf0,
10801        .ro = 0xfffffff0,
10802    },{ .name = "L0_TM_BG_1",  .addr = A_L0_TM_BG_1,
10803        .ro = 0xffffff00,
10804    },{ .name = "L0_TM_BG_2",  .addr = A_L0_TM_BG_2,
10805        .ro = 0xffffff00,
10806    },{ .name = "L0_TM_BG_3",  .addr = A_L0_TM_BG_3,
10807        .ro = 0xffffff00,
10808    },{ .name = "L0_TM_BG_4",  .addr = A_L0_TM_BG_4,
10809        .ro = 0xffffff00,
10810    },{ .name = "L0_TM_BG_5",  .addr = A_L0_TM_BG_5,
10811        .ro = 0xffffff00,
10812    },{ .name = "L0_TM_BG_6",  .addr = A_L0_TM_BG_6,
10813        .ro = 0xffffff00,
10814    },{ .name = "L0_TM_BG_7",  .addr = A_L0_TM_BG_7,
10815        .ro = 0xffffff00,
10816    },{ .name = "L0_TM_BG_8",  .addr = A_L0_TM_BG_8,
10817        .ro = 0xffffff00,
10818    },{ .name = "L0_TM_BG_9",  .addr = A_L0_TM_BG_9,
10819        .ro = 0xffffff00,
10820    },{ .name = "L0_TM_BG_10",  .addr = A_L0_TM_BG_10,
10821        .ro = 0xffffff00,
10822    },{ .name = "L0_TM_SD0",  .addr = A_L0_TM_SD0,
10823        .ro = 0xffffff00,
10824    },{ .name = "L0_TM_SD1",  .addr = A_L0_TM_SD1,
10825        .ro = 0xffffff00,
10826    },{ .name = "L0_TM_SD2",  .addr = A_L0_TM_SD2,
10827        .ro = 0xffffff00,
10828    },{ .name = "L0_TM_SD3",  .addr = A_L0_TM_SD3,
10829        .reset = 0x4,
10830        .ro = 0xffffff00,
10831    },{ .name = "L0_TM_SD4",  .addr = A_L0_TM_SD4,
10832        .rsvd = 0xe0,
10833        .ro = 0xffffffe0,
10834    },{ .name = "L0_TM_SD5",  .addr = A_L0_TM_SD5,
10835        .reset = 0xa,
10836        .ro = 0xffffff00,
10837    },{ .name = "L0_TM_SD6",  .addr = A_L0_TM_SD6,
10838        .rsvd = 0xe0,
10839        .ro = 0xffffffe0,
10840    },{ .name = "L0_TM_MISC1",  .addr = A_L0_TM_MISC1,
10841        .ro = 0xffffff00,
10842    },{ .name = "L0_TM_MISC2",  .addr = A_L0_TM_MISC2,
10843        .ro = 0xffffff03,
10844    },{ .name = "L0_TM_EYE_SURF0",  .addr = A_L0_TM_EYE_SURF0,
10845        .ro = 0xffffff80,
10846    },{ .name = "L0_TM_EYE_SURF1",  .addr = A_L0_TM_EYE_SURF1,
10847        .ro = 0xffffff00,
10848    },{ .name = "L0_TM_EYE_SURF2",  .addr = A_L0_TM_EYE_SURF2,
10849        .ro = 0xffffff00,
10850    },{ .name = "L0_TM_EYE_SURF3",  .addr = A_L0_TM_EYE_SURF3,
10851        .ro = 0xffffff00,
10852    },{ .name = "L0_TM_EYE_SURF4",  .addr = A_L0_TM_EYE_SURF4,
10853        .ro = 0xffffff00,
10854    },{ .name = "L0_TM_EYE_SURF5",  .addr = A_L0_TM_EYE_SURF5,
10855        .ro = 0xffffff00,
10856    },{ .name = "L0_TM_EYE_SURF6",  .addr = A_L0_TM_EYE_SURF6,
10857        .ro = 0xffffff00,
10858    },{ .name = "L0_TM_EYE_SURF7",  .addr = A_L0_TM_EYE_SURF7,
10859        .ro = 0xffffff00,
10860    },{ .name = "L0_TM_EYE_SURF8",  .addr = A_L0_TM_EYE_SURF8,
10861        .ro = 0xffffff00,
10862    },{ .name = "L0_TM_EYE_SURF9",  .addr = A_L0_TM_EYE_SURF9,
10863        .ro = 0xffffff00,
10864    },{ .name = "L0_TM_SPARE",  .addr = A_L0_TM_SPARE,
10865        .ro = 0xffffff00,
10866    },{ .name = "L0_TM_ANA_EQ1",  .addr = A_L0_TM_ANA_EQ1,
10867        .reset = 0xc,
10868        .ro = 0xffffffe0,
10869    },{ .name = "L0_TM_ANA_E_PI0",  .addr = A_L0_TM_ANA_E_PI0,
10870        .reset = 0xa0,
10871        .ro = 0xffffff1f,
10872    },{ .name = "L0_TM_ANA_IQ_PI0",  .addr = A_L0_TM_ANA_IQ_PI0,
10873        .reset = 0xa0,
10874        .ro = 0xffffff1f,
10875    },{ .name = "L0_TM_ANA_MISC0",  .addr = A_L0_TM_ANA_MISC0,
10876        .ro = 0xffffff3f,
10877    },{ .name = "L0_TM_SAMP_CODE_IQ_PH0",  .addr = A_L0_TM_SAMP_CODE_IQ_PH0,
10878        .ro = 0xffffff80,
10879    },{ .name = "L0_TM_SAMP_CODE_IQ_PH90",  .addr = A_L0_TM_SAMP_CODE_IQ_PH90,
10880        .ro = 0xffffff00,
10881    },{ .name = "L0_TM_SAMP_CODE_IQ_PH180",  .addr = A_L0_TM_SAMP_CODE_IQ_PH180,
10882        .ro = 0xffffffc0,
10883    },{ .name = "L0_TM_SAMP_CODE_IQ_PH270",  .addr = A_L0_TM_SAMP_CODE_IQ_PH270,
10884        .ro = 0xffffff00,
10885    },{ .name = "L0_TM_SAMP_CODE_E_PH0",  .addr = A_L0_TM_SAMP_CODE_E_PH0,
10886        .ro = 0xffffffc0,
10887    },{ .name = "L0_TM_SAMP_CODE_E_PH180",  .addr = A_L0_TM_SAMP_CODE_E_PH180,
10888        .ro = 0xffffffc0,
10889    },{ .name = "L0_TM_IQ_ILL0",  .addr = A_L0_TM_IQ_ILL0,
10890        .ro = 0xffffff00,
10891    },{ .name = "L0_TM_IQ_ILL1",  .addr = A_L0_TM_IQ_ILL1,
10892        .ro = 0xffffff00,
10893    },{ .name = "L0_TM_IQ_ILL2",  .addr = A_L0_TM_IQ_ILL2,
10894        .ro = 0xffffff00,
10895    },{ .name = "L0_TM_IQ_ILL3",  .addr = A_L0_TM_IQ_ILL3,
10896        .ro = 0xffffff00,
10897    },{ .name = "L0_TM_IQ_ILL4",  .addr = A_L0_TM_IQ_ILL4,
10898        .ro = 0xffffff00,
10899    },{ .name = "L0_TM_IQ_ILL5",  .addr = A_L0_TM_IQ_ILL5,
10900        .ro = 0xffffff00,
10901    },{ .name = "L0_TM_IQ_ILL6",  .addr = A_L0_TM_IQ_ILL6,
10902        .ro = 0xffffff00,
10903    },{ .name = "L0_TM_IQ_ILL7",  .addr = A_L0_TM_IQ_ILL7,
10904        .ro = 0xffffff00,
10905    },{ .name = "L0_TM_IQ_ILL8",  .addr = A_L0_TM_IQ_ILL8,
10906        .ro = 0xffffff00,
10907    },{ .name = "L0_TM_IQ_ILL9",  .addr = A_L0_TM_IQ_ILL9,
10908        .ro = 0xfffffff0,
10909    },{ .name = "L0_TM_IQ_ILL10",  .addr = A_L0_TM_IQ_ILL10,
10910        .reset = 0x3,
10911        .ro = 0xffffffc0,
10912    },{ .name = "L0_TM_E_ILL0",  .addr = A_L0_TM_E_ILL0,
10913        .ro = 0xffffff00,
10914    },{ .name = "L0_TM_E_ILL1",  .addr = A_L0_TM_E_ILL1,
10915        .ro = 0xffffff00,
10916    },{ .name = "L0_TM_E_ILL2",  .addr = A_L0_TM_E_ILL2,
10917        .ro = 0xffffff00,
10918    },{ .name = "L0_TM_E_ILL3",  .addr = A_L0_TM_E_ILL3,
10919        .ro = 0xffffff00,
10920    },{ .name = "L0_TM_E_ILL4",  .addr = A_L0_TM_E_ILL4,
10921        .ro = 0xffffff00,
10922    },{ .name = "L0_TM_E_ILL5",  .addr = A_L0_TM_E_ILL5,
10923        .ro = 0xffffff00,
10924    },{ .name = "L0_TM_E_ILL6",  .addr = A_L0_TM_E_ILL6,
10925        .ro = 0xffffff00,
10926    },{ .name = "L0_TM_E_ILL7",  .addr = A_L0_TM_E_ILL7,
10927        .ro = 0xffffff00,
10928    },{ .name = "L0_TM_E_ILL8",  .addr = A_L0_TM_E_ILL8,
10929        .ro = 0xffffff00,
10930    },{ .name = "L0_TM_E_ILL9",  .addr = A_L0_TM_E_ILL9,
10931        .ro = 0xfffffff0,
10932    },{ .name = "L0_TM_E_ILL10",  .addr = A_L0_TM_E_ILL10,
10933        .reset = 0x3,
10934        .ro = 0xffffffc0,
10935    },{ .name = "L0_TM_EQ0",  .addr = A_L0_TM_EQ0,
10936        .ro = 0xffffff00,
10937    },{ .name = "L0_TM_EQ1",  .addr = A_L0_TM_EQ1,
10938        .ro = 0xffffff00,
10939    },{ .name = "L0_TM_EQ2",  .addr = A_L0_TM_EQ2,
10940        .ro = 0xffffff80,
10941    },{ .name = "L0_TM_EQ3",  .addr = A_L0_TM_EQ3,
10942        .ro = 0xffffffe0,
10943    },{ .name = "L0_TM_EQ4",  .addr = A_L0_TM_EQ4,
10944        .ro = 0xffffffe0,
10945    },{ .name = "L0_TM_EQ5",  .addr = A_L0_TM_EQ5,
10946        .ro = 0xffffffc0,
10947    },{ .name = "L0_TM_EQ6",  .addr = A_L0_TM_EQ6,
10948        .ro = 0xffffffe0,
10949    },{ .name = "L0_TM_EQ7",  .addr = A_L0_TM_EQ7,
10950        .ro = 0xffffffc0,
10951    },{ .name = "L0_TM_EQ8",  .addr = A_L0_TM_EQ8,
10952        .ro = 0xffffff00,
10953    },{ .name = "L0_TM_EQ9",  .addr = A_L0_TM_EQ9,
10954        .ro = 0xffffff80,
10955    },{ .name = "L0_TM_EQ10",  .addr = A_L0_TM_EQ10,
10956        .ro = 0xffffff80,
10957    },{ .name = "L0_TM_EQ11",  .addr = A_L0_TM_EQ11,
10958        .ro = 0xffffff00,
10959    },{ .name = "L0_TM_ILL7",  .addr = A_L0_TM_ILL7,
10960        .reset = 0x5,
10961        .ro = 0xffffff00,
10962    },{ .name = "L0_TM_ILL8",  .addr = A_L0_TM_ILL8,
10963        .reset = 0x2,
10964        .ro = 0xffffff00,
10965    },{ .name = "L0_TM_ILL9",  .addr = A_L0_TM_ILL9,
10966        .reset = 0x40,
10967        .ro = 0xffffff00,
10968    },{ .name = "L0_TM_ILL10",  .addr = A_L0_TM_ILL10,
10969        .ro = 0xffffff00,
10970    },{ .name = "L0_TM_ILL11",  .addr = A_L0_TM_ILL11,
10971        .ro = 0xffffff00,
10972    },{ .name = "L0_TM_ILL12",  .addr = A_L0_TM_ILL12,
10973        .ro = 0xffffff00,
10974    },{ .name = "L0_TM_ILL13",  .addr = A_L0_TM_ILL13,
10975        .reset = 0x1,
10976        .rsvd = 0xf8,
10977        .ro = 0xfffffff8,
10978    },{ .name = "L0_TM_ILL14",  .addr = A_L0_TM_ILL14,
10979        .reset = 0x51,
10980        .ro = 0xffffff00,
10981    },{ .name = "L0_TM_FRZ_FSM0",  .addr = A_L0_TM_FRZ_FSM0,
10982        .ro = 0xffffff00,
10983    },{ .name = "L0_TM_FRZ_FSM1",  .addr = A_L0_TM_FRZ_FSM1,
10984        .ro = 0xffffffc0,
10985    },{ .name = "L0_TM_RST_DLY",  .addr = A_L0_TM_RST_DLY,
10986        .ro = 0xffffff00,
10987    },{ .name = "L0_TM_ILL15",  .addr = A_L0_TM_ILL15,
10988        .ro = 0xffffff00,
10989    },{ .name = "L0_TM_MISC3",  .addr = A_L0_TM_MISC3,
10990        .reset = 0x3,
10991        .ro = 0xffffff00,
10992    },{ .name = "L0_TM_EQ_OFFS1",  .addr = A_L0_TM_EQ_OFFS1,
10993        .ro = 0xffffff00,
10994    },{ .name = "L0_TM_SAMP0",  .addr = A_L0_TM_SAMP0,
10995        .ro = 0xffffff00,
10996    },{ .name = "L0_TM_EQ12",  .addr = A_L0_TM_EQ12,
10997        .ro = 0xffffff00,
10998    },{ .name = "L0_TM_MISC4",  .addr = A_L0_TM_MISC4,
10999        .rsvd = 0xf8,
11000        .ro = 0xfffffff8,

11001    },{ .name = "L0_TM_SAMP_STATUS0",  .addr = A_L0_TM_SAMP_STATUS0,
11002        .rsvd = 0xc0,
11003        .ro = 0xffffffff,
11004    },{ .name = "L0_TM_SAMP_STATUS1",  .addr = A_L0_TM_SAMP_STATUS1,
11005        .rsvd = 0xc0,
11006        .ro = 0xffffffff,
11007    },{ .name = "L0_TM_SAMP_STATUS2",  .addr = A_L0_TM_SAMP_STATUS2,
11008        .rsvd = 0xc0,
11009        .ro = 0xffffffff,
11010    },{ .name = "L0_TM_SAMP_STATUS3",  .addr = A_L0_TM_SAMP_STATUS3,
11011        .rsvd = 0xc0,
11012        .ro = 0xffffffff,
11013    },{ .name = "L0_TM_SAMP_STATUS4",  .addr = A_L0_TM_SAMP_STATUS4,
11014        .rsvd = 0xc0,
11015        .ro = 0xffffffff,
11016    },{ .name = "L0_TM_SAMP_STATUS5",  .addr = A_L0_TM_SAMP_STATUS5,
11017        .rsvd = 0xc0,
11018        .ro = 0xffffffff,
11019    },{ .name = "L0_TM_ILL_STATUS0",  .addr = A_L0_TM_ILL_STATUS0,
11020        .rsvd = 0x80,
11021        .ro = 0xffffffff,
11022    },{ .name = "L0_TM_ILL_STATUS1",  .addr = A_L0_TM_ILL_STATUS1,
11023        .rsvd = 0x80,
11024        .ro = 0xffffffff,
11025    },{ .name = "L0_TM_ILL_STATUS2",  .addr = A_L0_TM_ILL_STATUS2,
11026        .rsvd = 0x80,
11027        .ro = 0xffffffff,
11028    },{ .name = "L0_TM_ILL_STATUS3",  .addr = A_L0_TM_ILL_STATUS3,
11029        .rsvd = 0x80,
11030        .ro = 0xffffffff,
11031    },{ .name = "L0_TM_ILL_STATUS4",  .addr = A_L0_TM_ILL_STATUS4,
11032        .rsvd = 0x80,
11033        .ro = 0xffffffff,
11034    },{ .name = "L0_TM_ILL_STATUS5",  .addr = A_L0_TM_ILL_STATUS5,
11035        .rsvd = 0x80,
11036        .ro = 0xffffffff,
11037    },{ .name = "L0_TM_ILL_STATUS6",  .addr = A_L0_TM_ILL_STATUS6,
11038        .rsvd = 0x80,
11039        .ro = 0xffffffff,
11040    },{ .name = "L0_TM_ILL_STATUS7",  .addr = A_L0_TM_ILL_STATUS7,
11041        .rsvd = 0x80,
11042        .ro = 0xffffffff,
11043    },{ .name = "L0_TM_ILL_STATUS8",  .addr = A_L0_TM_ILL_STATUS8,
11044        .rsvd = 0x80,
11045        .ro = 0xffffffff,
11046    },{ .name = "L0_TM_ILL_STATUS9",  .addr = A_L0_TM_ILL_STATUS9,
11047        .rsvd = 0x80,
11048        .ro = 0xffffffff,
11049    },{ .name = "L0_TM_ILL_STATUS10",  .addr = A_L0_TM_ILL_STATUS10,
11050        .rsvd = 0x80,
11051        .ro = 0xffffffff,
11052    },{ .name = "L0_TM_ILL_STATUS11",  .addr = A_L0_TM_ILL_STATUS11,
11053        .rsvd = 0x80,
11054        .ro = 0xffffffff,
11055    },{ .name = "L0_TM_MISC_ST_0",  .addr = A_L0_TM_MISC_ST_0,
11056        .rsvd = 0xc0,
11057        .ro = 0xffffffff,
11058    },{ .name = "L0_TM_SD_ST_0",  .addr = A_L0_TM_SD_ST_0,
11059        .reset = 0x12,
11060        .rsvd = 0xc0,
11061        .ro = 0xffffffff,
11062    },{ .name = "L0_TM_EYESURF_ST0",  .addr = A_L0_TM_EYESURF_ST0,
11063        .ro = 0xffffffff,
11064    },{ .name = "L0_TM_EYESURF_ST1",  .addr = A_L0_TM_EYESURF_ST1,
11065        .ro = 0xffffffff,
11066    },{ .name = "L0_TM_EQ_ST0",  .addr = A_L0_TM_EQ_ST0,
11067        .reset = 0xff,
11068        .ro = 0xffffffff,
11069    },{ .name = "L0_TM_EQ_ST1",  .addr = A_L0_TM_EQ_ST1,
11070        .ro = 0xffffffff,
11071    },{ .name = "L0_TM_EQ_ST2",  .addr = A_L0_TM_EQ_ST2,
11072        .rsvd = 0x80,
11073        .ro = 0xffffffff,
11074    },{ .name = "L0_TM_RXPMA_ST1",  .addr = A_L0_TM_RXPMA_ST1,
11075        .ro = 0xffffffff,
11076    },{ .name = "L0_TM_CDR0",  .addr = A_L0_TM_CDR0,
11077        .ro = 0xffffff60,
11078    },{ .name = "L0_TM_CDR1",  .addr = A_L0_TM_CDR1,
11079        .ro = 0xffffff00,
11080    },{ .name = "L0_TM_CDR2",  .addr = A_L0_TM_CDR2,
11081        .ro = 0xffffff00,
11082    },{ .name = "L0_TM_CDR3",  .addr = A_L0_TM_CDR3,
11083        .ro = 0xffffff80,
11084    },{ .name = "L0_TM_CDR4",  .addr = A_L0_TM_CDR4,
11085        .ro = 0xffffff80,
11086    },{ .name = "L0_TM_CDR5",  .addr = A_L0_TM_CDR5,
11087        .ro = 0xffffff00,
11088    },{ .name = "L0_TM_CDR6",  .addr = A_L0_TM_CDR6,
11089        .ro = 0xffffff00,
11090    },{ .name = "L0_TM_CDR7",  .addr = A_L0_TM_CDR7,
11091        .ro = 0xffffff00,
11092    },{ .name = "L0_TM_CDR8",  .addr = A_L0_TM_CDR8,
11093        .ro = 0xffffff00,
11094    },{ .name = "L0_TM_CDR9",  .addr = A_L0_TM_CDR9,
11095        .ro = 0xffffff00,
11096    },{ .name = "L0_TM_CDR10",  .addr = A_L0_TM_CDR10,
11097        .ro = 0xffffff00,
11098    },{ .name = "L0_TM_CDR11",  .addr = A_L0_TM_CDR11,
11099        .ro = 0xffffffe0,
11100    },{ .name = "L0_TM_CDR12",  .addr = A_L0_TM_CDR12,
11101        .ro = 0xffffff00,
11102    },{ .name = "L0_TM_CDR13",  .addr = A_L0_TM_CDR13,
11103        .ro = 0xffffff00,
11104    },{ .name = "L0_TM_CDR14",  .addr = A_L0_TM_CDR14,
11105        .ro = 0xffffff00,
11106    },{ .name = "L0_TM_CDR15",  .addr = A_L0_TM_CDR15,
11107        .ro = 0xffffff00,
11108    },{ .name = "L0_TM_CDR16",  .addr = A_L0_TM_CDR16,
11109        .ro = 0xffffffe0,
11110    },{ .name = "L0_TM_CDR17",  .addr = A_L0_TM_CDR17,
11111        .ro = 0xffffffe0,
11112    },{ .name = "L0_TM_CDR18",  .addr = A_L0_TM_CDR18,
11113        .ro = 0xffffffe0,
11114    },{ .name = "L0_TM_CDR19",  .addr = A_L0_TM_CDR19,
11115        .ro = 0xffffffe0,
11116    },{ .name = "L0_TM_CDR20",  .addr = A_L0_TM_CDR20,
11117        .ro = 0xffffffe0,
11118    },{ .name = "L0_TM_CDR21",  .addr = A_L0_TM_CDR21,
11119        .ro = 0xffffffe0,
11120    },{ .name = "L0_TM_CDR22",  .addr = A_L0_TM_CDR22,
11121        .ro = 0xffffffe0,
11122    },{ .name = "L0_TM_CDR23",  .addr = A_L0_TM_CDR23,
11123        .ro = 0xffffff80,
11124    },{ .name = "L0_TM_MISC0",  .addr = A_L0_TM_MISC0,
11125        .ro = 0xfffffffc,
11126    },{ .name = "L0_TM_HSRX_ST0",  .addr = A_L0_TM_HSRX_ST0,
11127        .rsvd = 0xfe,
11128        .ro = 0xffffffff,
11129    },{ .name = "L0_TM_PLL_LS_CLOCK",  .addr = A_L0_TM_PLL_LS_CLOCK,
11130        .ro = 0xffffff00,
11131    },{ .name = "L0_TM_PLL_LOOP_FILT",  .addr = A_L0_TM_PLL_LOOP_FILT,
11132        .ro = 0xffffff00,
11133    },{ .name = "L0_TM_PLL_DIG2",  .addr = A_L0_TM_PLL_DIG2,
11134        .ro = 0xffffff00,
11135    },{ .name = "L0_TM_PLL_FBDIV",  .addr = A_L0_TM_PLL_FBDIV,
11136        .ro = 0xffffff00,
11137    },{ .name = "L0_TM_PLL_DIG4",  .addr = A_L0_TM_PLL_DIG4,
11138        .reset = 0x80,
11139        .ro = 0xffffff00,
11140    },{ .name = "L0_TM_PLL_DIG5",  .addr = A_L0_TM_PLL_DIG5,
11141        .reset = 0xc0,
11142        .ro = 0xffffff00,
11143    },{ .name = "L0_TM_PLL_DIG6",  .addr = A_L0_TM_PLL_DIG6,
11144        .reset = 0x3,
11145        .ro = 0xffffff00,
11146    },{ .name = "L0_TM_PLL_DIG7",  .addr = A_L0_TM_PLL_DIG7,
11147        .ro = 0xffffff00,
11148    },{ .name = "L0_TM_PLL_CPUMP_CODE_1",  .addr = A_L0_TM_PLL_CPUMP_CODE_1,
11149        .ro = 0xffffff00,
11150    },{ .name = "L0_TM_PLL_DIG9",  .addr = A_L0_TM_PLL_DIG9,
11151        .ro = 0xffffffc0,
11152    },{ .name = "L0_TM_PLL_COARSE_CODE_LSB",  .addr = A_L0_TM_PLL_COARSE_CODE_LSB,
11153        .ro = 0xffffff00,
11154    },{ .name = "L0_TM_PLL_DIG11",  .addr = A_L0_TM_PLL_DIG11,
11155        .ro = 0xffffff00,
11156    },{ .name = "L0_TM_PLL_DIG12",  .addr = A_L0_TM_PLL_DIG12,
11157        .ro = 0xffffff00,
11158    },{ .name = "L0_TM_PLL_CONST_PMOS",  .addr = A_L0_TM_PLL_CONST_PMOS,
11159        .ro = 0xffffff00,
11160    },{ .name = "L0_TM_PLL_DIG14",  .addr = A_L0_TM_PLL_DIG14,
11161        .ro = 0xffffff00,
11162    },{ .name = "L0_TM_PLL_DIG15",  .addr = A_L0_TM_PLL_DIG15,
11163        .ro = 0xffffff00,
11164    },{ .name = "L0_TM_PLL_DIG16",  .addr = A_L0_TM_PLL_DIG16,
11165        .ro = 0xffffff10,
11166    },{ .name = "L0_TM_PLL_DIG17",  .addr = A_L0_TM_PLL_DIG17,
11167        .ro = 0xffffff00,
11168    },{ .name = "L0_TM_PLL_DIG18",  .addr = A_L0_TM_PLL_DIG18,
11169        .ro = 0xffffff00,
11170    },{ .name = "L0_TM_PLL_DIG19",  .addr = A_L0_TM_PLL_DIG19,
11171        .ro = 0xffffff00,
11172    },{ .name = "L0_TM_PLL_DIG20",  .addr = A_L0_TM_PLL_DIG20,
11173        .ro = 0xffffff40,
11174    },{ .name = "L0_TM_PLL_DIG21",  .addr = A_L0_TM_PLL_DIG21,
11175        .reset = 0x20,
11176        .ro = 0xffffff0c,
11177    },{ .name = "L0_TM_PLL_DIG22",  .addr = A_L0_TM_PLL_DIG22,
11178        .ro = 0xffffff80,
11179    },{ .name = "L0_TM_PLL_DIG23",  .addr = A_L0_TM_PLL_DIG23,
11180        .reset = 0x31,
11181        .ro = 0xffffff00,
11182    },{ .name = "L0_TM_PLL_DIG24",  .addr = A_L0_TM_PLL_DIG24,
11183        .ro = 0xffffff80,
11184    },{ .name = "L0_TM_PLL_DIG25",  .addr = A_L0_TM_PLL_DIG25,
11185        .ro = 0xffffff00,
11186    },{ .name = "L0_TM_PLL_DIG26",  .addr = A_L0_TM_PLL_DIG26,
11187        .reset = 0x40,
11188        .ro = 0xffffff80,
11189    },{ .name = "L0_TM_PLL_CLK_DIST_NTRIM_LSB",  .addr = A_L0_TM_PLL_CLK_DIST_NTRIM_LSB,
11190        .ro = 0xffffff00,
11191    },{ .name = "L0_TM_PLL_CLK_DIST_PTRIM_LSB",  .addr = A_L0_TM_PLL_CLK_DIST_PTRIM_LSB,
11192        .ro = 0xffffff00,
11193    },{ .name = "L0_TM_PLL_DIG_29",  .addr = A_L0_TM_PLL_DIG_29,
11194        .ro = 0xffffff00,
11195    },{ .name = "L0_TM_PLL_DIG_30",  .addr = A_L0_TM_PLL_DIG_30,
11196        .ro = 0xffffff00,
11197    },{ .name = "L0_TM_PLL_DIG_31",  .addr = A_L0_TM_PLL_DIG_31,
11198        .ro = 0xffffff00,
11199    },{ .name = "L0_TM_PLL_DIG_32",  .addr = A_L0_TM_PLL_DIG_32,
11200        .ro = 0xffffff00,
11201    },{ .name = "L0_TM_PLL_DIG_33",  .addr = A_L0_TM_PLL_DIG_33,
11202        .ro = 0xffffff00,
11203    },{ .name = "L0_TM_PLL_DIG_34",  .addr = A_L0_TM_PLL_DIG_34,
11204        .ro = 0xffffff80,
11205    },{ .name = "L0_TM_PLL_DIG_35",  .addr = A_L0_TM_PLL_DIG_35,
11206        .ro = 0xffffff00,
11207    },{ .name = "L0_TM_PLL_DIG_36",  .addr = A_L0_TM_PLL_DIG_36,
11208        .ro = 0xffffff00,
11209    },{ .name = "L0_TM_PLL_DIG_37",  .addr = A_L0_TM_PLL_DIG_37,
11210        .ro = 0xffffff00,
11211    },{ .name = "L0_TM_PLL_COARSE_CODE_SAT_MSB",  .addr = A_L0_TM_PLL_COARSE_CODE_SAT_MSB,
11212        .ro = 0xffffff00,
11213    },{ .name = "L0_MPHY_CFG_HIB8",  .addr = A_L0_MPHY_CFG_HIB8,
11214        .ro = 0xfffffffe,
11215    },{ .name = "L0_MPHY_CFG_MODE",  .addr = A_L0_MPHY_CFG_MODE,
11216        .ro = 0xfffffffc,
11217    },{ .name = "L0_MPHY_CFG_HS_GEAR",  .addr = A_L0_MPHY_CFG_HS_GEAR,
11218        .ro = 0xfffffffc,
11219    },{ .name = "L0_MPHY_CFG_HS_RATE",  .addr = A_L0_MPHY_CFG_HS_RATE,
11220        .ro = 0xfffffffe,
11221    },{ .name = "L0_MPHY_CFG_PWM",  .addr = A_L0_MPHY_CFG_PWM,
11222        .ro = 0xfffffff8,
11223    },{ .name = "L0_PLL_OPDIV_LS",  .addr = A_L0_PLL_OPDIV_LS,
11224        .ro = 0xffffff00,
11225    },{ .name = "L0_MPHY_CFG_UPDT",  .addr = A_L0_MPHY_CFG_UPDT,
11226        .ro = 0xfffffffe,
11227    },{ .name = "L0_PLL_TM_DIV_CNTRLS",  .addr = A_L0_PLL_TM_DIV_CNTRLS,
11228        .reset = 0x40,
11229        .ro = 0xffffff20,
11230    },{ .name = "L0_PLL_FBDIV_G1A_LSB",  .addr = A_L0_PLL_FBDIV_G1A_LSB,
11231        .ro = 0xffffff00,
11232    },{ .name = "L0_PLL_FBDIV_G1B_LSB",  .addr = A_L0_PLL_FBDIV_G1B_LSB,
11233        .ro = 0xffffff00,
11234    },{ .name = "L0_PLL_FBDIV_G2A_LSB",  .addr = A_L0_PLL_FBDIV_G2A_LSB,
11235        .ro = 0xffffff00,
11236    },{ .name = "L0_PLL_FBDIV_G2B_LSB",  .addr = A_L0_PLL_FBDIV_G2B_LSB,
11237        .ro = 0xffffff00,
11238    },{ .name = "L0_PLL_FBDIV_G3A_LSB",  .addr = A_L0_PLL_FBDIV_G3A_LSB,
11239        .ro = 0xffffff00,
11240    },{ .name = "L0_PLL_FBDIV_G3B_LSB",  .addr = A_L0_PLL_FBDIV_G3B_LSB,
11241        .ro = 0xffffff00,
11242    },{ .name = "L0_PLL_FBDIV_G1A_MSB",  .addr = A_L0_PLL_FBDIV_G1A_MSB,
11243        .ro = 0xffffff00,
11244    },{ .name = "L0_PLL_FBDIV_G1B_MSB",  .addr = A_L0_PLL_FBDIV_G1B_MSB,
11245        .ro = 0xffffff00,
11246    },{ .name = "L0_PLL_FBDIV_G2A_MSB",  .addr = A_L0_PLL_FBDIV_G2A_MSB,
11247        .ro = 0xffffff00,
11248    },{ .name = "L0_PLL_FBDIV_G2B_MSB",  .addr = A_L0_PLL_FBDIV_G2B_MSB,
11249        .ro = 0xffffff00,
11250    },{ .name = "L0_PLL_FBDIV_G3A_MSB",  .addr = A_L0_PLL_FBDIV_G3A_MSB,
11251        .ro = 0xffffff00,
11252    },{ .name = "L0_PLL_FBDIV_G3B_MSB",  .addr = A_L0_PLL_FBDIV_G3B_MSB,
11253        .ro = 0xffffff00,
11254    },{ .name = "L0_PLL_IPDIV",  .addr = A_L0_PLL_IPDIV,
11255        .ro = 0xffffff00,
11256    },{ .name = "L0_PLL_FBDIV_FRAC_0_LSB",  .addr = A_L0_PLL_FBDIV_FRAC_0_LSB,
11257        .ro = 0xffffff00,
11258    },{ .name = "L0_PLL_FBDIV_FRAC_1",  .addr = A_L0_PLL_FBDIV_FRAC_1,
11259        .ro = 0xffffff00,
11260    },{ .name = "L0_PLL_FBDIV_FRAC_2",  .addr = A_L0_PLL_FBDIV_FRAC_2,
11261        .ro = 0xffffff00,
11262    },{ .name = "L0_PLL_FBDIV_FRAC_3_MSB",  .addr = A_L0_PLL_FBDIV_FRAC_3_MSB,
11263        .ro = 0xffffff98,
11264    },{ .name = "L0_PLL_PWR_SEQ_WAIT_TIME",  .addr = A_L0_PLL_PWR_SEQ_WAIT_TIME,
11265        .ro = 0xffffff00,
11266    },{ .name = "L0_PLL_SS_STEPS_0_LSB",  .addr = A_L0_PLL_SS_STEPS_0_LSB,
11267        .ro = 0xffffff00,
11268    },{ .name = "L0_PLL_SS_STEPS_1_MSB",  .addr = A_L0_PLL_SS_STEPS_1_MSB,
11269        .ro = 0xfffffff8,
11270    },{ .name = "L0_PLL_SS_STEP_SIZE_0_LSB",  .addr = A_L0_PLL_SS_STEP_SIZE_0_LSB,
11271        .ro = 0xffffff00,
11272    },{ .name = "L0_PLL_SS_STEP_SIZE_1",  .addr = A_L0_PLL_SS_STEP_SIZE_1,
11273        .ro = 0xffffff00,
11274    },{ .name = "L0_PLL_SS_STEP_SIZE_2",  .addr = A_L0_PLL_SS_STEP_SIZE_2,
11275        .ro = 0xffffff00,
11276    },{ .name = "L0_PLL_SS_STEP_SIZE_3_MSB",  .addr = A_L0_PLL_SS_STEP_SIZE_3_MSB,
11277        .ro = 0xffffff00,
11278    },{ .name = "L0_TM_MASK_CFG_UPDT",  .addr = A_L0_TM_MASK_CFG_UPDT,
11279        .ro = 0xffffff80,
11280    },{ .name = "L0_PLL_TM_FORCE_DIV",  .addr = A_L0_PLL_TM_FORCE_DIV,
11281        .ro = 0xffffff00,
11282    },{ .name = "L0_PLL_TM_COARSE_CODE_1_LSB",  .addr = A_L0_PLL_TM_COARSE_CODE_1_LSB,
11283        .ro = 0xffffff00,
11284    },{ .name = "L0_PLL_TM_COARSE_CODE_2_LSB",  .addr = A_L0_PLL_TM_COARSE_CODE_2_LSB,
11285        .ro = 0xffffff00,
11286    },{ .name = "L0_PLL_TM_COARSE_CODE_3_LSB",  .addr = A_L0_PLL_TM_COARSE_CODE_3_LSB,
11287        .ro = 0xffffff00,
11288    },{ .name = "L0_PLL_TM_COARSE_CODE_4_LSB",  .addr = A_L0_PLL_TM_COARSE_CODE_4_LSB,
11289        .ro = 0xffffff00,
11290    },{ .name = "L0_PLL_TM_COARSE_CODE_5_LSB",  .addr = A_L0_PLL_TM_COARSE_CODE_5_LSB,
11291        .ro = 0xffffff00,
11292    },{ .name = "L0_PLL_TM_COARSE_CODE_6_LSB",  .addr = A_L0_PLL_TM_COARSE_CODE_6_LSB,
11293        .ro = 0xffffff00,
11294    },{ .name = "L0_PLL_TM_COARSE_CODE_1_2_MSB",  .addr = A_L0_PLL_TM_COARSE_CODE_1_2_MSB,
11295        .ro = 0xffffffc0,
11296    },{ .name = "L0_PLL_TM_COARSE_CODE_3_4_MSB",  .addr = A_L0_PLL_TM_COARSE_CODE_3_4_MSB,
11297        .ro = 0xffffffc0,
11298    },{ .name = "L0_PLL_TM_COARSE_CODE_5_6_MSB",  .addr = A_L0_PLL_TM_COARSE_CODE_5_6_MSB,
11299        .ro = 0xffffffc0,
11300    },{ .name = "L0_PLL_TM_SHARED_0",  .addr = A_L0_PLL_TM_SHARED_0,
11301        .ro = 0xffffff00,
11302    },{ .name = "L0_PLL_TM_FRAC_OFFSET_0",  .addr = A_L0_PLL_TM_FRAC_OFFSET_0,
11303        .ro = 0xffffff00,
11304    },{ .name = "L0_PLL_TM_FRAC_OFFSET_1",  .addr = A_L0_PLL_TM_FRAC_OFFSET_1,
11305        .ro = 0xffffff00,
11306    },{ .name = "L0_PLL_TM_FRAC_OFFSET_2",  .addr = A_L0_PLL_TM_FRAC_OFFSET_2,
11307        .ro = 0xfffffffc,
11308    },{ .name = "L0_PLL_STATUS_READ_0",  .addr = A_L0_PLL_STATUS_READ_0,
11309        .ro = 0xffffffff,
11310    },{ .name = "L0_PLL_STATUS_READ_1",  .addr = A_L0_PLL_STATUS_READ_1,
11311        .reset = 0x1 | R_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK,
11312        .ro = 0xffffffff,
11313    },{ .name = "L0_TM_BG_PROG0",  .addr = A_L0_TM_BG_PROG0,
11314        .ro = 0xffffff80,
11315    },{ .name = "L0_TM_BG_PROG1",  .addr = A_L0_TM_BG_PROG1,
11316        .ro = 0xffffff00,
11317    },{ .name = "L0_TM_ANA_BG_TESTBIT0",  .addr = A_L0_TM_ANA_BG_TESTBIT0,
11318        .ro = 0xffffff00,
11319    },{ .name = "L0_TM_ANA_BG_TESTBIT1",  .addr = A_L0_TM_ANA_BG_TESTBIT1,
11320        .ro = 0xffffff00,
11321    },{ .name = "L0_TM_ANA_BG_TESTBIT2",  .addr = A_L0_TM_ANA_BG_TESTBIT2,
11322        .ro = 0xffffff00,
11323    },{ .name = "L0_TM_ANA_BG_TESTBIT3",  .addr = A_L0_TM_ANA_BG_TESTBIT3,
11324        .ro = 0xffffff00,
11325    },{ .name = "L0_TM_ANA_BG_TESTBIT4",  .addr = A_L0_TM_ANA_BG_TESTBIT4,
11326        .ro = 0xffffff00,
11327    },{ .name = "L0_TM_ANA_BG_TESTBIT5",  .addr = A_L0_TM_ANA_BG_TESTBIT5,
11328        .ro = 0xffffff00,
11329    },{ .name = "L0_TM_ANA_BG_TESTBIT6",  .addr = A_L0_TM_ANA_BG_TESTBIT6,
11330        .ro = 0xffffff00,
11331    },{ .name = "L0_TM_ANA_BG_TESTBIT7",  .addr = A_L0_TM_ANA_BG_TESTBIT7,
11332        .ro = 0xffffff00,
11333    },{ .name = "L0_TM_ANA_BG_TESTBIT8",  .addr = A_L0_TM_ANA_BG_TESTBIT8,
11334        .ro = 0xffffff00,
11335    },{ .name = "L0_TM_ANA_BG_TESTBIT9",  .addr = A_L0_TM_ANA_BG_TESTBIT9,
11336        .ro = 0xffffff00,
11337    },{ .name = "L0_TM_ANA_BG_TESTBIT10",  .addr = A_L0_TM_ANA_BG_TESTBIT10,
11338        .ro = 0xffffff00,
11339    },{ .name = "L0_TM_ANA_BG_TESTBIT11",  .addr = A_L0_TM_ANA_BG_TESTBIT11,
11340        .ro = 0xffffff00,
11341    },{ .name = "L0_TM_ANA_BG_TESTBIT12",  .addr = A_L0_TM_ANA_BG_TESTBIT12,
11342        .ro = 0xffffff00,
11343    },{ .name = "L0_TM_ANA_BG_TESTBIT13",  .addr = A_L0_TM_ANA_BG_TESTBIT13,
11344        .ro = 0xffffff00,
11345    },{ .name = "L0_TM_ANA_BG_TESTBIT14",  .addr = A_L0_TM_ANA_BG_TESTBIT14,
11346        .ro = 0xffffff00,
11347    },{ .name = "L0_TM_ANA_BG_TESTBIT15",  .addr = A_L0_TM_ANA_BG_TESTBIT15,
11348        .ro = 0xffffff00,
11349    },{ .name = "L0_TM_ANA_BG_TESTBIT16",  .addr = A_L0_TM_ANA_BG_TESTBIT16,
11350        .ro = 0xffffff00,
11351    },{ .name = "L0_TM_ANA_BG_TESTBIT17",  .addr = A_L0_TM_ANA_BG_TESTBIT17,
11352        .ro = 0xffffff00,
11353    },{ .name = "L0_TM_ANA_BG_TESTBIT18",  .addr = A_L0_TM_ANA_BG_TESTBIT18,
11354        .ro = 0xffffff00,
11355    },{ .name = "L0_TM_ANA_BG_TESTBIT19",  .addr = A_L0_TM_ANA_BG_TESTBIT19,
11356        .ro = 0xffffff00,
11357    },{ .name = "L0_TM_ANA_BG_TESTBIT20",  .addr = A_L0_TM_ANA_BG_TESTBIT20,
11358        .ro = 0xfffffffc,
11359    },{ .name = "L0_TM_BG_PROG2",  .addr = A_L0_TM_BG_PROG2,
11360        .ro = 0xffffffc0,
11361    },{ .name = "L0_L0_REF_CLK_SEL",  .addr = A_L0_L0_REF_CLK_SEL,
11362        .reset = 0x80,
11363        .ro = 0xffffff60,
11364    },{ .name = "L0_L1_REF_CLK_SEL",  .addr = A_L0_L1_REF_CLK_SEL,
11365        .reset = 0x80,
11366        .ro = 0xffffff60,
11367    },{ .name = "L0_L2_REF_CLK_SEL",  .addr = A_L0_L2_REF_CLK_SEL,
11368        .reset = 0x80,
11369        .ro = 0xffffff60,
11370    },{ .name = "L0_L3_REF_CLK_SEL",  .addr = A_L0_L3_REF_CLK_SEL,
11371        .reset = 0x80,
11372        .ro = 0xffffff60,
11373    },{ .name = "L0_L0_REF_CLK_PULLDN",  .addr = A_L0_L0_REF_CLK_PULLDN,
11374        .ro = 0xfffffff0,
11375    },{ .name = "L0_L1_REF_CLK_PULLDN",  .addr = A_L0_L1_REF_CLK_PULLDN,
11376        .ro = 0xfffffff0,
11377    },{ .name = "L0_L2_REF_CLK_PULLDN",  .addr = A_L0_L2_REF_CLK_PULLDN,
11378        .ro = 0xfffffff0,
11379    },{ .name = "L0_L3_REF_CLK_PULLDN",  .addr = A_L0_L3_REF_CLK_PULLDN,
11380        .ro = 0xfffffff0,
11381    },{ .name = "L0_TM_PG_CTRL0",  .addr = A_L0_TM_PG_CTRL0,
11382        .ro = 0xffffff00,
11383    },{ .name = "L0_TM_PG_CTRL1",  .addr = A_L0_TM_PG_CTRL1,
11384        .ro = 0xffffffc0,
11385    },{ .name = "L0_TM_SLICER0_CTRL",  .addr = A_L0_TM_SLICER0_CTRL,
11386        .ro = 0xffffff80,
11387    },{ .name = "L0_TM_SLICER01_BIAS_PROG0",  .addr = A_L0_TM_SLICER01_BIAS_PROG0,
11388        .ro = 0xffffff00,
11389    },{ .name = "L0_TM_SLICER01_BIAS_PROG1",  .addr = A_L0_TM_SLICER01_BIAS_PROG1,
11390        .ro = 0xfffffff0,
11391    },{ .name = "L0_TM_SLICER1_CTRL",  .addr = A_L0_TM_SLICER1_CTRL,
11392        .ro = 0xffffff81,
11393    },{ .name = "L0_TM_BG_IPTAT_PROG",  .addr = A_L0_TM_BG_IPTAT_PROG,
11394        .ro = 0xffffff00,
11395    },{ .name = "L0_TM_PG_MUX_SEL",  .addr = A_L0_TM_PG_MUX_SEL,
11396        .ro = 0xffffffe0,
11397    },{ .name = "L0_BG_SLICER_SPARE",  .addr = A_L0_BG_SLICER_SPARE,
11398        .ro = 0xffffffc0,
11399    },{ .name = "L0_TM_1US_COUNT",  .addr = A_L0_TM_1US_COUNT,
11400        .reset = 0x28,
11401        .ro = 0xffffff00,
11402    },{ .name = "L0_TM_BG_SETTLING_TIME",  .addr = A_L0_TM_BG_SETTLING_TIME,
11403        .ro = 0xfffffff8,
11404    },{ .name = "L0_SLICER0_ENABLE",  .addr = A_L0_SLICER0_ENABLE,
11405        .reset = 0x80,
11406        .ro = 0xffffff00,
11407    },{ .name = "L0_SLICER1_ENABLE",  .addr = A_L0_SLICER1_ENABLE,
11408        .ro = 0xffffff00,
11409    },{ .name = "L0_SLICER0_BYPASS",  .addr = A_L0_SLICER0_BYPASS,
11410        .ro = 0xffffff98,
11411    },{ .name = "L0_SLICER1_BYPASS",  .addr = A_L0_SLICER1_BYPASS,
11412        .ro = 0xffffff18,
11413    },{ .name = "L0_BG_POWER_GOOD_STATUS",  .addr = A_L0_BG_POWER_GOOD_STATUS,
11414        .ro = 0xffffffff,
11415    },{ .name = "L0_SUPPLY_POWER_GOOD_STATUS",  .addr = A_L0_SUPPLY_POWER_GOOD_STATUS,
11416        .ro = 0xffffffff,
11417        .reset = 0x000000ff,
11418    },{ .name = "L0_BG_ISO_CTRL",  .addr = A_L0_BG_ISO_CTRL,
11419        .ro = 0xfffffffc,
11420    },{ .name = "L0_UPHY_GLOBAL_CTRL",  .addr = A_L0_UPHY_GLOBAL_CTRL,
11421        .ro = 0xffffffe0,
11422    },{ .name = "L0_BIST_CTRL_1",  .addr = A_L0_BIST_CTRL_1,
11423        .ro = 0xffffff00,
11424    },{ .name = "L0_BIST_CTRL_2",  .addr = A_L0_BIST_CTRL_2,
11425        .ro = 0xfffffff8,
11426    },{ .name = "L0_BIST_RUN_LEN_L",  .addr = A_L0_BIST_RUN_LEN_L,
11427        .ro = 0xffffff00,
11428    },{ .name = "L0_BIST_ERR_INJ_POINT_L",  .addr = A_L0_BIST_ERR_INJ_POINT_L,
11429        .ro = 0xffffff00,
11430    },{ .name = "L0_BIST_RUNLEN_ERR_INJ_H",  .addr = A_L0_BIST_RUNLEN_ERR_INJ_H,
11431        .ro = 0xffffff00,
11432    },{ .name = "L0_BIST_IDLE_TIME",  .addr = A_L0_BIST_IDLE_TIME,
11433        .ro = 0xffffff00,
11434    },{ .name = "L0_BIST_MARKER_L",  .addr = A_L0_BIST_MARKER_L,
11435        .ro = 0xffffff00,
11436    },{ .name = "L0_BIST_IDLE_CHAR_L",  .addr = A_L0_BIST_IDLE_CHAR_L,
11437        .ro = 0xffffff00,
11438    },{ .name = "L0_BIST_MARKER_IDLE_H",  .addr = A_L0_BIST_MARKER_IDLE_H,
11439        .ro = 0xffffffcc,
11440    },{ .name = "L0_BIST_LOW_PULSE_TIME",  .addr = A_L0_BIST_LOW_PULSE_TIME,
11441        .ro = 0xffffff00,
11442    },{ .name = "L0_BIST_TOTAL_PULSE_TIME",  .addr = A_L0_BIST_TOTAL_PULSE_TIME,
11443        .ro = 0xffffff00,
11444    },{ .name = "L0_BIST_TEST_PAT_1",  .addr = A_L0_BIST_TEST_PAT_1,
11445        .ro = 0xffffff00,
11446    },{ .name = "L0_BIST_TEST_PAT_2",  .addr = A_L0_BIST_TEST_PAT_2,
11447        .ro = 0xffffff00,
11448    },{ .name = "L0_BIST_TEST_PAT_3",  .addr = A_L0_BIST_TEST_PAT_3,
11449        .ro = 0xffffff00,
11450    },{ .name = "L0_BIST_TEST_PAT_4",  .addr = A_L0_BIST_TEST_PAT_4,
11451        .ro = 0xffffff00,
11452    },{ .name = "L0_BIST_TEST_PAT_MSBS",  .addr = A_L0_BIST_TEST_PAT_MSBS,
11453        .ro = 0xffffff00,
11454    },{ .name = "L0_BIST_PKT_NUM",  .addr = A_L0_BIST_PKT_NUM,
11455        .ro = 0xffffff00,
11456    },{ .name = "L0_BIST_FRM_IDLE_TIME",  .addr = A_L0_BIST_FRM_IDLE_TIME,
11457        .ro = 0xffffff00,
11458    },{ .name = "L0_BIST_PKT_CTR_L",  .addr = A_L0_BIST_PKT_CTR_L,
11459        .ro = 0xffffffff,
11460    },{ .name = "L0_BIST_PKT_CTR_H",  .addr = A_L0_BIST_PKT_CTR_H,
11461        .ro = 0xffffffff,
11462    },{ .name = "L0_BIST_ERR_CTR_L",  .addr = A_L0_BIST_ERR_CTR_L,
11463        .ro = 0xffffffff,
11464    },{ .name = "L0_BIST_ERR_CTR_H",  .addr = A_L0_BIST_ERR_CTR_H,
11465        .ro = 0xffffffff,
11466    },{ .name = "L0_CLK_DIV_CNT",  .addr = A_L0_CLK_DIV_CNT,
11467        .reset = 0x19,
11468        .ro = 0xffffff00,
11469    },{ .name = "L0_DATA_BUS_WID",  .addr = A_L0_DATA_BUS_WID,
11470        .reset = 0x1,
11471        .ro = 0xffffff00,
11472    },{ .name = "L0_ANADIG_BYPASS",  .addr = A_L0_ANADIG_BYPASS,
11473        .ro = 0xffffff00,
11474    },{ .name = "L0_BIST_FILLER_OUT",  .addr = A_L0_BIST_FILLER_OUT,
11475        .reset = 0x1,
11476        .ro = 0xfffffffc,
11477    },{ .name = "L0_BIST_FORCE_MK_RST",  .addr = A_L0_BIST_FORCE_MK_RST,
11478        .rsvd = 0xfc,
11479        .ro = 0xfffffffc,
11480    },{ .name = "L0_SPARE_IN",  .addr = A_L0_SPARE_IN,
11481        .ro = 0xffffffff,
11482    },{ .name = "L0_SPARE_OUT",  .addr = A_L0_SPARE_OUT,
11483        .ro = 0xffffff00,
11484    },{ .name = "L1_TX_ANA_TM_0",  .addr = A_L1_TX_ANA_TM_0,
11485        .reset = 0x28,
11486        .ro = 0xffffffc3,
11487    },{ .name = "L1_TX_ANA_TM_3",  .addr = A_L1_TX_ANA_TM_3,
11488        .ro = 0xffffff00,
11489    },{ .name = "L1_TX_ANA_TM_4",  .addr = A_L1_TX_ANA_TM_4,
11490        .ro = 0xffffff80,
11491    },{ .name = "L1_TX_ANA_TM_5",  .addr = A_L1_TX_ANA_TM_5,
11492        .ro = 0xffffff80,
11493    },{ .name = "L1_TX_ANA_TM_9",  .addr = A_L1_TX_ANA_TM_9,
11494        .reset = 0x3f,
11495        .ro = 0xffffff00,
11496    },{ .name = "L1_TX_ANA_TM_10",  .addr = A_L1_TX_ANA_TM_10,
11497        .reset = 0x30,
11498        .ro = 0xffffff00,
11499    },{ .name = "L1_TX_ANA_TM_13",  .addr = A_L1_TX_ANA_TM_13,
11500        .reset = 0x2,
11501        .ro = 0xfffffff0,
11502    },{ .name = "L1_TX_ANA_TM_14",  .addr = A_L1_TX_ANA_TM_14,
11503        .ro = 0xffffffcf,
11504    },{ .name = "L1_TX_ANA_TM_15",  .addr = A_L1_TX_ANA_TM_15,
11505        .ro = 0xffffff00,
11506    },{ .name = "L1_TX_ANA_TM_16",  .addr = A_L1_TX_ANA_TM_16,
11507        .ro = 0xfffffff0,
11508    },{ .name = "L1_TX_ANA_TM_18",  .addr = A_L1_TX_ANA_TM_18,
11509        .reset = 0x2,
11510        .ro = 0xffffff00,
11511    },{ .name = "L1_TX_ANA_TM_19",  .addr = A_L1_TX_ANA_TM_19,
11512        .ro = 0xffffff00,
11513    },{ .name = "L1_TX_ANA_TM_20",  .addr = A_L1_TX_ANA_TM_20,
11514        .ro = 0xffffffe0,
11515    },{ .name = "L1_TX_ANA_TM_21",  .addr = A_L1_TX_ANA_TM_21,
11516        .ro = 0xffffffc0,
11517    },{ .name = "L1_TX_DIG_TM_61",  .addr = A_L1_TX_DIG_TM_61,
11518        .ro = 0xffffff34,
11519    },{ .name = "L1_TX_DIG_TM_62",  .addr = A_L1_TX_DIG_TM_62,
11520        .ro = 0xffffff00,
11521    },{ .name = "L1_TX_DIG_TM_65",  .addr = A_L1_TX_DIG_TM_65,
11522        .ro = 0xffffff01,
11523    },{ .name = "L1_TX_DIG_TM_67",  .addr = A_L1_TX_DIG_TM_67,
11524        .ro = 0xffffff00,
11525    },{ .name = "L1_TX_DIG_TM_68",  .addr = A_L1_TX_DIG_TM_68,
11526        .ro = 0xffffff00,
11527    },{ .name = "L1_TX_DIG_TM_69",  .addr = A_L1_TX_DIG_TM_69,
11528        .ro = 0xffffff00,
11529    },{ .name = "L1_TX_DIG_TM_76",  .addr = A_L1_TX_DIG_TM_76,
11530        .ro = 0xffffff00,
11531    },{ .name = "L1_TX_DIG_TM_77",  .addr = A_L1_TX_DIG_TM_77,
11532        .ro = 0xffffff00,
11533    },{ .name = "L1_TX_DIG_TM_78",  .addr = A_L1_TX_DIG_TM_78,
11534        .ro = 0xffffff00,
11535    },{ .name = "L1_TX_DIG_TM_79",  .addr = A_L1_TX_DIG_TM_79,
11536        .ro = 0xffffff00,
11537    },{ .name = "L1_TX_DIG_TM_80",  .addr = A_L1_TX_DIG_TM_80,
11538        .ro = 0xffffff00,
11539    },{ .name = "L1_TX_DIG_TM_81",  .addr = A_L1_TX_DIG_TM_81,
11540        .ro = 0xffffff00,
11541    },{ .name = "L1_TX_DIG_TM_82",  .addr = A_L1_TX_DIG_TM_82,
11542        .ro = 0xffffff00,
11543    },{ .name = "L1_TX_DIG_TM_83",  .addr = A_L1_TX_DIG_TM_83,
11544        .ro = 0xfffffff0,
11545    },{ .name = "L1_TX_DIG_TM_84",  .addr = A_L1_TX_DIG_TM_84,
11546        .ro = 0xffffff0a,
11547    },{ .name = "L1_TX_ANA_TM_85",  .addr = A_L1_TX_ANA_TM_85,
11548        .ro = 0xffffffca,
11549    },{ .name = "L1_TX_ANA_TM_87",  .addr = A_L1_TX_ANA_TM_87,
11550        .ro = 0xfffffff0,
11551    },{ .name = "L1_TX_ANA_TM_88",  .addr = A_L1_TX_ANA_TM_88,
11552        .reset = 0x96,
11553        .ro = 0xffffff00,
11554    },{ .name = "L1_TX_ANA_TM_89",  .addr = A_L1_TX_ANA_TM_89,
11555        .ro = 0xffffffd9,
11556    },{ .name = "L1_TX_ANA_TM_90",  .addr = A_L1_TX_ANA_TM_90,
11557        .ro = 0xffffffdf,
11558    },{ .name = "L1_TX_DIG_TM_91",  .addr = A_L1_TX_DIG_TM_91,
11559        .reset = 0x1a,
11560        .ro = 0xffffff00,
11561    },{ .name = "L1_TX_DIG_TM_92",  .addr = A_L1_TX_DIG_TM_92,
11562        .reset = 0xa,
11563        .ro = 0xffffff00,
11564    },{ .name = "L1_TX_ANA_TM_95",  .addr = A_L1_TX_ANA_TM_95,
11565        .ro = 0xffffffc3,
11566    },{ .name = "L1_TX_ANA_TM_96",  .addr = A_L1_TX_ANA_TM_96,
11567        .ro = 0xffffff00,
11568    },{ .name = "L1_TX_ANA_TM_97",  .addr = A_L1_TX_ANA_TM_97,
11569        .ro = 0xffffff00,
11570    },{ .name = "L1_TX_DIG_TM_98",  .addr = A_L1_TX_DIG_TM_98,
11571        .ro = 0xffffffc0,
11572    },{ .name = "L1_TX_DIG_TM_99",  .addr = A_L1_TX_DIG_TM_99,
11573        .ro = 0xffffff00,
11574    },{ .name = "L1_TX_DIG_TM_100",  .addr = A_L1_TX_DIG_TM_100,
11575        .ro = 0xffffff00,
11576    },{ .name = "L1_TX_DIG_TM_101",  .addr = A_L1_TX_DIG_TM_101,
11577        .ro = 0xffffff00,
11578    },{ .name = "L1_TX_DIG_TM_102",  .addr = A_L1_TX_DIG_TM_102,
11579        .ro = 0xffffff00,
11580    },{ .name = "L1_TX_DIG_TM_103",  .addr = A_L1_TX_DIG_TM_103,
11581        .ro = 0xffffff00,
11582    },{ .name = "L1_TX_DIG_TM_104",  .addr = A_L1_TX_DIG_TM_104,
11583        .ro = 0xffffff00,
11584    },{ .name = "L1_TX_DIG_TM_105",  .addr = A_L1_TX_DIG_TM_105,
11585        .ro = 0xffffff00,
11586    },{ .name = "L1_TX_DIG_TM_106",  .addr = A_L1_TX_DIG_TM_106,
11587        .ro = 0xffffff00,
11588    },{ .name = "L1_TX_DIG_TM_107",  .addr = A_L1_TX_DIG_TM_107,
11589        .ro = 0xffffff80,
11590    },{ .name = "L1_TX_DIG_TM_108",  .addr = A_L1_TX_DIG_TM_108,
11591        .ro = 0xffffff80,
11592    },{ .name = "L1_TX_DIG_TM_109",  .addr = A_L1_TX_DIG_TM_109,
11593        .ro = 0xffffff00,
11594    },{ .name = "L1_TX_DIG_TM_110",  .addr = A_L1_TX_DIG_TM_110,
11595        .reset = 0x9,
11596        .ro = 0xffffff00,
11597    },{ .name = "L1_TX_DIG_TM_111",  .addr = A_L1_TX_DIG_TM_111,
11598        .ro = 0xffffff00,
11599    },{ .name = "L1_TX_ANA_TM_112",  .addr = A_L1_TX_ANA_TM_112,
11600        .ro = 0xffffffc0,
11601    },{ .name = "L1_TX_ANA_TM_113",  .addr = A_L1_TX_ANA_TM_113,
11602        .ro = 0xffffff00,
11603    },{ .name = "L1_TX_ANA_TM_114",  .addr = A_L1_TX_ANA_TM_114,
11604        .ro = 0xffffffe0,
11605    },{ .name = "L1_TX_ANA_TM_115",  .addr = A_L1_TX_ANA_TM_115,
11606        .ro = 0xffffff80,
11607    },{ .name = "L1_TX_ANA_TM_116",  .addr = A_L1_TX_ANA_TM_116,
11608        .ro = 0xffffff80,
11609    },{ .name = "L1_TX_ANA_TM_117",  .addr = A_L1_TX_ANA_TM_117,
11610        .ro = 0xffffffc0,
11611    },{ .name = "L1_TX_ANA_TM_118",  .addr = A_L1_TX_ANA_TM_118,
11612        .ro = 0xfffffff0,
11613    },{ .name = "L1_TXPMA_TM_0",  .addr = A_L1_TXPMA_TM_0,
11614        .ro = 0xffffff00,
11615    },{ .name = "L1_TXPMA_TM_1",  .addr = A_L1_TXPMA_TM_1,
11616        .ro = 0xfffffff0,
11617    },{ .name = "L1_TXPMA_TM_2",  .addr = A_L1_TXPMA_TM_2,
11618        .ro = 0xffffff00,
11619    },{ .name = "L1_TXPMA_TM_3",  .addr = A_L1_TXPMA_TM_3,
11620        .ro = 0xffffffe0,
11621    },{ .name = "L1_TXPMA_TM_4",  .addr = A_L1_TXPMA_TM_4,
11622        .reset = 0x2,
11623        .ro = 0xffffff01,
11624    },{ .name = "L1_TXPMA_TM_5",  .addr = A_L1_TXPMA_TM_5,
11625        .ro = 0xfffffff0,
11626    },{ .name = "L1_TXPMA_TM_6",  .addr = A_L1_TXPMA_TM_6,
11627        .ro = 0xffffff00,
11628    },{ .name = "L1_TXPMA_TM_7",  .addr = A_L1_TXPMA_TM_7,
11629        .ro = 0xffffff00,
11630    },{ .name = "L1_TXPMA_TM_8",  .addr = A_L1_TXPMA_TM_8,
11631        .ro = 0xfffffffc,
11632    },{ .name = "L1_TXPMA_TM_9",  .addr = A_L1_TXPMA_TM_9,
11633        .ro = 0xffffff80,
11634    },{ .name = "L1_TXPMA_TM_10",  .addr = A_L1_TXPMA_TM_10,
11635        .ro = 0xffffffc0,
11636    },{ .name = "L1_TXPMA_TM_11",  .addr = A_L1_TXPMA_TM_11,
11637        .ro = 0xffffffe0,
11638    },{ .name = "L1_TXPMA_TM_12",  .addr = A_L1_TXPMA_TM_12,
11639        .ro = 0xffffff01,
11640    },{ .name = "L1_TXPMA_TM_13",  .addr = A_L1_TXPMA_TM_13,
11641        .ro = 0xffffff00,
11642    },{ .name = "L1_TXPMA_TM_14",  .addr = A_L1_TXPMA_TM_14,
11643        .ro = 0xffffffe0,
11644    },{ .name = "L1_TXPMA_TM_15",  .addr = A_L1_TXPMA_TM_15,
11645        .ro = 0xffffff00,
11646    },{ .name = "L1_TXPMA_TM_16",  .addr = A_L1_TXPMA_TM_16,
11647        .ro = 0xffffff00,
11648    },{ .name = "L1_TXPMA_TM_17",  .addr = A_L1_TXPMA_TM_17,
11649        .ro = 0xffffff00,
11650    },{ .name = "L1_TXPMA_TM_18",  .addr = A_L1_TXPMA_TM_18,
11651        .reset = 0xf,
11652        .ro = 0xffffff00,
11653    },{ .name = "L1_TXPMA_TM_19",  .addr = A_L1_TXPMA_TM_19,
11654        .reset = 0x3,
11655        .ro = 0xffffffc0,
11656    },{ .name = "L1_TXPMA_TM_20",  .addr = A_L1_TXPMA_TM_20,
11657        .reset = 0x6,
11658        .ro = 0xffffff00,
11659    },{ .name = "L1_TXPMA_TM_21",  .addr = A_L1_TXPMA_TM_21,
11660        .reset = 0x3,
11661        .ro = 0xffffff00,
11662    },{ .name = "L1_TXPMA_TM_22",  .addr = A_L1_TXPMA_TM_22,
11663        .reset = 0x6,
11664        .ro = 0xffffff00,
11665    },{ .name = "L1_TXPMA_TM_23",  .addr = A_L1_TXPMA_TM_23,
11666        .reset = 0x3,
11667        .ro = 0xffffff00,
11668    },{ .name = "L1_TXPMA_TM_24",  .addr = A_L1_TXPMA_TM_24,
11669        .ro = 0xffffff80,
11670    },{ .name = "L1_TXPMA_TM_25",  .addr = A_L1_TXPMA_TM_25,
11671        .ro = 0xffffffc0,
11672    },{ .name = "L1_TXPMA_TM_26",  .addr = A_L1_TXPMA_TM_26,
11673        .reset = 0x64,
11674        .ro = 0xffffff00,
11675    },{ .name = "L1_TXPMA_TM_27",  .addr = A_L1_TXPMA_TM_27,
11676        .ro = 0xffffff00,
11677    },{ .name = "L1_TXPMA_ST_0",  .addr = A_L1_TXPMA_ST_0,
11678        .reset = 0x1,
11679        .ro = 0xffffffff,
11680    },{ .name = "L1_TXPMA_ST_1",  .addr = A_L1_TXPMA_ST_1,
11681        .reset = 0x1,
11682        .ro = 0xffffffff,
11683    },{ .name = "L1_TXPMA_ST_2",  .addr = A_L1_TXPMA_ST_2,
11684        .reset = 0x4,
11685        .ro = 0xffffffff,
11686    },{ .name = "L1_TXPMA_ST_3",  .addr = A_L1_TXPMA_ST_3,
11687        .reset = 0x20,
11688        .ro = 0xffffffff,
11689    },{ .name = "L1_TXPMA_ST_4",  .addr = A_L1_TXPMA_ST_4,
11690        .reset = 0x20,
11691        .ro = 0xffffffff,
11692    },{ .name = "L1_TXPMA_ST_5",  .addr = A_L1_TXPMA_ST_5,
11693        .reset = 0x20,
11694        .ro = 0xffffffff,
11695    },{ .name = "L1_TXPMA_ST_6",  .addr = A_L1_TXPMA_ST_6,
11696        .reset = 0xb,
11697        .ro = 0xffffffff,
11698    },{ .name = "L1_TXPMA_ST_7",  .addr = A_L1_TXPMA_ST_7,
11699        .ro = 0xffffffff,
11700    },{ .name = "L1_TXPMA_ST_8",  .addr = A_L1_TXPMA_ST_8,
11701        .ro = 0xffffffff,
11702    },{ .name = "L1_TXPMA_ST_9",  .addr = A_L1_TXPMA_ST_9,
11703        .ro = 0xffffffff,
11704    },{ .name = "L1_TXPMD_TM_0",  .addr = A_L1_TXPMD_TM_0,
11705        .ro = 0xffffffe0,
11706    },{ .name = "L1_TXPMD_TM_1",  .addr = A_L1_TXPMD_TM_1,
11707        .ro = 0xffffffe0,
11708    },{ .name = "L1_TXPMD_TM_2",  .addr = A_L1_TXPMD_TM_2,
11709        .ro = 0xffffffe0,
11710    },{ .name = "L1_TXPMD_TM_3",  .addr = A_L1_TXPMD_TM_3,
11711        .ro = 0xffffffe0,
11712    },{ .name = "L1_TXPMD_TM_4",  .addr = A_L1_TXPMD_TM_4,
11713        .ro = 0xffffffe0,
11714    },{ .name = "L1_TXPMD_TM_5",  .addr = A_L1_TXPMD_TM_5,
11715        .ro = 0xffffffe0,
11716    },{ .name = "L1_TXPMD_TM_6",  .addr = A_L1_TXPMD_TM_6,
11717        .ro = 0xffffffe0,
11718    },{ .name = "L1_TXPMD_TM_7",  .addr = A_L1_TXPMD_TM_7,
11719        .ro = 0xffffffe0,
11720    },{ .name = "L1_TXPMD_TM_8",  .addr = A_L1_TXPMD_TM_8,
11721        .ro = 0xffffffe0,
11722    },{ .name = "L1_TXPMD_TM_9",  .addr = A_L1_TXPMD_TM_9,
11723        .ro = 0xffffffe0,
11724    },{ .name = "L1_TXPMD_TM_10",  .addr = A_L1_TXPMD_TM_10,
11725        .ro = 0xffffffe0,
11726    },{ .name = "L1_TXPMD_TM_11",  .addr = A_L1_TXPMD_TM_11,
11727        .ro = 0xffffffe0,
11728    },{ .name = "L1_TXPMD_TM_12",  .addr = A_L1_TXPMD_TM_12,
11729        .ro = 0xffffffe0,
11730    },{ .name = "L1_TXPMD_TM_13",  .addr = A_L1_TXPMD_TM_13,
11731        .ro = 0xffffffe0,
11732    },{ .name = "L1_TXPMD_TM_14",  .addr = A_L1_TXPMD_TM_14,
11733        .ro = 0xffffffe0,
11734    },{ .name = "L1_TXPMD_TM_15",  .addr = A_L1_TXPMD_TM_15,
11735        .ro = 0xffffffe0,
11736    },{ .name = "L1_TXPMD_TM_16",  .addr = A_L1_TXPMD_TM_16,
11737        .ro = 0xffffffe0,
11738    },{ .name = "L1_TXPMD_TM_17",  .addr = A_L1_TXPMD_TM_17,
11739        .ro = 0xffffffe0,
11740    },{ .name = "L1_TXPMD_TM_18",  .addr = A_L1_TXPMD_TM_18,
11741        .ro = 0xffffffe0,
11742    },{ .name = "L1_TXPMD_TM_19",  .addr = A_L1_TXPMD_TM_19,
11743        .ro = 0xffffffe0,
11744    },{ .name = "L1_TXPMD_TM_20",  .addr = A_L1_TXPMD_TM_20,
11745        .ro = 0xffffffe0,
11746    },{ .name = "L1_TXPMD_TM_21",  .addr = A_L1_TXPMD_TM_21,
11747        .ro = 0xffffffe0,
11748    },{ .name = "L1_TXPMD_TM_22",  .addr = A_L1_TXPMD_TM_22,
11749        .ro = 0xffffffe0,
11750    },{ .name = "L1_TXPMD_TM_23",  .addr = A_L1_TXPMD_TM_23,
11751        .ro = 0xffffffe0,
11752    },{ .name = "L1_TXPMD_TM_24",  .addr = A_L1_TXPMD_TM_24,
11753        .ro = 0xffffffe0,
11754    },{ .name = "L1_TXPMD_TM_25",  .addr = A_L1_TXPMD_TM_25,
11755        .ro = 0xffffffe0,
11756    },{ .name = "L1_TXPMD_TM_26",  .addr = A_L1_TXPMD_TM_26,
11757        .ro = 0xffffffe0,
11758    },{ .name = "L1_TXPMD_TM_27",  .addr = A_L1_TXPMD_TM_27,
11759        .ro = 0xffffffe0,
11760    },{ .name = "L1_TXPMD_TM_28",  .addr = A_L1_TXPMD_TM_28,
11761        .ro = 0xffffffe0,
11762    },{ .name = "L1_TXPMD_TM_29",  .addr = A_L1_TXPMD_TM_29,
11763        .ro = 0xffffffe0,
11764    },{ .name = "L1_TXPMD_TM_30",  .addr = A_L1_TXPMD_TM_30,
11765        .ro = 0xffffffe0,
11766    },{ .name = "L1_TXPMD_TM_31",  .addr = A_L1_TXPMD_TM_31,
11767        .ro = 0xffffffe0,
11768    },{ .name = "L1_TXPMD_TM_32",  .addr = A_L1_TXPMD_TM_32,
11769        .ro = 0xffffff00,
11770    },{ .name = "L1_TXPMD_TM_33",  .addr = A_L1_TXPMD_TM_33,
11771        .ro = 0xffffff00,
11772    },{ .name = "L1_TXPMD_TM_34",  .addr = A_L1_TXPMD_TM_34,
11773        .ro = 0xffffff00,
11774    },{ .name = "L1_TXPMD_TM_35",  .addr = A_L1_TXPMD_TM_35,
11775        .ro = 0xffffff00,
11776    },{ .name = "L1_TXPMD_TM_36",  .addr = A_L1_TXPMD_TM_36,
11777        .ro = 0xffffff00,
11778    },{ .name = "L1_TXPMD_TM_37",  .addr = A_L1_TXPMD_TM_37,
11779        .ro = 0xffffff00,
11780    },{ .name = "L1_TXPMD_TM_38",  .addr = A_L1_TXPMD_TM_38,
11781        .ro = 0xffffff80,
11782    },{ .name = "L1_TXPMD_TM_39",  .addr = A_L1_TXPMD_TM_39,
11783        .ro = 0xfffffff8,
11784    },{ .name = "L1_TXPMD_TM_40",  .addr = A_L1_TXPMD_TM_40,
11785        .ro = 0xffffff00,
11786    },{ .name = "L1_TXPMD_TM_41",  .addr = A_L1_TXPMD_TM_41,
11787        .ro = 0xffffff00,
11788    },{ .name = "L1_TXPMD_TM_42",  .addr = A_L1_TXPMD_TM_42,
11789        .ro = 0xffffffe0,
11790    },{ .name = "L1_TXPMD_TM_43",  .addr = A_L1_TXPMD_TM_43,
11791        .ro = 0xfffffff0,
11792    },{ .name = "L1_TXPMD_TM_44",  .addr = A_L1_TXPMD_TM_44,
11793        .ro = 0xffffffc0,
11794    },{ .name = "L1_TXPMD_TM_45",  .addr = A_L1_TXPMD_TM_45,
11795        .ro = 0xffffffc0,
11796    },{ .name = "L1_TXPMD_TM_46",  .addr = A_L1_TXPMD_TM_46,
11797        .ro = 0xffffffc0,
11798    },{ .name = "L1_TXPMD_TM_47",  .addr = A_L1_TXPMD_TM_47,
11799        .ro = 0xffffff00,
11800    },{ .name = "L1_TXPMD_TM_48",  .addr = A_L1_TXPMD_TM_48,
11801        .ro = 0xffffffc0,
11802    },{ .name = "L1_TM_ANA_BYP_1",  .addr = A_L1_TM_ANA_BYP_1,
11803        .ro = 0xffffff00,
11804    },{ .name = "L1_TM_ANA_BYP_2",  .addr = A_L1_TM_ANA_BYP_2,
11805        .ro = 0xffffff00,
11806    },{ .name = "L1_TM_ANA_BYP_3",  .addr = A_L1_TM_ANA_BYP_3,
11807        .ro = 0xffffff00,
11808    },{ .name = "L1_TM_ANA_BYP_4",  .addr = A_L1_TM_ANA_BYP_4,
11809        .ro = 0xffffff00,
11810    },{ .name = "L1_TM_ANA_BYP_5",  .addr = A_L1_TM_ANA_BYP_5,
11811        .rsvd = 0xc0,
11812        .ro = 0xffffffc0,
11813    },{ .name = "L1_TM_ANA_BYP_7",  .addr = A_L1_TM_ANA_BYP_7,
11814        .rsvd = 0xf,
11815        .ro = 0xffffff0f,
11816    },{ .name = "L1_TM_ANA_BYP_8",  .addr = A_L1_TM_ANA_BYP_8,
11817        .ro = 0xffffff00,
11818    },{ .name = "L1_TM_ANA_BYP_9",  .addr = A_L1_TM_ANA_BYP_9,
11819        .ro = 0xffffff00,
11820    },{ .name = "L1_TM_ANA_BYP_10",  .addr = A_L1_TM_ANA_BYP_10,
11821        .rsvd = 0xc0,
11822        .ro = 0xffffffc0,
11823    },{ .name = "L1_TM_ANA_BYP_11",  .addr = A_L1_TM_ANA_BYP_11,
11824        .rsvd = 0xc0,
11825        .ro = 0xffffffc0,
11826    },{ .name = "L1_TM_ANA_BYP_12",  .addr = A_L1_TM_ANA_BYP_12,
11827        .ro = 0xffffff00,
11828    },{ .name = "L1_TM_ANA_BYP_13",  .addr = A_L1_TM_ANA_BYP_13,
11829        .rsvd = 0xfc,
11830        .ro = 0xfffffffc,
11831    },{ .name = "L1_TM_ANA_BYP_14",  .addr = A_L1_TM_ANA_BYP_14,
11832        .rsvd = 0xc,
11833        .ro = 0xffffff0c,
11834    },{ .name = "L1_TM_ANA_BYP_15",  .addr = A_L1_TM_ANA_BYP_15,
11835        .ro = 0xffffff00,
11836    },{ .name = "L1_TM_ANA_BYP_16",  .addr = A_L1_TM_ANA_BYP_16,
11837        .ro = 0xffffff00,
11838    },{ .name = "L1_TM_ANA_BYP_17",  .addr = A_L1_TM_ANA_BYP_17,
11839        .rsvd = 0x80,
11840        .ro = 0xffffff80,
11841    },{ .name = "L1_TM_ANA_BYP_18",  .addr = A_L1_TM_ANA_BYP_18,
11842        .rsvd = 0xf0,
11843        .ro = 0xfffffff0,
11844    },{ .name = "L1_TM_ANA_BYP_20",  .addr = A_L1_TM_ANA_BYP_20,
11845        .ro = 0xffffff00,
11846    },{ .name = "L1_TM_ANA_BYP_21",  .addr = A_L1_TM_ANA_BYP_21,
11847        .ro = 0xffffff00,
11848    },{ .name = "L1_TM_ANA_BYP_22",  .addr = A_L1_TM_ANA_BYP_22,
11849        .ro = 0xffffff00,
11850    },{ .name = "L1_TM_ANA_BYP_23",  .addr = A_L1_TM_ANA_BYP_23,
11851        .ro = 0xffffff00,
11852    },{ .name = "L1_TM_DIG_1",  .addr = A_L1_TM_DIG_1,
11853        .reset = 0x40,
11854        .ro = 0xffffff00,
11855    },{ .name = "L1_TM_DIG_2",  .addr = A_L1_TM_DIG_2,
11856        .rsvd = 0xc0,
11857        .ro = 0xffffffc0,
11858    },{ .name = "L1_TM_DIG_3",  .addr = A_L1_TM_DIG_3,
11859        .ro = 0xffffff00,
11860    },{ .name = "L1_TM_DIG_4",  .addr = A_L1_TM_DIG_4,
11861        .rsvd = 0x7,
11862        .ro = 0xffffff07,
11863    },{ .name = "L1_TM_DIG_5",  .addr = A_L1_TM_DIG_5,
11864        .rsvd = 0xf8,
11865        .ro = 0xfffffff8,
11866    },{ .name = "L1_TM_DIG_6",  .addr = A_L1_TM_DIG_6,
11867        .rsvd = 0x80,
11868        .ro = 0xffffff80,
11869    },{ .name = "L1_TM_DIG_7",  .addr = A_L1_TM_DIG_7,
11870        .ro = 0xffffff00,
11871    },{ .name = "L1_TM_DIG_8",  .addr = A_L1_TM_DIG_8,
11872        .rsvd = 0xe0,
11873        .ro = 0xffffffe0,
11874    },{ .name = "L1_TM_DIG_9",  .addr = A_L1_TM_DIG_9,
11875        .rsvd = 0xf0,
11876        .ro = 0xfffffff0,
11877    },{ .name = "L1_TM_DIG_10",  .addr = A_L1_TM_DIG_10,
11878        .reset = 0x1,
11879        .rsvd = 0xf0,
11880        .ro = 0xfffffff0,
11881    },{ .name = "L1_TM_DIG_11",  .addr = A_L1_TM_DIG_11,
11882        .rsvd = 0xf,
11883        .ro = 0xffffff0f,
11884    },{ .name = "L1_TM_DIG_12",  .addr = A_L1_TM_DIG_12,
11885        .rsvd = 0xc0,
11886        .ro = 0xffffffc0,
11887    },{ .name = "L1_TM_DIG_13",  .addr = A_L1_TM_DIG_13,
11888        .reset = 0x1a,
11889        .rsvd = 0x80,
11890        .ro = 0xffffff80,
11891    },{ .name = "L1_TM_DIG_14",  .addr = A_L1_TM_DIG_14,
11892        .rsvd = 0xf,
11893        .ro = 0xffffff0f,
11894    },{ .name = "L1_TM_DIG_15",  .addr = A_L1_TM_DIG_15,
11895        .reset = 0xd,
11896        .rsvd = 0xc0,
11897        .ro = 0xffffffc0,
11898    },{ .name = "L1_TM_DIG_16",  .addr = A_L1_TM_DIG_16,
11899        .rsvd = 0xe0,
11900        .ro = 0xffffffe0,
11901    },{ .name = "L1_TM_DIG_17",  .addr = A_L1_TM_DIG_17,
11902        .rsvd = 0xe0,
11903        .ro = 0xffffffe0,
11904    },{ .name = "L1_TM_DIG_18",  .addr = A_L1_TM_DIG_18,
11905        .reset = 0x2a,
11906        .ro = 0xffffff00,
11907    },{ .name = "L1_TM_DIG_19",  .addr = A_L1_TM_DIG_19,
11908        .reset = 0x36,
11909        .ro = 0xffffff00,
11910    },{ .name = "L1_TM_DIG_20",  .addr = A_L1_TM_DIG_20,
11911        .reset = 0x10,
11912        .rsvd = 0x80,
11913        .ro = 0xffffff80,
11914    },{ .name = "L1_TM_DIG_21",  .addr = A_L1_TM_DIG_21,
11915        .rsvd = 0xe0,
11916        .ro = 0xffffffe0,
11917    },{ .name = "L1_TM_DIG_22",  .addr = A_L1_TM_DIG_22,
11918        .rsvd = 0xc0,
11919        .ro = 0xffffffc0,
11920    },{ .name = "L1_TM_DIG_23",  .addr = A_L1_TM_DIG_23,
11921        .reset = 0x5,
11922        .ro = 0xffffff00,
11923    },{ .name = "L1_TM_DIG_24",  .addr = A_L1_TM_DIG_24,
11924        .ro = 0xffffff00,
11925    },{ .name = "L1_TM_DIG_25",  .addr = A_L1_TM_DIG_25,
11926        .ro = 0xffffff00,
11927    },{ .name = "L1_TM_DIG_26",  .addr = A_L1_TM_DIG_26,
11928        .ro = 0xffffff00,
11929    },{ .name = "L1_TM_DIG_27",  .addr = A_L1_TM_DIG_27,
11930        .ro = 0xffffff00,
11931    },{ .name = "L1_TM_DIG_28",  .addr = A_L1_TM_DIG_28,
11932        .ro = 0xffffff00,
11933    },{ .name = "L1_TM_DIG_29",  .addr = A_L1_TM_DIG_29,
11934        .ro = 0xffffff00,
11935    },{ .name = "L1_TM_AUX_0",  .addr = A_L1_TM_AUX_0,
11936        .ro = 0xffffff00,
11937    },{ .name = "L1_TM_AUX_1",  .addr = A_L1_TM_AUX_1,
11938        .ro = 0xffffff00,
11939    },{ .name = "L1_TM_AUX_2",  .addr = A_L1_TM_AUX_2,
11940        .ro = 0xffffff00,
11941    },{ .name = "L1_TM_AUX_3",  .addr = A_L1_TM_AUX_3,
11942        .ro = 0xffffff00,
11943    },{ .name = "L1_TM_AUX_4",  .addr = A_L1_TM_AUX_4,
11944        .ro = 0xffffff00,
11945    },{ .name = "L1_TM_DIG_30",  .addr = A_L1_TM_DIG_30,
11946        .rsvd = 0xc0,
11947        .ro = 0xffffffc0,
11948    },{ .name = "L1_TM_DIG_31",  .addr = A_L1_TM_DIG_31,
11949        .reset = 0xfa,
11950        .ro = 0xffffff00,
11951    },{ .name = "L1_TM_DIG_32",  .addr = A_L1_TM_DIG_32,
11952        .reset = 0xfa,
11953        .ro = 0xffffff00,
11954    },{ .name = "L1_TM_DIG_33",  .addr = A_L1_TM_DIG_33,
11955        .ro = 0xffffff00,
11956    },{ .name = "L1_TM_DIG_34",  .addr = A_L1_TM_DIG_34,
11957        .reset = 0x1e,
11958        .rsvd = 0xc0,
11959        .ro = 0xffffffc0,
11960    },{ .name = "L1_TM_DIG_35",  .addr = A_L1_TM_DIG_35,
11961        .reset = 0x18,
11962        .rsvd = 0xc0,
11963        .ro = 0xffffffc0,
11964    },{ .name = "L1_TM_DIG_36",  .addr = A_L1_TM_DIG_36,
11965        .ro = 0xffffff00,
11966    },{ .name = "L1_TM_DIG_37",  .addr = A_L1_TM_DIG_37,
11967        .rsvd = 0xe0,
11968        .ro = 0xffffffe0,
11969    },{ .name = "L1_TM_LFPS_1",  .addr = A_L1_TM_LFPS_1,
11970        .reset = 0x88,
11971        .ro = 0xffffff00,
11972    },{ .name = "L1_TM_LFPS_2",  .addr = A_L1_TM_LFPS_2,
11973        .reset = 0x34,
11974        .rsvd = 0x80,
11975        .ro = 0xffffff80,
11976    },{ .name = "L1_TM_LFPS_3",  .addr = A_L1_TM_LFPS_3,
11977        .reset = 0x6c,
11978        .ro = 0xffffff00,
11979    },{ .name = "L1_TM_LFPS_4",  .addr = A_L1_TM_LFPS_4,
11980        .rsvd = 0xc0,
11981        .ro = 0xffffffc0,
11982    },{ .name = "L1_TM_RXPMA_1",  .addr = A_L1_TM_RXPMA_1,
11983        .ro = 0xffffff00,
11984    },{ .name = "L1_TM_BSCAN_1",  .addr = A_L1_TM_BSCAN_1,
11985        .rsvd = 0xf8,
11986        .ro = 0xfffffff8,
11987    },{ .name = "L1_TM_MPHY_SQ_1",  .addr = A_L1_TM_MPHY_SQ_1,
11988        .reset = 0x1,
11989        .rsvd = 0xe0,
11990        .ro = 0xffffffe0,
11991    },{ .name = "L1_TM_LSRX_1",  .addr = A_L1_TM_LSRX_1,
11992        .ro = 0xffffff00,
11993    },{ .name = "L1_TM_LSRX_2",  .addr = A_L1_TM_LSRX_2,
11994        .rsvd = 0xc0,
11995        .ro = 0xffffffc0,
11996    },{ .name = "L1_TM_SIGDET_1",  .addr = A_L1_TM_SIGDET_1,
11997        .reset = 0x34,
11998        .rsvd = 0x80,
11999        .ro = 0xffffff80,
12000    },{ .name = "L1_TM_SIGDET_2",  .addr = A_L1_TM_SIGDET_2,

12001        .reset = 0xf,
12002        .ro = 0xffffff00,
12003    },{ .name = "L1_TM_DFT_1",  .addr = A_L1_TM_DFT_1,
12004        .rsvd = 0x7,
12005        .ro = 0xffffff07,
12006    },{ .name = "L1_TM_DFT_2",  .addr = A_L1_TM_DFT_2,
12007        .rsvd = 0xf8,
12008        .ro = 0xfffffff8,
12009    },{ .name = "L1_TM_DFT_3",  .addr = A_L1_TM_DFT_3,
12010        .rsvd = 0xe0,
12011        .ro = 0xffffffe0,
12012    },{ .name = "L1_TM_DFT_4",  .addr = A_L1_TM_DFT_4,
12013        .rsvd = 0xfc,
12014        .ro = 0xfffffffc,
12015    },{ .name = "L1_TM_DFT_5",  .addr = A_L1_TM_DFT_5,
12016        .ro = 0xffffff00,
12017    },{ .name = "L1_TM_DFT_6",  .addr = A_L1_TM_DFT_6,
12018        .ro = 0xffffff00,
12019    },{ .name = "L1_TM_DFT_7",  .addr = A_L1_TM_DFT_7,
12020        .rsvd = 0xe0,
12021        .ro = 0xffffffe0,
12022    },{ .name = "L1_TM_DFT_8",  .addr = A_L1_TM_DFT_8,
12023        .rsvd = 0xe0,
12024        .ro = 0xffffffe0,
12025    },{ .name = "L1_TM_DFT_9",  .addr = A_L1_TM_DFT_9,
12026        .ro = 0xffffff00,
12027    },{ .name = "L1_TM_DFT_10",  .addr = A_L1_TM_DFT_10,
12028        .rsvd = 0xf0,
12029        .ro = 0xfffffff0,
12030    },{ .name = "L1_TM_BG_1",  .addr = A_L1_TM_BG_1,
12031        .ro = 0xffffff00,
12032    },{ .name = "L1_TM_BG_2",  .addr = A_L1_TM_BG_2,
12033        .ro = 0xffffff00,
12034    },{ .name = "L1_TM_BG_3",  .addr = A_L1_TM_BG_3,
12035        .ro = 0xffffff00,
12036    },{ .name = "L1_TM_BG_4",  .addr = A_L1_TM_BG_4,
12037        .ro = 0xffffff00,
12038    },{ .name = "L1_TM_BG_5",  .addr = A_L1_TM_BG_5,
12039        .ro = 0xffffff00,
12040    },{ .name = "L1_TM_BG_6",  .addr = A_L1_TM_BG_6,
12041        .ro = 0xffffff00,
12042    },{ .name = "L1_TM_BG_7",  .addr = A_L1_TM_BG_7,
12043        .ro = 0xffffff00,
12044    },{ .name = "L1_TM_BG_8",  .addr = A_L1_TM_BG_8,
12045        .ro = 0xffffff00,
12046    },{ .name = "L1_TM_BG_9",  .addr = A_L1_TM_BG_9,
12047        .ro = 0xffffff00,
12048    },{ .name = "L1_TM_BG_10",  .addr = A_L1_TM_BG_10,
12049        .ro = 0xffffff00,
12050    },{ .name = "L1_TM_SD0",  .addr = A_L1_TM_SD0,
12051        .ro = 0xffffff00,
12052    },{ .name = "L1_TM_SD1",  .addr = A_L1_TM_SD1,
12053        .ro = 0xffffff00,
12054    },{ .name = "L1_TM_SD2",  .addr = A_L1_TM_SD2,
12055        .ro = 0xffffff00,
12056    },{ .name = "L1_TM_SD3",  .addr = A_L1_TM_SD3,
12057        .reset = 0x4,
12058        .ro = 0xffffff00,
12059    },{ .name = "L1_TM_SD4",  .addr = A_L1_TM_SD4,
12060        .rsvd = 0xe0,
12061        .ro = 0xffffffe0,
12062    },{ .name = "L1_TM_SD5",  .addr = A_L1_TM_SD5,
12063        .reset = 0xa,
12064        .ro = 0xffffff00,
12065    },{ .name = "L1_TM_SD6",  .addr = A_L1_TM_SD6,
12066        .rsvd = 0xe0,
12067        .ro = 0xffffffe0,
12068    },{ .name = "L1_TM_MISC1",  .addr = A_L1_TM_MISC1,
12069        .ro = 0xffffff00,
12070    },{ .name = "L1_TM_MISC2",  .addr = A_L1_TM_MISC2,
12071        .ro = 0xffffff03,
12072    },{ .name = "L1_TM_EYE_SURF0",  .addr = A_L1_TM_EYE_SURF0,
12073        .ro = 0xffffff80,
12074    },{ .name = "L1_TM_EYE_SURF1",  .addr = A_L1_TM_EYE_SURF1,
12075        .ro = 0xffffff00,
12076    },{ .name = "L1_TM_EYE_SURF2",  .addr = A_L1_TM_EYE_SURF2,
12077        .ro = 0xffffff00,
12078    },{ .name = "L1_TM_EYE_SURF3",  .addr = A_L1_TM_EYE_SURF3,
12079        .ro = 0xffffff00,
12080    },{ .name = "L1_TM_EYE_SURF4",  .addr = A_L1_TM_EYE_SURF4,
12081        .ro = 0xffffff00,
12082    },{ .name = "L1_TM_EYE_SURF5",  .addr = A_L1_TM_EYE_SURF5,
12083        .ro = 0xffffff00,
12084    },{ .name = "L1_TM_EYE_SURF6",  .addr = A_L1_TM_EYE_SURF6,
12085        .ro = 0xffffff00,
12086    },{ .name = "L1_TM_EYE_SURF7",  .addr = A_L1_TM_EYE_SURF7,
12087        .ro = 0xffffff00,
12088    },{ .name = "L1_TM_EYE_SURF8",  .addr = A_L1_TM_EYE_SURF8,
12089        .ro = 0xffffff00,
12090    },{ .name = "L1_TM_EYE_SURF9",  .addr = A_L1_TM_EYE_SURF9,
12091        .ro = 0xffffff00,
12092    },{ .name = "L1_TM_SPARE",  .addr = A_L1_TM_SPARE,
12093        .ro = 0xffffff00,
12094    },{ .name = "L1_TM_ANA_EQ1",  .addr = A_L1_TM_ANA_EQ1,
12095        .reset = 0xc,
12096        .ro = 0xffffffe0,
12097    },{ .name = "L1_TM_ANA_E_PI0",  .addr = A_L1_TM_ANA_E_PI0,
12098        .reset = 0xa0,
12099        .ro = 0xffffff1f,
12100    },{ .name = "L1_TM_ANA_IQ_PI0",  .addr = A_L1_TM_ANA_IQ_PI0,
12101        .reset = 0xa0,
12102        .ro = 0xffffff1f,
12103    },{ .name = "L1_TM_ANA_MISC0",  .addr = A_L1_TM_ANA_MISC0,
12104        .ro = 0xffffff3f,
12105    },{ .name = "L1_TM_SAMP_CODE_IQ_PH0",  .addr = A_L1_TM_SAMP_CODE_IQ_PH0,
12106        .ro = 0xffffff80,
12107    },{ .name = "L1_TM_SAMP_CODE_IQ_PH90",  .addr = A_L1_TM_SAMP_CODE_IQ_PH90,
12108        .ro = 0xffffff00,
12109    },{ .name = "L1_TM_SAMP_CODE_IQ_PH180",  .addr = A_L1_TM_SAMP_CODE_IQ_PH180,
12110        .ro = 0xffffffc0,
12111    },{ .name = "L1_TM_SAMP_CODE_IQ_PH270",  .addr = A_L1_TM_SAMP_CODE_IQ_PH270,
12112        .ro = 0xffffff00,
12113    },{ .name = "L1_TM_SAMP_CODE_E_PH0",  .addr = A_L1_TM_SAMP_CODE_E_PH0,
12114        .ro = 0xffffffc0,
12115    },{ .name = "L1_TM_SAMP_CODE_E_PH180",  .addr = A_L1_TM_SAMP_CODE_E_PH180,
12116        .ro = 0xffffffc0,
12117    },{ .name = "L1_TM_IQ_ILL0",  .addr = A_L1_TM_IQ_ILL0,
12118        .ro = 0xffffff00,
12119    },{ .name = "L1_TM_IQ_ILL1",  .addr = A_L1_TM_IQ_ILL1,
12120        .ro = 0xffffff00,
12121    },{ .name = "L1_TM_IQ_ILL2",  .addr = A_L1_TM_IQ_ILL2,
12122        .ro = 0xffffff00,
12123    },{ .name = "L1_TM_IQ_ILL3",  .addr = A_L1_TM_IQ_ILL3,
12124        .ro = 0xffffff00,
12125    },{ .name = "L1_TM_IQ_ILL4",  .addr = A_L1_TM_IQ_ILL4,
12126        .ro = 0xffffff00,
12127    },{ .name = "L1_TM_IQ_ILL5",  .addr = A_L1_TM_IQ_ILL5,
12128        .ro = 0xffffff00,
12129    },{ .name = "L1_TM_IQ_ILL6",  .addr = A_L1_TM_IQ_ILL6,
12130        .ro = 0xffffff00,
12131    },{ .name = "L1_TM_IQ_ILL7",  .addr = A_L1_TM_IQ_ILL7,
12132        .ro = 0xffffff00,
12133    },{ .name = "L1_TM_IQ_ILL8",  .addr = A_L1_TM_IQ_ILL8,
12134        .ro = 0xffffff00,
12135    },{ .name = "L1_TM_IQ_ILL9",  .addr = A_L1_TM_IQ_ILL9,
12136        .ro = 0xfffffff0,
12137    },{ .name = "L1_TM_IQ_ILL10",  .addr = A_L1_TM_IQ_ILL10,
12138        .reset = 0x3,
12139        .ro = 0xffffffc0,
12140    },{ .name = "L1_TM_E_ILL0",  .addr = A_L1_TM_E_ILL0,
12141        .ro = 0xffffff00,
12142    },{ .name = "L1_TM_E_ILL1",  .addr = A_L1_TM_E_ILL1,
12143        .ro = 0xffffff00,
12144    },{ .name = "L1_TM_E_ILL2",  .addr = A_L1_TM_E_ILL2,
12145        .ro = 0xffffff00,
12146    },{ .name = "L1_TM_E_ILL3",  .addr = A_L1_TM_E_ILL3,
12147        .ro = 0xffffff00,
12148    },{ .name = "L1_TM_E_ILL4",  .addr = A_L1_TM_E_ILL4,
12149        .ro = 0xffffff00,
12150    },{ .name = "L1_TM_E_ILL5",  .addr = A_L1_TM_E_ILL5,
12151        .ro = 0xffffff00,
12152    },{ .name = "L1_TM_E_ILL6",  .addr = A_L1_TM_E_ILL6,
12153        .ro = 0xffffff00,
12154    },{ .name = "L1_TM_E_ILL7",  .addr = A_L1_TM_E_ILL7,
12155        .ro = 0xffffff00,
12156    },{ .name = "L1_TM_E_ILL8",  .addr = A_L1_TM_E_ILL8,
12157        .ro = 0xffffff00,
12158    },{ .name = "L1_TM_E_ILL9",  .addr = A_L1_TM_E_ILL9,
12159        .ro = 0xfffffff0,
12160    },{ .name = "L1_TM_E_ILL10",  .addr = A_L1_TM_E_ILL10,
12161        .reset = 0x3,
12162        .ro = 0xffffffc0,
12163    },{ .name = "L1_TM_EQ0",  .addr = A_L1_TM_EQ0,
12164        .ro = 0xffffff00,
12165    },{ .name = "L1_TM_EQ1",  .addr = A_L1_TM_EQ1,
12166        .ro = 0xffffff00,
12167    },{ .name = "L1_TM_EQ2",  .addr = A_L1_TM_EQ2,
12168        .ro = 0xffffff80,
12169    },{ .name = "L1_TM_EQ3",  .addr = A_L1_TM_EQ3,
12170        .ro = 0xffffffe0,
12171    },{ .name = "L1_TM_EQ4",  .addr = A_L1_TM_EQ4,
12172        .ro = 0xffffffe0,
12173    },{ .name = "L1_TM_EQ5",  .addr = A_L1_TM_EQ5,
12174        .ro = 0xffffffc0,
12175    },{ .name = "L1_TM_EQ6",  .addr = A_L1_TM_EQ6,
12176        .ro = 0xffffffe0,
12177    },{ .name = "L1_TM_EQ7",  .addr = A_L1_TM_EQ7,
12178        .ro = 0xffffffc0,
12179    },{ .name = "L1_TM_EQ8",  .addr = A_L1_TM_EQ8,
12180        .ro = 0xffffff00,
12181    },{ .name = "L1_TM_EQ9",  .addr = A_L1_TM_EQ9,
12182        .ro = 0xffffff80,
12183    },{ .name = "L1_TM_EQ10",  .addr = A_L1_TM_EQ10,
12184        .ro = 0xffffff80,
12185    },{ .name = "L1_TM_EQ11",  .addr = A_L1_TM_EQ11,
12186        .ro = 0xffffff00,
12187    },{ .name = "L1_TM_ILL7",  .addr = A_L1_TM_ILL7,
12188        .reset = 0x5,
12189        .ro = 0xffffff00,
12190    },{ .name = "L1_TM_ILL8",  .addr = A_L1_TM_ILL8,
12191        .reset = 0x2,
12192        .ro = 0xffffff00,
12193    },{ .name = "L1_TM_ILL9",  .addr = A_L1_TM_ILL9,
12194        .reset = 0x40,
12195        .ro = 0xffffff00,
12196    },{ .name = "L1_TM_ILL10",  .addr = A_L1_TM_ILL10,
12197        .ro = 0xffffff00,
12198    },{ .name = "L1_TM_ILL11",  .addr = A_L1_TM_ILL11,
12199        .ro = 0xffffff00,
12200    },{ .name = "L1_TM_ILL12",  .addr = A_L1_TM_ILL12,
12201        .ro = 0xffffff00,
12202    },{ .name = "L1_TM_ILL13",  .addr = A_L1_TM_ILL13,
12203        .reset = 0x1,
12204        .rsvd = 0xf8,
12205        .ro = 0xfffffff8,
12206    },{ .name = "L1_TM_ILL14",  .addr = A_L1_TM_ILL14,
12207        .reset = 0x51,
12208        .ro = 0xffffff00,
12209    },{ .name = "L1_TM_FRZ_FSM0",  .addr = A_L1_TM_FRZ_FSM0,
12210        .ro = 0xffffff00,
12211    },{ .name = "L1_TM_FRZ_FSM1",  .addr = A_L1_TM_FRZ_FSM1,
12212        .ro = 0xffffffc0,
12213    },{ .name = "L1_TM_RST_DLY",  .addr = A_L1_TM_RST_DLY,
12214        .ro = 0xffffff00,
12215    },{ .name = "L1_TM_ILL15",  .addr = A_L1_TM_ILL15,
12216        .ro = 0xffffff00,
12217    },{ .name = "L1_TM_MISC3",  .addr = A_L1_TM_MISC3,
12218        .reset = 0x3,
12219        .ro = 0xffffff00,
12220    },{ .name = "L1_TM_EQ_OFFS1",  .addr = A_L1_TM_EQ_OFFS1,
12221        .ro = 0xffffff00,
12222    },{ .name = "L1_TM_SAMP0",  .addr = A_L1_TM_SAMP0,
12223        .ro = 0xffffff00,
12224    },{ .name = "L1_TM_EQ12",  .addr = A_L1_TM_EQ12,
12225        .ro = 0xffffff00,
12226    },{ .name = "L1_TM_MISC4",  .addr = A_L1_TM_MISC4,
12227        .rsvd = 0xf8,
12228        .ro = 0xfffffff8,
12229    },{ .name = "L1_TM_SAMP_STATUS0",  .addr = A_L1_TM_SAMP_STATUS0,
12230        .rsvd = 0xc0,
12231        .ro = 0xffffffff,
12232    },{ .name = "L1_TM_SAMP_STATUS1",  .addr = A_L1_TM_SAMP_STATUS1,
12233        .rsvd = 0xc0,
12234        .ro = 0xffffffff,
12235    },{ .name = "L1_TM_SAMP_STATUS2",  .addr = A_L1_TM_SAMP_STATUS2,
12236        .rsvd = 0xc0,
12237        .ro = 0xffffffff,
12238    },{ .name = "L1_TM_SAMP_STATUS3",  .addr = A_L1_TM_SAMP_STATUS3,
12239        .rsvd = 0xc0,
12240        .ro = 0xffffffff,
12241    },{ .name = "L1_TM_SAMP_STATUS4",  .addr = A_L1_TM_SAMP_STATUS4,
12242        .rsvd = 0xc0,
12243        .ro = 0xffffffff,
12244    },{ .name = "L1_TM_SAMP_STATUS5",  .addr = A_L1_TM_SAMP_STATUS5,
12245        .rsvd = 0xc0,
12246        .ro = 0xffffffff,
12247    },{ .name = "L1_TM_ILL_STATUS0",  .addr = A_L1_TM_ILL_STATUS0,
12248        .rsvd = 0x80,
12249        .ro = 0xffffffff,
12250    },{ .name = "L1_TM_ILL_STATUS1",  .addr = A_L1_TM_ILL_STATUS1,
12251        .rsvd = 0x80,
12252        .ro = 0xffffffff,
12253    },{ .name = "L1_TM_ILL_STATUS2",  .addr = A_L1_TM_ILL_STATUS2,
12254        .rsvd = 0x80,
12255        .ro = 0xffffffff,
12256    },{ .name = "L1_TM_ILL_STATUS3",  .addr = A_L1_TM_ILL_STATUS3,
12257        .rsvd = 0x80,
12258        .ro = 0xffffffff,
12259    },{ .name = "L1_TM_ILL_STATUS4",  .addr = A_L1_TM_ILL_STATUS4,
12260        .rsvd = 0x80,
12261        .ro = 0xffffffff,
12262    },{ .name = "L1_TM_ILL_STATUS5",  .addr = A_L1_TM_ILL_STATUS5,
12263        .rsvd = 0x80,
12264        .ro = 0xffffffff,
12265    },{ .name = "L1_TM_ILL_STATUS6",  .addr = A_L1_TM_ILL_STATUS6,
12266        .rsvd = 0x80,
12267        .ro = 0xffffffff,
12268    },{ .name = "L1_TM_ILL_STATUS7",  .addr = A_L1_TM_ILL_STATUS7,
12269        .rsvd = 0x80,
12270        .ro = 0xffffffff,
12271    },{ .name = "L1_TM_ILL_STATUS8",  .addr = A_L1_TM_ILL_STATUS8,
12272        .rsvd = 0x80,
12273        .ro = 0xffffffff,
12274    },{ .name = "L1_TM_ILL_STATUS9",  .addr = A_L1_TM_ILL_STATUS9,
12275        .rsvd = 0x80,
12276        .ro = 0xffffffff,
12277    },{ .name = "L1_TM_ILL_STATUS10",  .addr = A_L1_TM_ILL_STATUS10,
12278        .rsvd = 0x80,
12279        .ro = 0xffffffff,
12280    },{ .name = "L1_TM_ILL_STATUS11",  .addr = A_L1_TM_ILL_STATUS11,
12281        .rsvd = 0x80,
12282        .ro = 0xffffffff,
12283    },{ .name = "L1_TM_MISC_ST_0",  .addr = A_L1_TM_MISC_ST_0,
12284        .rsvd = 0xc0,
12285        .ro = 0xffffffff,
12286    },{ .name = "L1_TM_SD_ST_0",  .addr = A_L1_TM_SD_ST_0,
12287        .reset = 0x12,
12288        .rsvd = 0xc0,
12289        .ro = 0xffffffff,
12290    },{ .name = "L1_TM_EYESURF_ST0",  .addr = A_L1_TM_EYESURF_ST0,
12291        .ro = 0xffffffff,
12292    },{ .name = "L1_TM_EYESURF_ST1",  .addr = A_L1_TM_EYESURF_ST1,
12293        .ro = 0xffffffff,
12294    },{ .name = "L1_TM_EQ_ST0",  .addr = A_L1_TM_EQ_ST0,
12295        .reset = 0xff,
12296        .ro = 0xffffffff,
12297    },{ .name = "L1_TM_EQ_ST1",  .addr = A_L1_TM_EQ_ST1,
12298        .ro = 0xffffffff,
12299    },{ .name = "L1_TM_EQ_ST2",  .addr = A_L1_TM_EQ_ST2,
12300        .rsvd = 0x80,
12301        .ro = 0xffffffff,
12302    },{ .name = "L1_TM_RXPMA_ST1",  .addr = A_L1_TM_RXPMA_ST1,
12303        .ro = 0xffffffff,
12304    },{ .name = "L1_TM_CDR0",  .addr = A_L1_TM_CDR0,
12305        .ro = 0xffffff60,
12306    },{ .name = "L1_TM_CDR1",  .addr = A_L1_TM_CDR1,
12307        .ro = 0xffffff00,
12308    },{ .name = "L1_TM_CDR2",  .addr = A_L1_TM_CDR2,
12309        .ro = 0xffffff00,
12310    },{ .name = "L1_TM_CDR3",  .addr = A_L1_TM_CDR3,
12311        .ro = 0xffffff80,
12312    },{ .name = "L1_TM_CDR4",  .addr = A_L1_TM_CDR4,
12313        .ro = 0xffffff80,
12314    },{ .name = "L1_TM_CDR5",  .addr = A_L1_TM_CDR5,
12315        .ro = 0xffffff00,
12316    },{ .name = "L1_TM_CDR6",  .addr = A_L1_TM_CDR6,
12317        .ro = 0xffffff00,
12318    },{ .name = "L1_TM_CDR7",  .addr = A_L1_TM_CDR7,
12319        .ro = 0xffffff00,
12320    },{ .name = "L1_TM_CDR8",  .addr = A_L1_TM_CDR8,
12321        .ro = 0xffffff00,
12322    },{ .name = "L1_TM_CDR9",  .addr = A_L1_TM_CDR9,
12323        .ro = 0xffffff00,
12324    },{ .name = "L1_TM_CDR10",  .addr = A_L1_TM_CDR10,
12325        .ro = 0xffffff00,
12326    },{ .name = "L1_TM_CDR11",  .addr = A_L1_TM_CDR11,
12327        .ro = 0xffffffe0,
12328    },{ .name = "L1_TM_CDR12",  .addr = A_L1_TM_CDR12,
12329        .ro = 0xffffff00,
12330    },{ .name = "L1_TM_CDR13",  .addr = A_L1_TM_CDR13,
12331        .ro = 0xffffff00,
12332    },{ .name = "L1_TM_CDR14",  .addr = A_L1_TM_CDR14,
12333        .ro = 0xffffff00,
12334    },{ .name = "L1_TM_CDR15",  .addr = A_L1_TM_CDR15,
12335        .ro = 0xffffff00,
12336    },{ .name = "L1_TM_CDR16",  .addr = A_L1_TM_CDR16,
12337        .ro = 0xffffffe0,
12338    },{ .name = "L1_TM_CDR17",  .addr = A_L1_TM_CDR17,
12339        .ro = 0xffffffe0,
12340    },{ .name = "L1_TM_CDR18",  .addr = A_L1_TM_CDR18,
12341        .ro = 0xffffffe0,
12342    },{ .name = "L1_TM_CDR19",  .addr = A_L1_TM_CDR19,
12343        .ro = 0xffffffe0,
12344    },{ .name = "L1_TM_CDR20",  .addr = A_L1_TM_CDR20,
12345        .ro = 0xffffffe0,
12346    },{ .name = "L1_TM_CDR21",  .addr = A_L1_TM_CDR21,
12347        .ro = 0xffffffe0,
12348    },{ .name = "L1_TM_CDR22",  .addr = A_L1_TM_CDR22,
12349        .ro = 0xffffffe0,
12350    },{ .name = "L1_TM_CDR23",  .addr = A_L1_TM_CDR23,
12351        .ro = 0xffffff80,
12352    },{ .name = "L1_TM_MISC0",  .addr = A_L1_TM_MISC0,
12353        .ro = 0xfffffffc,
12354    },{ .name = "L1_TM_HSRX_ST0",  .addr = A_L1_TM_HSRX_ST0,
12355        .rsvd = 0xfe,
12356        .ro = 0xffffffff,
12357    },{ .name = "L1_TM_PLL_LS_CLOCK",  .addr = A_L1_TM_PLL_LS_CLOCK,
12358        .ro = 0xffffff00,
12359    },{ .name = "L1_TM_PLL_LOOP_FILT",  .addr = A_L1_TM_PLL_LOOP_FILT,
12360        .ro = 0xffffff00,
12361    },{ .name = "L1_TM_PLL_DIG2",  .addr = A_L1_TM_PLL_DIG2,
12362        .ro = 0xffffff00,
12363    },{ .name = "L1_TM_PLL_FBDIV",  .addr = A_L1_TM_PLL_FBDIV,
12364        .ro = 0xffffff00,
12365    },{ .name = "L1_TM_PLL_DIG4",  .addr = A_L1_TM_PLL_DIG4,
12366        .reset = 0x80,
12367        .ro = 0xffffff00,
12368    },{ .name = "L1_TM_PLL_DIG5",  .addr = A_L1_TM_PLL_DIG5,
12369        .reset = 0xc0,
12370        .ro = 0xffffff00,
12371    },{ .name = "L1_TM_PLL_DIG6",  .addr = A_L1_TM_PLL_DIG6,
12372        .reset = 0x3,
12373        .ro = 0xffffff00,
12374    },{ .name = "L1_TM_PLL_DIG7",  .addr = A_L1_TM_PLL_DIG7,
12375        .ro = 0xffffff00,
12376    },{ .name = "L1_TM_PLL_CPUMP_CODE_1",  .addr = A_L1_TM_PLL_CPUMP_CODE_1,
12377        .ro = 0xffffff00,
12378    },{ .name = "L1_TM_PLL_DIG9",  .addr = A_L1_TM_PLL_DIG9,
12379        .ro = 0xffffffc0,
12380    },{ .name = "L1_TM_PLL_COARSE_CODE_LSB",  .addr = A_L1_TM_PLL_COARSE_CODE_LSB,
12381        .ro = 0xffffff00,
12382    },{ .name = "L1_TM_PLL_DIG11",  .addr = A_L1_TM_PLL_DIG11,
12383        .ro = 0xffffff00,
12384    },{ .name = "L1_TM_PLL_DIG12",  .addr = A_L1_TM_PLL_DIG12,
12385        .ro = 0xffffff00,
12386    },{ .name = "L1_TM_PLL_CONST_PMOS",  .addr = A_L1_TM_PLL_CONST_PMOS,
12387        .ro = 0xffffff00,
12388    },{ .name = "L1_TM_PLL_DIG14",  .addr = A_L1_TM_PLL_DIG14,
12389        .ro = 0xffffff00,
12390    },{ .name = "L1_TM_PLL_DIG15",  .addr = A_L1_TM_PLL_DIG15,
12391        .ro = 0xffffff00,
12392    },{ .name = "L1_TM_PLL_DIG16",  .addr = A_L1_TM_PLL_DIG16,
12393        .ro = 0xffffff10,
12394    },{ .name = "L1_TM_PLL_DIG17",  .addr = A_L1_TM_PLL_DIG17,
12395        .ro = 0xffffff00,
12396    },{ .name = "L1_TM_PLL_DIG18",  .addr = A_L1_TM_PLL_DIG18,
12397        .ro = 0xffffff00,
12398    },{ .name = "L1_TM_PLL_DIG19",  .addr = A_L1_TM_PLL_DIG19,
12399        .ro = 0xffffff00,
12400    },{ .name = "L1_TM_PLL_DIG20",  .addr = A_L1_TM_PLL_DIG20,
12401        .ro = 0xffffff40,
12402    },{ .name = "L1_TM_PLL_DIG21",  .addr = A_L1_TM_PLL_DIG21,
12403        .reset = 0x20,
12404        .ro = 0xffffff0c,
12405    },{ .name = "L1_TM_PLL_DIG22",  .addr = A_L1_TM_PLL_DIG22,
12406        .ro = 0xffffff80,
12407    },{ .name = "L1_TM_PLL_DIG23",  .addr = A_L1_TM_PLL_DIG23,
12408        .reset = 0x31,
12409        .ro = 0xffffff00,
12410    },{ .name = "L1_TM_PLL_DIG24",  .addr = A_L1_TM_PLL_DIG24,
12411        .ro = 0xffffff80,
12412    },{ .name = "L1_TM_PLL_DIG25",  .addr = A_L1_TM_PLL_DIG25,
12413        .ro = 0xffffff00,
12414    },{ .name = "L1_TM_PLL_DIG26",  .addr = A_L1_TM_PLL_DIG26,
12415        .reset = 0x40,
12416        .ro = 0xffffff80,
12417    },{ .name = "L1_TM_PLL_CLK_DIST_NTRIM_LSB",  .addr = A_L1_TM_PLL_CLK_DIST_NTRIM_LSB,
12418        .ro = 0xffffff00,
12419    },{ .name = "L1_TM_PLL_CLK_DIST_PTRIM_LSB",  .addr = A_L1_TM_PLL_CLK_DIST_PTRIM_LSB,
12420        .ro = 0xffffff00,
12421    },{ .name = "L1_TM_PLL_DIG_29",  .addr = A_L1_TM_PLL_DIG_29,
12422        .ro = 0xffffff00,
12423    },{ .name = "L1_TM_PLL_DIG_30",  .addr = A_L1_TM_PLL_DIG_30,
12424        .ro = 0xffffff00,
12425    },{ .name = "L1_TM_PLL_DIG_31",  .addr = A_L1_TM_PLL_DIG_31,
12426        .ro = 0xffffff00,
12427    },{ .name = "L1_TM_PLL_DIG_32",  .addr = A_L1_TM_PLL_DIG_32,
12428        .ro = 0xffffff00,
12429    },{ .name = "L1_TM_PLL_DIG_33",  .addr = A_L1_TM_PLL_DIG_33,
12430        .ro = 0xffffff00,
12431    },{ .name = "L1_TM_PLL_DIG_34",  .addr = A_L1_TM_PLL_DIG_34,
12432        .ro = 0xffffff80,
12433    },{ .name = "L1_TM_PLL_DIG_35",  .addr = A_L1_TM_PLL_DIG_35,
12434        .ro = 0xffffff00,
12435    },{ .name = "L1_TM_PLL_DIG_36",  .addr = A_L1_TM_PLL_DIG_36,
12436        .ro = 0xffffff00,
12437    },{ .name = "L1_TM_PLL_DIG_37",  .addr = A_L1_TM_PLL_DIG_37,
12438        .ro = 0xffffff00,
12439    },{ .name = "L1_TM_PLL_COARSE_CODE_SAT_MSB",  .addr = A_L1_TM_PLL_COARSE_CODE_SAT_MSB,
12440        .ro = 0xffffff00,
12441    },{ .name = "L1_MPHY_CFG_HIB8",  .addr = A_L1_MPHY_CFG_HIB8,
12442        .ro = 0xfffffffe,
12443    },{ .name = "L1_MPHY_CFG_MODE",  .addr = A_L1_MPHY_CFG_MODE,
12444        .ro = 0xfffffffc,
12445    },{ .name = "L1_MPHY_CFG_HS_GEAR",  .addr = A_L1_MPHY_CFG_HS_GEAR,
12446        .ro = 0xfffffffc,
12447    },{ .name = "L1_MPHY_CFG_HS_RATE",  .addr = A_L1_MPHY_CFG_HS_RATE,
12448        .ro = 0xfffffffe,
12449    },{ .name = "L1_MPHY_CFG_PWM",  .addr = A_L1_MPHY_CFG_PWM,
12450        .ro = 0xfffffff8,
12451    },{ .name = "L1_PLL_OPDIV_LS",  .addr = A_L1_PLL_OPDIV_LS,
12452        .ro = 0xffffff00,
12453    },{ .name = "L1_MPHY_CFG_UPDT",  .addr = A_L1_MPHY_CFG_UPDT,
12454        .ro = 0xfffffffe,
12455    },{ .name = "L1_PLL_TM_DIV_CNTRLS",  .addr = A_L1_PLL_TM_DIV_CNTRLS,
12456        .reset = 0x40,
12457        .ro = 0xffffff20,
12458    },{ .name = "L1_PLL_FBDIV_G1A_LSB",  .addr = A_L1_PLL_FBDIV_G1A_LSB,
12459        .ro = 0xffffff00,
12460    },{ .name = "L1_PLL_FBDIV_G1B_LSB",  .addr = A_L1_PLL_FBDIV_G1B_LSB,
12461        .ro = 0xffffff00,
12462    },{ .name = "L1_PLL_FBDIV_G2A_LSB",  .addr = A_L1_PLL_FBDIV_G2A_LSB,
12463        .ro = 0xffffff00,
12464    },{ .name = "L1_PLL_FBDIV_G2B_LSB",  .addr = A_L1_PLL_FBDIV_G2B_LSB,
12465        .ro = 0xffffff00,
12466    },{ .name = "L1_PLL_FBDIV_G3A_LSB",  .addr = A_L1_PLL_FBDIV_G3A_LSB,
12467        .ro = 0xffffff00,
12468    },{ .name = "L1_PLL_FBDIV_G3B_LSB",  .addr = A_L1_PLL_FBDIV_G3B_LSB,
12469        .ro = 0xffffff00,
12470    },{ .name = "L1_PLL_FBDIV_G1A_MSB",  .addr = A_L1_PLL_FBDIV_G1A_MSB,
12471        .ro = 0xffffff00,
12472    },{ .name = "L1_PLL_FBDIV_G1B_MSB",  .addr = A_L1_PLL_FBDIV_G1B_MSB,
12473        .ro = 0xffffff00,
12474    },{ .name = "L1_PLL_FBDIV_G2A_MSB",  .addr = A_L1_PLL_FBDIV_G2A_MSB,
12475        .ro = 0xffffff00,
12476    },{ .name = "L1_PLL_FBDIV_G2B_MSB",  .addr = A_L1_PLL_FBDIV_G2B_MSB,
12477        .ro = 0xffffff00,
12478    },{ .name = "L1_PLL_FBDIV_G3A_MSB",  .addr = A_L1_PLL_FBDIV_G3A_MSB,
12479        .ro = 0xffffff00,
12480    },{ .name = "L1_PLL_FBDIV_G3B_MSB",  .addr = A_L1_PLL_FBDIV_G3B_MSB,
12481        .ro = 0xffffff00,
12482    },{ .name = "L1_PLL_IPDIV",  .addr = A_L1_PLL_IPDIV,
12483        .ro = 0xffffff00,
12484    },{ .name = "L1_PLL_FBDIV_FRAC_0_LSB",  .addr = A_L1_PLL_FBDIV_FRAC_0_LSB,
12485        .ro = 0xffffff00,
12486    },{ .name = "L1_PLL_FBDIV_FRAC_1",  .addr = A_L1_PLL_FBDIV_FRAC_1,
12487        .ro = 0xffffff00,
12488    },{ .name = "L1_PLL_FBDIV_FRAC_2",  .addr = A_L1_PLL_FBDIV_FRAC_2,
12489        .ro = 0xffffff00,
12490    },{ .name = "L1_PLL_FBDIV_FRAC_3_MSB",  .addr = A_L1_PLL_FBDIV_FRAC_3_MSB,
12491        .ro = 0xffffff98,
12492    },{ .name = "L1_PLL_PWR_SEQ_WAIT_TIME",  .addr = A_L1_PLL_PWR_SEQ_WAIT_TIME,
12493        .ro = 0xffffff00,
12494    },{ .name = "L1_PLL_SS_STEPS_0_LSB",  .addr = A_L1_PLL_SS_STEPS_0_LSB,
12495        .ro = 0xffffff00,
12496    },{ .name = "L1_PLL_SS_STEPS_1_MSB",  .addr = A_L1_PLL_SS_STEPS_1_MSB,
12497        .ro = 0xfffffff8,
12498    },{ .name = "L1_PLL_SS_STEP_SIZE_0_LSB",  .addr = A_L1_PLL_SS_STEP_SIZE_0_LSB,
12499        .ro = 0xffffff00,
12500    },{ .name = "L1_PLL_SS_STEP_SIZE_1",  .addr = A_L1_PLL_SS_STEP_SIZE_1,
12501        .ro = 0xffffff00,
12502    },{ .name = "L1_PLL_SS_STEP_SIZE_2",  .addr = A_L1_PLL_SS_STEP_SIZE_2,
12503        .ro = 0xffffff00,
12504    },{ .name = "L1_PLL_SS_STEP_SIZE_3_MSB",  .addr = A_L1_PLL_SS_STEP_SIZE_3_MSB,
12505        .ro = 0xffffff00,
12506    },{ .name = "L1_TM_MASK_CFG_UPDT",  .addr = A_L1_TM_MASK_CFG_UPDT,
12507        .ro = 0xffffff80,
12508    },{ .name = "L1_PLL_TM_FORCE_DIV",  .addr = A_L1_PLL_TM_FORCE_DIV,
12509        .ro = 0xffffff00,
12510    },{ .name = "L1_PLL_TM_COARSE_CODE_1_LSB",  .addr = A_L1_PLL_TM_COARSE_CODE_1_LSB,
12511        .ro = 0xffffff00,
12512    },{ .name = "L1_PLL_TM_COARSE_CODE_2_LSB",  .addr = A_L1_PLL_TM_COARSE_CODE_2_LSB,
12513        .ro = 0xffffff00,
12514    },{ .name = "L1_PLL_TM_COARSE_CODE_3_LSB",  .addr = A_L1_PLL_TM_COARSE_CODE_3_LSB,
12515        .ro = 0xffffff00,
12516    },{ .name = "L1_PLL_TM_COARSE_CODE_4_LSB",  .addr = A_L1_PLL_TM_COARSE_CODE_4_LSB,
12517        .ro = 0xffffff00,
12518    },{ .name = "L1_PLL_TM_COARSE_CODE_5_LSB",  .addr = A_L1_PLL_TM_COARSE_CODE_5_LSB,
12519        .ro = 0xffffff00,
12520    },{ .name = "L1_PLL_TM_COARSE_CODE_6_LSB",  .addr = A_L1_PLL_TM_COARSE_CODE_6_LSB,
12521        .ro = 0xffffff00,
12522    },{ .name = "L1_PLL_TM_COARSE_CODE_1_2_MSB",  .addr = A_L1_PLL_TM_COARSE_CODE_1_2_MSB,
12523        .ro = 0xffffffc0,
12524    },{ .name = "L1_PLL_TM_COARSE_CODE_3_4_MSB",  .addr = A_L1_PLL_TM_COARSE_CODE_3_4_MSB,
12525        .ro = 0xffffffc0,
12526    },{ .name = "L1_PLL_TM_COARSE_CODE_5_6_MSB",  .addr = A_L1_PLL_TM_COARSE_CODE_5_6_MSB,
12527        .ro = 0xffffffc0,
12528    },{ .name = "L1_PLL_TM_SHARED_0",  .addr = A_L1_PLL_TM_SHARED_0,
12529        .ro = 0xffffff00,
12530    },{ .name = "L1_PLL_TM_FRAC_OFFSET_0",  .addr = A_L1_PLL_TM_FRAC_OFFSET_0,
12531        .ro = 0xffffff00,
12532    },{ .name = "L1_PLL_TM_FRAC_OFFSET_1",  .addr = A_L1_PLL_TM_FRAC_OFFSET_1,
12533        .ro = 0xffffff00,
12534    },{ .name = "L1_PLL_TM_FRAC_OFFSET_2",  .addr = A_L1_PLL_TM_FRAC_OFFSET_2,
12535        .ro = 0xfffffffc,
12536    },{ .name = "L1_PLL_STATUS_READ_0",  .addr = A_L1_PLL_STATUS_READ_0,
12537        .ro = 0xffffffff,
12538    },{ .name = "L1_PLL_STATUS_READ_1",  .addr = A_L1_PLL_STATUS_READ_1,
12539        .reset = 0x1 | R_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK,
12540        .ro = 0xffffffff,
12541    },{ .name = "L1_UPHY_GLOBAL_CTRL",  .addr = A_L1_UPHY_GLOBAL_CTRL,
12542        .ro = 0xffffffe0,
12543    },{ .name = "L1_BIST_CTRL_1",  .addr = A_L1_BIST_CTRL_1,
12544        .ro = 0xffffff00,
12545    },{ .name = "L1_BIST_CTRL_2",  .addr = A_L1_BIST_CTRL_2,
12546        .ro = 0xfffffff8,
12547    },{ .name = "L1_BIST_RUN_LEN_L",  .addr = A_L1_BIST_RUN_LEN_L,
12548        .ro = 0xffffff00,
12549    },{ .name = "L1_BIST_ERR_INJ_POINT_L",  .addr = A_L1_BIST_ERR_INJ_POINT_L,
12550        .ro = 0xffffff00,
12551    },{ .name = "L1_BIST_RUNLEN_ERR_INJ_H",  .addr = A_L1_BIST_RUNLEN_ERR_INJ_H,
12552        .ro = 0xffffff00,
12553    },{ .name = "L1_BIST_IDLE_TIME",  .addr = A_L1_BIST_IDLE_TIME,
12554        .ro = 0xffffff00,
12555    },{ .name = "L1_BIST_MARKER_L",  .addr = A_L1_BIST_MARKER_L,
12556        .ro = 0xffffff00,
12557    },{ .name = "L1_BIST_IDLE_CHAR_L",  .addr = A_L1_BIST_IDLE_CHAR_L,
12558        .ro = 0xffffff00,
12559    },{ .name = "L1_BIST_MARKER_IDLE_H",  .addr = A_L1_BIST_MARKER_IDLE_H,
12560        .ro = 0xffffffcc,
12561    },{ .name = "L1_BIST_LOW_PULSE_TIME",  .addr = A_L1_BIST_LOW_PULSE_TIME,
12562        .ro = 0xffffff00,
12563    },{ .name = "L1_BIST_TOTAL_PULSE_TIME",  .addr = A_L1_BIST_TOTAL_PULSE_TIME,
12564        .ro = 0xffffff00,
12565    },{ .name = "L1_BIST_TEST_PAT_1",  .addr = A_L1_BIST_TEST_PAT_1,
12566        .ro = 0xffffff00,
12567    },{ .name = "L1_BIST_TEST_PAT_2",  .addr = A_L1_BIST_TEST_PAT_2,
12568        .ro = 0xffffff00,
12569    },{ .name = "L1_BIST_TEST_PAT_3",  .addr = A_L1_BIST_TEST_PAT_3,
12570        .ro = 0xffffff00,
12571    },{ .name = "L1_BIST_TEST_PAT_4",  .addr = A_L1_BIST_TEST_PAT_4,
12572        .ro = 0xffffff00,
12573    },{ .name = "L1_BIST_TEST_PAT_MSBS",  .addr = A_L1_BIST_TEST_PAT_MSBS,
12574        .ro = 0xffffff00,
12575    },{ .name = "L1_BIST_PKT_NUM",  .addr = A_L1_BIST_PKT_NUM,
12576        .ro = 0xffffff00,
12577    },{ .name = "L1_BIST_FRM_IDLE_TIME",  .addr = A_L1_BIST_FRM_IDLE_TIME,
12578        .ro = 0xffffff00,
12579    },{ .name = "L1_BIST_PKT_CTR_L",  .addr = A_L1_BIST_PKT_CTR_L,
12580        .ro = 0xffffffff,
12581    },{ .name = "L1_BIST_PKT_CTR_H",  .addr = A_L1_BIST_PKT_CTR_H,
12582        .ro = 0xffffffff,
12583    },{ .name = "L1_BIST_ERR_CTR_L",  .addr = A_L1_BIST_ERR_CTR_L,
12584        .ro = 0xffffffff,
12585    },{ .name = "L1_BIST_ERR_CTR_H",  .addr = A_L1_BIST_ERR_CTR_H,
12586        .ro = 0xffffffff,
12587    },{ .name = "L1_CLK_DIV_CNT",  .addr = A_L1_CLK_DIV_CNT,
12588        .reset = 0x19,
12589        .ro = 0xffffff00,
12590    },{ .name = "L1_DATA_BUS_WID",  .addr = A_L1_DATA_BUS_WID,
12591        .reset = 0x1,
12592        .ro = 0xffffff00,
12593    },{ .name = "L1_ANADIG_BYPASS",  .addr = A_L1_ANADIG_BYPASS,
12594        .ro = 0xffffff00,
12595    },{ .name = "L1_BIST_FILLER_OUT",  .addr = A_L1_BIST_FILLER_OUT,
12596        .reset = 0x1,
12597        .ro = 0xfffffffc,
12598    },{ .name = "L1_BIST_FORCE_MK_RST",  .addr = A_L1_BIST_FORCE_MK_RST,
12599        .rsvd = 0xfc,
12600        .ro = 0xfffffffc,
12601    },{ .name = "L1_SPARE_IN",  .addr = A_L1_SPARE_IN,
12602        .ro = 0xffffffff,
12603    },{ .name = "L1_SPARE_OUT",  .addr = A_L1_SPARE_OUT,
12604        .ro = 0xffffff00,
12605    },{ .name = "L2_TX_ANA_TM_0",  .addr = A_L2_TX_ANA_TM_0,
12606        .reset = 0x28,
12607        .ro = 0xffffffc3,
12608    },{ .name = "L2_TX_ANA_TM_3",  .addr = A_L2_TX_ANA_TM_3,
12609        .ro = 0xffffff00,
12610    },{ .name = "L2_TX_ANA_TM_4",  .addr = A_L2_TX_ANA_TM_4,
12611        .ro = 0xffffff80,
12612    },{ .name = "L2_TX_ANA_TM_5",  .addr = A_L2_TX_ANA_TM_5,
12613        .ro = 0xffffff80,
12614    },{ .name = "L2_TX_ANA_TM_9",  .addr = A_L2_TX_ANA_TM_9,
12615        .reset = 0x3f,
12616        .ro = 0xffffff00,
12617    },{ .name = "L2_TX_ANA_TM_10",  .addr = A_L2_TX_ANA_TM_10,
12618        .reset = 0x30,
12619        .ro = 0xffffff00,
12620    },{ .name = "L2_TX_ANA_TM_13",  .addr = A_L2_TX_ANA_TM_13,
12621        .reset = 0x2,
12622        .ro = 0xfffffff0,
12623    },{ .name = "L2_TX_ANA_TM_14",  .addr = A_L2_TX_ANA_TM_14,
12624        .ro = 0xffffffcf,
12625    },{ .name = "L2_TX_ANA_TM_15",  .addr = A_L2_TX_ANA_TM_15,
12626        .ro = 0xffffff00,
12627    },{ .name = "L2_TX_ANA_TM_16",  .addr = A_L2_TX_ANA_TM_16,
12628        .ro = 0xfffffff0,
12629    },{ .name = "L2_TX_ANA_TM_18",  .addr = A_L2_TX_ANA_TM_18,
12630        .reset = 0x2,
12631        .ro = 0xffffff00,
12632    },{ .name = "L2_TX_ANA_TM_19",  .addr = A_L2_TX_ANA_TM_19,
12633        .ro = 0xffffff00,
12634    },{ .name = "L2_TX_ANA_TM_20",  .addr = A_L2_TX_ANA_TM_20,
12635        .ro = 0xffffffe0,
12636    },{ .name = "L2_TX_ANA_TM_21",  .addr = A_L2_TX_ANA_TM_21,
12637        .ro = 0xffffffc0,
12638    },{ .name = "L2_TX_DIG_TM_61",  .addr = A_L2_TX_DIG_TM_61,
12639        .ro = 0xffffff34,
12640    },{ .name = "L2_TX_DIG_TM_62",  .addr = A_L2_TX_DIG_TM_62,
12641        .ro = 0xffffff00,
12642    },{ .name = "L2_TX_DIG_TM_65",  .addr = A_L2_TX_DIG_TM_65,
12643        .ro = 0xffffff01,
12644    },{ .name = "L2_TX_DIG_TM_67",  .addr = A_L2_TX_DIG_TM_67,
12645        .ro = 0xffffff00,
12646    },{ .name = "L2_TX_DIG_TM_68",  .addr = A_L2_TX_DIG_TM_68,
12647        .ro = 0xffffff00,
12648    },{ .name = "L2_TX_DIG_TM_69",  .addr = A_L2_TX_DIG_TM_69,
12649        .ro = 0xffffff00,
12650    },{ .name = "L2_TX_DIG_TM_76",  .addr = A_L2_TX_DIG_TM_76,
12651        .ro = 0xffffff00,
12652    },{ .name = "L2_TX_DIG_TM_77",  .addr = A_L2_TX_DIG_TM_77,
12653        .ro = 0xffffff00,
12654    },{ .name = "L2_TX_DIG_TM_78",  .addr = A_L2_TX_DIG_TM_78,
12655        .ro = 0xffffff00,
12656    },{ .name = "L2_TX_DIG_TM_79",  .addr = A_L2_TX_DIG_TM_79,
12657        .ro = 0xffffff00,
12658    },{ .name = "L2_TX_DIG_TM_80",  .addr = A_L2_TX_DIG_TM_80,
12659        .ro = 0xffffff00,
12660    },{ .name = "L2_TX_DIG_TM_81",  .addr = A_L2_TX_DIG_TM_81,
12661        .ro = 0xffffff00,
12662    },{ .name = "L2_TX_DIG_TM_82",  .addr = A_L2_TX_DIG_TM_82,
12663        .ro = 0xffffff00,
12664    },{ .name = "L2_TX_DIG_TM_83",  .addr = A_L2_TX_DIG_TM_83,
12665        .ro = 0xfffffff0,
12666    },{ .name = "L2_TX_DIG_TM_84",  .addr = A_L2_TX_DIG_TM_84,
12667        .ro = 0xffffff0a,
12668    },{ .name = "L2_TX_ANA_TM_85",  .addr = A_L2_TX_ANA_TM_85,
12669        .ro = 0xffffffca,
12670    },{ .name = "L2_TX_ANA_TM_87",  .addr = A_L2_TX_ANA_TM_87,
12671        .ro = 0xfffffff0,
12672    },{ .name = "L2_TX_ANA_TM_88",  .addr = A_L2_TX_ANA_TM_88,
12673        .reset = 0x96,
12674        .ro = 0xffffff00,
12675    },{ .name = "L2_TX_ANA_TM_89",  .addr = A_L2_TX_ANA_TM_89,
12676        .ro = 0xffffffd9,
12677    },{ .name = "L2_TX_ANA_TM_90",  .addr = A_L2_TX_ANA_TM_90,
12678        .ro = 0xffffffdf,
12679    },{ .name = "L2_TX_DIG_TM_91",  .addr = A_L2_TX_DIG_TM_91,
12680        .reset = 0x1a,
12681        .ro = 0xffffff00,
12682    },{ .name = "L2_TX_DIG_TM_92",  .addr = A_L2_TX_DIG_TM_92,
12683        .reset = 0xa,
12684        .ro = 0xffffff00,
12685    },{ .name = "L2_TX_ANA_TM_95",  .addr = A_L2_TX_ANA_TM_95,
12686        .ro = 0xffffffc3,
12687    },{ .name = "L2_TX_ANA_TM_96",  .addr = A_L2_TX_ANA_TM_96,
12688        .ro = 0xffffff00,
12689    },{ .name = "L2_TX_ANA_TM_97",  .addr = A_L2_TX_ANA_TM_97,
12690        .ro = 0xffffff00,
12691    },{ .name = "L2_TX_DIG_TM_98",  .addr = A_L2_TX_DIG_TM_98,
12692        .ro = 0xffffffc0,
12693    },{ .name = "L2_TX_DIG_TM_99",  .addr = A_L2_TX_DIG_TM_99,
12694        .ro = 0xffffff00,
12695    },{ .name = "L2_TX_DIG_TM_100",  .addr = A_L2_TX_DIG_TM_100,
12696        .ro = 0xffffff00,
12697    },{ .name = "L2_TX_DIG_TM_101",  .addr = A_L2_TX_DIG_TM_101,
12698        .ro = 0xffffff00,
12699    },{ .name = "L2_TX_DIG_TM_102",  .addr = A_L2_TX_DIG_TM_102,
12700        .ro = 0xffffff00,
12701    },{ .name = "L2_TX_DIG_TM_103",  .addr = A_L2_TX_DIG_TM_103,
12702        .ro = 0xffffff00,
12703    },{ .name = "L2_TX_DIG_TM_104",  .addr = A_L2_TX_DIG_TM_104,
12704        .ro = 0xffffff00,
12705    },{ .name = "L2_TX_DIG_TM_105",  .addr = A_L2_TX_DIG_TM_105,
12706        .ro = 0xffffff00,
12707    },{ .name = "L2_TX_DIG_TM_106",  .addr = A_L2_TX_DIG_TM_106,
12708        .ro = 0xffffff00,
12709    },{ .name = "L2_TX_DIG_TM_107",  .addr = A_L2_TX_DIG_TM_107,
12710        .ro = 0xffffff80,
12711    },{ .name = "L2_TX_DIG_TM_108",  .addr = A_L2_TX_DIG_TM_108,
12712        .ro = 0xffffff80,
12713    },{ .name = "L2_TX_DIG_TM_109",  .addr = A_L2_TX_DIG_TM_109,
12714        .ro = 0xffffff00,
12715    },{ .name = "L2_TX_DIG_TM_110",  .addr = A_L2_TX_DIG_TM_110,
12716        .reset = 0x9,
12717        .ro = 0xffffff00,
12718    },{ .name = "L2_TX_DIG_TM_111",  .addr = A_L2_TX_DIG_TM_111,
12719        .ro = 0xffffff00,
12720    },{ .name = "L2_TX_ANA_TM_112",  .addr = A_L2_TX_ANA_TM_112,
12721        .ro = 0xffffffc0,
12722    },{ .name = "L2_TX_ANA_TM_113",  .addr = A_L2_TX_ANA_TM_113,
12723        .ro = 0xffffff00,
12724    },{ .name = "L2_TX_ANA_TM_114",  .addr = A_L2_TX_ANA_TM_114,
12725        .ro = 0xffffffe0,
12726    },{ .name = "L2_TX_ANA_TM_115",  .addr = A_L2_TX_ANA_TM_115,
12727        .ro = 0xffffff80,
12728    },{ .name = "L2_TX_ANA_TM_116",  .addr = A_L2_TX_ANA_TM_116,
12729        .ro = 0xffffff80,
12730    },{ .name = "L2_TX_ANA_TM_117",  .addr = A_L2_TX_ANA_TM_117,
12731        .ro = 0xffffffc0,
12732    },{ .name = "L2_TX_ANA_TM_118",  .addr = A_L2_TX_ANA_TM_118,
12733        .ro = 0xfffffff0,
12734    },{ .name = "L2_TXPMA_TM_0",  .addr = A_L2_TXPMA_TM_0,
12735        .ro = 0xffffff00,
12736    },{ .name = "L2_TXPMA_TM_1",  .addr = A_L2_TXPMA_TM_1,
12737        .ro = 0xfffffff0,
12738    },{ .name = "L2_TXPMA_TM_2",  .addr = A_L2_TXPMA_TM_2,
12739        .ro = 0xffffff00,
12740    },{ .name = "L2_TXPMA_TM_3",  .addr = A_L2_TXPMA_TM_3,
12741        .ro = 0xffffffe0,
12742    },{ .name = "L2_TXPMA_TM_4",  .addr = A_L2_TXPMA_TM_4,
12743        .reset = 0x2,
12744        .ro = 0xffffff01,
12745    },{ .name = "L2_TXPMA_TM_5",  .addr = A_L2_TXPMA_TM_5,
12746        .ro = 0xfffffff0,
12747    },{ .name = "L2_TXPMA_TM_6",  .addr = A_L2_TXPMA_TM_6,
12748        .ro = 0xffffff00,
12749    },{ .name = "L2_TXPMA_TM_7",  .addr = A_L2_TXPMA_TM_7,
12750        .ro = 0xffffff00,
12751    },{ .name = "L2_TXPMA_TM_8",  .addr = A_L2_TXPMA_TM_8,
12752        .ro = 0xfffffffc,
12753    },{ .name = "L2_TXPMA_TM_9",  .addr = A_L2_TXPMA_TM_9,
12754        .ro = 0xffffff80,
12755    },{ .name = "L2_TXPMA_TM_10",  .addr = A_L2_TXPMA_TM_10,
12756        .ro = 0xffffffc0,
12757    },{ .name = "L2_TXPMA_TM_11",  .addr = A_L2_TXPMA_TM_11,
12758        .ro = 0xffffffe0,
12759    },{ .name = "L2_TXPMA_TM_12",  .addr = A_L2_TXPMA_TM_12,
12760        .ro = 0xffffff01,
12761    },{ .name = "L2_TXPMA_TM_13",  .addr = A_L2_TXPMA_TM_13,
12762        .ro = 0xffffff00,
12763    },{ .name = "L2_TXPMA_TM_14",  .addr = A_L2_TXPMA_TM_14,
12764        .ro = 0xffffffe0,
12765    },{ .name = "L2_TXPMA_TM_15",  .addr = A_L2_TXPMA_TM_15,
12766        .ro = 0xffffff00,
12767    },{ .name = "L2_TXPMA_TM_16",  .addr = A_L2_TXPMA_TM_16,
12768        .ro = 0xffffff00,
12769    },{ .name = "L2_TXPMA_TM_17",  .addr = A_L2_TXPMA_TM_17,
12770        .ro = 0xffffff00,
12771    },{ .name = "L2_TXPMA_TM_18",  .addr = A_L2_TXPMA_TM_18,
12772        .reset = 0xf,
12773        .ro = 0xffffff00,
12774    },{ .name = "L2_TXPMA_TM_19",  .addr = A_L2_TXPMA_TM_19,
12775        .reset = 0x3,
12776        .ro = 0xffffffc0,
12777    },{ .name = "L2_TXPMA_TM_20",  .addr = A_L2_TXPMA_TM_20,
12778        .reset = 0x6,
12779        .ro = 0xffffff00,
12780    },{ .name = "L2_TXPMA_TM_21",  .addr = A_L2_TXPMA_TM_21,
12781        .reset = 0x3,
12782        .ro = 0xffffff00,
12783    },{ .name = "L2_TXPMA_TM_22",  .addr = A_L2_TXPMA_TM_22,
12784        .reset = 0x6,
12785        .ro = 0xffffff00,
12786    },{ .name = "L2_TXPMA_TM_23",  .addr = A_L2_TXPMA_TM_23,
12787        .reset = 0x3,
12788        .ro = 0xffffff00,
12789    },{ .name = "L2_TXPMA_TM_24",  .addr = A_L2_TXPMA_TM_24,
12790        .ro = 0xffffff80,
12791    },{ .name = "L2_TXPMA_TM_25",  .addr = A_L2_TXPMA_TM_25,
12792        .ro = 0xffffffc0,
12793    },{ .name = "L2_TXPMA_TM_26",  .addr = A_L2_TXPMA_TM_26,
12794        .reset = 0x64,
12795        .ro = 0xffffff00,
12796    },{ .name = "L2_TXPMA_TM_27",  .addr = A_L2_TXPMA_TM_27,
12797        .ro = 0xffffff00,
12798    },{ .name = "L2_TXPMA_ST_0",  .addr = A_L2_TXPMA_ST_0,
12799        .reset = 0x1,
12800        .ro = 0xffffffff,
12801    },{ .name = "L2_TXPMA_ST_1",  .addr = A_L2_TXPMA_ST_1,
12802        .reset = 0x1,
12803        .ro = 0xffffffff,
12804    },{ .name = "L2_TXPMA_ST_2",  .addr = A_L2_TXPMA_ST_2,
12805        .reset = 0x4,
12806        .ro = 0xffffffff,
12807    },{ .name = "L2_TXPMA_ST_3",  .addr = A_L2_TXPMA_ST_3,
12808        .reset = 0x20,
12809        .ro = 0xffffffff,
12810    },{ .name = "L2_TXPMA_ST_4",  .addr = A_L2_TXPMA_ST_4,
12811        .reset = 0x20,
12812        .ro = 0xffffffff,
12813    },{ .name = "L2_TXPMA_ST_5",  .addr = A_L2_TXPMA_ST_5,
12814        .reset = 0x20,
12815        .ro = 0xffffffff,
12816    },{ .name = "L2_TXPMA_ST_6",  .addr = A_L2_TXPMA_ST_6,
12817        .reset = 0xb,
12818        .ro = 0xffffffff,
12819    },{ .name = "L2_TXPMA_ST_7",  .addr = A_L2_TXPMA_ST_7,
12820        .ro = 0xffffffff,
12821    },{ .name = "L2_TXPMA_ST_8",  .addr = A_L2_TXPMA_ST_8,
12822        .ro = 0xffffffff,
12823    },{ .name = "L2_TXPMA_ST_9",  .addr = A_L2_TXPMA_ST_9,
12824        .ro = 0xffffffff,
12825    },{ .name = "L2_TXPMD_TM_0",  .addr = A_L2_TXPMD_TM_0,
12826        .ro = 0xffffffe0,
12827    },{ .name = "L2_TXPMD_TM_1",  .addr = A_L2_TXPMD_TM_1,
12828        .ro = 0xffffffe0,
12829    },{ .name = "L2_TXPMD_TM_2",  .addr = A_L2_TXPMD_TM_2,
12830        .ro = 0xffffffe0,
12831    },{ .name = "L2_TXPMD_TM_3",  .addr = A_L2_TXPMD_TM_3,
12832        .ro = 0xffffffe0,
12833    },{ .name = "L2_TXPMD_TM_4",  .addr = A_L2_TXPMD_TM_4,
12834        .ro = 0xffffffe0,
12835    },{ .name = "L2_TXPMD_TM_5",  .addr = A_L2_TXPMD_TM_5,
12836        .ro = 0xffffffe0,
12837    },{ .name = "L2_TXPMD_TM_6",  .addr = A_L2_TXPMD_TM_6,
12838        .ro = 0xffffffe0,
12839    },{ .name = "L2_TXPMD_TM_7",  .addr = A_L2_TXPMD_TM_7,
12840        .ro = 0xffffffe0,
12841    },{ .name = "L2_TXPMD_TM_8",  .addr = A_L2_TXPMD_TM_8,
12842        .ro = 0xffffffe0,
12843    },{ .name = "L2_TXPMD_TM_9",  .addr = A_L2_TXPMD_TM_9,
12844        .ro = 0xffffffe0,
12845    },{ .name = "L2_TXPMD_TM_10",  .addr = A_L2_TXPMD_TM_10,
12846        .ro = 0xffffffe0,
12847    },{ .name = "L2_TXPMD_TM_11",  .addr = A_L2_TXPMD_TM_11,
12848        .ro = 0xffffffe0,
12849    },{ .name = "L2_TXPMD_TM_12",  .addr = A_L2_TXPMD_TM_12,
12850        .ro = 0xffffffe0,
12851    },{ .name = "L2_TXPMD_TM_13",  .addr = A_L2_TXPMD_TM_13,
12852        .ro = 0xffffffe0,
12853    },{ .name = "L2_TXPMD_TM_14",  .addr = A_L2_TXPMD_TM_14,
12854        .ro = 0xffffffe0,
12855    },{ .name = "L2_TXPMD_TM_15",  .addr = A_L2_TXPMD_TM_15,
12856        .ro = 0xffffffe0,
12857    },{ .name = "L2_TXPMD_TM_16",  .addr = A_L2_TXPMD_TM_16,
12858        .ro = 0xffffffe0,
12859    },{ .name = "L2_TXPMD_TM_17",  .addr = A_L2_TXPMD_TM_17,
12860        .ro = 0xffffffe0,
12861    },{ .name = "L2_TXPMD_TM_18",  .addr = A_L2_TXPMD_TM_18,
12862        .ro = 0xffffffe0,
12863    },{ .name = "L2_TXPMD_TM_19",  .addr = A_L2_TXPMD_TM_19,
12864        .ro = 0xffffffe0,
12865    },{ .name = "L2_TXPMD_TM_20",  .addr = A_L2_TXPMD_TM_20,
12866        .ro = 0xffffffe0,
12867    },{ .name = "L2_TXPMD_TM_21",  .addr = A_L2_TXPMD_TM_21,
12868        .ro = 0xffffffe0,
12869    },{ .name = "L2_TXPMD_TM_22",  .addr = A_L2_TXPMD_TM_22,
12870        .ro = 0xffffffe0,
12871    },{ .name = "L2_TXPMD_TM_23",  .addr = A_L2_TXPMD_TM_23,
12872        .ro = 0xffffffe0,
12873    },{ .name = "L2_TXPMD_TM_24",  .addr = A_L2_TXPMD_TM_24,
12874        .ro = 0xffffffe0,
12875    },{ .name = "L2_TXPMD_TM_25",  .addr = A_L2_TXPMD_TM_25,
12876        .ro = 0xffffffe0,
12877    },{ .name = "L2_TXPMD_TM_26",  .addr = A_L2_TXPMD_TM_26,
12878        .ro = 0xffffffe0,
12879    },{ .name = "L2_TXPMD_TM_27",  .addr = A_L2_TXPMD_TM_27,
12880        .ro = 0xffffffe0,
12881    },{ .name = "L2_TXPMD_TM_28",  .addr = A_L2_TXPMD_TM_28,
12882        .ro = 0xffffffe0,
12883    },{ .name = "L2_TXPMD_TM_29",  .addr = A_L2_TXPMD_TM_29,
12884        .ro = 0xffffffe0,
12885    },{ .name = "L2_TXPMD_TM_30",  .addr = A_L2_TXPMD_TM_30,
12886        .ro = 0xffffffe0,
12887    },{ .name = "L2_TXPMD_TM_31",  .addr = A_L2_TXPMD_TM_31,
12888        .ro = 0xffffffe0,
12889    },{ .name = "L2_TXPMD_TM_32",  .addr = A_L2_TXPMD_TM_32,
12890        .ro = 0xffffff00,
12891    },{ .name = "L2_TXPMD_TM_33",  .addr = A_L2_TXPMD_TM_33,
12892        .ro = 0xffffff00,
12893    },{ .name = "L2_TXPMD_TM_34",  .addr = A_L2_TXPMD_TM_34,
12894        .ro = 0xffffff00,
12895    },{ .name = "L2_TXPMD_TM_35",  .addr = A_L2_TXPMD_TM_35,
12896        .ro = 0xffffff00,
12897    },{ .name = "L2_TXPMD_TM_36",  .addr = A_L2_TXPMD_TM_36,
12898        .ro = 0xffffff00,
12899    },{ .name = "L2_TXPMD_TM_37",  .addr = A_L2_TXPMD_TM_37,
12900        .ro = 0xffffff00,
12901    },{ .name = "L2_TXPMD_TM_38",  .addr = A_L2_TXPMD_TM_38,
12902        .ro = 0xffffff80,
12903    },{ .name = "L2_TXPMD_TM_39",  .addr = A_L2_TXPMD_TM_39,
12904        .ro = 0xfffffff8,
12905    },{ .name = "L2_TXPMD_TM_40",  .addr = A_L2_TXPMD_TM_40,
12906        .ro = 0xffffff00,
12907    },{ .name = "L2_TXPMD_TM_41",  .addr = A_L2_TXPMD_TM_41,
12908        .ro = 0xffffff00,
12909    },{ .name = "L2_TXPMD_TM_42",  .addr = A_L2_TXPMD_TM_42,
12910        .ro = 0xffffffe0,
12911    },{ .name = "L2_TXPMD_TM_43",  .addr = A_L2_TXPMD_TM_43,
12912        .ro = 0xfffffff0,
12913    },{ .name = "L2_TXPMD_TM_44",  .addr = A_L2_TXPMD_TM_44,
12914        .ro = 0xffffffc0,
12915    },{ .name = "L2_TXPMD_TM_45",  .addr = A_L2_TXPMD_TM_45,
12916        .ro = 0xffffffc0,
12917    },{ .name = "L2_TXPMD_TM_46",  .addr = A_L2_TXPMD_TM_46,
12918        .ro = 0xffffffc0,
12919    },{ .name = "L2_TXPMD_TM_47",  .addr = A_L2_TXPMD_TM_47,
12920        .ro = 0xffffff00,
12921    },{ .name = "L2_TXPMD_TM_48",  .addr = A_L2_TXPMD_TM_48,
12922        .ro = 0xffffffc0,
12923    },{ .name = "L2_TM_ANA_BYP_1",  .addr = A_L2_TM_ANA_BYP_1,
12924        .ro = 0xffffff00,
12925    },{ .name = "L2_TM_ANA_BYP_2",  .addr = A_L2_TM_ANA_BYP_2,
12926        .ro = 0xffffff00,
12927    },{ .name = "L2_TM_ANA_BYP_3",  .addr = A_L2_TM_ANA_BYP_3,
12928        .ro = 0xffffff00,
12929    },{ .name = "L2_TM_ANA_BYP_4",  .addr = A_L2_TM_ANA_BYP_4,
12930        .ro = 0xffffff00,
12931    },{ .name = "L2_TM_ANA_BYP_5",  .addr = A_L2_TM_ANA_BYP_5,
12932        .rsvd = 0xc0,
12933        .ro = 0xffffffc0,
12934    },{ .name = "L2_TM_ANA_BYP_7",  .addr = A_L2_TM_ANA_BYP_7,
12935        .rsvd = 0xf,
12936        .ro = 0xffffff0f,
12937    },{ .name = "L2_TM_ANA_BYP_8",  .addr = A_L2_TM_ANA_BYP_8,
12938        .ro = 0xffffff00,
12939    },{ .name = "L2_TM_ANA_BYP_9",  .addr = A_L2_TM_ANA_BYP_9,
12940        .ro = 0xffffff00,
12941    },{ .name = "L2_TM_ANA_BYP_10",  .addr = A_L2_TM_ANA_BYP_10,
12942        .rsvd = 0xc0,
12943        .ro = 0xffffffc0,
12944    },{ .name = "L2_TM_ANA_BYP_11",  .addr = A_L2_TM_ANA_BYP_11,
12945        .rsvd = 0xc0,
12946        .ro = 0xffffffc0,
12947    },{ .name = "L2_TM_ANA_BYP_12",  .addr = A_L2_TM_ANA_BYP_12,
12948        .ro = 0xffffff00,
12949    },{ .name = "L2_TM_ANA_BYP_13",  .addr = A_L2_TM_ANA_BYP_13,
12950        .rsvd = 0xfc,
12951        .ro = 0xfffffffc,
12952    },{ .name = "L2_TM_ANA_BYP_14",  .addr = A_L2_TM_ANA_BYP_14,
12953        .rsvd = 0xc,
12954        .ro = 0xffffff0c,
12955    },{ .name = "L2_TM_ANA_BYP_15",  .addr = A_L2_TM_ANA_BYP_15,
12956        .ro = 0xffffff00,
12957    },{ .name = "L2_TM_ANA_BYP_16",  .addr = A_L2_TM_ANA_BYP_16,
12958        .ro = 0xffffff00,
12959    },{ .name = "L2_TM_ANA_BYP_17",  .addr = A_L2_TM_ANA_BYP_17,
12960        .rsvd = 0x80,
12961        .ro = 0xffffff80,
12962    },{ .name = "L2_TM_ANA_BYP_18",  .addr = A_L2_TM_ANA_BYP_18,
12963        .rsvd = 0xf0,
12964        .ro = 0xfffffff0,
12965    },{ .name = "L2_TM_ANA_BYP_20",  .addr = A_L2_TM_ANA_BYP_20,
12966        .ro = 0xffffff00,
12967    },{ .name = "L2_TM_ANA_BYP_21",  .addr = A_L2_TM_ANA_BYP_21,
12968        .ro = 0xffffff00,
12969    },{ .name = "L2_TM_ANA_BYP_22",  .addr = A_L2_TM_ANA_BYP_22,
12970        .ro = 0xffffff00,
12971    },{ .name = "L2_TM_ANA_BYP_23",  .addr = A_L2_TM_ANA_BYP_23,
12972        .ro = 0xffffff00,
12973    },{ .name = "L2_TM_DIG_1",  .addr = A_L2_TM_DIG_1,
12974        .reset = 0x40,
12975        .ro = 0xffffff00,
12976    },{ .name = "L2_TM_DIG_2",  .addr = A_L2_TM_DIG_2,
12977        .rsvd = 0xc0,
12978        .ro = 0xffffffc0,
12979    },{ .name = "L2_TM_DIG_3",  .addr = A_L2_TM_DIG_3,
12980        .ro = 0xffffff00,
12981    },{ .name = "L2_TM_DIG_4",  .addr = A_L2_TM_DIG_4,
12982        .rsvd = 0x7,
12983        .ro = 0xffffff07,
12984    },{ .name = "L2_TM_DIG_5",  .addr = A_L2_TM_DIG_5,
12985        .rsvd = 0xf8,
12986        .ro = 0xfffffff8,
12987    },{ .name = "L2_TM_DIG_6",  .addr = A_L2_TM_DIG_6,
12988        .rsvd = 0x80,
12989        .ro = 0xffffff80,
12990    },{ .name = "L2_TM_DIG_7",  .addr = A_L2_TM_DIG_7,
12991        .ro = 0xffffff00,
12992    },{ .name = "L2_TM_DIG_8",  .addr = A_L2_TM_DIG_8,
12993        .rsvd = 0xe0,
12994        .ro = 0xffffffe0,
12995    },{ .name = "L2_TM_DIG_9",  .addr = A_L2_TM_DIG_9,
12996        .rsvd = 0xf0,
12997        .ro = 0xfffffff0,
12998    },{ .name = "L2_TM_DIG_10",  .addr = A_L2_TM_DIG_10,
12999        .reset = 0x1,
13000        .rsvd = 0xf0,

13001        .ro = 0xfffffff0,
13002    },{ .name = "L2_TM_DIG_11",  .addr = A_L2_TM_DIG_11,
13003        .rsvd = 0xf,
13004        .ro = 0xffffff0f,
13005    },{ .name = "L2_TM_DIG_12",  .addr = A_L2_TM_DIG_12,
13006        .rsvd = 0xc0,
13007        .ro = 0xffffffc0,
13008    },{ .name = "L2_TM_DIG_13",  .addr = A_L2_TM_DIG_13,
13009        .reset = 0x1a,
13010        .rsvd = 0x80,
13011        .ro = 0xffffff80,
13012    },{ .name = "L2_TM_DIG_14",  .addr = A_L2_TM_DIG_14,
13013        .rsvd = 0xf,
13014        .ro = 0xffffff0f,
13015    },{ .name = "L2_TM_DIG_15",  .addr = A_L2_TM_DIG_15,
13016        .reset = 0xd,
13017        .rsvd = 0xc0,
13018        .ro = 0xffffffc0,
13019    },{ .name = "L2_TM_DIG_16",  .addr = A_L2_TM_DIG_16,
13020        .rsvd = 0xe0,
13021        .ro = 0xffffffe0,
13022    },{ .name = "L2_TM_DIG_17",  .addr = A_L2_TM_DIG_17,
13023        .rsvd = 0xe0,
13024        .ro = 0xffffffe0,
13025    },{ .name = "L2_TM_DIG_18",  .addr = A_L2_TM_DIG_18,
13026        .reset = 0x2a,
13027        .ro = 0xffffff00,
13028    },{ .name = "L2_TM_DIG_19",  .addr = A_L2_TM_DIG_19,
13029        .reset = 0x36,
13030        .ro = 0xffffff00,
13031    },{ .name = "L2_TM_DIG_20",  .addr = A_L2_TM_DIG_20,
13032        .reset = 0x10,
13033        .rsvd = 0x80,
13034        .ro = 0xffffff80,
13035    },{ .name = "L2_TM_DIG_21",  .addr = A_L2_TM_DIG_21,
13036        .rsvd = 0xe0,
13037        .ro = 0xffffffe0,
13038    },{ .name = "L2_TM_DIG_22",  .addr = A_L2_TM_DIG_22,
13039        .rsvd = 0xc0,
13040        .ro = 0xffffffc0,
13041    },{ .name = "L2_TM_DIG_23",  .addr = A_L2_TM_DIG_23,
13042        .reset = 0x5,
13043        .ro = 0xffffff00,
13044    },{ .name = "L2_TM_DIG_24",  .addr = A_L2_TM_DIG_24,
13045        .ro = 0xffffff00,
13046    },{ .name = "L2_TM_DIG_25",  .addr = A_L2_TM_DIG_25,
13047        .ro = 0xffffff00,
13048    },{ .name = "L2_TM_DIG_26",  .addr = A_L2_TM_DIG_26,
13049        .ro = 0xffffff00,
13050    },{ .name = "L2_TM_DIG_27",  .addr = A_L2_TM_DIG_27,
13051        .ro = 0xffffff00,
13052    },{ .name = "L2_TM_DIG_28",  .addr = A_L2_TM_DIG_28,
13053        .ro = 0xffffff00,
13054    },{ .name = "L2_TM_DIG_29",  .addr = A_L2_TM_DIG_29,
13055        .ro = 0xffffff00,
13056    },{ .name = "L2_TM_AUX_0",  .addr = A_L2_TM_AUX_0,
13057        .ro = 0xffffff00,
13058    },{ .name = "L2_TM_AUX_1",  .addr = A_L2_TM_AUX_1,
13059        .ro = 0xffffff00,
13060    },{ .name = "L2_TM_AUX_2",  .addr = A_L2_TM_AUX_2,
13061        .ro = 0xffffff00,
13062    },{ .name = "L2_TM_AUX_3",  .addr = A_L2_TM_AUX_3,
13063        .ro = 0xffffff00,
13064    },{ .name = "L2_TM_AUX_4",  .addr = A_L2_TM_AUX_4,
13065        .ro = 0xffffff00,
13066    },{ .name = "L2_TM_DIG_30",  .addr = A_L2_TM_DIG_30,
13067        .rsvd = 0xc0,
13068        .ro = 0xffffffc0,
13069    },{ .name = "L2_TM_DIG_31",  .addr = A_L2_TM_DIG_31,
13070        .reset = 0xfa,
13071        .ro = 0xffffff00,
13072    },{ .name = "L2_TM_DIG_32",  .addr = A_L2_TM_DIG_32,
13073        .reset = 0xfa,
13074        .ro = 0xffffff00,
13075    },{ .name = "L2_TM_DIG_33",  .addr = A_L2_TM_DIG_33,
13076        .ro = 0xffffff00,
13077    },{ .name = "L2_TM_DIG_34",  .addr = A_L2_TM_DIG_34,
13078        .reset = 0x1e,
13079        .rsvd = 0xc0,
13080        .ro = 0xffffffc0,
13081    },{ .name = "L2_TM_DIG_35",  .addr = A_L2_TM_DIG_35,
13082        .reset = 0x18,
13083        .rsvd = 0xc0,
13084        .ro = 0xffffffc0,
13085    },{ .name = "L2_TM_DIG_36",  .addr = A_L2_TM_DIG_36,
13086        .ro = 0xffffff00,
13087    },{ .name = "L2_TM_DIG_37",  .addr = A_L2_TM_DIG_37,
13088        .rsvd = 0xe0,
13089        .ro = 0xffffffe0,
13090    },{ .name = "L2_TM_LFPS_1",  .addr = A_L2_TM_LFPS_1,
13091        .reset = 0x88,
13092        .ro = 0xffffff00,
13093    },{ .name = "L2_TM_LFPS_2",  .addr = A_L2_TM_LFPS_2,
13094        .reset = 0x34,
13095        .rsvd = 0x80,
13096        .ro = 0xffffff80,
13097    },{ .name = "L2_TM_LFPS_3",  .addr = A_L2_TM_LFPS_3,
13098        .reset = 0x6c,
13099        .ro = 0xffffff00,
13100    },{ .name = "L2_TM_LFPS_4",  .addr = A_L2_TM_LFPS_4,
13101        .rsvd = 0xc0,
13102        .ro = 0xffffffc0,
13103    },{ .name = "L2_TM_RXPMA_1",  .addr = A_L2_TM_RXPMA_1,
13104        .ro = 0xffffff00,
13105    },{ .name = "L2_TM_BSCAN_1",  .addr = A_L2_TM_BSCAN_1,
13106        .rsvd = 0xf8,
13107        .ro = 0xfffffff8,
13108    },{ .name = "L2_TM_MPHY_SQ_1",  .addr = A_L2_TM_MPHY_SQ_1,
13109        .reset = 0x1,
13110        .rsvd = 0xe0,
13111        .ro = 0xffffffe0,
13112    },{ .name = "L2_TM_LSRX_1",  .addr = A_L2_TM_LSRX_1,
13113        .ro = 0xffffff00,
13114    },{ .name = "L2_TM_LSRX_2",  .addr = A_L2_TM_LSRX_2,
13115        .rsvd = 0xc0,
13116        .ro = 0xffffffc0,
13117    },{ .name = "L2_TM_SIGDET_1",  .addr = A_L2_TM_SIGDET_1,
13118        .reset = 0x34,
13119        .rsvd = 0x80,
13120        .ro = 0xffffff80,
13121    },{ .name = "L2_TM_SIGDET_2",  .addr = A_L2_TM_SIGDET_2,
13122        .reset = 0xf,
13123        .ro = 0xffffff00,
13124    },{ .name = "L2_TM_DFT_1",  .addr = A_L2_TM_DFT_1,
13125        .rsvd = 0x7,
13126        .ro = 0xffffff07,
13127    },{ .name = "L2_TM_DFT_2",  .addr = A_L2_TM_DFT_2,
13128        .rsvd = 0xf8,
13129        .ro = 0xfffffff8,
13130    },{ .name = "L2_TM_DFT_3",  .addr = A_L2_TM_DFT_3,
13131        .rsvd = 0xe0,
13132        .ro = 0xffffffe0,
13133    },{ .name = "L2_TM_DFT_4",  .addr = A_L2_TM_DFT_4,
13134        .rsvd = 0xfc,
13135        .ro = 0xfffffffc,
13136    },{ .name = "L2_TM_DFT_5",  .addr = A_L2_TM_DFT_5,
13137        .ro = 0xffffff00,
13138    },{ .name = "L2_TM_DFT_6",  .addr = A_L2_TM_DFT_6,
13139        .ro = 0xffffff00,
13140    },{ .name = "L2_TM_DFT_7",  .addr = A_L2_TM_DFT_7,
13141        .rsvd = 0xe0,
13142        .ro = 0xffffffe0,
13143    },{ .name = "L2_TM_DFT_8",  .addr = A_L2_TM_DFT_8,
13144        .rsvd = 0xe0,
13145        .ro = 0xffffffe0,
13146    },{ .name = "L2_TM_DFT_9",  .addr = A_L2_TM_DFT_9,
13147        .ro = 0xffffff00,
13148    },{ .name = "L2_TM_DFT_10",  .addr = A_L2_TM_DFT_10,
13149        .rsvd = 0xf0,
13150        .ro = 0xfffffff0,
13151    },{ .name = "L2_TM_BG_1",  .addr = A_L2_TM_BG_1,
13152        .ro = 0xffffff00,
13153    },{ .name = "L2_TM_BG_2",  .addr = A_L2_TM_BG_2,
13154        .ro = 0xffffff00,
13155    },{ .name = "L2_TM_BG_3",  .addr = A_L2_TM_BG_3,
13156        .ro = 0xffffff00,
13157    },{ .name = "L2_TM_BG_4",  .addr = A_L2_TM_BG_4,
13158        .ro = 0xffffff00,
13159    },{ .name = "L2_TM_BG_5",  .addr = A_L2_TM_BG_5,
13160        .ro = 0xffffff00,
13161    },{ .name = "L2_TM_BG_6",  .addr = A_L2_TM_BG_6,
13162        .ro = 0xffffff00,
13163    },{ .name = "L2_TM_BG_7",  .addr = A_L2_TM_BG_7,
13164        .ro = 0xffffff00,
13165    },{ .name = "L2_TM_BG_8",  .addr = A_L2_TM_BG_8,
13166        .ro = 0xffffff00,
13167    },{ .name = "L2_TM_BG_9",  .addr = A_L2_TM_BG_9,
13168        .ro = 0xffffff00,
13169    },{ .name = "L2_TM_BG_10",  .addr = A_L2_TM_BG_10,
13170        .ro = 0xffffff00,
13171    },{ .name = "L2_TM_SD0",  .addr = A_L2_TM_SD0,
13172        .ro = 0xffffff00,
13173    },{ .name = "L2_TM_SD1",  .addr = A_L2_TM_SD1,
13174        .ro = 0xffffff00,
13175    },{ .name = "L2_TM_SD2",  .addr = A_L2_TM_SD2,
13176        .ro = 0xffffff00,
13177    },{ .name = "L2_TM_SD3",  .addr = A_L2_TM_SD3,
13178        .reset = 0x4,
13179        .ro = 0xffffff00,
13180    },{ .name = "L2_TM_SD4",  .addr = A_L2_TM_SD4,
13181        .rsvd = 0xe0,
13182        .ro = 0xffffffe0,
13183    },{ .name = "L2_TM_SD5",  .addr = A_L2_TM_SD5,
13184        .reset = 0xa,
13185        .ro = 0xffffff00,
13186    },{ .name = "L2_TM_SD6",  .addr = A_L2_TM_SD6,
13187        .rsvd = 0xe0,
13188        .ro = 0xffffffe0,
13189    },{ .name = "L2_TM_MISC1",  .addr = A_L2_TM_MISC1,
13190        .ro = 0xffffff00,
13191    },{ .name = "L2_TM_MISC2",  .addr = A_L2_TM_MISC2,
13192        .ro = 0xffffff03,
13193    },{ .name = "L2_TM_EYE_SURF0",  .addr = A_L2_TM_EYE_SURF0,
13194        .ro = 0xffffff80,
13195    },{ .name = "L2_TM_EYE_SURF1",  .addr = A_L2_TM_EYE_SURF1,
13196        .ro = 0xffffff00,
13197    },{ .name = "L2_TM_EYE_SURF2",  .addr = A_L2_TM_EYE_SURF2,
13198        .ro = 0xffffff00,
13199    },{ .name = "L2_TM_EYE_SURF3",  .addr = A_L2_TM_EYE_SURF3,
13200        .ro = 0xffffff00,
13201    },{ .name = "L2_TM_EYE_SURF4",  .addr = A_L2_TM_EYE_SURF4,
13202        .ro = 0xffffff00,
13203    },{ .name = "L2_TM_EYE_SURF5",  .addr = A_L2_TM_EYE_SURF5,
13204        .ro = 0xffffff00,
13205    },{ .name = "L2_TM_EYE_SURF6",  .addr = A_L2_TM_EYE_SURF6,
13206        .ro = 0xffffff00,
13207    },{ .name = "L2_TM_EYE_SURF7",  .addr = A_L2_TM_EYE_SURF7,
13208        .ro = 0xffffff00,
13209    },{ .name = "L2_TM_EYE_SURF8",  .addr = A_L2_TM_EYE_SURF8,
13210        .ro = 0xffffff00,
13211    },{ .name = "L2_TM_EYE_SURF9",  .addr = A_L2_TM_EYE_SURF9,
13212        .ro = 0xffffff00,
13213    },{ .name = "L2_TM_SPARE",  .addr = A_L2_TM_SPARE,
13214        .ro = 0xffffff00,
13215    },{ .name = "L2_TM_ANA_EQ1",  .addr = A_L2_TM_ANA_EQ1,
13216        .reset = 0xc,
13217        .ro = 0xffffffe0,
13218    },{ .name = "L2_TM_ANA_E_PI0",  .addr = A_L2_TM_ANA_E_PI0,
13219        .reset = 0xa0,
13220        .ro = 0xffffff1f,
13221    },{ .name = "L2_TM_ANA_IQ_PI0",  .addr = A_L2_TM_ANA_IQ_PI0,
13222        .reset = 0xa0,
13223        .ro = 0xffffff1f,
13224    },{ .name = "L2_TM_ANA_MISC0",  .addr = A_L2_TM_ANA_MISC0,
13225        .ro = 0xffffff3f,
13226    },{ .name = "L2_TM_SAMP_CODE_IQ_PH0",  .addr = A_L2_TM_SAMP_CODE_IQ_PH0,
13227        .ro = 0xffffff80,
13228    },{ .name = "L2_TM_SAMP_CODE_IQ_PH90",  .addr = A_L2_TM_SAMP_CODE_IQ_PH90,
13229        .ro = 0xffffff00,
13230    },{ .name = "L2_TM_SAMP_CODE_IQ_PH180",  .addr = A_L2_TM_SAMP_CODE_IQ_PH180,
13231        .ro = 0xffffffc0,
13232    },{ .name = "L2_TM_SAMP_CODE_IQ_PH270",  .addr = A_L2_TM_SAMP_CODE_IQ_PH270,
13233        .ro = 0xffffff00,
13234    },{ .name = "L2_TM_SAMP_CODE_E_PH0",  .addr = A_L2_TM_SAMP_CODE_E_PH0,
13235        .ro = 0xffffffc0,
13236    },{ .name = "L2_TM_SAMP_CODE_E_PH180",  .addr = A_L2_TM_SAMP_CODE_E_PH180,
13237        .ro = 0xffffffc0,
13238    },{ .name = "L2_TM_IQ_ILL0",  .addr = A_L2_TM_IQ_ILL0,
13239        .ro = 0xffffff00,
13240    },{ .name = "L2_TM_IQ_ILL1",  .addr = A_L2_TM_IQ_ILL1,
13241        .ro = 0xffffff00,
13242    },{ .name = "L2_TM_IQ_ILL2",  .addr = A_L2_TM_IQ_ILL2,
13243        .ro = 0xffffff00,
13244    },{ .name = "L2_TM_IQ_ILL3",  .addr = A_L2_TM_IQ_ILL3,
13245        .ro = 0xffffff00,
13246    },{ .name = "L2_TM_IQ_ILL4",  .addr = A_L2_TM_IQ_ILL4,
13247        .ro = 0xffffff00,
13248    },{ .name = "L2_TM_IQ_ILL5",  .addr = A_L2_TM_IQ_ILL5,
13249        .ro = 0xffffff00,
13250    },{ .name = "L2_TM_IQ_ILL6",  .addr = A_L2_TM_IQ_ILL6,
13251        .ro = 0xffffff00,
13252    },{ .name = "L2_TM_IQ_ILL7",  .addr = A_L2_TM_IQ_ILL7,
13253        .ro = 0xffffff00,
13254    },{ .name = "L2_TM_IQ_ILL8",  .addr = A_L2_TM_IQ_ILL8,
13255        .ro = 0xffffff00,
13256    },{ .name = "L2_TM_IQ_ILL9",  .addr = A_L2_TM_IQ_ILL9,
13257        .ro = 0xfffffff0,
13258    },{ .name = "L2_TM_IQ_ILL10",  .addr = A_L2_TM_IQ_ILL10,
13259        .reset = 0x3,
13260        .ro = 0xffffffc0,
13261    },{ .name = "L2_TM_E_ILL0",  .addr = A_L2_TM_E_ILL0,
13262        .ro = 0xffffff00,
13263    },{ .name = "L2_TM_E_ILL1",  .addr = A_L2_TM_E_ILL1,
13264        .ro = 0xffffff00,
13265    },{ .name = "L2_TM_E_ILL2",  .addr = A_L2_TM_E_ILL2,
13266        .ro = 0xffffff00,
13267    },{ .name = "L2_TM_E_ILL3",  .addr = A_L2_TM_E_ILL3,
13268        .ro = 0xffffff00,
13269    },{ .name = "L2_TM_E_ILL4",  .addr = A_L2_TM_E_ILL4,
13270        .ro = 0xffffff00,
13271    },{ .name = "L2_TM_E_ILL5",  .addr = A_L2_TM_E_ILL5,
13272        .ro = 0xffffff00,
13273    },{ .name = "L2_TM_E_ILL6",  .addr = A_L2_TM_E_ILL6,
13274        .ro = 0xffffff00,
13275    },{ .name = "L2_TM_E_ILL7",  .addr = A_L2_TM_E_ILL7,
13276        .ro = 0xffffff00,
13277    },{ .name = "L2_TM_E_ILL8",  .addr = A_L2_TM_E_ILL8,
13278        .ro = 0xffffff00,
13279    },{ .name = "L2_TM_E_ILL9",  .addr = A_L2_TM_E_ILL9,
13280        .ro = 0xfffffff0,
13281    },{ .name = "L2_TM_E_ILL10",  .addr = A_L2_TM_E_ILL10,
13282        .reset = 0x3,
13283        .ro = 0xffffffc0,
13284    },{ .name = "L2_TM_EQ0",  .addr = A_L2_TM_EQ0,
13285        .ro = 0xffffff00,
13286    },{ .name = "L2_TM_EQ1",  .addr = A_L2_TM_EQ1,
13287        .ro = 0xffffff00,
13288    },{ .name = "L2_TM_EQ2",  .addr = A_L2_TM_EQ2,
13289        .ro = 0xffffff80,
13290    },{ .name = "L2_TM_EQ3",  .addr = A_L2_TM_EQ3,
13291        .ro = 0xffffffe0,
13292    },{ .name = "L2_TM_EQ4",  .addr = A_L2_TM_EQ4,
13293        .ro = 0xffffffe0,
13294    },{ .name = "L2_TM_EQ5",  .addr = A_L2_TM_EQ5,
13295        .ro = 0xffffffc0,
13296    },{ .name = "L2_TM_EQ6",  .addr = A_L2_TM_EQ6,
13297        .ro = 0xffffffe0,
13298    },{ .name = "L2_TM_EQ7",  .addr = A_L2_TM_EQ7,
13299        .ro = 0xffffffc0,
13300    },{ .name = "L2_TM_EQ8",  .addr = A_L2_TM_EQ8,
13301        .ro = 0xffffff00,
13302    },{ .name = "L2_TM_EQ9",  .addr = A_L2_TM_EQ9,
13303        .ro = 0xffffff80,
13304    },{ .name = "L2_TM_EQ10",  .addr = A_L2_TM_EQ10,
13305        .ro = 0xffffff80,
13306    },{ .name = "L2_TM_EQ11",  .addr = A_L2_TM_EQ11,
13307        .ro = 0xffffff00,
13308    },{ .name = "L2_TM_ILL7",  .addr = A_L2_TM_ILL7,
13309        .reset = 0x5,
13310        .ro = 0xffffff00,
13311    },{ .name = "L2_TM_ILL8",  .addr = A_L2_TM_ILL8,
13312        .reset = 0x2,
13313        .ro = 0xffffff00,
13314    },{ .name = "L2_TM_ILL9",  .addr = A_L2_TM_ILL9,
13315        .reset = 0x40,
13316        .ro = 0xffffff00,
13317    },{ .name = "L2_TM_ILL10",  .addr = A_L2_TM_ILL10,
13318        .ro = 0xffffff00,
13319    },{ .name = "L2_TM_ILL11",  .addr = A_L2_TM_ILL11,
13320        .ro = 0xffffff00,
13321    },{ .name = "L2_TM_ILL12",  .addr = A_L2_TM_ILL12,
13322        .ro = 0xffffff00,
13323    },{ .name = "L2_TM_ILL13",  .addr = A_L2_TM_ILL13,
13324        .reset = 0x1,
13325        .rsvd = 0xf8,
13326        .ro = 0xfffffff8,
13327    },{ .name = "L2_TM_ILL14",  .addr = A_L2_TM_ILL14,
13328        .reset = 0x51,
13329        .ro = 0xffffff00,
13330    },{ .name = "L2_TM_FRZ_FSM0",  .addr = A_L2_TM_FRZ_FSM0,
13331        .ro = 0xffffff00,
13332    },{ .name = "L2_TM_FRZ_FSM1",  .addr = A_L2_TM_FRZ_FSM1,
13333        .ro = 0xffffffc0,
13334    },{ .name = "L2_TM_RST_DLY",  .addr = A_L2_TM_RST_DLY,
13335        .ro = 0xffffff00,
13336    },{ .name = "L2_TM_ILL15",  .addr = A_L2_TM_ILL15,
13337        .ro = 0xffffff00,
13338    },{ .name = "L2_TM_MISC3",  .addr = A_L2_TM_MISC3,
13339        .reset = 0x3,
13340        .ro = 0xffffff00,
13341    },{ .name = "L2_TM_EQ_OFFS1",  .addr = A_L2_TM_EQ_OFFS1,
13342        .ro = 0xffffff00,
13343    },{ .name = "L2_TM_SAMP0",  .addr = A_L2_TM_SAMP0,
13344        .ro = 0xffffff00,
13345    },{ .name = "L2_TM_EQ12",  .addr = A_L2_TM_EQ12,
13346        .ro = 0xffffff00,
13347    },{ .name = "L2_TM_MISC4",  .addr = A_L2_TM_MISC4,
13348        .rsvd = 0xf8,
13349        .ro = 0xfffffff8,
13350    },{ .name = "L2_TM_SAMP_STATUS0",  .addr = A_L2_TM_SAMP_STATUS0,
13351        .rsvd = 0xc0,
13352        .ro = 0xffffffff,
13353    },{ .name = "L2_TM_SAMP_STATUS1",  .addr = A_L2_TM_SAMP_STATUS1,
13354        .rsvd = 0xc0,
13355        .ro = 0xffffffff,
13356    },{ .name = "L2_TM_SAMP_STATUS2",  .addr = A_L2_TM_SAMP_STATUS2,
13357        .rsvd = 0xc0,
13358        .ro = 0xffffffff,
13359    },{ .name = "L2_TM_SAMP_STATUS3",  .addr = A_L2_TM_SAMP_STATUS3,
13360        .rsvd = 0xc0,
13361        .ro = 0xffffffff,
13362    },{ .name = "L2_TM_SAMP_STATUS4",  .addr = A_L2_TM_SAMP_STATUS4,
13363        .rsvd = 0xc0,
13364        .ro = 0xffffffff,
13365    },{ .name = "L2_TM_SAMP_STATUS5",  .addr = A_L2_TM_SAMP_STATUS5,
13366        .rsvd = 0xc0,
13367        .ro = 0xffffffff,
13368    },{ .name = "L2_TM_ILL_STATUS0",  .addr = A_L2_TM_ILL_STATUS0,
13369        .rsvd = 0x80,
13370        .ro = 0xffffffff,
13371    },{ .name = "L2_TM_ILL_STATUS1",  .addr = A_L2_TM_ILL_STATUS1,
13372        .rsvd = 0x80,
13373        .ro = 0xffffffff,
13374    },{ .name = "L2_TM_ILL_STATUS2",  .addr = A_L2_TM_ILL_STATUS2,
13375        .rsvd = 0x80,
13376        .ro = 0xffffffff,
13377    },{ .name = "L2_TM_ILL_STATUS3",  .addr = A_L2_TM_ILL_STATUS3,
13378        .rsvd = 0x80,
13379        .ro = 0xffffffff,
13380    },{ .name = "L2_TM_ILL_STATUS4",  .addr = A_L2_TM_ILL_STATUS4,
13381        .rsvd = 0x80,
13382        .ro = 0xffffffff,
13383    },{ .name = "L2_TM_ILL_STATUS5",  .addr = A_L2_TM_ILL_STATUS5,
13384        .rsvd = 0x80,
13385        .ro = 0xffffffff,
13386    },{ .name = "L2_TM_ILL_STATUS6",  .addr = A_L2_TM_ILL_STATUS6,
13387        .rsvd = 0x80,
13388        .ro = 0xffffffff,
13389    },{ .name = "L2_TM_ILL_STATUS7",  .addr = A_L2_TM_ILL_STATUS7,
13390        .rsvd = 0x80,
13391        .ro = 0xffffffff,
13392    },{ .name = "L2_TM_ILL_STATUS8",  .addr = A_L2_TM_ILL_STATUS8,
13393        .rsvd = 0x80,
13394        .ro = 0xffffffff,
13395    },{ .name = "L2_TM_ILL_STATUS9",  .addr = A_L2_TM_ILL_STATUS9,
13396        .rsvd = 0x80,
13397        .ro = 0xffffffff,
13398    },{ .name = "L2_TM_ILL_STATUS10",  .addr = A_L2_TM_ILL_STATUS10,
13399        .rsvd = 0x80,
13400        .ro = 0xffffffff,
13401    },{ .name = "L2_TM_ILL_STATUS11",  .addr = A_L2_TM_ILL_STATUS11,
13402        .rsvd = 0x80,
13403        .ro = 0xffffffff,
13404    },{ .name = "L2_TM_MISC_ST_0",  .addr = A_L2_TM_MISC_ST_0,
13405        .rsvd = 0xc0,
13406        .ro = 0xffffffff,
13407    },{ .name = "L2_TM_SD_ST_0",  .addr = A_L2_TM_SD_ST_0,
13408        .reset = 0x12,
13409        .rsvd = 0xc0,
13410        .ro = 0xffffffff,
13411    },{ .name = "L2_TM_EYESURF_ST0",  .addr = A_L2_TM_EYESURF_ST0,
13412        .ro = 0xffffffff,
13413    },{ .name = "L2_TM_EYESURF_ST1",  .addr = A_L2_TM_EYESURF_ST1,
13414        .ro = 0xffffffff,
13415    },{ .name = "L2_TM_EQ_ST0",  .addr = A_L2_TM_EQ_ST0,
13416        .reset = 0xff,
13417        .ro = 0xffffffff,
13418    },{ .name = "L2_TM_EQ_ST1",  .addr = A_L2_TM_EQ_ST1,
13419        .ro = 0xffffffff,
13420    },{ .name = "L2_TM_EQ_ST2",  .addr = A_L2_TM_EQ_ST2,
13421        .rsvd = 0x80,
13422        .ro = 0xffffffff,
13423    },{ .name = "L2_TM_RXPMA_ST1",  .addr = A_L2_TM_RXPMA_ST1,
13424        .ro = 0xffffffff,
13425    },{ .name = "L2_TM_CDR0",  .addr = A_L2_TM_CDR0,
13426        .ro = 0xffffff60,
13427    },{ .name = "L2_TM_CDR1",  .addr = A_L2_TM_CDR1,
13428        .ro = 0xffffff00,
13429    },{ .name = "L2_TM_CDR2",  .addr = A_L2_TM_CDR2,
13430        .ro = 0xffffff00,
13431    },{ .name = "L2_TM_CDR3",  .addr = A_L2_TM_CDR3,
13432        .ro = 0xffffff80,
13433    },{ .name = "L2_TM_CDR4",  .addr = A_L2_TM_CDR4,
13434        .ro = 0xffffff80,
13435    },{ .name = "L2_TM_CDR5",  .addr = A_L2_TM_CDR5,
13436        .ro = 0xffffff00,
13437    },{ .name = "L2_TM_CDR6",  .addr = A_L2_TM_CDR6,
13438        .ro = 0xffffff00,
13439    },{ .name = "L2_TM_CDR7",  .addr = A_L2_TM_CDR7,
13440        .ro = 0xffffff00,
13441    },{ .name = "L2_TM_CDR8",  .addr = A_L2_TM_CDR8,
13442        .ro = 0xffffff00,
13443    },{ .name = "L2_TM_CDR9",  .addr = A_L2_TM_CDR9,
13444        .ro = 0xffffff00,
13445    },{ .name = "L2_TM_CDR10",  .addr = A_L2_TM_CDR10,
13446        .ro = 0xffffff00,
13447    },{ .name = "L2_TM_CDR11",  .addr = A_L2_TM_CDR11,
13448        .ro = 0xffffffe0,
13449    },{ .name = "L2_TM_CDR12",  .addr = A_L2_TM_CDR12,
13450        .ro = 0xffffff00,
13451    },{ .name = "L2_TM_CDR13",  .addr = A_L2_TM_CDR13,
13452        .ro = 0xffffff00,
13453    },{ .name = "L2_TM_CDR14",  .addr = A_L2_TM_CDR14,
13454        .ro = 0xffffff00,
13455    },{ .name = "L2_TM_CDR15",  .addr = A_L2_TM_CDR15,
13456        .ro = 0xffffff00,
13457    },{ .name = "L2_TM_CDR16",  .addr = A_L2_TM_CDR16,
13458        .ro = 0xffffffe0,
13459    },{ .name = "L2_TM_CDR17",  .addr = A_L2_TM_CDR17,
13460        .ro = 0xffffffe0,
13461    },{ .name = "L2_TM_CDR18",  .addr = A_L2_TM_CDR18,
13462        .ro = 0xffffffe0,
13463    },{ .name = "L2_TM_CDR19",  .addr = A_L2_TM_CDR19,
13464        .ro = 0xffffffe0,
13465    },{ .name = "L2_TM_CDR20",  .addr = A_L2_TM_CDR20,
13466        .ro = 0xffffffe0,
13467    },{ .name = "L2_TM_CDR21",  .addr = A_L2_TM_CDR21,
13468        .ro = 0xffffffe0,
13469    },{ .name = "L2_TM_CDR22",  .addr = A_L2_TM_CDR22,
13470        .ro = 0xffffffe0,
13471    },{ .name = "L2_TM_CDR23",  .addr = A_L2_TM_CDR23,
13472        .ro = 0xffffff80,
13473    },{ .name = "L2_TM_MISC0",  .addr = A_L2_TM_MISC0,
13474        .ro = 0xfffffffc,
13475    },{ .name = "L2_TM_HSRX_ST0",  .addr = A_L2_TM_HSRX_ST0,
13476        .rsvd = 0xfe,
13477        .ro = 0xffffffff,
13478    },{ .name = "L2_TM_PLL_LS_CLOCK",  .addr = A_L2_TM_PLL_LS_CLOCK,
13479        .ro = 0xffffff00,
13480    },{ .name = "L2_TM_PLL_LOOP_FILT",  .addr = A_L2_TM_PLL_LOOP_FILT,
13481        .ro = 0xffffff00,
13482    },{ .name = "L2_TM_PLL_DIG2",  .addr = A_L2_TM_PLL_DIG2,
13483        .ro = 0xffffff00,
13484    },{ .name = "L2_TM_PLL_FBDIV",  .addr = A_L2_TM_PLL_FBDIV,
13485        .ro = 0xffffff00,
13486    },{ .name = "L2_TM_PLL_DIG4",  .addr = A_L2_TM_PLL_DIG4,
13487        .reset = 0x80,
13488        .ro = 0xffffff00,
13489    },{ .name = "L2_TM_PLL_DIG5",  .addr = A_L2_TM_PLL_DIG5,
13490        .reset = 0xc0,
13491        .ro = 0xffffff00,
13492    },{ .name = "L2_TM_PLL_DIG6",  .addr = A_L2_TM_PLL_DIG6,
13493        .reset = 0x3,
13494        .ro = 0xffffff00,
13495    },{ .name = "L2_TM_PLL_DIG7",  .addr = A_L2_TM_PLL_DIG7,
13496        .ro = 0xffffff00,
13497    },{ .name = "L2_TM_PLL_CPUMP_CODE_1",  .addr = A_L2_TM_PLL_CPUMP_CODE_1,
13498        .ro = 0xffffff00,
13499    },{ .name = "L2_TM_PLL_DIG9",  .addr = A_L2_TM_PLL_DIG9,
13500        .ro = 0xffffffc0,
13501    },{ .name = "L2_TM_PLL_COARSE_CODE_LSB",  .addr = A_L2_TM_PLL_COARSE_CODE_LSB,
13502        .ro = 0xffffff00,
13503    },{ .name = "L2_TM_PLL_DIG11",  .addr = A_L2_TM_PLL_DIG11,
13504        .ro = 0xffffff00,
13505    },{ .name = "L2_TM_PLL_DIG12",  .addr = A_L2_TM_PLL_DIG12,
13506        .ro = 0xffffff00,
13507    },{ .name = "L2_TM_PLL_CONST_PMOS",  .addr = A_L2_TM_PLL_CONST_PMOS,
13508        .ro = 0xffffff00,
13509    },{ .name = "L2_TM_PLL_DIG14",  .addr = A_L2_TM_PLL_DIG14,
13510        .ro = 0xffffff00,
13511    },{ .name = "L2_TM_PLL_DIG15",  .addr = A_L2_TM_PLL_DIG15,
13512        .ro = 0xffffff00,
13513    },{ .name = "L2_TM_PLL_DIG16",  .addr = A_L2_TM_PLL_DIG16,
13514        .ro = 0xffffff10,
13515    },{ .name = "L2_TM_PLL_DIG17",  .addr = A_L2_TM_PLL_DIG17,
13516        .ro = 0xffffff00,
13517    },{ .name = "L2_TM_PLL_DIG18",  .addr = A_L2_TM_PLL_DIG18,
13518        .ro = 0xffffff00,
13519    },{ .name = "L2_TM_PLL_DIG19",  .addr = A_L2_TM_PLL_DIG19,
13520        .ro = 0xffffff00,
13521    },{ .name = "L2_TM_PLL_DIG20",  .addr = A_L2_TM_PLL_DIG20,
13522        .ro = 0xffffff40,
13523    },{ .name = "L2_TM_PLL_DIG21",  .addr = A_L2_TM_PLL_DIG21,
13524        .reset = 0x20,
13525        .ro = 0xffffff0c,
13526    },{ .name = "L2_TM_PLL_DIG22",  .addr = A_L2_TM_PLL_DIG22,
13527        .ro = 0xffffff80,
13528    },{ .name = "L2_TM_PLL_DIG23",  .addr = A_L2_TM_PLL_DIG23,
13529        .reset = 0x31,
13530        .ro = 0xffffff00,
13531    },{ .name = "L2_TM_PLL_DIG24",  .addr = A_L2_TM_PLL_DIG24,
13532        .ro = 0xffffff80,
13533    },{ .name = "L2_TM_PLL_DIG25",  .addr = A_L2_TM_PLL_DIG25,
13534        .ro = 0xffffff00,
13535    },{ .name = "L2_TM_PLL_DIG26",  .addr = A_L2_TM_PLL_DIG26,
13536        .reset = 0x40,
13537        .ro = 0xffffff80,
13538    },{ .name = "L2_TM_PLL_CLK_DIST_NTRIM_LSB",  .addr = A_L2_TM_PLL_CLK_DIST_NTRIM_LSB,
13539        .ro = 0xffffff00,
13540    },{ .name = "L2_TM_PLL_CLK_DIST_PTRIM_LSB",  .addr = A_L2_TM_PLL_CLK_DIST_PTRIM_LSB,
13541        .ro = 0xffffff00,
13542    },{ .name = "L2_TM_PLL_DIG_29",  .addr = A_L2_TM_PLL_DIG_29,
13543        .ro = 0xffffff00,
13544    },{ .name = "L2_TM_PLL_DIG_30",  .addr = A_L2_TM_PLL_DIG_30,
13545        .ro = 0xffffff00,
13546    },{ .name = "L2_TM_PLL_DIG_31",  .addr = A_L2_TM_PLL_DIG_31,
13547        .ro = 0xffffff00,
13548    },{ .name = "L2_TM_PLL_DIG_32",  .addr = A_L2_TM_PLL_DIG_32,
13549        .ro = 0xffffff00,
13550    },{ .name = "L2_TM_PLL_DIG_33",  .addr = A_L2_TM_PLL_DIG_33,
13551        .ro = 0xffffff00,
13552    },{ .name = "L2_TM_PLL_DIG_34",  .addr = A_L2_TM_PLL_DIG_34,
13553        .ro = 0xffffff80,
13554    },{ .name = "L2_TM_PLL_DIG_35",  .addr = A_L2_TM_PLL_DIG_35,
13555        .ro = 0xffffff00,
13556    },{ .name = "L2_TM_PLL_DIG_36",  .addr = A_L2_TM_PLL_DIG_36,
13557        .ro = 0xffffff00,
13558    },{ .name = "L2_TM_PLL_DIG_37",  .addr = A_L2_TM_PLL_DIG_37,
13559        .ro = 0xffffff00,
13560    },{ .name = "L2_TM_PLL_COARSE_CODE_SAT_MSB",  .addr = A_L2_TM_PLL_COARSE_CODE_SAT_MSB,
13561        .ro = 0xffffff00,
13562    },{ .name = "L2_MPHY_CFG_HIB8",  .addr = A_L2_MPHY_CFG_HIB8,
13563        .ro = 0xfffffffe,
13564    },{ .name = "L2_MPHY_CFG_MODE",  .addr = A_L2_MPHY_CFG_MODE,
13565        .ro = 0xfffffffc,
13566    },{ .name = "L2_MPHY_CFG_HS_GEAR",  .addr = A_L2_MPHY_CFG_HS_GEAR,
13567        .ro = 0xfffffffc,
13568    },{ .name = "L2_MPHY_CFG_HS_RATE",  .addr = A_L2_MPHY_CFG_HS_RATE,
13569        .ro = 0xfffffffe,
13570    },{ .name = "L2_MPHY_CFG_PWM",  .addr = A_L2_MPHY_CFG_PWM,
13571        .ro = 0xfffffff8,
13572    },{ .name = "L2_PLL_OPDIV_LS",  .addr = A_L2_PLL_OPDIV_LS,
13573        .ro = 0xffffff00,
13574    },{ .name = "L2_MPHY_CFG_UPDT",  .addr = A_L2_MPHY_CFG_UPDT,
13575        .ro = 0xfffffffe,
13576    },{ .name = "L2_PLL_TM_DIV_CNTRLS",  .addr = A_L2_PLL_TM_DIV_CNTRLS,
13577        .reset = 0x40,
13578        .ro = 0xffffff20,
13579    },{ .name = "L2_PLL_FBDIV_G1A_LSB",  .addr = A_L2_PLL_FBDIV_G1A_LSB,
13580        .ro = 0xffffff00,
13581    },{ .name = "L2_PLL_FBDIV_G1B_LSB",  .addr = A_L2_PLL_FBDIV_G1B_LSB,
13582        .ro = 0xffffff00,
13583    },{ .name = "L2_PLL_FBDIV_G2A_LSB",  .addr = A_L2_PLL_FBDIV_G2A_LSB,
13584        .ro = 0xffffff00,
13585    },{ .name = "L2_PLL_FBDIV_G2B_LSB",  .addr = A_L2_PLL_FBDIV_G2B_LSB,
13586        .ro = 0xffffff00,
13587    },{ .name = "L2_PLL_FBDIV_G3A_LSB",  .addr = A_L2_PLL_FBDIV_G3A_LSB,
13588        .ro = 0xffffff00,
13589    },{ .name = "L2_PLL_FBDIV_G3B_LSB",  .addr = A_L2_PLL_FBDIV_G3B_LSB,
13590        .ro = 0xffffff00,
13591    },{ .name = "L2_PLL_FBDIV_G1A_MSB",  .addr = A_L2_PLL_FBDIV_G1A_MSB,
13592        .ro = 0xffffff00,
13593    },{ .name = "L2_PLL_FBDIV_G1B_MSB",  .addr = A_L2_PLL_FBDIV_G1B_MSB,
13594        .ro = 0xffffff00,
13595    },{ .name = "L2_PLL_FBDIV_G2A_MSB",  .addr = A_L2_PLL_FBDIV_G2A_MSB,
13596        .ro = 0xffffff00,
13597    },{ .name = "L2_PLL_FBDIV_G2B_MSB",  .addr = A_L2_PLL_FBDIV_G2B_MSB,
13598        .ro = 0xffffff00,
13599    },{ .name = "L2_PLL_FBDIV_G3A_MSB",  .addr = A_L2_PLL_FBDIV_G3A_MSB,
13600        .ro = 0xffffff00,
13601    },{ .name = "L2_PLL_FBDIV_G3B_MSB",  .addr = A_L2_PLL_FBDIV_G3B_MSB,
13602        .ro = 0xffffff00,
13603    },{ .name = "L2_PLL_IPDIV",  .addr = A_L2_PLL_IPDIV,
13604        .ro = 0xffffff00,
13605    },{ .name = "L2_PLL_FBDIV_FRAC_0_LSB",  .addr = A_L2_PLL_FBDIV_FRAC_0_LSB,
13606        .ro = 0xffffff00,
13607    },{ .name = "L2_PLL_FBDIV_FRAC_1",  .addr = A_L2_PLL_FBDIV_FRAC_1,
13608        .ro = 0xffffff00,
13609    },{ .name = "L2_PLL_FBDIV_FRAC_2",  .addr = A_L2_PLL_FBDIV_FRAC_2,
13610        .ro = 0xffffff00,
13611    },{ .name = "L2_PLL_FBDIV_FRAC_3_MSB",  .addr = A_L2_PLL_FBDIV_FRAC_3_MSB,
13612        .ro = 0xffffff98,
13613    },{ .name = "L2_PLL_PWR_SEQ_WAIT_TIME",  .addr = A_L2_PLL_PWR_SEQ_WAIT_TIME,
13614        .ro = 0xffffff00,
13615    },{ .name = "L2_PLL_SS_STEPS_0_LSB",  .addr = A_L2_PLL_SS_STEPS_0_LSB,
13616        .ro = 0xffffff00,
13617    },{ .name = "L2_PLL_SS_STEPS_1_MSB",  .addr = A_L2_PLL_SS_STEPS_1_MSB,
13618        .ro = 0xfffffff8,
13619    },{ .name = "L2_PLL_SS_STEP_SIZE_0_LSB",  .addr = A_L2_PLL_SS_STEP_SIZE_0_LSB,
13620        .ro = 0xffffff00,
13621    },{ .name = "L2_PLL_SS_STEP_SIZE_1",  .addr = A_L2_PLL_SS_STEP_SIZE_1,
13622        .ro = 0xffffff00,
13623    },{ .name = "L2_PLL_SS_STEP_SIZE_2",  .addr = A_L2_PLL_SS_STEP_SIZE_2,
13624        .ro = 0xffffff00,
13625    },{ .name = "L2_PLL_SS_STEP_SIZE_3_MSB",  .addr = A_L2_PLL_SS_STEP_SIZE_3_MSB,
13626        .ro = 0xffffff00,
13627    },{ .name = "L2_TM_MASK_CFG_UPDT",  .addr = A_L2_TM_MASK_CFG_UPDT,
13628        .ro = 0xffffff80,
13629    },{ .name = "L2_PLL_TM_FORCE_DIV",  .addr = A_L2_PLL_TM_FORCE_DIV,
13630        .ro = 0xffffff00,
13631    },{ .name = "L2_PLL_TM_COARSE_CODE_1_LSB",  .addr = A_L2_PLL_TM_COARSE_CODE_1_LSB,
13632        .ro = 0xffffff00,
13633    },{ .name = "L2_PLL_TM_COARSE_CODE_2_LSB",  .addr = A_L2_PLL_TM_COARSE_CODE_2_LSB,
13634        .ro = 0xffffff00,
13635    },{ .name = "L2_PLL_TM_COARSE_CODE_3_LSB",  .addr = A_L2_PLL_TM_COARSE_CODE_3_LSB,
13636        .ro = 0xffffff00,
13637    },{ .name = "L2_PLL_TM_COARSE_CODE_4_LSB",  .addr = A_L2_PLL_TM_COARSE_CODE_4_LSB,
13638        .ro = 0xffffff00,
13639    },{ .name = "L2_PLL_TM_COARSE_CODE_5_LSB",  .addr = A_L2_PLL_TM_COARSE_CODE_5_LSB,
13640        .ro = 0xffffff00,
13641    },{ .name = "L2_PLL_TM_COARSE_CODE_6_LSB",  .addr = A_L2_PLL_TM_COARSE_CODE_6_LSB,
13642        .ro = 0xffffff00,
13643    },{ .name = "L2_PLL_TM_COARSE_CODE_1_2_MSB",  .addr = A_L2_PLL_TM_COARSE_CODE_1_2_MSB,
13644        .ro = 0xffffffc0,
13645    },{ .name = "L2_PLL_TM_COARSE_CODE_3_4_MSB",  .addr = A_L2_PLL_TM_COARSE_CODE_3_4_MSB,
13646        .ro = 0xffffffc0,
13647    },{ .name = "L2_PLL_TM_COARSE_CODE_5_6_MSB",  .addr = A_L2_PLL_TM_COARSE_CODE_5_6_MSB,
13648        .ro = 0xffffffc0,
13649    },{ .name = "L2_PLL_TM_SHARED_0",  .addr = A_L2_PLL_TM_SHARED_0,
13650        .ro = 0xffffff00,
13651    },{ .name = "L2_PLL_TM_FRAC_OFFSET_0",  .addr = A_L2_PLL_TM_FRAC_OFFSET_0,
13652        .ro = 0xffffff00,
13653    },{ .name = "L2_PLL_TM_FRAC_OFFSET_1",  .addr = A_L2_PLL_TM_FRAC_OFFSET_1,
13654        .ro = 0xffffff00,
13655    },{ .name = "L2_PLL_TM_FRAC_OFFSET_2",  .addr = A_L2_PLL_TM_FRAC_OFFSET_2,
13656        .ro = 0xfffffffc,
13657    },{ .name = "L2_PLL_STATUS_READ_0",  .addr = A_L2_PLL_STATUS_READ_0,
13658        .ro = 0xffffffff,
13659    },{ .name = "L2_PLL_STATUS_READ_1",  .addr = A_L2_PLL_STATUS_READ_1,
13660        .reset = 0x1 | R_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK,
13661        .ro = 0xffffffff,
13662    },{ .name = "L2_UPHY_GLOBAL_CTRL",  .addr = A_L2_UPHY_GLOBAL_CTRL,
13663        .ro = 0xffffffe0,
13664    },{ .name = "L2_BIST_CTRL_1",  .addr = A_L2_BIST_CTRL_1,
13665        .ro = 0xffffff00,
13666    },{ .name = "L2_BIST_CTRL_2",  .addr = A_L2_BIST_CTRL_2,
13667        .ro = 0xfffffff8,
13668    },{ .name = "L2_BIST_RUN_LEN_L",  .addr = A_L2_BIST_RUN_LEN_L,
13669        .ro = 0xffffff00,
13670    },{ .name = "L2_BIST_ERR_INJ_POINT_L",  .addr = A_L2_BIST_ERR_INJ_POINT_L,
13671        .ro = 0xffffff00,
13672    },{ .name = "L2_BIST_RUNLEN_ERR_INJ_H",  .addr = A_L2_BIST_RUNLEN_ERR_INJ_H,
13673        .ro = 0xffffff00,
13674    },{ .name = "L2_BIST_IDLE_TIME",  .addr = A_L2_BIST_IDLE_TIME,
13675        .ro = 0xffffff00,
13676    },{ .name = "L2_BIST_MARKER_L",  .addr = A_L2_BIST_MARKER_L,
13677        .ro = 0xffffff00,
13678    },{ .name = "L2_BIST_IDLE_CHAR_L",  .addr = A_L2_BIST_IDLE_CHAR_L,
13679        .ro = 0xffffff00,
13680    },{ .name = "L2_BIST_MARKER_IDLE_H",  .addr = A_L2_BIST_MARKER_IDLE_H,
13681        .ro = 0xffffffcc,
13682    },{ .name = "L2_BIST_LOW_PULSE_TIME",  .addr = A_L2_BIST_LOW_PULSE_TIME,
13683        .ro = 0xffffff00,
13684    },{ .name = "L2_BIST_TOTAL_PULSE_TIME",  .addr = A_L2_BIST_TOTAL_PULSE_TIME,
13685        .ro = 0xffffff00,
13686    },{ .name = "L2_BIST_TEST_PAT_1",  .addr = A_L2_BIST_TEST_PAT_1,
13687        .ro = 0xffffff00,
13688    },{ .name = "L2_BIST_TEST_PAT_2",  .addr = A_L2_BIST_TEST_PAT_2,
13689        .ro = 0xffffff00,
13690    },{ .name = "L2_BIST_TEST_PAT_3",  .addr = A_L2_BIST_TEST_PAT_3,
13691        .ro = 0xffffff00,
13692    },{ .name = "L2_BIST_TEST_PAT_4",  .addr = A_L2_BIST_TEST_PAT_4,
13693        .ro = 0xffffff00,
13694    },{ .name = "L2_BIST_TEST_PAT_MSBS",  .addr = A_L2_BIST_TEST_PAT_MSBS,
13695        .ro = 0xffffff00,
13696    },{ .name = "L2_BIST_PKT_NUM",  .addr = A_L2_BIST_PKT_NUM,
13697        .ro = 0xffffff00,
13698    },{ .name = "L2_BIST_FRM_IDLE_TIME",  .addr = A_L2_BIST_FRM_IDLE_TIME,
13699        .ro = 0xffffff00,
13700    },{ .name = "L2_BIST_PKT_CTR_L",  .addr = A_L2_BIST_PKT_CTR_L,
13701        .ro = 0xffffffff,
13702    },{ .name = "L2_BIST_PKT_CTR_H",  .addr = A_L2_BIST_PKT_CTR_H,
13703        .ro = 0xffffffff,
13704    },{ .name = "L2_BIST_ERR_CTR_L",  .addr = A_L2_BIST_ERR_CTR_L,
13705        .ro = 0xffffffff,
13706    },{ .name = "L2_BIST_ERR_CTR_H",  .addr = A_L2_BIST_ERR_CTR_H,
13707        .ro = 0xffffffff,
13708    },{ .name = "L2_CLK_DIV_CNT",  .addr = A_L2_CLK_DIV_CNT,
13709        .reset = 0x19,
13710        .ro = 0xffffff00,
13711    },{ .name = "L2_DATA_BUS_WID",  .addr = A_L2_DATA_BUS_WID,
13712        .reset = 0x1,
13713        .ro = 0xffffff00,
13714    },{ .name = "L2_ANADIG_BYPASS",  .addr = A_L2_ANADIG_BYPASS,
13715        .ro = 0xffffff00,
13716    },{ .name = "L2_BIST_FILLER_OUT",  .addr = A_L2_BIST_FILLER_OUT,
13717        .reset = 0x1,
13718        .ro = 0xfffffffc,
13719    },{ .name = "L2_BIST_FORCE_MK_RST",  .addr = A_L2_BIST_FORCE_MK_RST,
13720        .rsvd = 0xfc,
13721        .ro = 0xfffffffc,
13722    },{ .name = "L2_SPARE_IN",  .addr = A_L2_SPARE_IN,
13723        .ro = 0xffffffff,
13724    },{ .name = "L2_SPARE_OUT",  .addr = A_L2_SPARE_OUT,
13725        .ro = 0xffffff00,
13726    },{ .name = "L3_TX_ANA_TM_0",  .addr = A_L3_TX_ANA_TM_0,
13727        .reset = 0x28,
13728        .ro = 0xffffffc3,
13729    },{ .name = "L3_TX_ANA_TM_3",  .addr = A_L3_TX_ANA_TM_3,
13730        .ro = 0xffffff00,
13731    },{ .name = "L3_TX_ANA_TM_4",  .addr = A_L3_TX_ANA_TM_4,
13732        .ro = 0xffffff80,
13733    },{ .name = "L3_TX_ANA_TM_5",  .addr = A_L3_TX_ANA_TM_5,
13734        .ro = 0xffffff80,
13735    },{ .name = "L3_TX_ANA_TM_9",  .addr = A_L3_TX_ANA_TM_9,
13736        .reset = 0x3f,
13737        .ro = 0xffffff00,
13738    },{ .name = "L3_TX_ANA_TM_10",  .addr = A_L3_TX_ANA_TM_10,
13739        .reset = 0x30,
13740        .ro = 0xffffff00,
13741    },{ .name = "L3_TX_ANA_TM_13",  .addr = A_L3_TX_ANA_TM_13,
13742        .reset = 0x2,
13743        .ro = 0xfffffff0,
13744    },{ .name = "L3_TX_ANA_TM_14",  .addr = A_L3_TX_ANA_TM_14,
13745        .ro = 0xffffffcf,
13746    },{ .name = "L3_TX_ANA_TM_15",  .addr = A_L3_TX_ANA_TM_15,
13747        .ro = 0xffffff00,
13748    },{ .name = "L3_TX_ANA_TM_16",  .addr = A_L3_TX_ANA_TM_16,
13749        .ro = 0xfffffff0,
13750    },{ .name = "L3_TX_ANA_TM_18",  .addr = A_L3_TX_ANA_TM_18,
13751        .reset = 0x2,
13752        .ro = 0xffffff00,
13753    },{ .name = "L3_TX_ANA_TM_19",  .addr = A_L3_TX_ANA_TM_19,
13754        .ro = 0xffffff00,
13755    },{ .name = "L3_TX_ANA_TM_20",  .addr = A_L3_TX_ANA_TM_20,
13756        .ro = 0xffffffe0,
13757    },{ .name = "L3_TX_ANA_TM_21",  .addr = A_L3_TX_ANA_TM_21,
13758        .ro = 0xffffffc0,
13759    },{ .name = "L3_TX_DIG_TM_61",  .addr = A_L3_TX_DIG_TM_61,
13760        .ro = 0xffffff34,
13761    },{ .name = "L3_TX_DIG_TM_62",  .addr = A_L3_TX_DIG_TM_62,
13762        .ro = 0xffffff00,
13763    },{ .name = "L3_TX_DIG_TM_65",  .addr = A_L3_TX_DIG_TM_65,
13764        .ro = 0xffffff01,
13765    },{ .name = "L3_TX_DIG_TM_67",  .addr = A_L3_TX_DIG_TM_67,
13766        .ro = 0xffffff00,
13767    },{ .name = "L3_TX_DIG_TM_68",  .addr = A_L3_TX_DIG_TM_68,
13768        .ro = 0xffffff00,
13769    },{ .name = "L3_TX_DIG_TM_69",  .addr = A_L3_TX_DIG_TM_69,
13770        .ro = 0xffffff00,
13771    },{ .name = "L3_TX_DIG_TM_76",  .addr = A_L3_TX_DIG_TM_76,
13772        .ro = 0xffffff00,
13773    },{ .name = "L3_TX_DIG_TM_77",  .addr = A_L3_TX_DIG_TM_77,
13774        .ro = 0xffffff00,
13775    },{ .name = "L3_TX_DIG_TM_78",  .addr = A_L3_TX_DIG_TM_78,
13776        .ro = 0xffffff00,
13777    },{ .name = "L3_TX_DIG_TM_79",  .addr = A_L3_TX_DIG_TM_79,
13778        .ro = 0xffffff00,
13779    },{ .name = "L3_TX_DIG_TM_80",  .addr = A_L3_TX_DIG_TM_80,
13780        .ro = 0xffffff00,
13781    },{ .name = "L3_TX_DIG_TM_81",  .addr = A_L3_TX_DIG_TM_81,
13782        .ro = 0xffffff00,
13783    },{ .name = "L3_TX_DIG_TM_82",  .addr = A_L3_TX_DIG_TM_82,
13784        .ro = 0xffffff00,
13785    },{ .name = "L3_TX_DIG_TM_83",  .addr = A_L3_TX_DIG_TM_83,
13786        .ro = 0xfffffff0,
13787    },{ .name = "L3_TX_DIG_TM_84",  .addr = A_L3_TX_DIG_TM_84,
13788        .ro = 0xffffff0a,
13789    },{ .name = "L3_TX_ANA_TM_85",  .addr = A_L3_TX_ANA_TM_85,
13790        .ro = 0xffffffca,
13791    },{ .name = "L3_TX_ANA_TM_87",  .addr = A_L3_TX_ANA_TM_87,
13792        .ro = 0xfffffff0,
13793    },{ .name = "L3_TX_ANA_TM_88",  .addr = A_L3_TX_ANA_TM_88,
13794        .reset = 0x96,
13795        .ro = 0xffffff00,
13796    },{ .name = "L3_TX_ANA_TM_89",  .addr = A_L3_TX_ANA_TM_89,
13797        .ro = 0xffffffd9,
13798    },{ .name = "L3_TX_ANA_TM_90",  .addr = A_L3_TX_ANA_TM_90,
13799        .ro = 0xffffffdf,
13800    },{ .name = "L3_TX_DIG_TM_91",  .addr = A_L3_TX_DIG_TM_91,
13801        .reset = 0x1a,
13802        .ro = 0xffffff00,
13803    },{ .name = "L3_TX_DIG_TM_92",  .addr = A_L3_TX_DIG_TM_92,
13804        .reset = 0xa,
13805        .ro = 0xffffff00,
13806    },{ .name = "L3_TX_ANA_TM_95",  .addr = A_L3_TX_ANA_TM_95,
13807        .ro = 0xffffffc3,
13808    },{ .name = "L3_TX_ANA_TM_96",  .addr = A_L3_TX_ANA_TM_96,
13809        .ro = 0xffffff00,
13810    },{ .name = "L3_TX_ANA_TM_97",  .addr = A_L3_TX_ANA_TM_97,
13811        .ro = 0xffffff00,
13812    },{ .name = "L3_TX_DIG_TM_98",  .addr = A_L3_TX_DIG_TM_98,
13813        .ro = 0xffffffc0,
13814    },{ .name = "L3_TX_DIG_TM_99",  .addr = A_L3_TX_DIG_TM_99,
13815        .ro = 0xffffff00,
13816    },{ .name = "L3_TX_DIG_TM_100",  .addr = A_L3_TX_DIG_TM_100,
13817        .ro = 0xffffff00,
13818    },{ .name = "L3_TX_DIG_TM_101",  .addr = A_L3_TX_DIG_TM_101,
13819        .ro = 0xffffff00,
13820    },{ .name = "L3_TX_DIG_TM_102",  .addr = A_L3_TX_DIG_TM_102,
13821        .ro = 0xffffff00,
13822    },{ .name = "L3_TX_DIG_TM_103",  .addr = A_L3_TX_DIG_TM_103,
13823        .ro = 0xffffff00,
13824    },{ .name = "L3_TX_DIG_TM_104",  .addr = A_L3_TX_DIG_TM_104,
13825        .ro = 0xffffff00,
13826    },{ .name = "L3_TX_DIG_TM_105",  .addr = A_L3_TX_DIG_TM_105,
13827        .ro = 0xffffff00,
13828    },{ .name = "L3_TX_DIG_TM_106",  .addr = A_L3_TX_DIG_TM_106,
13829        .ro = 0xffffff00,
13830    },{ .name = "L3_TX_DIG_TM_107",  .addr = A_L3_TX_DIG_TM_107,
13831        .ro = 0xffffff80,
13832    },{ .name = "L3_TX_DIG_TM_108",  .addr = A_L3_TX_DIG_TM_108,
13833        .ro = 0xffffff80,
13834    },{ .name = "L3_TX_DIG_TM_109",  .addr = A_L3_TX_DIG_TM_109,
13835        .ro = 0xffffff00,
13836    },{ .name = "L3_TX_DIG_TM_110",  .addr = A_L3_TX_DIG_TM_110,
13837        .reset = 0x9,
13838        .ro = 0xffffff00,
13839    },{ .name = "L3_TX_DIG_TM_111",  .addr = A_L3_TX_DIG_TM_111,
13840        .ro = 0xffffff00,
13841    },{ .name = "L3_TX_ANA_TM_112",  .addr = A_L3_TX_ANA_TM_112,
13842        .ro = 0xffffffc0,
13843    },{ .name = "L3_TX_ANA_TM_113",  .addr = A_L3_TX_ANA_TM_113,
13844        .ro = 0xffffff00,
13845    },{ .name = "L3_TX_ANA_TM_114",  .addr = A_L3_TX_ANA_TM_114,
13846        .ro = 0xffffffe0,
13847    },{ .name = "L3_TX_ANA_TM_115",  .addr = A_L3_TX_ANA_TM_115,
13848        .ro = 0xffffff80,
13849    },{ .name = "L3_TX_ANA_TM_116",  .addr = A_L3_TX_ANA_TM_116,
13850        .ro = 0xffffff80,
13851    },{ .name = "L3_TX_ANA_TM_117",  .addr = A_L3_TX_ANA_TM_117,
13852        .ro = 0xffffffc0,
13853    },{ .name = "L3_TX_ANA_TM_118",  .addr = A_L3_TX_ANA_TM_118,
13854        .ro = 0xfffffff0,
13855    },{ .name = "L3_TXPMA_TM_0",  .addr = A_L3_TXPMA_TM_0,
13856        .ro = 0xffffff00,
13857    },{ .name = "L3_TXPMA_TM_1",  .addr = A_L3_TXPMA_TM_1,
13858        .ro = 0xfffffff0,
13859    },{ .name = "L3_TXPMA_TM_2",  .addr = A_L3_TXPMA_TM_2,
13860        .ro = 0xffffff00,
13861    },{ .name = "L3_TXPMA_TM_3",  .addr = A_L3_TXPMA_TM_3,
13862        .ro = 0xffffffe0,
13863    },{ .name = "L3_TXPMA_TM_4",  .addr = A_L3_TXPMA_TM_4,
13864        .reset = 0x2,
13865        .ro = 0xffffff01,
13866    },{ .name = "L3_TXPMA_TM_5",  .addr = A_L3_TXPMA_TM_5,
13867        .ro = 0xfffffff0,
13868    },{ .name = "L3_TXPMA_TM_6",  .addr = A_L3_TXPMA_TM_6,
13869        .ro = 0xffffff00,
13870    },{ .name = "L3_TXPMA_TM_7",  .addr = A_L3_TXPMA_TM_7,
13871        .ro = 0xffffff00,
13872    },{ .name = "L3_TXPMA_TM_8",  .addr = A_L3_TXPMA_TM_8,
13873        .ro = 0xfffffffc,
13874    },{ .name = "L3_TXPMA_TM_9",  .addr = A_L3_TXPMA_TM_9,
13875        .ro = 0xffffff80,
13876    },{ .name = "L3_TXPMA_TM_10",  .addr = A_L3_TXPMA_TM_10,
13877        .ro = 0xffffffc0,
13878    },{ .name = "L3_TXPMA_TM_11",  .addr = A_L3_TXPMA_TM_11,
13879        .ro = 0xffffffe0,
13880    },{ .name = "L3_TXPMA_TM_12",  .addr = A_L3_TXPMA_TM_12,
13881        .ro = 0xffffff01,
13882    },{ .name = "L3_TXPMA_TM_13",  .addr = A_L3_TXPMA_TM_13,
13883        .ro = 0xffffff00,
13884    },{ .name = "L3_TXPMA_TM_14",  .addr = A_L3_TXPMA_TM_14,
13885        .ro = 0xffffffe0,
13886    },{ .name = "L3_TXPMA_TM_15",  .addr = A_L3_TXPMA_TM_15,
13887        .ro = 0xffffff00,
13888    },{ .name = "L3_TXPMA_TM_16",  .addr = A_L3_TXPMA_TM_16,
13889        .ro = 0xffffff00,
13890    },{ .name = "L3_TXPMA_TM_17",  .addr = A_L3_TXPMA_TM_17,
13891        .ro = 0xffffff00,
13892    },{ .name = "L3_TXPMA_TM_18",  .addr = A_L3_TXPMA_TM_18,
13893        .reset = 0xf,
13894        .ro = 0xffffff00,
13895    },{ .name = "L3_TXPMA_TM_19",  .addr = A_L3_TXPMA_TM_19,
13896        .reset = 0x3,
13897        .ro = 0xffffffc0,
13898    },{ .name = "L3_TXPMA_TM_20",  .addr = A_L3_TXPMA_TM_20,
13899        .reset = 0x6,
13900        .ro = 0xffffff00,
13901    },{ .name = "L3_TXPMA_TM_21",  .addr = A_L3_TXPMA_TM_21,
13902        .reset = 0x3,
13903        .ro = 0xffffff00,
13904    },{ .name = "L3_TXPMA_TM_22",  .addr = A_L3_TXPMA_TM_22,
13905        .reset = 0x6,
13906        .ro = 0xffffff00,
13907    },{ .name = "L3_TXPMA_TM_23",  .addr = A_L3_TXPMA_TM_23,
13908        .reset = 0x3,
13909        .ro = 0xffffff00,
13910    },{ .name = "L3_TXPMA_TM_24",  .addr = A_L3_TXPMA_TM_24,
13911        .ro = 0xffffff80,
13912    },{ .name = "L3_TXPMA_TM_25",  .addr = A_L3_TXPMA_TM_25,
13913        .ro = 0xffffffc0,
13914    },{ .name = "L3_TXPMA_TM_26",  .addr = A_L3_TXPMA_TM_26,
13915        .reset = 0x64,
13916        .ro = 0xffffff00,
13917    },{ .name = "L3_TXPMA_TM_27",  .addr = A_L3_TXPMA_TM_27,
13918        .ro = 0xffffff00,
13919    },{ .name = "L3_TXPMA_ST_0",  .addr = A_L3_TXPMA_ST_0,
13920        .reset = 0x1,
13921        .ro = 0xffffffff,
13922    },{ .name = "L3_TXPMA_ST_1",  .addr = A_L3_TXPMA_ST_1,
13923        .reset = 0x1,
13924        .ro = 0xffffffff,
13925    },{ .name = "L3_TXPMA_ST_2",  .addr = A_L3_TXPMA_ST_2,
13926        .reset = 0x4,
13927        .ro = 0xffffffff,
13928    },{ .name = "L3_TXPMA_ST_3",  .addr = A_L3_TXPMA_ST_3,
13929        .reset = 0x20,
13930        .ro = 0xffffffff,
13931    },{ .name = "L3_TXPMA_ST_4",  .addr = A_L3_TXPMA_ST_4,
13932        .reset = 0x20,
13933        .ro = 0xffffffff,
13934    },{ .name = "L3_TXPMA_ST_5",  .addr = A_L3_TXPMA_ST_5,
13935        .reset = 0x20,
13936        .ro = 0xffffffff,
13937    },{ .name = "L3_TXPMA_ST_6",  .addr = A_L3_TXPMA_ST_6,
13938        .reset = 0xb,
13939        .ro = 0xffffffff,
13940    },{ .name = "L3_TXPMA_ST_7",  .addr = A_L3_TXPMA_ST_7,
13941        .ro = 0xffffffff,
13942    },{ .name = "L3_TXPMA_ST_8",  .addr = A_L3_TXPMA_ST_8,
13943        .ro = 0xffffffff,
13944    },{ .name = "L3_TXPMA_ST_9",  .addr = A_L3_TXPMA_ST_9,
13945        .ro = 0xffffffff,
13946    },{ .name = "L3_TXPMD_TM_0",  .addr = A_L3_TXPMD_TM_0,
13947        .ro = 0xffffffe0,
13948    },{ .name = "L3_TXPMD_TM_1",  .addr = A_L3_TXPMD_TM_1,
13949        .ro = 0xffffffe0,
13950    },{ .name = "L3_TXPMD_TM_2",  .addr = A_L3_TXPMD_TM_2,
13951        .ro = 0xffffffe0,
13952    },{ .name = "L3_TXPMD_TM_3",  .addr = A_L3_TXPMD_TM_3,
13953        .ro = 0xffffffe0,
13954    },{ .name = "L3_TXPMD_TM_4",  .addr = A_L3_TXPMD_TM_4,
13955        .ro = 0xffffffe0,
13956    },{ .name = "L3_TXPMD_TM_5",  .addr = A_L3_TXPMD_TM_5,
13957        .ro = 0xffffffe0,
13958    },{ .name = "L3_TXPMD_TM_6",  .addr = A_L3_TXPMD_TM_6,
13959        .ro = 0xffffffe0,
13960    },{ .name = "L3_TXPMD_TM_7",  .addr = A_L3_TXPMD_TM_7,
13961        .ro = 0xffffffe0,
13962    },{ .name = "L3_TXPMD_TM_8",  .addr = A_L3_TXPMD_TM_8,
13963        .ro = 0xffffffe0,
13964    },{ .name = "L3_TXPMD_TM_9",  .addr = A_L3_TXPMD_TM_9,
13965        .ro = 0xffffffe0,
13966    },{ .name = "L3_TXPMD_TM_10",  .addr = A_L3_TXPMD_TM_10,
13967        .ro = 0xffffffe0,
13968    },{ .name = "L3_TXPMD_TM_11",  .addr = A_L3_TXPMD_TM_11,
13969        .ro = 0xffffffe0,
13970    },{ .name = "L3_TXPMD_TM_12",  .addr = A_L3_TXPMD_TM_12,
13971        .ro = 0xffffffe0,
13972    },{ .name = "L3_TXPMD_TM_13",  .addr = A_L3_TXPMD_TM_13,
13973        .ro = 0xffffffe0,
13974    },{ .name = "L3_TXPMD_TM_14",  .addr = A_L3_TXPMD_TM_14,
13975        .ro = 0xffffffe0,
13976    },{ .name = "L3_TXPMD_TM_15",  .addr = A_L3_TXPMD_TM_15,
13977        .ro = 0xffffffe0,
13978    },{ .name = "L3_TXPMD_TM_16",  .addr = A_L3_TXPMD_TM_16,
13979        .ro = 0xffffffe0,
13980    },{ .name = "L3_TXPMD_TM_17",  .addr = A_L3_TXPMD_TM_17,
13981        .ro = 0xffffffe0,
13982    },{ .name = "L3_TXPMD_TM_18",  .addr = A_L3_TXPMD_TM_18,
13983        .ro = 0xffffffe0,
13984    },{ .name = "L3_TXPMD_TM_19",  .addr = A_L3_TXPMD_TM_19,
13985        .ro = 0xffffffe0,
13986    },{ .name = "L3_TXPMD_TM_20",  .addr = A_L3_TXPMD_TM_20,
13987        .ro = 0xffffffe0,
13988    },{ .name = "L3_TXPMD_TM_21",  .addr = A_L3_TXPMD_TM_21,
13989        .ro = 0xffffffe0,
13990    },{ .name = "L3_TXPMD_TM_22",  .addr = A_L3_TXPMD_TM_22,
13991        .ro = 0xffffffe0,
13992    },{ .name = "L3_TXPMD_TM_23",  .addr = A_L3_TXPMD_TM_23,
13993        .ro = 0xffffffe0,
13994    },{ .name = "L3_TXPMD_TM_24",  .addr = A_L3_TXPMD_TM_24,
13995        .ro = 0xffffffe0,
13996    },{ .name = "L3_TXPMD_TM_25",  .addr = A_L3_TXPMD_TM_25,
13997        .ro = 0xffffffe0,
13998    },{ .name = "L3_TXPMD_TM_26",  .addr = A_L3_TXPMD_TM_26,
13999        .ro = 0xffffffe0,
14000    },{ .name = "L3_TXPMD_TM_27",  .addr = A_L3_TXPMD_TM_27,

14001        .ro = 0xffffffe0,
14002    },{ .name = "L3_TXPMD_TM_28",  .addr = A_L3_TXPMD_TM_28,
14003        .ro = 0xffffffe0,
14004    },{ .name = "L3_TXPMD_TM_29",  .addr = A_L3_TXPMD_TM_29,
14005        .ro = 0xffffffe0,
14006    },{ .name = "L3_TXPMD_TM_30",  .addr = A_L3_TXPMD_TM_30,
14007        .ro = 0xffffffe0,
14008    },{ .name = "L3_TXPMD_TM_31",  .addr = A_L3_TXPMD_TM_31,
14009        .ro = 0xffffffe0,
14010    },{ .name = "L3_TXPMD_TM_32",  .addr = A_L3_TXPMD_TM_32,
14011        .ro = 0xffffff00,
14012    },{ .name = "L3_TXPMD_TM_33",  .addr = A_L3_TXPMD_TM_33,
14013        .ro = 0xffffff00,
14014    },{ .name = "L3_TXPMD_TM_34",  .addr = A_L3_TXPMD_TM_34,
14015        .ro = 0xffffff00,
14016    },{ .name = "L3_TXPMD_TM_35",  .addr = A_L3_TXPMD_TM_35,
14017        .ro = 0xffffff00,
14018    },{ .name = "L3_TXPMD_TM_36",  .addr = A_L3_TXPMD_TM_36,
14019        .ro = 0xffffff00,
14020    },{ .name = "L3_TXPMD_TM_37",  .addr = A_L3_TXPMD_TM_37,
14021        .ro = 0xffffff00,
14022    },{ .name = "L3_TXPMD_TM_38",  .addr = A_L3_TXPMD_TM_38,
14023        .ro = 0xffffff80,
14024    },{ .name = "L3_TXPMD_TM_39",  .addr = A_L3_TXPMD_TM_39,
14025        .ro = 0xfffffff8,
14026    },{ .name = "L3_TXPMD_TM_40",  .addr = A_L3_TXPMD_TM_40,
14027        .ro = 0xffffff00,
14028    },{ .name = "L3_TXPMD_TM_41",  .addr = A_L3_TXPMD_TM_41,
14029        .ro = 0xffffff00,
14030    },{ .name = "L3_TXPMD_TM_42",  .addr = A_L3_TXPMD_TM_42,
14031        .ro = 0xffffffe0,
14032    },{ .name = "L3_TXPMD_TM_43",  .addr = A_L3_TXPMD_TM_43,
14033        .ro = 0xfffffff0,
14034    },{ .name = "L3_TXPMD_TM_44",  .addr = A_L3_TXPMD_TM_44,
14035        .ro = 0xffffffc0,
14036    },{ .name = "L3_TXPMD_TM_45",  .addr = A_L3_TXPMD_TM_45,
14037        .ro = 0xffffffc0,
14038    },{ .name = "L3_TXPMD_TM_46",  .addr = A_L3_TXPMD_TM_46,
14039        .ro = 0xffffffc0,
14040    },{ .name = "L3_TXPMD_TM_47",  .addr = A_L3_TXPMD_TM_47,
14041        .ro = 0xffffff00,
14042    },{ .name = "L3_TXPMD_TM_48",  .addr = A_L3_TXPMD_TM_48,
14043        .ro = 0xffffffc0,
14044    },{ .name = "L3_TM_ANA_BYP_1",  .addr = A_L3_TM_ANA_BYP_1,
14045        .ro = 0xffffff00,
14046    },{ .name = "L3_TM_ANA_BYP_2",  .addr = A_L3_TM_ANA_BYP_2,
14047        .ro = 0xffffff00,
14048    },{ .name = "L3_TM_ANA_BYP_3",  .addr = A_L3_TM_ANA_BYP_3,
14049        .ro = 0xffffff00,
14050    },{ .name = "L3_TM_ANA_BYP_4",  .addr = A_L3_TM_ANA_BYP_4,
14051        .ro = 0xffffff00,
14052    },{ .name = "L3_TM_ANA_BYP_5",  .addr = A_L3_TM_ANA_BYP_5,
14053        .rsvd = 0xc0,
14054        .ro = 0xffffffc0,
14055    },{ .name = "L3_TM_ANA_BYP_7",  .addr = A_L3_TM_ANA_BYP_7,
14056        .rsvd = 0xf,
14057        .ro = 0xffffff0f,
14058    },{ .name = "L3_TM_ANA_BYP_8",  .addr = A_L3_TM_ANA_BYP_8,
14059        .ro = 0xffffff00,
14060    },{ .name = "L3_TM_ANA_BYP_9",  .addr = A_L3_TM_ANA_BYP_9,
14061        .ro = 0xffffff00,
14062    },{ .name = "L3_TM_ANA_BYP_10",  .addr = A_L3_TM_ANA_BYP_10,
14063        .rsvd = 0xc0,
14064        .ro = 0xffffffc0,
14065    },{ .name = "L3_TM_ANA_BYP_11",  .addr = A_L3_TM_ANA_BYP_11,
14066        .rsvd = 0xc0,
14067        .ro = 0xffffffc0,
14068    },{ .name = "L3_TM_ANA_BYP_12",  .addr = A_L3_TM_ANA_BYP_12,
14069        .ro = 0xffffff00,
14070    },{ .name = "L3_TM_ANA_BYP_13",  .addr = A_L3_TM_ANA_BYP_13,
14071        .rsvd = 0xfc,
14072        .ro = 0xfffffffc,
14073    },{ .name = "L3_TM_ANA_BYP_14",  .addr = A_L3_TM_ANA_BYP_14,
14074        .rsvd = 0xc,
14075        .ro = 0xffffff0c,
14076    },{ .name = "L3_TM_ANA_BYP_15",  .addr = A_L3_TM_ANA_BYP_15,
14077        .ro = 0xffffff00,
14078    },{ .name = "L3_TM_ANA_BYP_16",  .addr = A_L3_TM_ANA_BYP_16,
14079        .ro = 0xffffff00,
14080    },{ .name = "L3_TM_ANA_BYP_17",  .addr = A_L3_TM_ANA_BYP_17,
14081        .rsvd = 0x80,
14082        .ro = 0xffffff80,
14083    },{ .name = "L3_TM_ANA_BYP_18",  .addr = A_L3_TM_ANA_BYP_18,
14084        .rsvd = 0xf0,
14085        .ro = 0xfffffff0,
14086    },{ .name = "L3_TM_ANA_BYP_20",  .addr = A_L3_TM_ANA_BYP_20,
14087        .ro = 0xffffff00,
14088    },{ .name = "L3_TM_ANA_BYP_21",  .addr = A_L3_TM_ANA_BYP_21,
14089        .ro = 0xffffff00,
14090    },{ .name = "L3_TM_ANA_BYP_22",  .addr = A_L3_TM_ANA_BYP_22,
14091        .ro = 0xffffff00,
14092    },{ .name = "L3_TM_ANA_BYP_23",  .addr = A_L3_TM_ANA_BYP_23,
14093        .ro = 0xffffff00,
14094    },{ .name = "L3_TM_DIG_1",  .addr = A_L3_TM_DIG_1,
14095        .reset = 0x40,
14096        .ro = 0xffffff00,
14097    },{ .name = "L3_TM_DIG_2",  .addr = A_L3_TM_DIG_2,
14098        .rsvd = 0xc0,
14099        .ro = 0xffffffc0,
14100    },{ .name = "L3_TM_DIG_3",  .addr = A_L3_TM_DIG_3,
14101        .ro = 0xffffff00,
14102    },{ .name = "L3_TM_DIG_4",  .addr = A_L3_TM_DIG_4,
14103        .rsvd = 0x7,
14104        .ro = 0xffffff07,
14105    },{ .name = "L3_TM_DIG_5",  .addr = A_L3_TM_DIG_5,
14106        .rsvd = 0xf8,
14107        .ro = 0xfffffff8,
14108    },{ .name = "L3_TM_DIG_6",  .addr = A_L3_TM_DIG_6,
14109        .rsvd = 0x80,
14110        .ro = 0xffffff80,
14111    },{ .name = "L3_TM_DIG_7",  .addr = A_L3_TM_DIG_7,
14112        .ro = 0xffffff00,
14113    },{ .name = "L3_TM_DIG_8",  .addr = A_L3_TM_DIG_8,
14114        .rsvd = 0xe0,
14115        .ro = 0xffffffe0,
14116    },{ .name = "L3_TM_DIG_9",  .addr = A_L3_TM_DIG_9,
14117        .rsvd = 0xf0,
14118        .ro = 0xfffffff0,
14119    },{ .name = "L3_TM_DIG_10",  .addr = A_L3_TM_DIG_10,
14120        .reset = 0x1,
14121        .rsvd = 0xf0,
14122        .ro = 0xfffffff0,
14123    },{ .name = "L3_TM_DIG_11",  .addr = A_L3_TM_DIG_11,
14124        .rsvd = 0xf,
14125        .ro = 0xffffff0f,
14126    },{ .name = "L3_TM_DIG_12",  .addr = A_L3_TM_DIG_12,
14127        .rsvd = 0xc0,
14128        .ro = 0xffffffc0,
14129    },{ .name = "L3_TM_DIG_13",  .addr = A_L3_TM_DIG_13,
14130        .reset = 0x1a,
14131        .rsvd = 0x80,
14132        .ro = 0xffffff80,
14133    },{ .name = "L3_TM_DIG_14",  .addr = A_L3_TM_DIG_14,
14134        .rsvd = 0xf,
14135        .ro = 0xffffff0f,
14136    },{ .name = "L3_TM_DIG_15",  .addr = A_L3_TM_DIG_15,
14137        .reset = 0xd,
14138        .rsvd = 0xc0,
14139        .ro = 0xffffffc0,
14140    },{ .name = "L3_TM_DIG_16",  .addr = A_L3_TM_DIG_16,
14141        .rsvd = 0xe0,
14142        .ro = 0xffffffe0,
14143    },{ .name = "L3_TM_DIG_17",  .addr = A_L3_TM_DIG_17,
14144        .rsvd = 0xe0,
14145        .ro = 0xffffffe0,
14146    },{ .name = "L3_TM_DIG_18",  .addr = A_L3_TM_DIG_18,
14147        .reset = 0x2a,
14148        .ro = 0xffffff00,
14149    },{ .name = "L3_TM_DIG_19",  .addr = A_L3_TM_DIG_19,
14150        .reset = 0x36,
14151        .ro = 0xffffff00,
14152    },{ .name = "L3_TM_DIG_20",  .addr = A_L3_TM_DIG_20,
14153        .reset = 0x10,
14154        .rsvd = 0x80,
14155        .ro = 0xffffff80,
14156    },{ .name = "L3_TM_DIG_21",  .addr = A_L3_TM_DIG_21,
14157        .rsvd = 0xe0,
14158        .ro = 0xffffffe0,
14159    },{ .name = "L3_TM_DIG_22",  .addr = A_L3_TM_DIG_22,
14160        .rsvd = 0xc0,
14161        .ro = 0xffffffc0,
14162    },{ .name = "L3_TM_DIG_23",  .addr = A_L3_TM_DIG_23,
14163        .reset = 0x5,
14164        .ro = 0xffffff00,
14165    },{ .name = "L3_TM_DIG_24",  .addr = A_L3_TM_DIG_24,
14166        .ro = 0xffffff00,
14167    },{ .name = "L3_TM_DIG_25",  .addr = A_L3_TM_DIG_25,
14168        .ro = 0xffffff00,
14169    },{ .name = "L3_TM_DIG_26",  .addr = A_L3_TM_DIG_26,
14170        .ro = 0xffffff00,
14171    },{ .name = "L3_TM_DIG_27",  .addr = A_L3_TM_DIG_27,
14172        .ro = 0xffffff00,
14173    },{ .name = "L3_TM_DIG_28",  .addr = A_L3_TM_DIG_28,
14174        .ro = 0xffffff00,
14175    },{ .name = "L3_TM_DIG_29",  .addr = A_L3_TM_DIG_29,
14176        .ro = 0xffffff00,
14177    },{ .name = "L3_TM_AUX_0",  .addr = A_L3_TM_AUX_0,
14178        .ro = 0xffffff00,
14179    },{ .name = "L3_TM_AUX_1",  .addr = A_L3_TM_AUX_1,
14180        .ro = 0xffffff00,
14181    },{ .name = "L3_TM_AUX_2",  .addr = A_L3_TM_AUX_2,
14182        .ro = 0xffffff00,
14183    },{ .name = "L3_TM_AUX_3",  .addr = A_L3_TM_AUX_3,
14184        .ro = 0xffffff00,
14185    },{ .name = "L3_TM_AUX_4",  .addr = A_L3_TM_AUX_4,
14186        .ro = 0xffffff00,
14187    },{ .name = "L3_TM_DIG_30",  .addr = A_L3_TM_DIG_30,
14188        .rsvd = 0xc0,
14189        .ro = 0xffffffc0,
14190    },{ .name = "L3_TM_DIG_31",  .addr = A_L3_TM_DIG_31,
14191        .reset = 0xfa,
14192        .ro = 0xffffff00,
14193    },{ .name = "L3_TM_DIG_32",  .addr = A_L3_TM_DIG_32,
14194        .reset = 0xfa,
14195        .ro = 0xffffff00,
14196    },{ .name = "L3_TM_DIG_33",  .addr = A_L3_TM_DIG_33,
14197        .ro = 0xffffff00,
14198    },{ .name = "L3_TM_DIG_34",  .addr = A_L3_TM_DIG_34,
14199        .reset = 0x1e,
14200        .rsvd = 0xc0,
14201        .ro = 0xffffffc0,
14202    },{ .name = "L3_TM_DIG_35",  .addr = A_L3_TM_DIG_35,
14203        .reset = 0x18,
14204        .rsvd = 0xc0,
14205        .ro = 0xffffffc0,
14206    },{ .name = "L3_TM_DIG_36",  .addr = A_L3_TM_DIG_36,
14207        .ro = 0xffffff00,
14208    },{ .name = "L3_TM_DIG_37",  .addr = A_L3_TM_DIG_37,
14209        .rsvd = 0xe0,
14210        .ro = 0xffffffe0,
14211    },{ .name = "L3_TM_LFPS_1",  .addr = A_L3_TM_LFPS_1,
14212        .reset = 0x88,
14213        .ro = 0xffffff00,
14214    },{ .name = "L3_TM_LFPS_2",  .addr = A_L3_TM_LFPS_2,
14215        .reset = 0x34,
14216        .rsvd = 0x80,
14217        .ro = 0xffffff80,
14218    },{ .name = "L3_TM_LFPS_3",  .addr = A_L3_TM_LFPS_3,
14219        .reset = 0x6c,
14220        .ro = 0xffffff00,
14221    },{ .name = "L3_TM_LFPS_4",  .addr = A_L3_TM_LFPS_4,
14222        .rsvd = 0xc0,
14223        .ro = 0xffffffc0,
14224    },{ .name = "L3_TM_RXPMA_1",  .addr = A_L3_TM_RXPMA_1,
14225        .ro = 0xffffff00,
14226    },{ .name = "L3_TM_BSCAN_1",  .addr = A_L3_TM_BSCAN_1,
14227        .rsvd = 0xf8,
14228        .ro = 0xfffffff8,
14229    },{ .name = "L3_TM_MPHY_SQ_1",  .addr = A_L3_TM_MPHY_SQ_1,
14230        .reset = 0x1,
14231        .rsvd = 0xe0,
14232        .ro = 0xffffffe0,
14233    },{ .name = "L3_TM_LSRX_1",  .addr = A_L3_TM_LSRX_1,
14234        .ro = 0xffffff00,
14235    },{ .name = "L3_TM_LSRX_2",  .addr = A_L3_TM_LSRX_2,
14236        .rsvd = 0xc0,
14237        .ro = 0xffffffc0,
14238    },{ .name = "L3_TM_SIGDET_1",  .addr = A_L3_TM_SIGDET_1,
14239        .reset = 0x34,
14240        .rsvd = 0x80,
14241        .ro = 0xffffff80,
14242    },{ .name = "L3_TM_SIGDET_2",  .addr = A_L3_TM_SIGDET_2,
14243        .reset = 0xf,
14244        .ro = 0xffffff00,
14245    },{ .name = "L3_TM_DFT_1",  .addr = A_L3_TM_DFT_1,
14246        .rsvd = 0x7,
14247        .ro = 0xffffff07,
14248    },{ .name = "L3_TM_DFT_2",  .addr = A_L3_TM_DFT_2,
14249        .rsvd = 0xf8,
14250        .ro = 0xfffffff8,
14251    },{ .name = "L3_TM_DFT_3",  .addr = A_L3_TM_DFT_3,
14252        .rsvd = 0xe0,
14253        .ro = 0xffffffe0,
14254    },{ .name = "L3_TM_DFT_4",  .addr = A_L3_TM_DFT_4,
14255        .rsvd = 0xfc,
14256        .ro = 0xfffffffc,
14257    },{ .name = "L3_TM_DFT_5",  .addr = A_L3_TM_DFT_5,
14258        .ro = 0xffffff00,
14259    },{ .name = "L3_TM_DFT_6",  .addr = A_L3_TM_DFT_6,
14260        .ro = 0xffffff00,
14261    },{ .name = "L3_TM_DFT_7",  .addr = A_L3_TM_DFT_7,
14262        .rsvd = 0xe0,
14263        .ro = 0xffffffe0,
14264    },{ .name = "L3_TM_DFT_8",  .addr = A_L3_TM_DFT_8,
14265        .rsvd = 0xe0,
14266        .ro = 0xffffffe0,
14267    },{ .name = "L3_TM_DFT_9",  .addr = A_L3_TM_DFT_9,
14268        .ro = 0xffffff00,
14269    },{ .name = "L3_TM_DFT_10",  .addr = A_L3_TM_DFT_10,
14270        .rsvd = 0xf0,
14271        .ro = 0xfffffff0,
14272    },{ .name = "L3_TM_BG_1",  .addr = A_L3_TM_BG_1,
14273        .ro = 0xffffff00,
14274    },{ .name = "L3_TM_BG_2",  .addr = A_L3_TM_BG_2,
14275        .ro = 0xffffff00,
14276    },{ .name = "L3_TM_BG_3",  .addr = A_L3_TM_BG_3,
14277        .ro = 0xffffff00,
14278    },{ .name = "L3_TM_BG_4",  .addr = A_L3_TM_BG_4,
14279        .ro = 0xffffff00,
14280    },{ .name = "L3_TM_BG_5",  .addr = A_L3_TM_BG_5,
14281        .ro = 0xffffff00,
14282    },{ .name = "L3_TM_BG_6",  .addr = A_L3_TM_BG_6,
14283        .ro = 0xffffff00,
14284    },{ .name = "L3_TM_BG_7",  .addr = A_L3_TM_BG_7,
14285        .ro = 0xffffff00,
14286    },{ .name = "L3_TM_BG_8",  .addr = A_L3_TM_BG_8,
14287        .ro = 0xffffff00,
14288    },{ .name = "L3_TM_BG_9",  .addr = A_L3_TM_BG_9,
14289        .ro = 0xffffff00,
14290    },{ .name = "L3_TM_BG_10",  .addr = A_L3_TM_BG_10,
14291        .ro = 0xffffff00,
14292    },{ .name = "L3_TM_SD0",  .addr = A_L3_TM_SD0,
14293        .ro = 0xffffff00,
14294    },{ .name = "L3_TM_SD1",  .addr = A_L3_TM_SD1,
14295        .ro = 0xffffff00,
14296    },{ .name = "L3_TM_SD2",  .addr = A_L3_TM_SD2,
14297        .ro = 0xffffff00,
14298    },{ .name = "L3_TM_SD3",  .addr = A_L3_TM_SD3,
14299        .reset = 0x4,
14300        .ro = 0xffffff00,
14301    },{ .name = "L3_TM_SD4",  .addr = A_L3_TM_SD4,
14302        .rsvd = 0xe0,
14303        .ro = 0xffffffe0,
14304    },{ .name = "L3_TM_SD5",  .addr = A_L3_TM_SD5,
14305        .reset = 0xa,
14306        .ro = 0xffffff00,
14307    },{ .name = "L3_TM_SD6",  .addr = A_L3_TM_SD6,
14308        .rsvd = 0xe0,
14309        .ro = 0xffffffe0,
14310    },{ .name = "L3_TM_MISC1",  .addr = A_L3_TM_MISC1,
14311        .ro = 0xffffff00,
14312    },{ .name = "L3_TM_MISC2",  .addr = A_L3_TM_MISC2,
14313        .ro = 0xffffff03,
14314    },{ .name = "L3_TM_EYE_SURF0",  .addr = A_L3_TM_EYE_SURF0,
14315        .ro = 0xffffff80,
14316    },{ .name = "L3_TM_EYE_SURF1",  .addr = A_L3_TM_EYE_SURF1,
14317        .ro = 0xffffff00,
14318    },{ .name = "L3_TM_EYE_SURF2",  .addr = A_L3_TM_EYE_SURF2,
14319        .ro = 0xffffff00,
14320    },{ .name = "L3_TM_EYE_SURF3",  .addr = A_L3_TM_EYE_SURF3,
14321        .ro = 0xffffff00,
14322    },{ .name = "L3_TM_EYE_SURF4",  .addr = A_L3_TM_EYE_SURF4,
14323        .ro = 0xffffff00,
14324    },{ .name = "L3_TM_EYE_SURF5",  .addr = A_L3_TM_EYE_SURF5,
14325        .ro = 0xffffff00,
14326    },{ .name = "L3_TM_EYE_SURF6",  .addr = A_L3_TM_EYE_SURF6,
14327        .ro = 0xffffff00,
14328    },{ .name = "L3_TM_EYE_SURF7",  .addr = A_L3_TM_EYE_SURF7,
14329        .ro = 0xffffff00,
14330    },{ .name = "L3_TM_EYE_SURF8",  .addr = A_L3_TM_EYE_SURF8,
14331        .ro = 0xffffff00,
14332    },{ .name = "L3_TM_EYE_SURF9",  .addr = A_L3_TM_EYE_SURF9,
14333        .ro = 0xffffff00,
14334    },{ .name = "L3_TM_SPARE",  .addr = A_L3_TM_SPARE,
14335        .ro = 0xffffff00,
14336    },{ .name = "L3_TM_ANA_EQ1",  .addr = A_L3_TM_ANA_EQ1,
14337        .reset = 0xc,
14338        .ro = 0xffffffe0,
14339    },{ .name = "L3_TM_ANA_E_PI0",  .addr = A_L3_TM_ANA_E_PI0,
14340        .reset = 0xa0,
14341        .ro = 0xffffff1f,
14342    },{ .name = "L3_TM_ANA_IQ_PI0",  .addr = A_L3_TM_ANA_IQ_PI0,
14343        .reset = 0xa0,
14344        .ro = 0xffffff1f,
14345    },{ .name = "L3_TM_ANA_MISC0",  .addr = A_L3_TM_ANA_MISC0,
14346        .ro = 0xffffff3f,
14347    },{ .name = "L3_TM_SAMP_CODE_IQ_PH0",  .addr = A_L3_TM_SAMP_CODE_IQ_PH0,
14348        .ro = 0xffffff80,
14349    },{ .name = "L3_TM_SAMP_CODE_IQ_PH90",  .addr = A_L3_TM_SAMP_CODE_IQ_PH90,
14350        .ro = 0xffffff00,
14351    },{ .name = "L3_TM_SAMP_CODE_IQ_PH180",  .addr = A_L3_TM_SAMP_CODE_IQ_PH180,
14352        .ro = 0xffffffc0,
14353    },{ .name = "L3_TM_SAMP_CODE_IQ_PH270",  .addr = A_L3_TM_SAMP_CODE_IQ_PH270,
14354        .ro = 0xffffff00,
14355    },{ .name = "L3_TM_SAMP_CODE_E_PH0",  .addr = A_L3_TM_SAMP_CODE_E_PH0,
14356        .ro = 0xffffffc0,
14357    },{ .name = "L3_TM_SAMP_CODE_E_PH180",  .addr = A_L3_TM_SAMP_CODE_E_PH180,
14358        .ro = 0xffffffc0,
14359    },{ .name = "L3_TM_IQ_ILL0",  .addr = A_L3_TM_IQ_ILL0,
14360        .ro = 0xffffff00,
14361    },{ .name = "L3_TM_IQ_ILL1",  .addr = A_L3_TM_IQ_ILL1,
14362        .ro = 0xffffff00,
14363    },{ .name = "L3_TM_IQ_ILL2",  .addr = A_L3_TM_IQ_ILL2,
14364        .ro = 0xffffff00,
14365    },{ .name = "L3_TM_IQ_ILL3",  .addr = A_L3_TM_IQ_ILL3,
14366        .ro = 0xffffff00,
14367    },{ .name = "L3_TM_IQ_ILL4",  .addr = A_L3_TM_IQ_ILL4,
14368        .ro = 0xffffff00,
14369    },{ .name = "L3_TM_IQ_ILL5",  .addr = A_L3_TM_IQ_ILL5,
14370        .ro = 0xffffff00,
14371    },{ .name = "L3_TM_IQ_ILL6",  .addr = A_L3_TM_IQ_ILL6,
14372        .ro = 0xffffff00,
14373    },{ .name = "L3_TM_IQ_ILL7",  .addr = A_L3_TM_IQ_ILL7,
14374        .ro = 0xffffff00,
14375    },{ .name = "L3_TM_IQ_ILL8",  .addr = A_L3_TM_IQ_ILL8,
14376        .ro = 0xffffff00,
14377    },{ .name = "L3_TM_IQ_ILL9",  .addr = A_L3_TM_IQ_ILL9,
14378        .ro = 0xfffffff0,
14379    },{ .name = "L3_TM_IQ_ILL10",  .addr = A_L3_TM_IQ_ILL10,
14380        .reset = 0x3,
14381        .ro = 0xffffffc0,
14382    },{ .name = "L3_TM_E_ILL0",  .addr = A_L3_TM_E_ILL0,
14383        .ro = 0xffffff00,
14384    },{ .name = "L3_TM_E_ILL1",  .addr = A_L3_TM_E_ILL1,
14385        .ro = 0xffffff00,
14386    },{ .name = "L3_TM_E_ILL2",  .addr = A_L3_TM_E_ILL2,
14387        .ro = 0xffffff00,
14388    },{ .name = "L3_TM_E_ILL3",  .addr = A_L3_TM_E_ILL3,
14389        .ro = 0xffffff00,
14390    },{ .name = "L3_TM_E_ILL4",  .addr = A_L3_TM_E_ILL4,
14391        .ro = 0xffffff00,
14392    },{ .name = "L3_TM_E_ILL5",  .addr = A_L3_TM_E_ILL5,
14393        .ro = 0xffffff00,
14394    },{ .name = "L3_TM_E_ILL6",  .addr = A_L3_TM_E_ILL6,
14395        .ro = 0xffffff00,
14396    },{ .name = "L3_TM_E_ILL7",  .addr = A_L3_TM_E_ILL7,
14397        .ro = 0xffffff00,
14398    },{ .name = "L3_TM_E_ILL8",  .addr = A_L3_TM_E_ILL8,
14399        .ro = 0xffffff00,
14400    },{ .name = "L3_TM_E_ILL9",  .addr = A_L3_TM_E_ILL9,
14401        .ro = 0xfffffff0,
14402    },{ .name = "L3_TM_E_ILL10",  .addr = A_L3_TM_E_ILL10,
14403        .reset = 0x3,
14404        .ro = 0xffffffc0,
14405    },{ .name = "L3_TM_EQ0",  .addr = A_L3_TM_EQ0,
14406        .ro = 0xffffff00,
14407    },{ .name = "L3_TM_EQ1",  .addr = A_L3_TM_EQ1,
14408        .ro = 0xffffff00,
14409    },{ .name = "L3_TM_EQ2",  .addr = A_L3_TM_EQ2,
14410        .ro = 0xffffff80,
14411    },{ .name = "L3_TM_EQ3",  .addr = A_L3_TM_EQ3,
14412        .ro = 0xffffffe0,
14413    },{ .name = "L3_TM_EQ4",  .addr = A_L3_TM_EQ4,
14414        .ro = 0xffffffe0,
14415    },{ .name = "L3_TM_EQ5",  .addr = A_L3_TM_EQ5,
14416        .ro = 0xffffffc0,
14417    },{ .name = "L3_TM_EQ6",  .addr = A_L3_TM_EQ6,
14418        .ro = 0xffffffe0,
14419    },{ .name = "L3_TM_EQ7",  .addr = A_L3_TM_EQ7,
14420        .ro = 0xffffffc0,
14421    },{ .name = "L3_TM_EQ8",  .addr = A_L3_TM_EQ8,
14422        .ro = 0xffffff00,
14423    },{ .name = "L3_TM_EQ9",  .addr = A_L3_TM_EQ9,
14424        .ro = 0xffffff80,
14425    },{ .name = "L3_TM_EQ10",  .addr = A_L3_TM_EQ10,
14426        .ro = 0xffffff80,
14427    },{ .name = "L3_TM_EQ11",  .addr = A_L3_TM_EQ11,
14428        .ro = 0xffffff00,
14429    },{ .name = "L3_TM_ILL7",  .addr = A_L3_TM_ILL7,
14430        .reset = 0x5,
14431        .ro = 0xffffff00,
14432    },{ .name = "L3_TM_ILL8",  .addr = A_L3_TM_ILL8,
14433        .reset = 0x2,
14434        .ro = 0xffffff00,
14435    },{ .name = "L3_TM_ILL9",  .addr = A_L3_TM_ILL9,
14436        .reset = 0x40,
14437        .ro = 0xffffff00,
14438    },{ .name = "L3_TM_ILL10",  .addr = A_L3_TM_ILL10,
14439        .ro = 0xffffff00,
14440    },{ .name = "L3_TM_ILL11",  .addr = A_L3_TM_ILL11,
14441        .ro = 0xffffff00,
14442    },{ .name = "L3_TM_ILL12",  .addr = A_L3_TM_ILL12,
14443        .ro = 0xffffff00,
14444    },{ .name = "L3_TM_ILL13",  .addr = A_L3_TM_ILL13,
14445        .reset = 0x1,
14446        .rsvd = 0xf8,
14447        .ro = 0xfffffff8,
14448    },{ .name = "L3_TM_ILL14",  .addr = A_L3_TM_ILL14,
14449        .reset = 0x51,
14450        .ro = 0xffffff00,
14451    },{ .name = "L3_TM_FRZ_FSM0",  .addr = A_L3_TM_FRZ_FSM0,
14452        .ro = 0xffffff00,
14453    },{ .name = "L3_TM_FRZ_FSM1",  .addr = A_L3_TM_FRZ_FSM1,
14454        .ro = 0xffffffc0,
14455    },{ .name = "L3_TM_RST_DLY",  .addr = A_L3_TM_RST_DLY,
14456        .ro = 0xffffff00,
14457    },{ .name = "L3_TM_ILL15",  .addr = A_L3_TM_ILL15,
14458        .ro = 0xffffff00,
14459    },{ .name = "L3_TM_MISC3",  .addr = A_L3_TM_MISC3,
14460        .reset = 0x3,
14461        .ro = 0xffffff00,
14462    },{ .name = "L3_TM_EQ_OFFS1",  .addr = A_L3_TM_EQ_OFFS1,
14463        .ro = 0xffffff00,
14464    },{ .name = "L3_TM_SAMP0",  .addr = A_L3_TM_SAMP0,
14465        .ro = 0xffffff00,
14466    },{ .name = "L3_TM_EQ12",  .addr = A_L3_TM_EQ12,
14467        .ro = 0xffffff00,
14468    },{ .name = "L3_TM_MISC4",  .addr = A_L3_TM_MISC4,
14469        .rsvd = 0xf8,
14470        .ro = 0xfffffff8,
14471    },{ .name = "L3_TM_SAMP_STATUS0",  .addr = A_L3_TM_SAMP_STATUS0,
14472        .rsvd = 0xc0,
14473        .ro = 0xffffffff,
14474    },{ .name = "L3_TM_SAMP_STATUS1",  .addr = A_L3_TM_SAMP_STATUS1,
14475        .rsvd = 0xc0,
14476        .ro = 0xffffffff,
14477    },{ .name = "L3_TM_SAMP_STATUS2",  .addr = A_L3_TM_SAMP_STATUS2,
14478        .rsvd = 0xc0,
14479        .ro = 0xffffffff,
14480    },{ .name = "L3_TM_SAMP_STATUS3",  .addr = A_L3_TM_SAMP_STATUS3,
14481        .rsvd = 0xc0,
14482        .ro = 0xffffffff,
14483    },{ .name = "L3_TM_SAMP_STATUS4",  .addr = A_L3_TM_SAMP_STATUS4,
14484        .rsvd = 0xc0,
14485        .ro = 0xffffffff,
14486    },{ .name = "L3_TM_SAMP_STATUS5",  .addr = A_L3_TM_SAMP_STATUS5,
14487        .rsvd = 0xc0,
14488        .ro = 0xffffffff,
14489    },{ .name = "L3_TM_ILL_STATUS0",  .addr = A_L3_TM_ILL_STATUS0,
14490        .rsvd = 0x80,
14491        .ro = 0xffffffff,
14492    },{ .name = "L3_TM_ILL_STATUS1",  .addr = A_L3_TM_ILL_STATUS1,
14493        .rsvd = 0x80,
14494        .ro = 0xffffffff,
14495    },{ .name = "L3_TM_ILL_STATUS2",  .addr = A_L3_TM_ILL_STATUS2,
14496        .rsvd = 0x80,
14497        .ro = 0xffffffff,
14498    },{ .name = "L3_TM_ILL_STATUS3",  .addr = A_L3_TM_ILL_STATUS3,
14499        .rsvd = 0x80,
14500        .ro = 0xffffffff,
14501    },{ .name = "L3_TM_ILL_STATUS4",  .addr = A_L3_TM_ILL_STATUS4,
14502        .rsvd = 0x80,
14503        .ro = 0xffffffff,
14504    },{ .name = "L3_TM_ILL_STATUS5",  .addr = A_L3_TM_ILL_STATUS5,
14505        .rsvd = 0x80,
14506        .ro = 0xffffffff,
14507    },{ .name = "L3_TM_ILL_STATUS6",  .addr = A_L3_TM_ILL_STATUS6,
14508        .rsvd = 0x80,
14509        .ro = 0xffffffff,
14510    },{ .name = "L3_TM_ILL_STATUS7",  .addr = A_L3_TM_ILL_STATUS7,
14511        .rsvd = 0x80,
14512        .ro = 0xffffffff,
14513    },{ .name = "L3_TM_ILL_STATUS8",  .addr = A_L3_TM_ILL_STATUS8,
14514        .rsvd = 0x80,
14515        .ro = 0xffffffff,
14516    },{ .name = "L3_TM_ILL_STATUS9",  .addr = A_L3_TM_ILL_STATUS9,
14517        .rsvd = 0x80,
14518        .ro = 0xffffffff,
14519    },{ .name = "L3_TM_ILL_STATUS10",  .addr = A_L3_TM_ILL_STATUS10,
14520        .rsvd = 0x80,
14521        .ro = 0xffffffff,
14522    },{ .name = "L3_TM_ILL_STATUS11",  .addr = A_L3_TM_ILL_STATUS11,
14523        .rsvd = 0x80,
14524        .ro = 0xffffffff,
14525    },{ .name = "L3_TM_MISC_ST_0",  .addr = A_L3_TM_MISC_ST_0,
14526        .rsvd = 0xc0,
14527        .ro = 0xffffffff,
14528    },{ .name = "L3_TM_SD_ST_0",  .addr = A_L3_TM_SD_ST_0,
14529        .reset = 0x12,
14530        .rsvd = 0xc0,
14531        .ro = 0xffffffff,
14532    },{ .name = "L3_TM_EYESURF_ST0",  .addr = A_L3_TM_EYESURF_ST0,
14533        .ro = 0xffffffff,
14534    },{ .name = "L3_TM_EYESURF_ST1",  .addr = A_L3_TM_EYESURF_ST1,
14535        .ro = 0xffffffff,
14536    },{ .name = "L3_TM_EQ_ST0",  .addr = A_L3_TM_EQ_ST0,
14537        .reset = 0xff,
14538        .ro = 0xffffffff,
14539    },{ .name = "L3_TM_EQ_ST1",  .addr = A_L3_TM_EQ_ST1,
14540        .ro = 0xffffffff,
14541    },{ .name = "L3_TM_EQ_ST2",  .addr = A_L3_TM_EQ_ST2,
14542        .rsvd = 0x80,
14543        .ro = 0xffffffff,
14544    },{ .name = "L3_TM_RXPMA_ST1",  .addr = A_L3_TM_RXPMA_ST1,
14545        .ro = 0xffffffff,
14546    },{ .name = "L3_TM_CDR0",  .addr = A_L3_TM_CDR0,
14547        .ro = 0xffffff60,
14548    },{ .name = "L3_TM_CDR1",  .addr = A_L3_TM_CDR1,
14549        .ro = 0xffffff00,
14550    },{ .name = "L3_TM_CDR2",  .addr = A_L3_TM_CDR2,
14551        .ro = 0xffffff00,
14552    },{ .name = "L3_TM_CDR3",  .addr = A_L3_TM_CDR3,
14553        .ro = 0xffffff80,
14554    },{ .name = "L3_TM_CDR4",  .addr = A_L3_TM_CDR4,
14555        .ro = 0xffffff80,
14556    },{ .name = "L3_TM_CDR5",  .addr = A_L3_TM_CDR5,
14557        .ro = 0xffffff00,
14558    },{ .name = "L3_TM_CDR6",  .addr = A_L3_TM_CDR6,
14559        .ro = 0xffffff00,
14560    },{ .name = "L3_TM_CDR7",  .addr = A_L3_TM_CDR7,
14561        .ro = 0xffffff00,
14562    },{ .name = "L3_TM_CDR8",  .addr = A_L3_TM_CDR8,
14563        .ro = 0xffffff00,
14564    },{ .name = "L3_TM_CDR9",  .addr = A_L3_TM_CDR9,
14565        .ro = 0xffffff00,
14566    },{ .name = "L3_TM_CDR10",  .addr = A_L3_TM_CDR10,
14567        .ro = 0xffffff00,
14568    },{ .name = "L3_TM_CDR11",  .addr = A_L3_TM_CDR11,
14569        .ro = 0xffffffe0,
14570    },{ .name = "L3_TM_CDR12",  .addr = A_L3_TM_CDR12,
14571        .ro = 0xffffff00,
14572    },{ .name = "L3_TM_CDR13",  .addr = A_L3_TM_CDR13,
14573        .ro = 0xffffff00,
14574    },{ .name = "L3_TM_CDR14",  .addr = A_L3_TM_CDR14,
14575        .ro = 0xffffff00,
14576    },{ .name = "L3_TM_CDR15",  .addr = A_L3_TM_CDR15,
14577        .ro = 0xffffff00,
14578    },{ .name = "L3_TM_CDR16",  .addr = A_L3_TM_CDR16,
14579        .ro = 0xffffffe0,
14580    },{ .name = "L3_TM_CDR17",  .addr = A_L3_TM_CDR17,
14581        .ro = 0xffffffe0,
14582    },{ .name = "L3_TM_CDR18",  .addr = A_L3_TM_CDR18,
14583        .ro = 0xffffffe0,
14584    },{ .name = "L3_TM_CDR19",  .addr = A_L3_TM_CDR19,
14585        .ro = 0xffffffe0,
14586    },{ .name = "L3_TM_CDR20",  .addr = A_L3_TM_CDR20,
14587        .ro = 0xffffffe0,
14588    },{ .name = "L3_TM_CDR21",  .addr = A_L3_TM_CDR21,
14589        .ro = 0xffffffe0,
14590    },{ .name = "L3_TM_CDR22",  .addr = A_L3_TM_CDR22,
14591        .ro = 0xffffffe0,
14592    },{ .name = "L3_TM_CDR23",  .addr = A_L3_TM_CDR23,
14593        .ro = 0xffffff80,
14594    },{ .name = "L3_TM_MISC0",  .addr = A_L3_TM_MISC0,
14595        .ro = 0xfffffffc,
14596    },{ .name = "L3_TM_HSRX_ST0",  .addr = A_L3_TM_HSRX_ST0,
14597        .rsvd = 0xfe,
14598        .ro = 0xffffffff,
14599    },{ .name = "L3_TM_PLL_LS_CLOCK",  .addr = A_L3_TM_PLL_LS_CLOCK,
14600        .ro = 0xffffff00,
14601    },{ .name = "L3_TM_PLL_LOOP_FILT",  .addr = A_L3_TM_PLL_LOOP_FILT,
14602        .ro = 0xffffff00,
14603    },{ .name = "L3_TM_PLL_DIG2",  .addr = A_L3_TM_PLL_DIG2,
14604        .ro = 0xffffff00,
14605    },{ .name = "L3_TM_PLL_FBDIV",  .addr = A_L3_TM_PLL_FBDIV,
14606        .ro = 0xffffff00,
14607    },{ .name = "L3_TM_PLL_DIG4",  .addr = A_L3_TM_PLL_DIG4,
14608        .reset = 0x80,
14609        .ro = 0xffffff00,
14610    },{ .name = "L3_TM_PLL_DIG5",  .addr = A_L3_TM_PLL_DIG5,
14611        .reset = 0xc0,
14612        .ro = 0xffffff00,
14613    },{ .name = "L3_TM_PLL_DIG6",  .addr = A_L3_TM_PLL_DIG6,
14614        .reset = 0x3,
14615        .ro = 0xffffff00,
14616    },{ .name = "L3_TM_PLL_DIG7",  .addr = A_L3_TM_PLL_DIG7,
14617        .ro = 0xffffff00,
14618    },{ .name = "L3_TM_PLL_CPUMP_CODE_1",  .addr = A_L3_TM_PLL_CPUMP_CODE_1,
14619        .ro = 0xffffff00,
14620    },{ .name = "L3_TM_PLL_DIG9",  .addr = A_L3_TM_PLL_DIG9,
14621        .ro = 0xffffffc0,
14622    },{ .name = "L3_TM_PLL_COARSE_CODE_LSB",  .addr = A_L3_TM_PLL_COARSE_CODE_LSB,
14623        .ro = 0xffffff00,
14624    },{ .name = "L3_TM_PLL_DIG11",  .addr = A_L3_TM_PLL_DIG11,
14625        .ro = 0xffffff00,
14626    },{ .name = "L3_TM_PLL_DIG12",  .addr = A_L3_TM_PLL_DIG12,
14627        .ro = 0xffffff00,
14628    },{ .name = "L3_TM_PLL_CONST_PMOS",  .addr = A_L3_TM_PLL_CONST_PMOS,
14629        .ro = 0xffffff00,
14630    },{ .name = "L3_TM_PLL_DIG14",  .addr = A_L3_TM_PLL_DIG14,
14631        .ro = 0xffffff00,
14632    },{ .name = "L3_TM_PLL_DIG15",  .addr = A_L3_TM_PLL_DIG15,
14633        .ro = 0xffffff00,
14634    },{ .name = "L3_TM_PLL_DIG16",  .addr = A_L3_TM_PLL_DIG16,
14635        .ro = 0xffffff10,
14636    },{ .name = "L3_TM_PLL_DIG17",  .addr = A_L3_TM_PLL_DIG17,
14637        .ro = 0xffffff00,
14638    },{ .name = "L3_TM_PLL_DIG18",  .addr = A_L3_TM_PLL_DIG18,
14639        .ro = 0xffffff00,
14640    },{ .name = "L3_TM_PLL_DIG19",  .addr = A_L3_TM_PLL_DIG19,
14641        .ro = 0xffffff00,
14642    },{ .name = "L3_TM_PLL_DIG20",  .addr = A_L3_TM_PLL_DIG20,
14643        .ro = 0xffffff40,
14644    },{ .name = "L3_TM_PLL_DIG21",  .addr = A_L3_TM_PLL_DIG21,
14645        .reset = 0x20,
14646        .ro = 0xffffff0c,
14647    },{ .name = "L3_TM_PLL_DIG22",  .addr = A_L3_TM_PLL_DIG22,
14648        .ro = 0xffffff80,
14649    },{ .name = "L3_TM_PLL_DIG23",  .addr = A_L3_TM_PLL_DIG23,
14650        .reset = 0x31,
14651        .ro = 0xffffff00,
14652    },{ .name = "L3_TM_PLL_DIG24",  .addr = A_L3_TM_PLL_DIG24,
14653        .ro = 0xffffff80,
14654    },{ .name = "L3_TM_PLL_DIG25",  .addr = A_L3_TM_PLL_DIG25,
14655        .ro = 0xffffff00,
14656    },{ .name = "L3_TM_PLL_DIG26",  .addr = A_L3_TM_PLL_DIG26,
14657        .reset = 0x40,
14658        .ro = 0xffffff80,
14659    },{ .name = "L3_TM_PLL_CLK_DIST_NTRIM_LSB",  .addr = A_L3_TM_PLL_CLK_DIST_NTRIM_LSB,
14660        .ro = 0xffffff00,
14661    },{ .name = "L3_TM_PLL_CLK_DIST_PTRIM_LSB",  .addr = A_L3_TM_PLL_CLK_DIST_PTRIM_LSB,
14662        .ro = 0xffffff00,
14663    },{ .name = "L3_TM_PLL_DIG_29",  .addr = A_L3_TM_PLL_DIG_29,
14664        .ro = 0xffffff00,
14665    },{ .name = "L3_TM_PLL_DIG_30",  .addr = A_L3_TM_PLL_DIG_30,
14666        .ro = 0xffffff00,
14667    },{ .name = "L3_TM_PLL_DIG_31",  .addr = A_L3_TM_PLL_DIG_31,
14668        .ro = 0xffffff00,
14669    },{ .name = "L3_TM_PLL_DIG_32",  .addr = A_L3_TM_PLL_DIG_32,
14670        .ro = 0xffffff00,
14671    },{ .name = "L3_TM_PLL_DIG_33",  .addr = A_L3_TM_PLL_DIG_33,
14672        .ro = 0xffffff00,
14673    },{ .name = "L3_TM_PLL_DIG_34",  .addr = A_L3_TM_PLL_DIG_34,
14674        .ro = 0xffffff80,
14675    },{ .name = "L3_TM_PLL_DIG_35",  .addr = A_L3_TM_PLL_DIG_35,
14676        .ro = 0xffffff00,
14677    },{ .name = "L3_TM_PLL_DIG_36",  .addr = A_L3_TM_PLL_DIG_36,
14678        .ro = 0xffffff00,
14679    },{ .name = "L3_TM_PLL_DIG_37",  .addr = A_L3_TM_PLL_DIG_37,
14680        .ro = 0xffffff00,
14681    },{ .name = "L3_TM_PLL_COARSE_CODE_SAT_MSB",  .addr = A_L3_TM_PLL_COARSE_CODE_SAT_MSB,
14682        .ro = 0xffffff00,
14683    },{ .name = "L3_MPHY_CFG_HIB8",  .addr = A_L3_MPHY_CFG_HIB8,
14684        .ro = 0xfffffffe,
14685    },{ .name = "L3_MPHY_CFG_MODE",  .addr = A_L3_MPHY_CFG_MODE,
14686        .ro = 0xfffffffc,
14687    },{ .name = "L3_MPHY_CFG_HS_GEAR",  .addr = A_L3_MPHY_CFG_HS_GEAR,
14688        .ro = 0xfffffffc,
14689    },{ .name = "L3_MPHY_CFG_HS_RATE",  .addr = A_L3_MPHY_CFG_HS_RATE,
14690        .ro = 0xfffffffe,
14691    },{ .name = "L3_MPHY_CFG_PWM",  .addr = A_L3_MPHY_CFG_PWM,
14692        .ro = 0xfffffff8,
14693    },{ .name = "L3_PLL_OPDIV_LS",  .addr = A_L3_PLL_OPDIV_LS,
14694        .ro = 0xffffff00,
14695    },{ .name = "L3_MPHY_CFG_UPDT",  .addr = A_L3_MPHY_CFG_UPDT,
14696        .ro = 0xfffffffe,
14697    },{ .name = "L3_PLL_TM_DIV_CNTRLS",  .addr = A_L3_PLL_TM_DIV_CNTRLS,
14698        .reset = 0x40,
14699        .ro = 0xffffff20,
14700    },{ .name = "L3_PLL_FBDIV_G1A_LSB",  .addr = A_L3_PLL_FBDIV_G1A_LSB,
14701        .ro = 0xffffff00,
14702    },{ .name = "L3_PLL_FBDIV_G1B_LSB",  .addr = A_L3_PLL_FBDIV_G1B_LSB,
14703        .ro = 0xffffff00,
14704    },{ .name = "L3_PLL_FBDIV_G2A_LSB",  .addr = A_L3_PLL_FBDIV_G2A_LSB,
14705        .ro = 0xffffff00,
14706    },{ .name = "L3_PLL_FBDIV_G2B_LSB",  .addr = A_L3_PLL_FBDIV_G2B_LSB,
14707        .ro = 0xffffff00,
14708    },{ .name = "L3_PLL_FBDIV_G3A_LSB",  .addr = A_L3_PLL_FBDIV_G3A_LSB,
14709        .ro = 0xffffff00,
14710    },{ .name = "L3_PLL_FBDIV_G3B_LSB",  .addr = A_L3_PLL_FBDIV_G3B_LSB,
14711        .ro = 0xffffff00,
14712    },{ .name = "L3_PLL_FBDIV_G1A_MSB",  .addr = A_L3_PLL_FBDIV_G1A_MSB,
14713        .ro = 0xffffff00,
14714    },{ .name = "L3_PLL_FBDIV_G1B_MSB",  .addr = A_L3_PLL_FBDIV_G1B_MSB,
14715        .ro = 0xffffff00,
14716    },{ .name = "L3_PLL_FBDIV_G2A_MSB",  .addr = A_L3_PLL_FBDIV_G2A_MSB,
14717        .ro = 0xffffff00,
14718    },{ .name = "L3_PLL_FBDIV_G2B_MSB",  .addr = A_L3_PLL_FBDIV_G2B_MSB,
14719        .ro = 0xffffff00,
14720    },{ .name = "L3_PLL_FBDIV_G3A_MSB",  .addr = A_L3_PLL_FBDIV_G3A_MSB,
14721        .ro = 0xffffff00,
14722    },{ .name = "L3_PLL_FBDIV_G3B_MSB",  .addr = A_L3_PLL_FBDIV_G3B_MSB,
14723        .ro = 0xffffff00,
14724    },{ .name = "L3_PLL_IPDIV",  .addr = A_L3_PLL_IPDIV,
14725        .ro = 0xffffff00,
14726    },{ .name = "L3_PLL_FBDIV_FRAC_0_LSB",  .addr = A_L3_PLL_FBDIV_FRAC_0_LSB,
14727        .ro = 0xffffff00,
14728    },{ .name = "L3_PLL_FBDIV_FRAC_1",  .addr = A_L3_PLL_FBDIV_FRAC_1,
14729        .ro = 0xffffff00,
14730    },{ .name = "L3_PLL_FBDIV_FRAC_2",  .addr = A_L3_PLL_FBDIV_FRAC_2,
14731        .ro = 0xffffff00,
14732    },{ .name = "L3_PLL_FBDIV_FRAC_3_MSB",  .addr = A_L3_PLL_FBDIV_FRAC_3_MSB,
14733        .ro = 0xffffff98,
14734    },{ .name = "L3_PLL_PWR_SEQ_WAIT_TIME",  .addr = A_L3_PLL_PWR_SEQ_WAIT_TIME,
14735        .ro = 0xffffff00,
14736    },{ .name = "L3_PLL_SS_STEPS_0_LSB",  .addr = A_L3_PLL_SS_STEPS_0_LSB,
14737        .ro = 0xffffff00,
14738    },{ .name = "L3_PLL_SS_STEPS_1_MSB",  .addr = A_L3_PLL_SS_STEPS_1_MSB,
14739        .ro = 0xfffffff8,
14740    },{ .name = "L3_PLL_SS_STEP_SIZE_0_LSB",  .addr = A_L3_PLL_SS_STEP_SIZE_0_LSB,
14741        .ro = 0xffffff00,
14742    },{ .name = "L3_PLL_SS_STEP_SIZE_1",  .addr = A_L3_PLL_SS_STEP_SIZE_1,
14743        .ro = 0xffffff00,
14744    },{ .name = "L3_PLL_SS_STEP_SIZE_2",  .addr = A_L3_PLL_SS_STEP_SIZE_2,
14745        .ro = 0xffffff00,
14746    },{ .name = "L3_PLL_SS_STEP_SIZE_3_MSB",  .addr = A_L3_PLL_SS_STEP_SIZE_3_MSB,
14747        .ro = 0xffffff00,
14748    },{ .name = "L3_TM_MASK_CFG_UPDT",  .addr = A_L3_TM_MASK_CFG_UPDT,
14749        .ro = 0xffffff80,
14750    },{ .name = "L3_PLL_TM_FORCE_DIV",  .addr = A_L3_PLL_TM_FORCE_DIV,
14751        .ro = 0xffffff00,
14752    },{ .name = "L3_PLL_TM_COARSE_CODE_1_LSB",  .addr = A_L3_PLL_TM_COARSE_CODE_1_LSB,
14753        .ro = 0xffffff00,
14754    },{ .name = "L3_PLL_TM_COARSE_CODE_2_LSB",  .addr = A_L3_PLL_TM_COARSE_CODE_2_LSB,
14755        .ro = 0xffffff00,
14756    },{ .name = "L3_PLL_TM_COARSE_CODE_3_LSB",  .addr = A_L3_PLL_TM_COARSE_CODE_3_LSB,
14757        .ro = 0xffffff00,
14758    },{ .name = "L3_PLL_TM_COARSE_CODE_4_LSB",  .addr = A_L3_PLL_TM_COARSE_CODE_4_LSB,
14759        .ro = 0xffffff00,
14760    },{ .name = "L3_PLL_TM_COARSE_CODE_5_LSB",  .addr = A_L3_PLL_TM_COARSE_CODE_5_LSB,
14761        .ro = 0xffffff00,
14762    },{ .name = "L3_PLL_TM_COARSE_CODE_6_LSB",  .addr = A_L3_PLL_TM_COARSE_CODE_6_LSB,
14763        .ro = 0xffffff00,
14764    },{ .name = "L3_PLL_TM_COARSE_CODE_1_2_MSB",  .addr = A_L3_PLL_TM_COARSE_CODE_1_2_MSB,
14765        .ro = 0xffffffc0,
14766    },{ .name = "L3_PLL_TM_COARSE_CODE_3_4_MSB",  .addr = A_L3_PLL_TM_COARSE_CODE_3_4_MSB,
14767        .ro = 0xffffffc0,
14768    },{ .name = "L3_PLL_TM_COARSE_CODE_5_6_MSB",  .addr = A_L3_PLL_TM_COARSE_CODE_5_6_MSB,
14769        .ro = 0xffffffc0,
14770    },{ .name = "L3_PLL_TM_SHARED_0",  .addr = A_L3_PLL_TM_SHARED_0,
14771        .ro = 0xffffff00,
14772    },{ .name = "L3_PLL_TM_FRAC_OFFSET_0",  .addr = A_L3_PLL_TM_FRAC_OFFSET_0,
14773        .ro = 0xffffff00,
14774    },{ .name = "L3_PLL_TM_FRAC_OFFSET_1",  .addr = A_L3_PLL_TM_FRAC_OFFSET_1,
14775        .ro = 0xffffff00,
14776    },{ .name = "L3_PLL_TM_FRAC_OFFSET_2",  .addr = A_L3_PLL_TM_FRAC_OFFSET_2,
14777        .ro = 0xfffffffc,
14778    },{ .name = "L3_PLL_STATUS_READ_0",  .addr = A_L3_PLL_STATUS_READ_0,
14779        .ro = 0xffffffff,
14780    },{ .name = "L3_PLL_STATUS_READ_1",  .addr = A_L3_PLL_STATUS_READ_1,
14781        .reset = 0x1 | R_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK,
14782        .ro = 0xffffffff,
14783    },{ .name = "L3_TM_CALIB_DIG0",  .addr = A_L3_TM_CALIB_DIG0,
14784        .ro = 0xffffffc3,
14785    },{ .name = "L3_TM_CALIB_DIG1",  .addr = A_L3_TM_CALIB_DIG1,
14786        .ro = 0xfffffff6,
14787    },{ .name = "L3_TM_CALIB_DIG2",  .addr = A_L3_TM_CALIB_DIG2,
14788        .ro = 0xffffff00,
14789    },{ .name = "L3_TM_CALIB_DIG3",  .addr = A_L3_TM_CALIB_DIG3,
14790        .ro = 0xffffff00,
14791    },{ .name = "L3_TM_CALIB_DIG4",  .addr = A_L3_TM_CALIB_DIG4,
14792        .ro = 0xffffff00,
14793    },{ .name = "L3_TM_CALIB_DIG5",  .addr = A_L3_TM_CALIB_DIG5,
14794        .ro = 0xffffff00,
14795    },{ .name = "L3_TM_CALIB_DIG6",  .addr = A_L3_TM_CALIB_DIG6,
14796        .ro = 0xffffff00,
14797    },{ .name = "L3_TM_CALIB_DIG7",  .addr = A_L3_TM_CALIB_DIG7,
14798        .ro = 0xffffff00,
14799    },{ .name = "L3_TM_CALIB_DIG8",  .addr = A_L3_TM_CALIB_DIG8,
14800        .ro = 0xffffff00,
14801    },{ .name = "L3_TM_CALIB_DIG9",  .addr = A_L3_TM_CALIB_DIG9,
14802        .ro = 0xffffff00,
14803    },{ .name = "L3_TM_CALIB_DIG10",  .addr = A_L3_TM_CALIB_DIG10,
14804        .ro = 0xffffff00,
14805    },{ .name = "L3_TM_CALIB_DIG11",  .addr = A_L3_TM_CALIB_DIG11,
14806        .ro = 0xffffff00,
14807    },{ .name = "L3_TM_CALIB_DIG12",  .addr = A_L3_TM_CALIB_DIG12,
14808        .ro = 0xffffff80,
14809    },{ .name = "L3_TM_CALIB_DIG13",  .addr = A_L3_TM_CALIB_DIG13,
14810        .ro = 0xffffffc0,
14811    },{ .name = "L3_TM_CALIB_DIG14",  .addr = A_L3_TM_CALIB_DIG14,
14812        .ro = 0xffffff00,
14813    },{ .name = "L3_TM_CALIB_DIG15",  .addr = A_L3_TM_CALIB_DIG15,
14814        .ro = 0xffffff00,
14815    },{ .name = "L3_TM_CALIB_DIG16",  .addr = A_L3_TM_CALIB_DIG16,
14816        .ro = 0xffffff00,
14817    },{ .name = "L3_TM_CALIB_DIG17",  .addr = A_L3_TM_CALIB_DIG17,
14818        .ro = 0xffffff00,
14819    },{ .name = "L3_TM_CALIB_DIG18",  .addr = A_L3_TM_CALIB_DIG18,
14820        .ro = 0xffffff00,
14821    },{ .name = "L3_TM_CALIB_DIG19",  .addr = A_L3_TM_CALIB_DIG19,
14822        .ro = 0xffffff00,
14823    },{ .name = "L3_TM_CALIB_DIG20",  .addr = A_L3_TM_CALIB_DIG20,
14824        .rsvd = 0x30,
14825        .ro = 0xffffff30,
14826    },{ .name = "L3_TM_CALIB_DIG21",  .addr = A_L3_TM_CALIB_DIG21,
14827        .ro = 0xffffff04,
14828    },{ .name = "L3_TM_CALIB_DIG22",  .addr = A_L3_TM_CALIB_DIG22,
14829        .ro = 0xffffff80,
14830    },{ .name = "L3_TM_SLICER2_CTRL",  .addr = A_L3_TM_SLICER2_CTRL,
14831        .ro = 0xffffff80,
14832    },{ .name = "L3_TM_SLICER23_BIAS_PROG0",  .addr = A_L3_TM_SLICER23_BIAS_PROG0,
14833        .ro = 0xffffff00,
14834    },{ .name = "L3_TM_SLICER23_BIAS_PROG1",  .addr = A_L3_TM_SLICER23_BIAS_PROG1,
14835        .ro = 0xfffffff0,
14836    },{ .name = "L3_TM_SLICER3_CTRL",  .addr = A_L3_TM_SLICER3_CTRL,
14837        .ro = 0xffffff81,
14838    },{ .name = "L3_CAL_SLICER_SPARE",  .addr = A_L3_CAL_SLICER_SPARE,
14839        .ro = 0xffffffc0,
14840    },{ .name = "L3_SLICER2_ENABLE",  .addr = A_L3_SLICER2_ENABLE,
14841        .reset = 0x80,
14842        .ro = 0xffffff00,
14843    },{ .name = "L3_SLICER3_ENABLE",  .addr = A_L3_SLICER3_ENABLE,
14844        .ro = 0xffffff00,
14845    },{ .name = "L3_SLICER2_BYPASS",  .addr = A_L3_SLICER2_BYPASS,
14846        .rsvd = 0x18,
14847        .ro = 0xffffff98,
14848    },{ .name = "L3_SLICER3_BYPASS",  .addr = A_L3_SLICER3_BYPASS,
14849        .rsvd = 0x18,
14850        .ro = 0xffffff18,
14851    },{ .name = "L3_TM_BRINGUP_CONTROL",  .addr = A_L3_TM_BRINGUP_CONTROL,
14852        .ro = 0xfffffffd,
14853    },{ .name = "L3_CALIB_DONE_STATUS",  .addr = A_L3_CALIB_DONE_STATUS,
14854        .ro = 0xffffffff,
14855        /* Signal that calibration is done.  */
14856        .reset = 0x3,
14857    },{ .name = "L3_CALIB_PIPE_PSW_CODE_STATUS",  .addr = A_L3_CALIB_PIPE_PSW_CODE_STATUS,
14858        .reset = 0x20,
14859        .ro = 0xffffffff,
14860    },{ .name = "L3_CALIB_PIPE_NSW_CODE_STATUS",  .addr = A_L3_CALIB_PIPE_NSW_CODE_STATUS,
14861        .reset = 0x20,
14862        .ro = 0xffffffff,
14863    },{ .name = "L3_CALIB_MPHY_TX_CODE_STATUS",  .addr = A_L3_CALIB_MPHY_TX_CODE_STATUS,
14864        .reset = 0x8,
14865        .ro = 0xffffffff,
14866    },{ .name = "L3_CALIB_ICAL_CODE_STATUS",  .addr = A_L3_CALIB_ICAL_CODE_STATUS,
14867        .reset = 0x10,
14868        .ro = 0xffffffff,
14869    },{ .name = "L3_CALIB_RX_CODE_STATUS",  .addr = A_L3_CALIB_RX_CODE_STATUS,
14870        .reset = 0x8,
14871        .ro = 0xffffffff,
14872    },{ .name = "L3_CALIB_USB2_TX_CODE_STATUS",  .addr = A_L3_CALIB_USB2_TX_CODE_STATUS,
14873        .reset = 0x10,
14874        .ro = 0xffffffff,
14875    },{ .name = "L3_CAL_ISO_CTRL",  .addr = A_L3_CAL_ISO_CTRL,
14876        .ro = 0xfffffffc,
14877    },{ .name = "L3_UPHY_GLOBAL_CTRL",  .addr = A_L3_UPHY_GLOBAL_CTRL,
14878        .ro = 0xffffffe0,
14879    },{ .name = "L3_BIST_CTRL_1",  .addr = A_L3_BIST_CTRL_1,
14880        .ro = 0xffffff00,
14881    },{ .name = "L3_BIST_CTRL_2",  .addr = A_L3_BIST_CTRL_2,
14882        .ro = 0xfffffff8,
14883    },{ .name = "L3_BIST_RUN_LEN_L",  .addr = A_L3_BIST_RUN_LEN_L,
14884        .ro = 0xffffff00,
14885    },{ .name = "L3_BIST_ERR_INJ_POINT_L",  .addr = A_L3_BIST_ERR_INJ_POINT_L,
14886        .ro = 0xffffff00,
14887    },{ .name = "L3_BIST_RUNLEN_ERR_INJ_H",  .addr = A_L3_BIST_RUNLEN_ERR_INJ_H,
14888        .ro = 0xffffff00,
14889    },{ .name = "L3_BIST_IDLE_TIME",  .addr = A_L3_BIST_IDLE_TIME,
14890        .ro = 0xffffff00,
14891    },{ .name = "L3_BIST_MARKER_L",  .addr = A_L3_BIST_MARKER_L,
14892        .ro = 0xffffff00,
14893    },{ .name = "L3_BIST_IDLE_CHAR_L",  .addr = A_L3_BIST_IDLE_CHAR_L,
14894        .ro = 0xffffff00,
14895    },{ .name = "L3_BIST_MARKER_IDLE_H",  .addr = A_L3_BIST_MARKER_IDLE_H,
14896        .ro = 0xffffffcc,
14897    },{ .name = "L3_BIST_LOW_PULSE_TIME",  .addr = A_L3_BIST_LOW_PULSE_TIME,
14898        .ro = 0xffffff00,
14899    },{ .name = "L3_BIST_TOTAL_PULSE_TIME",  .addr = A_L3_BIST_TOTAL_PULSE_TIME,
14900        .ro = 0xffffff00,
14901    },{ .name = "L3_BIST_TEST_PAT_1",  .addr = A_L3_BIST_TEST_PAT_1,
14902        .ro = 0xffffff00,
14903    },{ .name = "L3_BIST_TEST_PAT_2",  .addr = A_L3_BIST_TEST_PAT_2,
14904        .ro = 0xffffff00,
14905    },{ .name = "L3_BIST_TEST_PAT_3",  .addr = A_L3_BIST_TEST_PAT_3,
14906        .ro = 0xffffff00,
14907    },{ .name = "L3_BIST_TEST_PAT_4",  .addr = A_L3_BIST_TEST_PAT_4,
14908        .ro = 0xffffff00,
14909    },{ .name = "L3_BIST_TEST_PAT_MSBS",  .addr = A_L3_BIST_TEST_PAT_MSBS,
14910        .ro = 0xffffff00,
14911    },{ .name = "L3_BIST_PKT_NUM",  .addr = A_L3_BIST_PKT_NUM,
14912        .ro = 0xffffff00,
14913    },{ .name = "L3_BIST_FRM_IDLE_TIME",  .addr = A_L3_BIST_FRM_IDLE_TIME,
14914        .ro = 0xffffff00,
14915    },{ .name = "L3_BIST_PKT_CTR_L",  .addr = A_L3_BIST_PKT_CTR_L,
14916        .ro = 0xffffffff,
14917    },{ .name = "L3_BIST_PKT_CTR_H",  .addr = A_L3_BIST_PKT_CTR_H,
14918        .ro = 0xffffffff,
14919    },{ .name = "L3_BIST_ERR_CTR_L",  .addr = A_L3_BIST_ERR_CTR_L,
14920        .ro = 0xffffffff,
14921    },{ .name = "L3_BIST_ERR_CTR_H",  .addr = A_L3_BIST_ERR_CTR_H,
14922        .ro = 0xffffffff,
14923    },{ .name = "L3_CLK_DIV_CNT",  .addr = A_L3_CLK_DIV_CNT,
14924        .reset = 0x19,
14925        .ro = 0xffffff00,
14926    },{ .name = "L3_DATA_BUS_WID",  .addr = A_L3_DATA_BUS_WID,
14927        .reset = 0x1,
14928        .ro = 0xffffff00,
14929    },{ .name = "L3_ANADIG_BYPASS",  .addr = A_L3_ANADIG_BYPASS,
14930        .ro = 0xffffff00,
14931    },{ .name = "L3_BIST_FILLER_OUT",  .addr = A_L3_BIST_FILLER_OUT,
14932        .reset = 0x1,
14933        .ro = 0xfffffffc,
14934    },{ .name = "L3_BIST_FORCE_MK_RST",  .addr = A_L3_BIST_FORCE_MK_RST,
14935        .rsvd = 0xfc,
14936        .ro = 0xfffffffc,
14937    },{ .name = "L3_SPARE_IN",  .addr = A_L3_SPARE_IN,
14938        .ro = 0xffffffff,
14939    },{ .name = "L3_SPARE_OUT",  .addr = A_L3_SPARE_OUT,
14940        .ro = 0xffffff00,
14941    },{ .name = "PLL_REF_SEL0",  .addr = A_PLL_REF_SEL0,
14942        .reset = 0xd,
14943        .ro = 0xffffffe0,
14944    },{ .name = "PLL_REF_SEL1",  .addr = A_PLL_REF_SEL1,
14945        .reset = 0x8,
14946        .ro = 0xffffffe0,
14947    },{ .name = "PLL_REF_SEL2",  .addr = A_PLL_REF_SEL2,
14948        .reset = 0xf,
14949        .ro = 0xffffffe0,
14950    },{ .name = "PLL_REF_SEL3",  .addr = A_PLL_REF_SEL3,
14951        .reset = 0xe,
14952        .ro = 0xffffffe0,
14953    },{ .name = "ICM_CFG0",  .addr = A_ICM_CFG0,
14954        .ro = 0xffffff88,
14955    },{ .name = "ICM_CFG1",  .addr = A_ICM_CFG1,
14956        .ro = 0xffffff88,
14957    },{ .name = "TM_CMN_RST",  .addr = A_TM_CMN_RST,
14958        .reset = 0x2,
14959        .ro = 0xfffffffc,
14960    },{ .name = "PCIE_DYNDESKEW_PAT0",  .addr = A_PCIE_DYNDESKEW_PAT0,
14961        .reset = 0x1c,
14962        .ro = 0xffffff00,
14963    },{ .name = "PCIE_DYNDESKEW_PAT1",  .addr = A_PCIE_DYNDESKEW_PAT1,
14964        .reset = 0x1c,
14965        .ro = 0xffffff00,
14966    },{ .name = "LANE_RPTR_CTRL",  .addr = A_LANE_RPTR_CTRL,
14967        .ro = 0xfffffffe,
14968    },{ .name = "BGCAL_REF_SEL",  .addr = A_BGCAL_REF_SEL,
14969        .reset = 0xc,
14970        .ro = 0xffffffe0,
14971    },{ .name = "PCIE_RXSTAT_CTRL",  .addr = A_PCIE_RXSTAT_CTRL,
14972        .ro = 0xfffffffe,
14973    },{ .name = "PLLLOCK2PCIEPHYRDY_CNT",  .addr = A_PLLLOCK2PCIEPHYRDY_CNT,
14974        .ro = 0xffffff00,
14975    },{ .name = "LPBK_CTRL0",  .addr = A_LPBK_CTRL0,
14976        .ro = 0xffffff88,
14977    },{ .name = "LPBK_CTRL1",  .addr = A_LPBK_CTRL1,
14978        .ro = 0xffffff88,
14979    },{ .name = "TX_PROT_BUS_WIDTH",  .addr = A_TX_PROT_BUS_WIDTH,
14980        .reset = 0x55,
14981        .ro = 0xffffff00,
14982    },{ .name = "RX_PROT_BUS_WIDTH",  .addr = A_RX_PROT_BUS_WIDTH,
14983        .reset = 0x55,
14984        .ro = 0xffffff00,
14985    },{ .name = "RMMI_RST_CTRL",  .addr = A_RMMI_RST_CTRL,
14986        .reset = 0xff,
14987        .ro = 0xffffff00,
14988    },{ .name = "TM_RX_COUPLING_CTRL",  .addr = A_TM_RX_COUPLING_CTRL,
14989        .ro = 0xffffff00,
14990    },{ .name = "TM_PCIE_DESKEW_CTRL",  .addr = A_TM_PCIE_DESKEW_CTRL,
14991        .reset = 0x80,
14992        .ro = 0xffffff00,
14993    },{ .name = "TM_PCIE_LANEMAP",  .addr = A_TM_PCIE_LANEMAP,
14994        .ro = 0xffffffe0,
14995    },{ .name = "RX_DETECT_CTRL",  .addr = A_RX_DETECT_CTRL,
14996        .ro = 0xffffff00,
14997    },{ .name = "DESKEW_ST0",  .addr = A_DESKEW_ST0,
14998        .ro = 0xffffffff,
14999    },{ .name = "DESKEW_ST1",  .addr = A_DESKEW_ST1,
15000        .ro = 0xffffffff,

15001    },{ .name = "AFE_RX0_CTRL",  .addr = A_AFE_RX0_CTRL,
15002        .ro = 0xffffffe0,
15003    },{ .name = "AFE_RX1_CTRL",  .addr = A_AFE_RX1_CTRL,
15004        .ro = 0xffffffe0,
15005    },{ .name = "AFE_RX2_CTRL",  .addr = A_AFE_RX2_CTRL,
15006        .ro = 0xffffffe0,
15007    },{ .name = "AFE_RX3_CTRL",  .addr = A_AFE_RX3_CTRL,
15008        .ro = 0xffffffe0,
15009    },{ .name = "SPARE_IN0",  .addr = A_SPARE_IN0,
15010        .ro = 0xffffff00,
15011    },{ .name = "SPARE_OUT0",  .addr = A_SPARE_OUT0,
15012        .ro = 0xffffffff,
15013    },{ .name = "SPARE_IN1",  .addr = A_SPARE_IN1,
15014        .ro = 0xffffff00,
15015    },{ .name = "SPARE_OUT1",  .addr = A_SPARE_OUT1,
15016        .ro = 0xffffffff,
15017    },{ .name = "SPARE_IN2",  .addr = A_SPARE_IN2,
15018        .ro = 0xffffff00,
15019    },{ .name = "SPARE_OUT2",  .addr = A_SPARE_OUT2,
15020        .ro = 0xffffffff,
15021    },{ .name = "SPARE_IN3",  .addr = A_SPARE_IN3,
15022        .ro = 0xffffff00,
15023    },{ .name = "SPARE_OUT3",  .addr = A_SPARE_OUT3,
15024        .ro = 0xffffffff,
15025    },{ .name = "SGMII_CDET_CTRL",  .addr = A_SGMII_CDET_CTRL,
15026        .reset = 0xff,
15027        .ro = 0xffffff00,
15028    },{ .name = "UPHY_SPARE0",  .addr = A_UPHY_SPARE0,
15029        .ro = 0xffffff00,
15030    },{ .name = "UPHY_SPARE1",  .addr = A_UPHY_SPARE1,
15031        .ro = 0xffffff00,
15032    },{ .name = "UPHY_SPARE2",  .addr = A_UPHY_SPARE2,
15033        .ro = 0xffffff00,
15034    },{ .name = "UPHY_SPARE3",  .addr = A_UPHY_SPARE3,
15035        .ro = 0xffffff00,
15036    },{ .name = "CIRRUS_SPARE_OUT0",  .addr = A_CIRRUS_SPARE_OUT0,
15037        .ro = 0xffffff00,
15038    },{ .name = "CIRRUS_SPARE_OUT1",  .addr = A_CIRRUS_SPARE_OUT1,
15039        .ro = 0xffffff00,
15040    },{ .name = "CIRRUS_SPARE_OUT2",  .addr = A_CIRRUS_SPARE_OUT2,
15041        .ro = 0xffffff00,
15042    },{ .name = "CIRRUS_SPARE_OUT3",  .addr = A_CIRRUS_SPARE_OUT3,
15043        .ro = 0xffffff00,
15044    },{ .name = "CIRRUS_SPARE_IN0",  .addr = A_CIRRUS_SPARE_IN0,
15045        .ro = 0xffffffff,
15046    },{ .name = "CIRRUS_SPARE_IN1",  .addr = A_CIRRUS_SPARE_IN1,
15047        .ro = 0xffffffff,
15048    },{ .name = "CIRRUS_SPARE_IN2",  .addr = A_CIRRUS_SPARE_IN2,
15049        .ro = 0xffffffff,
15050    },{ .name = "CIRRUS_SPARE_IN3",  .addr = A_CIRRUS_SPARE_IN3,
15051        .ro = 0xffffffff,
15052    },{ .name = "AFE_EQ_PSO_DELAY",  .addr = A_AFE_EQ_PSO_DELAY,
15053        .reset = 0x11,
15054        .ro = 0xffffff88,
15055    },{ .name = "USB_TXFIFO0_CTRL",  .addr = A_USB_TXFIFO0_CTRL,
15056        .ro = 0xffffff40,
15057    },{ .name = "USB_TXFIFO1_CTRL",  .addr = A_USB_TXFIFO1_CTRL,
15058        .ro = 0xffffff40,
15059    },{ .name = "DP_TXFIFO0_CTRL",  .addr = A_DP_TXFIFO0_CTRL,
15060        .ro = 0xffffff40,
15061    },{ .name = "DP_TXFIFO1_CTRL",  .addr = A_DP_TXFIFO1_CTRL,
15062        .ro = 0xffffff40,
15063    }
15064};
15065
15066static void serdes_reset(DeviceState *dev)
15067{
15068    SERDES *s = XILINX_SERDES(dev);
15069    unsigned int i;
15070
15071    for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
15072        register_reset(&s->regs_info[i]);
15073    }
15074
15075}
15076
15077/* Returns a device object from a register region created by
15078 * register_init_block32() */
15079static SERDES *serdes_from_mr(void *mr_accessor)
15080{
15081    RegisterInfoArray *reg_array = mr_accessor;
15082    Object *obj;
15083
15084    assert(reg_array != NULL);
15085
15086    obj = reg_array->mem.owner;
15087    assert(obj);
15088
15089    return XILINX_SERDES(obj);
15090}
15091
15092static uint64_t serdes_read(void *opaque, hwaddr addr, unsigned size)
15093{
15094    SERDES *s = serdes_from_mr(opaque);
15095    RegisterInfo *r = &s->regs_info[addr / 4];
15096
15097    if (!r->data) {
15098        qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
15099                 object_get_canonical_path(OBJECT(s)),
15100                 addr);
15101        return 0;
15102    }
15103    return register_read(r, ~0, s->prefix, XILINX_SERDES_ERR_DEBUG);
15104}
15105
15106static void serdes_write(void *opaque, hwaddr addr, uint64_t value,
15107                      unsigned size)
15108{
15109    SERDES *s = serdes_from_mr(opaque);
15110    RegisterInfo *r = &s->regs_info[addr / 4];
15111
15112    if (!r->data) {
15113        qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
15114                 object_get_canonical_path(OBJECT(s)),
15115                 addr, value);
15116        return;
15117    }
15118    register_write(r, value, ~0, s->prefix, XILINX_SERDES_ERR_DEBUG);
15119}
15120
15121static const MemoryRegionOps serdes_ops = {
15122    .read = serdes_read,
15123    .write = serdes_write,
15124   .endianness = DEVICE_LITTLE_ENDIAN,
15125    .valid = {
15126        .min_access_size = 4,
15127        .max_access_size = 4,
15128    },
15129};
15130
15131static void serdes_init(Object *obj)
15132{
15133    SERDES *s = XILINX_SERDES(obj);
15134    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
15135    RegisterInfoArray *reg_array;
15136
15137    s->prefix = object_get_canonical_path(obj);
15138    reg_array =
15139     register_init_block32(DEVICE(obj), serdes_regs_info,
15140                           ARRAY_SIZE(serdes_regs_info),
15141                           s->regs_info, s->regs,
15142                           &serdes_ops,
15143                           XILINX_SERDES_ERR_DEBUG,
15144                           SERDES_R_MAX * 4);
15145    memory_region_init_io(&s->iomem, obj, &serdes_ops, s,
15146                          TYPE_XILINX_SERDES, SERDES_R_MAX * 4);
15147    memory_region_add_subregion(&s->iomem, 0x0, &reg_array->mem);
15148    sysbus_init_mmio(sbd, &s->iomem);
15149}
15150
15151static const VMStateDescription vmstate_serdes = {
15152    .name = TYPE_XILINX_SERDES,
15153    .version_id = 1,
15154    .minimum_version_id = 1,
15155    .fields = (VMStateField[]) {
15156        VMSTATE_UINT32_ARRAY(regs, SERDES, SERDES_R_MAX),
15157        VMSTATE_END_OF_LIST(),
15158    }
15159};
15160
15161static void serdes_class_init(ObjectClass *klass, void *data)
15162{
15163    DeviceClass *dc = DEVICE_CLASS(klass);
15164
15165    dc->reset = serdes_reset;
15166    dc->vmsd = &vmstate_serdes;
15167}
15168
15169static const TypeInfo serdes_info = {
15170    .name          = TYPE_XILINX_SERDES,
15171    .parent        = TYPE_SYS_BUS_DEVICE,
15172    .instance_size = sizeof(SERDES),
15173    .class_init    = serdes_class_init,
15174    .instance_init = serdes_init,
15175};
15176
15177static void serdes_register_types(void)
15178{
15179    type_register_static(&serdes_info);
15180}
15181
15182type_init(serdes_register_types)
15183