1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27#include "qemu/osdep.h"
28#include "hw/sysbus.h"
29#include "hw/register.h"
30#include "qemu/bitops.h"
31#include "qemu/log.h"
32#include "migration/vmstate.h"
33#include "hw/qdev-properties.h"
34
35#ifndef XILINX_CMT_XPLL_ERR_DEBUG
36#define XILINX_CMT_XPLL_ERR_DEBUG 0
37#endif
38
39#define TYPE_XILINX_CMT_XPLL "xlnx.versal-cmt-xpll"
40
41#define XILINX_CMT_XPLL(obj) \
42 OBJECT_CHECK(CMT_XPLL, (obj), TYPE_XILINX_CMT_XPLL)
43
44REG32(REG_PCSR_MASK, 0x0)
45 FIELD(REG_PCSR_MASK, TEST_SAFE, 20, 1)
46 FIELD(REG_PCSR_MASK, SLVERREN, 19, 1)
47 FIELD(REG_PCSR_MASK, MEM_CLEAR_TRIGGER, 18, 1)
48 FIELD(REG_PCSR_MASK, SYS_RST_MASK, 15, 3)
49 FIELD(REG_PCSR_MASK, PWRDN, 14, 1)
50 FIELD(REG_PCSR_MASK, DISNPICLK, 13, 1)
51 FIELD(REG_PCSR_MASK, APBEN, 12, 1)
52 FIELD(REG_PCSR_MASK, SCAN_CLEAR_TRIGGER, 11, 1)
53 FIELD(REG_PCSR_MASK, STARTCAL, 10, 1)
54 FIELD(REG_PCSR_MASK, FABRICEN, 9, 1)
55 FIELD(REG_PCSR_MASK, TRISTATE, 8, 1)
56 FIELD(REG_PCSR_MASK, HOLDSTATE, 7, 1)
57 FIELD(REG_PCSR_MASK, INITSTATE, 6, 1)
58 FIELD(REG_PCSR_MASK, ODISABLE, 2, 4)
59 FIELD(REG_PCSR_MASK, GATEREG, 1, 1)
60 FIELD(REG_PCSR_MASK, PCOMPLETE, 0, 1)
61REG32(REG_PCSR_CONTROL, 0x4)
62 FIELD(REG_PCSR_CONTROL, TEST_SAFE, 20, 1)
63 FIELD(REG_PCSR_CONTROL, SLVERREN, 19, 1)
64 FIELD(REG_PCSR_CONTROL, MEM_CLEAR_TRIGGER, 18, 1)
65 FIELD(REG_PCSR_CONTROL, SYS_RST_MASK, 15, 3)
66 FIELD(REG_PCSR_CONTROL, PWRDN, 14, 1)
67 FIELD(REG_PCSR_CONTROL, DISNPICLK, 13, 1)
68 FIELD(REG_PCSR_CONTROL, APBEN, 12, 1)
69 FIELD(REG_PCSR_CONTROL, SCAN_CLEAR_TRIGGER, 11, 1)
70 FIELD(REG_PCSR_CONTROL, STARTCAL, 10, 1)
71 FIELD(REG_PCSR_CONTROL, FABRICEN, 9, 1)
72 FIELD(REG_PCSR_CONTROL, TRISTATE, 8, 1)
73 FIELD(REG_PCSR_CONTROL, HOLDSTATE, 7, 1)
74 FIELD(REG_PCSR_CONTROL, INITSTATE, 6, 1)
75 FIELD(REG_PCSR_CONTROL, ODISABLE, 2, 4)
76 FIELD(REG_PCSR_CONTROL, GATEREG, 1, 1)
77 FIELD(REG_PCSR_CONTROL, PCOMPLETE, 0, 1)
78REG32(REG_PCSR_STATUS, 0x8)
79 FIELD(REG_PCSR_STATUS, HARD_FAIL_OR, 11, 3)
80 FIELD(REG_PCSR_STATUS, HARD_FAIL_AND, 8, 3)
81 FIELD(REG_PCSR_STATUS, MEM_CLEAR_PASS, 7, 1)
82 FIELD(REG_PCSR_STATUS, MEM_CLEAR_DONE, 6, 1)
83 FIELD(REG_PCSR_STATUS, CALERROR, 5, 1)
84 FIELD(REG_PCSR_STATUS, CALDONE, 4, 1)
85 FIELD(REG_PCSR_STATUS, INCAL, 3, 1)
86 FIELD(REG_PCSR_STATUS, SCAN_CLEAR_PASS, 2, 1)
87 FIELD(REG_PCSR_STATUS, SCAN_CLEAR_DONE, 1, 1)
88 FIELD(REG_PCSR_STATUS, PCSRLOCK, 0, 1)
89REG32(REG_PCSR_LOCK, 0xc)
90 FIELD(REG_PCSR_LOCK, STATE, 0, 1)
91REG32(REG_ITR, 0x10)
92 FIELD(REG_ITR, LOCK_B, 0, 1)
93REG32(REG_ISR, 0x14)
94 FIELD(REG_ISR, LOCK_B, 0, 1)
95REG32(REG_IMR0, 0x18)
96 FIELD(REG_IMR0, LOCK_B, 0, 1)
97REG32(REG_IER0, 0x1c)
98 FIELD(REG_IER0, LOCK_B, 0, 1)
99REG32(REG_IDR0, 0x20)
100 FIELD(REG_IDR0, LOCK_B, 0, 1)
101REG32(REG_IOR, 0x24)
102 FIELD(REG_IOR, OFFSET, 0, 5)
103REG32(REG_0, 0x28)
104 FIELD(REG_0, AVDD_VBG_SEL, 11, 5)
105 FIELD(REG_0, AVDD_COMP_SET, 8, 3)
106 FIELD(REG_0, ANALOG_MISC, 3, 4)
107 FIELD(REG_0, AVDD_VBG_PD, 0, 3)
108REG32(REG_1, 0x2c)
109 FIELD(REG_1, CLKBURST_ENABLE, 4, 1)
110 FIELD(REG_1, CLKBURST_CNT, 0, 4)
111REG32(REG_2, 0x30)
112 FIELD(REG_2, CLKOUTPHY_DIVMODE, 13, 3)
113 FIELD(REG_2, CLKFBOUT_PREDIV2, 12, 1)
114 FIELD(REG_2, CLKFBOUT_MX, 10, 2)
115 FIELD(REG_2, CLKFBOUT_EN, 9, 1)
116 FIELD(REG_2, CLKFBOUT_EDGE, 8, 1)
117 FIELD(REG_2, CLKFBOUT_DT, 0, 8)
118REG32(REG_3, 0x34)
119 FIELD(REG_3, CLKFBOUT_HT, 8, 8)
120 FIELD(REG_3, CLKFBOUT_LT, 0, 8)
121REG32(REG_4, 0x38)
122 FIELD(REG_4, CLKOUT0_P5_FEDGE, 15, 1)
123 FIELD(REG_4, CLKOUT0_START_H, 14, 1)
124 FIELD(REG_4, CLKOUT0_P5EN, 13, 1)
125 FIELD(REG_4, CLKOUT0_USED, 12, 1)
126 FIELD(REG_4, CLKOUT0_PREDIV2, 11, 1)
127 FIELD(REG_4, CLKOUT0_MX, 9, 2)
128 FIELD(REG_4, CLKOUT0_EDGE, 8, 1)
129 FIELD(REG_4, CLKOUT0_DT, 0, 8)
130REG32(REG_5, 0x3c)
131 FIELD(REG_5, CLKOUT0_HT, 8, 8)
132 FIELD(REG_5, CLKOUT0_LT, 0, 8)
133REG32(REG_6, 0x40)
134 FIELD(REG_6, CLKOUT1_P5_FEDGE, 15, 1)
135 FIELD(REG_6, CLKOUT1_START_H, 14, 1)
136 FIELD(REG_6, CLKOUT1_P5EN, 13, 1)
137 FIELD(REG_6, CLKOUT1_USED, 12, 1)
138 FIELD(REG_6, CLKOUT1_PREDIV2, 11, 1)
139 FIELD(REG_6, CLKOUT1_MX, 9, 2)
140 FIELD(REG_6, CLKOUT1_EDGE, 8, 1)
141 FIELD(REG_6, CLKOUT1_DT, 0, 8)
142REG32(REG_7, 0x44)
143 FIELD(REG_7, CLKOUT1_HT, 8, 8)
144 FIELD(REG_7, CLKOUT1_LT, 0, 8)
145REG32(REG_8, 0x48)
146 FIELD(REG_8, CLKOUT2_P5_FEDGE, 15, 1)
147 FIELD(REG_8, CLKOUT2_START_H, 14, 1)
148 FIELD(REG_8, CLKOUT2_P5EN, 13, 1)
149 FIELD(REG_8, CLKOUT2_USED, 12, 1)
150 FIELD(REG_8, CLKOUT2_PREDIV2, 11, 1)
151 FIELD(REG_8, CLKOUT2_MX, 9, 2)
152 FIELD(REG_8, CLKOUT2_EDGE, 8, 1)
153 FIELD(REG_8, CLKOUT2_DT, 0, 8)
154REG32(REG_9, 0x4c)
155 FIELD(REG_9, CLKOUT2_HT, 8, 8)
156 FIELD(REG_9, CLKOUT2_LT, 0, 8)
157REG32(REG_10, 0x50)
158 FIELD(REG_10, CLKOUT3_P5_FEDGE, 15, 1)
159 FIELD(REG_10, CLKOUT3_START_H, 14, 1)
160 FIELD(REG_10, CLKOUT3_P5EN, 13, 1)
161 FIELD(REG_10, CLKOUT3_USED, 12, 1)
162 FIELD(REG_10, CLKOUT3_PREDIV2, 11, 1)
163 FIELD(REG_10, CLKOUT3_MX, 9, 2)
164 FIELD(REG_10, CLKOUT3_EDGE, 8, 1)
165 FIELD(REG_10, CLKOUT3_DT, 0, 8)
166REG32(REG_11, 0x54)
167 FIELD(REG_11, CLKOUT3_HT, 8, 8)
168 FIELD(REG_11, CLKOUT3_LT, 0, 8)
169REG32(REG_12, 0x58)
170 FIELD(REG_12, CONTROL_0, 0, 16)
171REG32(REG_13, 0x5c)
172 FIELD(REG_13, CONTROL_1, 0, 16)
173REG32(REG_14, 0x60)
174 FIELD(REG_14, CONTROL_2, 0, 16)
175REG32(REG_15, 0x64)
176 FIELD(REG_15, CONTROL_3, 0, 16)
177REG32(REG_16, 0x68)
178 FIELD(REG_16, CONTROL_4, 0, 16)
179REG32(REG_17, 0x6c)
180 FIELD(REG_17, CONTROL_5, 0, 16)
181REG32(REG_18, 0x70)
182 FIELD(REG_18, CONTROL_6, 0, 16)
183REG32(REG_19, 0x74)
184 FIELD(REG_19, CONTROL_7, 0, 16)
185REG32(REG_20, 0x78)
186 FIELD(REG_20, CP_RES_L, 8, 2)
187 FIELD(REG_20, CP_RES_H, 6, 2)
188 FIELD(REG_20, CP_OPAMP_BN, 5, 1)
189 FIELD(REG_20, CP_BIAS_TRIP_SET, 4, 1)
190 FIELD(REG_20, CP, 0, 4)
191REG32(REG_21, 0x7c)
192 FIELD(REG_21, DESKEW_EN, 8, 1)
193 FIELD(REG_21, DESKEW_DLY_PATH, 7, 1)
194 FIELD(REG_21, DESKEW_DLY_EN, 6, 1)
195 FIELD(REG_21, DESKEW_DLY, 0, 6)
196REG32(REG_22, 0x80)
197 FIELD(REG_22, DIVCLK_EDGE, 10, 1)
198 FIELD(REG_22, DIRECT_PATH_CNTRL, 9, 1)
199 FIELD(REG_22, DESKEW_EN_2ND, 8, 1)
200 FIELD(REG_22, DESKEW_DLY_PATH_2ND, 7, 1)
201 FIELD(REG_22, DESKEW_DLY_EN_2ND, 6, 1)
202 FIELD(REG_22, DESKEW_DLY_2ND, 0, 6)
203REG32(REG_23, 0x84)
204 FIELD(REG_23, DIVCLK_HT, 8, 8)
205 FIELD(REG_23, DIVCLK_LT, 0, 8)
206REG32(REG_24, 0x88)
207 FIELD(REG_24, EN_VCO_DIV6, 7, 1)
208 FIELD(REG_24, EN_VCO_DIV1, 6, 1)
209 FIELD(REG_24, EN_TESTIN, 5, 1)
210 FIELD(REG_24, EN_SYNC_CK_TEST, 4, 1)
211 FIELD(REG_24, EN_LOCKED_DESKEW_2ND, 3, 1)
212 FIELD(REG_24, EN_LOCKED_DESKEW, 2, 1)
213 FIELD(REG_24, EN_DESKEW_TRACK_2ND, 1, 1)
214 FIELD(REG_24, EN_DESKEW_TRACK, 0, 1)
215REG32(REG_25, 0x8c)
216 FIELD(REG_25, HVLF_CNT_TEST_EN, 10, 1)
217 FIELD(REG_25, HVLF_CNT_TEST, 4, 6)
218 FIELD(REG_25, FREQ_COMP, 1, 3)
219 FIELD(REG_25, FORCE_SENSE_SHORT, 0, 1)
220REG32(REG_26, 0x90)
221 FIELD(REG_26, IN_DLY_SET, 9, 6)
222 FIELD(REG_26, IN_DLY_MX_DVDD, 3, 6)
223 FIELD(REG_26, IN_DLY_MX_CVDD, 1, 2)
224 FIELD(REG_26, IN_DLY_EN, 0, 1)
225REG32(REG_27, 0x94)
226 FIELD(REG_27, INTERP1_SKEW, 10, 5)
227 FIELD(REG_27, INTERP1_SEL, 8, 2)
228 FIELD(REG_27, INTERP0_SKEW, 2, 5)
229 FIELD(REG_27, INTERP0_SEL, 0, 2)
230REG32(REG_28, 0x98)
231 FIELD(REG_28, INTERP3_SKEW, 10, 5)
232 FIELD(REG_28, INTERP3_SEL, 8, 2)
233 FIELD(REG_28, INTERP2_SKEW, 2, 5)
234 FIELD(REG_28, INTERP2_SEL, 0, 2)
235REG32(REG_29, 0x9c)
236 FIELD(REG_29, LFHF, 10, 2)
237 FIELD(REG_29, LF_PEN, 8, 2)
238 FIELD(REG_29, LF_NEN, 6, 2)
239 FIELD(REG_29, LF_LOW_SEL, 5, 1)
240 FIELD(REG_29, IS_RST_INVERTED, 4, 1)
241 FIELD(REG_29, IS_PWRDWN_INVERTED, 3, 1)
242 FIELD(REG_29, IS_PSINCDEC_INVERTED, 2, 1)
243 FIELD(REG_29, IS_PSEN_INVERTED, 1, 1)
244 FIELD(REG_29, IS_CLKIN_INVERTED, 0, 1)
245REG32(REG_30, 0xa0)
246 FIELD(REG_30, LOCK_FB_DLY, 10, 5)
247 FIELD(REG_30, LOCK_CNT, 0, 10)
248REG32(REG_31, 0xa4)
249 FIELD(REG_31, LOCK_REF_DLY, 10, 5)
250 FIELD(REG_31, LOCK_SAT_HIGH, 0, 10)
251REG32(REG_32, 0xa8)
252 FIELD(REG_32, PLL_EN, 12, 1)
253 FIELD(REG_32, PI_PROGRAM, 11, 1)
254 FIELD(REG_32, PFD_STARTUP, 10, 1)
255 FIELD(REG_32, PFD, 3, 7)
256 FIELD(REG_32, MAN_LF, 0, 3)
257REG32(REG_33, 0xac)
258 FIELD(REG_33, SKEW_SEL, 8, 6)
259 FIELD(REG_33, SENSE_TEST_EN, 7, 1)
260 FIELD(REG_33, SEL_SLIPD, 6, 1)
261 FIELD(REG_33, SCAN_MODE, 5, 1)
262 FIELD(REG_33, RES, 1, 4)
263 FIELD(REG_33, REGLPF_RES_SHORT, 0, 1)
264REG32(REG_34, 0xb0)
265 FIELD(REG_34, SPARE_ANALOG, 0, 16)
266REG32(REG_35, 0xb4)
267 FIELD(REG_35, SPARE_DIGITAL, 0, 16)
268REG32(REG_36, 0xb8)
269 FIELD(REG_36, TC_GEN_MODE, 8, 1)
270 FIELD(REG_36, SYNTH_CLK_DIV, 6, 2)
271 FIELD(REG_36, SUP_SEL_VCCINT, 5, 1)
272 FIELD(REG_36, SUP_SEL_VCCAUX, 4, 1)
273 FIELD(REG_36, SUP_SEL_VBGHALF, 3, 1)
274 FIELD(REG_36, SUP_SEL_VBG, 2, 1)
275 FIELD(REG_36, SUP_SEL_DVDD, 1, 1)
276 FIELD(REG_36, SUP_SEL_AVDD, 0, 1)
277REG32(REG_37, 0xbc)
278 FIELD(REG_37, TESTOUT1_MUX_SEL, 6, 6)
279 FIELD(REG_37, TESTOUT0_MUX_SEL, 0, 6)
280REG32(REG_38, 0xc0)
281 FIELD(REG_38, TMUX_MUX_SEL, 12, 2)
282 FIELD(REG_38, TESTOUT3_MUX_SEL, 6, 6)
283 FIELD(REG_38, TESTOUT2_MUX_SEL, 0, 6)
284REG32(REG_39, 0xc4)
285 FIELD(REG_39, UNLOCK_CNT, 0, 10)
286REG32(REG_40, 0xc8)
287 FIELD(REG_40, VCO_STARTUP_HYST_DISABLE, 7, 1)
288 FIELD(REG_40, VCO_STARTUP_ALT_EN, 6, 1)
289 FIELD(REG_40, VCO_STARTUP_ADJ, 5, 1)
290 FIELD(REG_40, VCO_SINGLE_BAND_DEFAULT, 4, 1)
291 FIELD(REG_40, VCO_KICK_DISABLE, 3, 1)
292 FIELD(REG_40, VCO_HIGH_RANGE_EN, 2, 1)
293 FIELD(REG_40, VCO_GATE_CCI_B, 1, 1)
294 FIELD(REG_40, VCO_BAND_MODE, 0, 1)
295REG32(REG_41, 0xcc)
296 FIELD(REG_41, VLF_VALID_SEL, 9, 3)
297 FIELD(REG_41, VLF_VALID_PWDN, 8, 1)
298 FIELD(REG_41, VLF_SWITCH_SEL, 5, 3)
299 FIELD(REG_41, VLF_SWITCH_PWDN, 4, 1)
300 FIELD(REG_41, VLF_HIGH_SEL, 2, 2)
301 FIELD(REG_41, VLF_HIGH_PWDN_B, 1, 1)
302 FIELD(REG_41, VLF_HIGH_EN, 0, 1)
303REG32(REG_42, 0xd0)
304 FIELD(REG_42, DVDD_VBG_SEL, 0, 4)
305
306#define CMT_XPLL_R_MAX (R_REG_42 + 1)
307
308typedef struct CMT_XPLL {
309 SysBusDevice parent_obj;
310 MemoryRegion iomem;
311
312 uint32_t regs[CMT_XPLL_R_MAX];
313 RegisterInfo regs_info[CMT_XPLL_R_MAX];
314} CMT_XPLL;
315
316#define LOCK_VAL 0xF9E8D7C6
317
318static void cmt_xpll_lock_postw(RegisterInfo *reg, uint64_t val64)
319{
320 CMT_XPLL *s = XILINX_CMT_XPLL(reg->opaque);
321 bool locked = val64 != LOCK_VAL;
322
323 ARRAY_FIELD_DP32(s->regs, REG_PCSR_STATUS, PCSRLOCK, locked);
324 ARRAY_FIELD_DP32(s->regs, REG_PCSR_LOCK, STATE, locked);
325}
326
327static const RegisterAccessInfo cmt_xpll_regs_info[] = {
328 { .name = "REG_PCSR_MASK", .addr = A_REG_PCSR_MASK,
329 .rsvd = 0xffe00000,
330 },{ .name = "REG_PCSR_CONTROL", .addr = A_REG_PCSR_CONTROL,
331 .reset = 0x1fe,
332 .rsvd = 0xffe00000,
333 },{ .name = "REG_PCSR_STATUS", .addr = A_REG_PCSR_STATUS,
334 .reset = R_REG_PCSR_STATUS_PCSRLOCK_MASK \
335 | R_REG_PCSR_STATUS_MEM_CLEAR_PASS_MASK \
336 | R_REG_PCSR_STATUS_MEM_CLEAR_DONE_MASK \
337 | R_REG_PCSR_STATUS_CALDONE_MASK \
338 | R_REG_PCSR_STATUS_SCAN_CLEAR_PASS_MASK \
339 | R_REG_PCSR_STATUS_SCAN_CLEAR_DONE_MASK,
340 .rsvd = 0xffffc000,
341 .ro = 0x3fff,
342 },{ .name = "REG_PCSR_LOCK", .addr = A_REG_PCSR_LOCK,
343 .reset = 0x1,
344 .post_write = cmt_xpll_lock_postw
345 },{ .name = "REG_ITR", .addr = A_REG_ITR,
346 .rsvd = 0xfffffffe,
347 },{ .name = "REG_ISR", .addr = A_REG_ISR,
348 .rsvd = 0xfffffffe,
349 .w1c = 0x1,
350 },{ .name = "REG_IMR0", .addr = A_REG_IMR0,
351 .reset = 0x1,
352 .rsvd = 0xfffffffe,
353 .ro = 0x1,
354 },{ .name = "REG_IER0", .addr = A_REG_IER0,
355 .rsvd = 0xfffffffe,
356 },{ .name = "REG_IDR0", .addr = A_REG_IDR0,
357 .rsvd = 0xfffffffe,
358 },{ .name = "REG_IOR", .addr = A_REG_IOR,
359 .reset = 0xb,
360 .rsvd = 0xffffffe0,
361 },{ .name = "REG_0", .addr = A_REG_0,
362 .reset = 0x4b06,
363 .rsvd = 0xffff0080,
364 .ro = 0x80,
365 },{ .name = "REG_1", .addr = A_REG_1,
366 .reset = 0x1,
367 .rsvd = 0xffffffe0,
368 },{ .name = "REG_2", .addr = A_REG_2,
369 .reset = 0x7600,
370 .rsvd = 0xffff0000,
371 },{ .name = "REG_3", .addr = A_REG_3,
372 .reset = 0x1515,
373 .rsvd = 0xffff0000,
374 },{ .name = "REG_4", .addr = A_REG_4,
375 .reset = 0xa00,
376 .rsvd = 0xffff0000,
377 },{ .name = "REG_5", .addr = A_REG_5,
378 .reset = 0x101,
379 .rsvd = 0xffff0000,
380 },{ .name = "REG_6", .addr = A_REG_6,
381 .reset = 0xa00,
382 .rsvd = 0xffff0000,
383 },{ .name = "REG_7", .addr = A_REG_7,
384 .reset = 0x101,
385 .rsvd = 0xffff0000,
386 },{ .name = "REG_8", .addr = A_REG_8,
387 .reset = 0xa00,
388 .rsvd = 0xffff0000,
389 },{ .name = "REG_9", .addr = A_REG_9,
390 .reset = 0x101,
391 .rsvd = 0xffff0000,
392 },{ .name = "REG_10", .addr = A_REG_10,
393 .reset = 0xa00,
394 .rsvd = 0xffff0000,
395 },{ .name = "REG_11", .addr = A_REG_11,
396 .reset = 0x101,
397 .rsvd = 0xffff0000,
398 },{ .name = "REG_12", .addr = A_REG_12,
399 .reset = 0xf37c,
400 .rsvd = 0xffff0000,
401 },{ .name = "REG_13", .addr = A_REG_13,
402 .reset = 0x7c4d,
403 .rsvd = 0xffff0000,
404 },{ .name = "REG_14", .addr = A_REG_14,
405 .reset = 0xd042,
406 .rsvd = 0xffff0000,
407 },{ .name = "REG_15", .addr = A_REG_15,
408 .reset = 0xebd8,
409 .rsvd = 0xffff0000,
410 },{ .name = "REG_16", .addr = A_REG_16,
411 .reset = 0xec5f,
412 .rsvd = 0xffff0000,
413 },{ .name = "REG_17", .addr = A_REG_17,
414 .reset = 0xedfb,
415 .rsvd = 0xffff0000,
416 },{ .name = "REG_18", .addr = A_REG_18,
417 .reset = 0xaacd,
418 .rsvd = 0xffff0000,
419 },{ .name = "REG_19", .addr = A_REG_19,
420 .reset = 0x4428,
421 .rsvd = 0xffff0000,
422 },{ .name = "REG_20", .addr = A_REG_20,
423 .reset = 0x24,
424 .rsvd = 0xfffffc00,
425 },{ .name = "REG_21", .addr = A_REG_21,
426 .rsvd = 0xfffffe00,
427 },{ .name = "REG_22", .addr = A_REG_22,
428 .reset = 0x400,
429 .rsvd = 0xfffff800,
430 },{ .name = "REG_23", .addr = A_REG_23,
431 .rsvd = 0xffff0000,
432 },{ .name = "REG_24", .addr = A_REG_24,
433 .reset = 0x20,
434 .rsvd = 0xffffff00,
435 },{ .name = "REG_25", .addr = A_REG_25,
436 .reset = 0x6,
437 .rsvd = 0xfffff800,
438 },{ .name = "REG_26", .addr = A_REG_26,
439 .reset = 0x4d74,
440 .rsvd = 0xffff8000,
441 },{ .name = "REG_27", .addr = A_REG_27,
442 .rsvd = 0xffff8080,
443 .ro = 0x80,
444 },{ .name = "REG_28", .addr = A_REG_28,
445 .rsvd = 0xffff8080,
446 .ro = 0x80,
447 },{ .name = "REG_29", .addr = A_REG_29,
448 .reset = 0xe80,
449 .rsvd = 0xfffff000,
450 },{ .name = "REG_30", .addr = A_REG_30,
451 .reset = 0x3be8,
452 .rsvd = 0xffff8000,
453 },{ .name = "REG_31", .addr = A_REG_31,
454 .reset = 0x3be9,
455 .rsvd = 0xffff8000,
456 },{ .name = "REG_32", .addr = A_REG_32,
457 .reset = 0x1588,
458 .rsvd = 0xffffe000,
459 },{ .name = "REG_33", .addr = A_REG_33,
460 .reset = 0x1e,
461 .rsvd = 0xffffc000,
462 },{ .name = "REG_34", .addr = A_REG_34,
463 .reset = 0x1,
464 .rsvd = 0xffff0000,
465 },{ .name = "REG_35", .addr = A_REG_35,
466 .rsvd = 0xffff0000,
467 },{ .name = "REG_36", .addr = A_REG_36,
468 .reset = 0xc0,
469 .rsvd = 0xfffffe00,
470 },{ .name = "REG_37", .addr = A_REG_37,
471 .rsvd = 0xfffff000,
472 },{ .name = "REG_38", .addr = A_REG_38,
473 .rsvd = 0xffffc000,
474 },{ .name = "REG_39", .addr = A_REG_39,
475 .reset = 0x1,
476 .rsvd = 0xfffffc00,
477 },{ .name = "REG_40", .addr = A_REG_40,
478 .reset = 0x2,
479 .rsvd = 0xffffff00,
480 },{ .name = "REG_41", .addr = A_REG_41,
481 .reset = 0x68b,
482 .rsvd = 0xfffff000,
483 },{ .name = "REG_42", .addr = A_REG_42,
484 .reset = 0x6,
485 .rsvd = 0xfffffff0,
486 }
487};
488
489static void cmt_xpll_reset(DeviceState *dev)
490{
491 CMT_XPLL *s = XILINX_CMT_XPLL(dev);
492 unsigned int i;
493
494 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
495 register_reset(&s->regs_info[i]);
496 }
497}
498
499static MemTxResult reg_write(void *opaque, hwaddr addr,
500 uint64_t data, unsigned size, MemTxAttrs attrs)
501{
502 RegisterInfoArray *reg_array = opaque;
503 CMT_XPLL *s = XILINX_CMT_XPLL(reg_array->r[0]->opaque);
504
505
506 if (ARRAY_FIELD_EX32(s->regs, REG_PCSR_LOCK, STATE)
507 && addr != A_REG_PCSR_LOCK) {
508 return MEMTX_ERROR;
509 }
510
511 register_write_memory(opaque, addr, data, size);
512 return MEMTX_OK;
513}
514
515static const MemoryRegionOps cmt_xpll_ops = {
516 .read = register_read_memory,
517 .write_with_attrs = reg_write,
518 .endianness = DEVICE_LITTLE_ENDIAN,
519 .valid = {
520 .min_access_size = 4,
521 .max_access_size = 4,
522 },
523};
524
525static void cmt_xpll_realize(DeviceState *dev, Error **errp)
526{
527
528}
529
530static void cmt_xpll_init(Object *obj)
531{
532 CMT_XPLL *s = XILINX_CMT_XPLL(obj);
533 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
534 RegisterInfoArray *reg_array;
535
536 memory_region_init(&s->iomem, obj, TYPE_XILINX_CMT_XPLL,
537 CMT_XPLL_R_MAX * 4);
538 reg_array =
539 register_init_block32(DEVICE(obj), cmt_xpll_regs_info,
540 ARRAY_SIZE(cmt_xpll_regs_info),
541 s->regs_info, s->regs,
542 &cmt_xpll_ops,
543 XILINX_CMT_XPLL_ERR_DEBUG,
544 CMT_XPLL_R_MAX * 4);
545 memory_region_add_subregion(&s->iomem,
546 0x0,
547 ®_array->mem);
548 sysbus_init_mmio(sbd, &s->iomem);
549}
550
551static const VMStateDescription vmstate_cmt_xpll = {
552 .name = TYPE_XILINX_CMT_XPLL,
553 .version_id = 1,
554 .minimum_version_id = 1,
555 .fields = (VMStateField[]) {
556 VMSTATE_UINT32_ARRAY(regs, CMT_XPLL, CMT_XPLL_R_MAX),
557 VMSTATE_END_OF_LIST(),
558 }
559};
560
561static void cmt_xpll_class_init(ObjectClass *klass, void *data)
562{
563 DeviceClass *dc = DEVICE_CLASS(klass);
564
565 dc->reset = cmt_xpll_reset;
566 dc->realize = cmt_xpll_realize;
567 dc->vmsd = &vmstate_cmt_xpll;
568}
569
570static const TypeInfo cmt_xpll_info = {
571 .name = TYPE_XILINX_CMT_XPLL,
572 .parent = TYPE_SYS_BUS_DEVICE,
573 .instance_size = sizeof(CMT_XPLL),
574 .class_init = cmt_xpll_class_init,
575 .instance_init = cmt_xpll_init,
576};
577
578static void cmt_xpll_register_types(void)
579{
580 type_register_static(&cmt_xpll_info);
581}
582
583type_init(cmt_xpll_register_types)
584
