1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28#include "qemu/osdep.h"
29#include "hw/sysbus.h"
30#include "hw/register.h"
31#include "qemu/bitops.h"
32#include "qemu/log.h"
33#include "migration/vmstate.h"
34#include "hw/irq.h"
35
36#ifndef XILINX_CPM_SLCR_SECURE_ERR_DEBUG
37#define XILINX_CPM_SLCR_SECURE_ERR_DEBUG 0
38#endif
39
40#define TYPE_XILINX_CPM_SLCR_SECURE "xlnx.cpm_slcr_secure"
41
42#define XILINX_CPM_SLCR_SECURE(obj) \
43 OBJECT_CHECK(CPM_SLCR_SECURE, (obj), TYPE_XILINX_CPM_SLCR_SECURE)
44
45REG32(WPROT0, 0x0)
46 FIELD(WPROT0, ACTIVE, 0, 1)
47REG32(REG_CTRL, 0x4)
48 FIELD(REG_CTRL, SLVERR_ENABLE, 0, 1)
49REG32(IR_STATUS, 0x10)
50 FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
51REG32(IR_MASK, 0x14)
52 FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
53REG32(IR_ENABLE, 0x18)
54 FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
55REG32(IR_DISABLE, 0x1c)
56 FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
57REG32(IR_TRIGGER, 0x20)
58 FIELD(IR_TRIGGER, ADDR_DECODE_ERR, 0, 1)
59REG32(TZ_PCIE, 0x100)
60 FIELD(TZ_PCIE, ATTR_DMA_CH3_SEC, 31, 1)
61 FIELD(TZ_PCIE, ATTR_DMA_CH2_SEC, 30, 1)
62 FIELD(TZ_PCIE, ATTR_DMA_CH1_SEC, 29, 1)
63 FIELD(TZ_PCIE, ATTR_DMA_CH0_SEC, 28, 1)
64 FIELD(TZ_PCIE, ATTR_DMA_PF3_VF_SEC, 27, 1)
65 FIELD(TZ_PCIE, ATTR_DMA_PF2_VF_SEC, 26, 1)
66 FIELD(TZ_PCIE, ATTR_DMA_PF1_VF_SEC, 25, 1)
67 FIELD(TZ_PCIE, ATTR_DMA_PF0_VF_SEC, 24, 1)
68 FIELD(TZ_PCIE, ATTR_DMA_PF3_SEC, 23, 1)
69 FIELD(TZ_PCIE, ATTR_DMA_PF2_SEC, 22, 1)
70 FIELD(TZ_PCIE, ATTR_DMA_PF1_SEC, 21, 1)
71 FIELD(TZ_PCIE, ATTR_DMA_PF0_SEC, 20, 1)
72 FIELD(TZ_PCIE, ATTR_DMA_ENABLE_SECURE, 19, 1)
73 FIELD(TZ_PCIE, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF3_VF, 18, 1)
74 FIELD(TZ_PCIE, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF2_VF, 17, 1)
75 FIELD(TZ_PCIE, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF1_VF, 16, 1)
76 FIELD(TZ_PCIE, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF0_VF, 15, 1)
77 FIELD(TZ_PCIE, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF3, 14, 1)
78 FIELD(TZ_PCIE, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF2, 13, 1)
79 FIELD(TZ_PCIE, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF1, 12, 1)
80 FIELD(TZ_PCIE, ATTR_DMA_PCIEBAR2AXIBAR_SEC_PF0, 11, 1)
81 FIELD(TZ_PCIE, ATTR_DMA_AXIBAR2PCIEBAR_SEC_5, 10, 1)
82 FIELD(TZ_PCIE, ATTR_DMA_AXIBAR2PCIEBAR_SEC_4, 9, 1)
83 FIELD(TZ_PCIE, ATTR_DMA_AXIBAR2PCIEBAR_SEC_3, 8, 1)
84 FIELD(TZ_PCIE, ATTR_DMA_AXIBAR2PCIEBAR_SEC_2, 7, 1)
85 FIELD(TZ_PCIE, ATTR_DMA_AXIBAR2PCIEBAR_SEC_1, 6, 1)
86 FIELD(TZ_PCIE, ATTR_DMA_AXIBAR2PCIEBAR_SEC_0, 5, 1)
87 FIELD(TZ_PCIE, ATTRIB_DMA, 4, 1)
88 FIELD(TZ_PCIE, ATTRIB_PCIE_1, 3, 1)
89 FIELD(TZ_PCIE, ATTRIB_PCIE_0, 2, 1)
90 FIELD(TZ_PCIE, CFG_MGMT_PCIE1, 1, 1)
91 FIELD(TZ_PCIE, CFG_MGMT_PCIE0, 0, 1)
92REG32(TZ_CPI, 0x104)
93 FIELD(TZ_CPI, PORT1_CFG, 3, 1)
94 FIELD(TZ_CPI, PORT1_EN, 2, 1)
95 FIELD(TZ_CPI, PORT0_CFG, 1, 1)
96 FIELD(TZ_CPI, PORT0_EN, 0, 1)
97REG32(TZ_CRCPM, 0x108)
98 FIELD(TZ_CRCPM, CFG, 0, 1)
99REG32(TZ_SLCR, 0x10c)
100 FIELD(TZ_SLCR, CFG, 0, 1)
101REG32(TZ_ADDRREMAP, 0x110)
102 FIELD(TZ_ADDRREMAP, CFG, 0, 1)
103REG32(TZ_MCAP, 0x114)
104 FIELD(TZ_MCAP, MCAP1_OVERRIDE_VAL, 3, 1)
105 FIELD(TZ_MCAP, MCAP1_OVERRIDE_EN, 2, 1)
106 FIELD(TZ_MCAP, MCAP0_OVERRIDE_VAL, 1, 1)
107 FIELD(TZ_MCAP, MCAP0_OVERRIDE_EN, 0, 1)
108REG32(PCIE0_SMID_EN, 0x200)
109 FIELD(PCIE0_SMID_EN, SELECT_ENABLE, 10, 10)
110 FIELD(PCIE0_SMID_EN, BASE, 0, 10)
111REG32(PCIE0_SMID_CFG0, 0x204)
112 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_7, 28, 4)
113 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_6, 24, 4)
114 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_5, 20, 4)
115 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_4, 16, 4)
116 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_3, 12, 4)
117 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_2, 8, 4)
118 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_1, 4, 4)
119 FIELD(PCIE0_SMID_CFG0, BDF_BIT_SEL_0, 0, 4)
120REG32(PCIE0_SMID_CFG1, 0x208)
121 FIELD(PCIE0_SMID_CFG1, BDF_BIT_SEL_9, 4, 4)
122 FIELD(PCIE0_SMID_CFG1, BDF_BIT_SEL_8, 0, 4)
123REG32(PCIE1_SMID_EN, 0x20c)
124 FIELD(PCIE1_SMID_EN, SELECT_ENABLE, 10, 10)
125 FIELD(PCIE1_SMID_EN, BASE, 0, 10)
126REG32(PCIE1_SMID_CFG0, 0x210)
127 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_7, 28, 4)
128 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_6, 24, 4)
129 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_5, 20, 4)
130 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_4, 16, 4)
131 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_3, 12, 4)
132 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_2, 8, 4)
133 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_1, 4, 4)
134 FIELD(PCIE1_SMID_CFG0, BDF_BIT_SEL_0, 0, 4)
135REG32(PCIE1_SMID_CFG1, 0x214)
136 FIELD(PCIE1_SMID_CFG1, BDF_BIT_SEL_9, 4, 4)
137 FIELD(PCIE1_SMID_CFG1, BDF_BIT_SEL_8, 0, 4)
138REG32(PCIE0_FUNC_NUM, 0x218)
139 FIELD(PCIE0_FUNC_NUM, DBG, 8, 8)
140 FIELD(PCIE0_FUNC_NUM, PS, 0, 8)
141REG32(CMN_SMID, 0x220)
142 FIELD(CMN_SMID, BASE, 0, 10)
143REG32(TZPROT, 0x300)
144 FIELD(TZPROT, ACTIVE, 0, 1)
145REG32(OD_MBIST_RESET_N, 0x420)
146 FIELD(OD_MBIST_RESET_N, CPM_POR_HNF_1, 7, 1)
147 FIELD(OD_MBIST_RESET_N, CPM_POR_HNF_0, 6, 1)
148 FIELD(OD_MBIST_RESET_N, CPM_INT_WRAP, 5, 1)
149 FIELD(OD_MBIST_RESET_N, CPM_POR_CXRH_1, 4, 1)
150 FIELD(OD_MBIST_RESET_N, CPM_POR_CXRH_0, 3, 1)
151 FIELD(OD_MBIST_RESET_N, CPM_PCIEA, 2, 1)
152 FIELD(OD_MBIST_RESET_N, PCIEA_DMA, 1, 1)
153 FIELD(OD_MBIST_RESET_N, CPM_L2, 0, 1)
154REG32(OD_MBIST_PG_EN, 0x424)
155 FIELD(OD_MBIST_PG_EN, CPM_POR_HNF_1, 7, 1)
156 FIELD(OD_MBIST_PG_EN, CPM_POR_HNF_0, 6, 1)
157 FIELD(OD_MBIST_PG_EN, CPM_INT_WRAP, 5, 1)
158 FIELD(OD_MBIST_PG_EN, CPM_POR_CXRH_1, 4, 1)
159 FIELD(OD_MBIST_PG_EN, CPM_POR_CXRH_0, 3, 1)
160 FIELD(OD_MBIST_PG_EN, CPM_PCIEA, 2, 1)
161 FIELD(OD_MBIST_PG_EN, PCIEA_DMA, 1, 1)
162 FIELD(OD_MBIST_PG_EN, CPM_L2, 0, 1)
163REG32(OD_MBIST_SETUP, 0x428)
164 FIELD(OD_MBIST_SETUP, CPM_POR_HNF_1, 7, 1)
165 FIELD(OD_MBIST_SETUP, CPM_POR_HNF_0, 6, 1)
166 FIELD(OD_MBIST_SETUP, CPM_INT_WRAP, 5, 1)
167 FIELD(OD_MBIST_SETUP, CPM_POR_CXRH_1, 4, 1)
168 FIELD(OD_MBIST_SETUP, CPM_POR_CXRH_0, 3, 1)
169 FIELD(OD_MBIST_SETUP, CPM_PCIEA, 2, 1)
170 FIELD(OD_MBIST_SETUP, PCIEA_DMA, 1, 1)
171 FIELD(OD_MBIST_SETUP, CPM_L2, 0, 1)
172REG32(OD_MBIST_DONE, 0x42c)
173 FIELD(OD_MBIST_DONE, CPM_POR_HNF_1, 7, 1)
174 FIELD(OD_MBIST_DONE, CPM_POR_HNF_0, 6, 1)
175 FIELD(OD_MBIST_DONE, CPM_INT_WRAP, 5, 1)
176 FIELD(OD_MBIST_DONE, CPM_POR_CXRH_1, 4, 1)
177 FIELD(OD_MBIST_DONE, CPM_POR_CXRH_0, 3, 1)
178 FIELD(OD_MBIST_DONE, CPM_PCIEA, 2, 1)
179 FIELD(OD_MBIST_DONE, PCIEA_DMA, 1, 1)
180 FIELD(OD_MBIST_DONE, CPM_L2, 0, 1)
181REG32(OD_MBIST_GO, 0x430)
182 FIELD(OD_MBIST_GO, CPM_POR_HNF_1, 7, 1)
183 FIELD(OD_MBIST_GO, CPM_POR_HNF_0, 6, 1)
184 FIELD(OD_MBIST_GO, CPM_INT_WRAP, 5, 1)
185 FIELD(OD_MBIST_GO, CPM_POR_CXRH_1, 4, 1)
186 FIELD(OD_MBIST_GO, CPM_POR_CXRH_0, 3, 1)
187 FIELD(OD_MBIST_GO, CPM_PCIEA, 2, 1)
188 FIELD(OD_MBIST_GO, PCIEA_DMA, 1, 1)
189 FIELD(OD_MBIST_GO, CPM_L2, 0, 1)
190
191#define CPM_SLCR_SECURE_R_MAX (R_OD_MBIST_GO + 1)
192
193typedef struct CPM_SLCR_SECURE {
194 SysBusDevice parent_obj;
195 MemoryRegion iomem;
196 qemu_irq irq_ir;
197
198 uint32_t regs[CPM_SLCR_SECURE_R_MAX];
199 RegisterInfo regs_info[CPM_SLCR_SECURE_R_MAX];
200} CPM_SLCR_SECURE;
201
202static void ir_update_irq(CPM_SLCR_SECURE *s)
203{
204 bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
205 qemu_set_irq(s->irq_ir, pending);
206}
207
208static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
209{
210 CPM_SLCR_SECURE *s = XILINX_CPM_SLCR_SECURE(reg->opaque);
211 ir_update_irq(s);
212}
213
214static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
215{
216 CPM_SLCR_SECURE *s = XILINX_CPM_SLCR_SECURE(reg->opaque);
217 uint32_t val = val64;
218
219 s->regs[R_IR_MASK] &= ~val;
220 ir_update_irq(s);
221 return 0;
222}
223
224static void od_mbist_pg_en_postw(RegisterInfo *reg, uint64_t val64)
225{
226 CPM_SLCR_SECURE *s = XILINX_CPM_SLCR_SECURE(reg->opaque);
227 uint32_t val = val64;
228
229 s->regs[R_OD_MBIST_DONE] = s->regs[R_OD_MBIST_SETUP] & val;
230 s->regs[R_OD_MBIST_GO] = s->regs[R_OD_MBIST_DONE];
231}
232
233static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
234{
235 CPM_SLCR_SECURE *s = XILINX_CPM_SLCR_SECURE(reg->opaque);
236 uint32_t val = val64;
237
238 s->regs[R_IR_MASK] |= val;
239 ir_update_irq(s);
240 return 0;
241}
242
243static uint64_t ir_trigger_prew(RegisterInfo *reg, uint64_t val64)
244{
245 CPM_SLCR_SECURE *s = XILINX_CPM_SLCR_SECURE(reg->opaque);
246 uint32_t val = val64;
247
248 s->regs[R_IR_STATUS] |= val;
249 ir_update_irq(s);
250 return 0;
251}
252
253static const RegisterAccessInfo cpm_slcr_secure_regs_info[] = {
254 { .name = "WPROT0", .addr = A_WPROT0,
255 .reset = 0x1,
256 },{ .name = "REG_CTRL", .addr = A_REG_CTRL,
257 .rsvd = 0xfffffffe,
258 .ro = 0xfffffffe,
259 },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
260 .rsvd = 0xfffffffe,
261 .ro = 0xfffffffe,
262 .w1c = 0x1,
263 .post_write = ir_status_postw,
264 },{ .name = "IR_MASK", .addr = A_IR_MASK,
265 .reset = 0x1,
266 .rsvd = 0xfffffffe,
267 .ro = 0xffffffff,
268 },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
269 .rsvd = 0xfffffffe,
270 .ro = 0xfffffffe,
271 .pre_write = ir_enable_prew,
272 },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
273 .rsvd = 0xfffffffe,
274 .ro = 0xfffffffe,
275 .pre_write = ir_disable_prew,
276 },{ .name = "IR_TRIGGER", .addr = A_IR_TRIGGER,
277 .rsvd = 0xfffffffe,
278 .ro = 0xfffffffe,
279 .pre_write = ir_trigger_prew,
280 },{ .name = "TZ_PCIE", .addr = A_TZ_PCIE,
281 .reset = 0xffffffff,
282 },{ .name = "TZ_CPI", .addr = A_TZ_CPI,
283 .reset = 0xf,
284 .rsvd = 0xfffffff0,
285 .ro = 0xfffffff0,
286 },{ .name = "TZ_CRCPM", .addr = A_TZ_CRCPM,
287 .reset = 0x1,
288 .rsvd = 0xfffffffe,
289 .ro = 0xfffffffe,
290 },{ .name = "TZ_SLCR", .addr = A_TZ_SLCR,
291 .reset = 0x1,
292 .rsvd = 0xfffffffe,
293 .ro = 0xfffffffe,
294 },{ .name = "TZ_ADDRREMAP", .addr = A_TZ_ADDRREMAP,
295 .reset = 0x1,
296 .rsvd = 0xfffffffe,
297 .ro = 0xfffffffe,
298 },{ .name = "TZ_MCAP", .addr = A_TZ_MCAP,
299 .reset = 0xf,
300 .rsvd = 0xfffffff0,
301 .ro = 0xfffffff0,
302 },{ .name = "PCIE0_SMID_EN", .addr = A_PCIE0_SMID_EN,
303 .rsvd = 0xfff00000,
304 .ro = 0xfff00000,
305 },{ .name = "PCIE0_SMID_CFG0", .addr = A_PCIE0_SMID_CFG0,
306 },{ .name = "PCIE0_SMID_CFG1", .addr = A_PCIE0_SMID_CFG1,
307 .rsvd = 0xffffff00,
308 .ro = 0xffffff00,
309 },{ .name = "PCIE1_SMID_EN", .addr = A_PCIE1_SMID_EN,
310 .rsvd = 0xfff00000,
311 .ro = 0xfff00000,
312 },{ .name = "PCIE1_SMID_CFG0", .addr = A_PCIE1_SMID_CFG0,
313 },{ .name = "PCIE1_SMID_CFG1", .addr = A_PCIE1_SMID_CFG1,
314 .rsvd = 0xffffff00,
315 .ro = 0xffffff00,
316 },{ .name = "PCIE0_FUNC_NUM", .addr = A_PCIE0_FUNC_NUM,
317 .rsvd = 0xffff0000,
318 .ro = 0xffff0000,
319 },{ .name = "CMN_SMID", .addr = A_CMN_SMID,
320 },{ .name = "TZPROT", .addr = A_TZPROT,
321 },{ .name = "OD_MBIST_RESET_N", .addr = A_OD_MBIST_RESET_N,
322 .rsvd = 0xffffff00,
323 .ro = 0xffffff00,
324 },{ .name = "OD_MBIST_PG_EN", .addr = A_OD_MBIST_PG_EN,
325 .rsvd = 0xffffff00,
326 .ro = 0xffffff00,
327 .post_write = od_mbist_pg_en_postw,
328 },{ .name = "OD_MBIST_SETUP", .addr = A_OD_MBIST_SETUP,
329 .rsvd = 0xffffff00,
330 .ro = 0xffffff00,
331 },{ .name = "OD_MBIST_DONE", .addr = A_OD_MBIST_DONE,
332 .rsvd = 0xffffff00,
333 .ro = 0xffffffff,
334 },{ .name = "OD_MBIST_GO", .addr = A_OD_MBIST_GO,
335 .rsvd = 0xffffff00,
336 .ro = 0xffffffff,
337 }
338};
339
340static void cpm_slcr_secure_reset_enter(Object *obj, ResetType type)
341{
342 CPM_SLCR_SECURE *s = XILINX_CPM_SLCR_SECURE(obj);
343 unsigned int i;
344
345 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
346 register_reset(&s->regs_info[i]);
347 }
348}
349
350static void cpm_slcr_secure_reset_hold(Object *obj)
351{
352 CPM_SLCR_SECURE *s = XILINX_CPM_SLCR_SECURE(obj);
353
354 ir_update_irq(s);
355}
356
357static const MemoryRegionOps cpm_slcr_secure_ops = {
358 .read = register_read_memory,
359 .write = register_write_memory,
360 .endianness = DEVICE_LITTLE_ENDIAN,
361 .valid = {
362 .min_access_size = 4,
363 .max_access_size = 4,
364 },
365};
366
367static void cpm_slcr_secure_realize(DeviceState *dev, Error **errp)
368{
369
370}
371
372static void cpm_slcr_secure_init(Object *obj)
373{
374 CPM_SLCR_SECURE *s = XILINX_CPM_SLCR_SECURE(obj);
375 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
376 RegisterInfoArray *reg_array;
377
378 memory_region_init(&s->iomem, obj, TYPE_XILINX_CPM_SLCR_SECURE,
379 CPM_SLCR_SECURE_R_MAX * 4);
380 reg_array =
381 register_init_block32(DEVICE(obj), cpm_slcr_secure_regs_info,
382 ARRAY_SIZE(cpm_slcr_secure_regs_info),
383 s->regs_info, s->regs,
384 &cpm_slcr_secure_ops,
385 XILINX_CPM_SLCR_SECURE_ERR_DEBUG,
386 CPM_SLCR_SECURE_R_MAX * 4);
387 memory_region_add_subregion(&s->iomem,
388 0x0,
389 ®_array->mem);
390 sysbus_init_mmio(sbd, &s->iomem);
391 sysbus_init_irq(sbd, &s->irq_ir);
392}
393
394static const VMStateDescription vmstate_cpm_slcr_secure = {
395 .name = TYPE_XILINX_CPM_SLCR_SECURE,
396 .version_id = 1,
397 .minimum_version_id = 1,
398 .fields = (VMStateField[]) {
399 VMSTATE_UINT32_ARRAY(regs, CPM_SLCR_SECURE, CPM_SLCR_SECURE_R_MAX),
400 VMSTATE_END_OF_LIST(),
401 }
402};
403
404static void cpm_slcr_secure_class_init(ObjectClass *klass, void *data)
405{
406 ResettableClass *rc = RESETTABLE_CLASS(klass);
407 DeviceClass *dc = DEVICE_CLASS(klass);
408
409 dc->realize = cpm_slcr_secure_realize;
410 dc->vmsd = &vmstate_cpm_slcr_secure;
411 rc->phases.enter = cpm_slcr_secure_reset_enter;
412 rc->phases.hold = cpm_slcr_secure_reset_hold;
413}
414
415static const TypeInfo cpm_slcr_secure_info = {
416 .name = TYPE_XILINX_CPM_SLCR_SECURE,
417 .parent = TYPE_SYS_BUS_DEVICE,
418 .instance_size = sizeof(CPM_SLCR_SECURE),
419 .class_init = cpm_slcr_secure_class_init,
420 .instance_init = cpm_slcr_secure_init,
421};
422
423static void cpm_slcr_secure_register_types(void)
424{
425 type_register_static(&cpm_slcr_secure_info);
426}
427
428type_init(cpm_slcr_secure_register_types)
429
