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20#include "qemu/osdep.h"
21#include "qemu-common.h"
22#include "qemu/datadir.h"
23#include "qemu/units.h"
24#include "qemu/cutils.h"
25#include "qapi/error.h"
26#include "sysemu/qtest.h"
27#include "sysemu/sysemu.h"
28#include "sysemu/numa.h"
29#include "sysemu/reset.h"
30#include "sysemu/runstate.h"
31#include "sysemu/cpus.h"
32#include "sysemu/device_tree.h"
33#include "sysemu/hw_accel.h"
34#include "target/ppc/cpu.h"
35#include "hw/ppc/fdt.h"
36#include "hw/ppc/ppc.h"
37#include "hw/ppc/pnv.h"
38#include "hw/ppc/pnv_core.h"
39#include "hw/loader.h"
40#include "hw/nmi.h"
41#include "qapi/visitor.h"
42#include "monitor/monitor.h"
43#include "hw/intc/intc.h"
44#include "hw/ipmi/ipmi.h"
45#include "target/ppc/mmu-hash64.h"
46#include "hw/pci/msi.h"
47
48#include "hw/ppc/xics.h"
49#include "hw/qdev-properties.h"
50#include "hw/ppc/pnv_xscom.h"
51#include "hw/ppc/pnv_pnor.h"
52
53#include "hw/isa/isa.h"
54#include "hw/char/serial.h"
55#include "hw/rtc/mc146818rtc.h"
56
57#include <libfdt.h>
58
59#define FDT_MAX_SIZE (1 * MiB)
60
61#define FW_FILE_NAME "skiboot.lid"
62#define FW_LOAD_ADDR 0x0
63#define FW_MAX_SIZE (16 * MiB)
64
65#define KERNEL_LOAD_ADDR 0x20000000
66#define KERNEL_MAX_SIZE (128 * MiB)
67#define INITRD_LOAD_ADDR 0x28000000
68#define INITRD_MAX_SIZE (128 * MiB)
69
70static const char *pnv_chip_core_typename(const PnvChip *o)
71{
72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
75 const char *core_type = object_class_get_name(object_class_by_name(s));
76 g_free(s);
77 return core_type;
78}
79
80
81
82
83
84
85#define MAX_CPUS 2048
86
87
88
89
90
91
92static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
93{
94 char *mem_name;
95 uint64_t mem_reg_property[2];
96 int off;
97
98 mem_reg_property[0] = cpu_to_be64(start);
99 mem_reg_property[1] = cpu_to_be64(size);
100
101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
102 off = fdt_add_subnode(fdt, 0, mem_name);
103 g_free(mem_name);
104
105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
107 sizeof(mem_reg_property))));
108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
109}
110
111static int get_cpus_node(void *fdt)
112{
113 int cpus_offset = fdt_path_offset(fdt, "/cpus");
114
115 if (cpus_offset < 0) {
116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
117 if (cpus_offset) {
118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
120 }
121 }
122 _FDT(cpus_offset);
123 return cpus_offset;
124}
125
126
127
128
129
130
131
132
133static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
134{
135 PowerPCCPU *cpu = pc->threads[0];
136 CPUState *cs = CPU(cpu);
137 DeviceClass *dc = DEVICE_GET_CLASS(cs);
138 int smt_threads = CPU_CORE(pc)->nr_threads;
139 CPUPPCState *env = &cpu->env;
140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
141 uint32_t servers_prop[smt_threads];
142 int i;
143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
144 0xffffffff, 0xffffffff};
145 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
146 uint32_t cpufreq = 1000000000;
147 uint32_t page_sizes_prop[64];
148 size_t page_sizes_prop_size;
149 const uint8_t pa_features[] = { 24, 0,
150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
154 int offset;
155 char *nodename;
156 int cpus_offset = get_cpus_node(fdt);
157
158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
159 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
160 _FDT(offset);
161 g_free(nodename);
162
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
164
165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
168
169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
171 env->dcache_line_size)));
172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
173 env->dcache_line_size)));
174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
175 env->icache_line_size)));
176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
177 env->icache_line_size)));
178
179 if (pcc->l1_dcache_size) {
180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
181 pcc->l1_dcache_size)));
182 } else {
183 warn_report("Unknown L1 dcache size for cpu");
184 }
185 if (pcc->l1_icache_size) {
186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
187 pcc->l1_icache_size)));
188 } else {
189 warn_report("Unknown L1 icache size for cpu");
190 }
191
192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
195 cpu->hash64_opts->slb_size)));
196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
198
199 if (ppc_has_spr(cpu, SPR_PURR)) {
200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
201 }
202
203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
205 segs, sizeof(segs))));
206 }
207
208
209
210
211
212
213
214 if (env->insns_flags & PPC_ALTIVEC) {
215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
216
217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
218 }
219
220
221
222
223
224
225 if (env->insns_flags2 & PPC2_DFP) {
226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
227 }
228
229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
230 sizeof(page_sizes_prop));
231 if (page_sizes_prop_size) {
232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
233 page_sizes_prop, page_sizes_prop_size)));
234 }
235
236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
237 pa_features, sizeof(pa_features))));
238
239
240 for (i = 0; i < smt_threads; i++) {
241 servers_prop[i] = cpu_to_be32(pc->pir + i);
242 }
243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
244 servers_prop, sizeof(servers_prop))));
245}
246
247static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
248 uint32_t nr_threads)
249{
250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
251 char *name;
252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
253 uint32_t irange[2], i, rsize;
254 uint64_t *reg;
255 int offset;
256
257 irange[0] = cpu_to_be32(pir);
258 irange[1] = cpu_to_be32(nr_threads);
259
260 rsize = sizeof(uint64_t) * 2 * nr_threads;
261 reg = g_malloc(rsize);
262 for (i = 0; i < nr_threads; i++) {
263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
264 reg[i * 2 + 1] = cpu_to_be64(0x1000);
265 }
266
267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
268 offset = fdt_add_subnode(fdt, 0, name);
269 _FDT(offset);
270 g_free(name);
271
272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
274 _FDT((fdt_setprop_string(fdt, offset, "device_type",
275 "PowerPC-External-Interrupt-Presentation")));
276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
278 irange, sizeof(irange))));
279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
281 g_free(reg);
282}
283
284static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
285{
286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
287 int i;
288
289 pnv_dt_xscom(chip, fdt, 0,
290 cpu_to_be64(PNV_XSCOM_BASE(chip)),
291 cpu_to_be64(PNV_XSCOM_SIZE),
292 compat, sizeof(compat));
293
294 for (i = 0; i < chip->nr_cores; i++) {
295 PnvCore *pnv_core = chip->cores[i];
296
297 pnv_dt_core(chip, pnv_core, fdt);
298
299
300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
301 }
302
303 if (chip->ram_size) {
304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
305 }
306}
307
308static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
309{
310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
311 int i;
312
313 pnv_dt_xscom(chip, fdt, 0,
314 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
315 cpu_to_be64(PNV9_XSCOM_SIZE),
316 compat, sizeof(compat));
317
318 for (i = 0; i < chip->nr_cores; i++) {
319 PnvCore *pnv_core = chip->cores[i];
320
321 pnv_dt_core(chip, pnv_core, fdt);
322 }
323
324 if (chip->ram_size) {
325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
326 }
327
328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
329}
330
331static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
332{
333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
334 int i;
335
336 pnv_dt_xscom(chip, fdt, 0,
337 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
338 cpu_to_be64(PNV10_XSCOM_SIZE),
339 compat, sizeof(compat));
340
341 for (i = 0; i < chip->nr_cores; i++) {
342 PnvCore *pnv_core = chip->cores[i];
343
344 pnv_dt_core(chip, pnv_core, fdt);
345 }
346
347 if (chip->ram_size) {
348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
349 }
350
351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
352}
353
354static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
355{
356 uint32_t io_base = d->ioport_id;
357 uint32_t io_regs[] = {
358 cpu_to_be32(1),
359 cpu_to_be32(io_base),
360 cpu_to_be32(2)
361 };
362 char *name;
363 int node;
364
365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
366 node = fdt_add_subnode(fdt, lpc_off, name);
367 _FDT(node);
368 g_free(name);
369
370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
372}
373
374static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
375{
376 const char compatible[] = "ns16550\0pnpPNP,501";
377 uint32_t io_base = d->ioport_id;
378 uint32_t io_regs[] = {
379 cpu_to_be32(1),
380 cpu_to_be32(io_base),
381 cpu_to_be32(8)
382 };
383 char *name;
384 int node;
385
386 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
387 node = fdt_add_subnode(fdt, lpc_off, name);
388 _FDT(node);
389 g_free(name);
390
391 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
392 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
393 sizeof(compatible))));
394
395 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
396 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
397 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
398 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
399 fdt_get_phandle(fdt, lpc_off))));
400
401
402 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
403}
404
405static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
406{
407 const char compatible[] = "bt\0ipmi-bt";
408 uint32_t io_base;
409 uint32_t io_regs[] = {
410 cpu_to_be32(1),
411 0,
412 cpu_to_be32(3)
413 };
414 uint32_t irq;
415 char *name;
416 int node;
417
418 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
419 io_regs[1] = cpu_to_be32(io_base);
420
421 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
422
423 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
424 node = fdt_add_subnode(fdt, lpc_off, name);
425 _FDT(node);
426 g_free(name);
427
428 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
429 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
430 sizeof(compatible))));
431
432
433 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
434 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
435 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
436 fdt_get_phandle(fdt, lpc_off))));
437}
438
439typedef struct ForeachPopulateArgs {
440 void *fdt;
441 int offset;
442} ForeachPopulateArgs;
443
444static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
445{
446 ForeachPopulateArgs *args = opaque;
447 ISADevice *d = ISA_DEVICE(dev);
448
449 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
450 pnv_dt_rtc(d, args->fdt, args->offset);
451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
452 pnv_dt_serial(d, args->fdt, args->offset);
453 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
454 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
455 } else {
456 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
457 d->ioport_id);
458 }
459
460 return 0;
461}
462
463
464
465
466
467static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
468{
469 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
470 ForeachPopulateArgs args = {
471 .fdt = fdt,
472 .offset = isa_offset,
473 };
474 uint32_t phandle;
475
476 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
477
478 phandle = qemu_fdt_alloc_phandle(fdt);
479 assert(phandle > 0);
480 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
481
482
483
484
485
486 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
487 &args);
488}
489
490static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
491{
492 int off;
493
494 off = fdt_add_subnode(fdt, 0, "ibm,opal");
495 off = fdt_add_subnode(fdt, off, "power-mgt");
496
497 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
498}
499
500static void *pnv_dt_create(MachineState *machine)
501{
502 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
503 PnvMachineState *pnv = PNV_MACHINE(machine);
504 void *fdt;
505 char *buf;
506 int off;
507 int i;
508
509 fdt = g_malloc0(FDT_MAX_SIZE);
510 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
511
512
513 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
514
515
516 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
517 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
518 _FDT((fdt_setprop_string(fdt, 0, "model",
519 "IBM PowerNV (emulated by qemu)")));
520 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
521
522 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
523 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
524 if (qemu_uuid_set) {
525 _FDT((fdt_property_string(fdt, "system-id", buf)));
526 }
527 g_free(buf);
528
529 off = fdt_add_subnode(fdt, 0, "chosen");
530 if (machine->kernel_cmdline) {
531 _FDT((fdt_setprop_string(fdt, off, "bootargs",
532 machine->kernel_cmdline)));
533 }
534
535 if (pnv->initrd_size) {
536 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
537 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
538
539 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
540 &start_prop, sizeof(start_prop))));
541 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
542 &end_prop, sizeof(end_prop))));
543 }
544
545
546 for (i = 0; i < pnv->num_chips; i++) {
547 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
548 }
549
550
551 pnv_dt_isa(pnv, fdt);
552
553 if (pnv->bmc) {
554 pnv_dt_bmc_sensors(pnv->bmc, fdt);
555 }
556
557
558 if (pmc->dt_power_mgt) {
559 pmc->dt_power_mgt(pnv, fdt);
560 }
561
562 return fdt;
563}
564
565static void pnv_powerdown_notify(Notifier *n, void *opaque)
566{
567 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
568
569 if (pnv->bmc) {
570 pnv_bmc_powerdown(pnv->bmc);
571 }
572}
573
574static void pnv_reset(MachineState *machine)
575{
576 PnvMachineState *pnv = PNV_MACHINE(machine);
577 IPMIBmc *bmc;
578 void *fdt;
579
580 qemu_devices_reset();
581
582
583
584
585
586
587 bmc = pnv_bmc_find(&error_fatal);
588 if (!pnv->bmc) {
589 if (!bmc) {
590 if (!qtest_enabled()) {
591 warn_report("machine has no BMC device. Use '-device "
592 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
593 "to define one");
594 }
595 } else {
596 pnv_bmc_set_pnor(bmc, pnv->pnor);
597 pnv->bmc = bmc;
598 }
599 }
600
601 fdt = pnv_dt_create(machine);
602
603
604 _FDT((fdt_pack(fdt)));
605
606 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
607 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
608
609 g_free(fdt);
610}
611
612static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
613{
614 Pnv8Chip *chip8 = PNV8_CHIP(chip);
615 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
616}
617
618static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
619{
620 Pnv8Chip *chip8 = PNV8_CHIP(chip);
621 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
622}
623
624static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
625{
626 Pnv9Chip *chip9 = PNV9_CHIP(chip);
627 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
628}
629
630static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
631{
632 Pnv10Chip *chip10 = PNV10_CHIP(chip);
633 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
634}
635
636static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
637{
638 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
639}
640
641static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
642{
643 Pnv8Chip *chip8 = PNV8_CHIP(chip);
644 int i;
645
646 ics_pic_print_info(&chip8->psi.ics, mon);
647 for (i = 0; i < chip->num_phbs; i++) {
648 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon);
649 ics_pic_print_info(&chip8->phbs[i].lsis, mon);
650 }
651}
652
653static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
654{
655 Pnv9Chip *chip9 = PNV9_CHIP(chip);
656 int i, j;
657
658 pnv_xive_pic_print_info(&chip9->xive, mon);
659 pnv_psi_pic_print_info(&chip9->psi, mon);
660
661 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
662 PnvPhb4PecState *pec = &chip9->pecs[i];
663 for (j = 0; j < pec->num_stacks; j++) {
664 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon);
665 }
666 }
667}
668
669static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
670 uint32_t core_id)
671{
672 return PNV_XSCOM_EX_BASE(core_id);
673}
674
675static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
676 uint32_t core_id)
677{
678 return PNV9_XSCOM_EC_BASE(core_id);
679}
680
681static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
682 uint32_t core_id)
683{
684 return PNV10_XSCOM_EC_BASE(core_id);
685}
686
687static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
688{
689 PowerPCCPUClass *ppc_default =
690 POWERPC_CPU_CLASS(object_class_by_name(default_type));
691 PowerPCCPUClass *ppc =
692 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
693
694 return ppc_default->pvr_match(ppc_default, ppc->pvr);
695}
696
697static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
698{
699 ISADevice *dev = isa_new("isa-ipmi-bt");
700
701 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal);
702 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal);
703 isa_realize_and_unref(dev, bus, &error_fatal);
704}
705
706static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
707{
708 Pnv10Chip *chip10 = PNV10_CHIP(chip);
709
710 pnv_psi_pic_print_info(&chip10->psi, mon);
711}
712
713static void pnv_init(MachineState *machine)
714{
715 const char *bios_name = machine->firmware ?: FW_FILE_NAME;
716 PnvMachineState *pnv = PNV_MACHINE(machine);
717 MachineClass *mc = MACHINE_GET_CLASS(machine);
718 char *fw_filename;
719 long fw_size;
720 int i;
721 char *chip_typename;
722 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
723 DeviceState *dev;
724
725
726 if (machine->ram_size < mc->default_ram_size) {
727 char *sz = size_to_str(mc->default_ram_size);
728 error_report("Invalid RAM size, should be bigger than %s", sz);
729 g_free(sz);
730 exit(EXIT_FAILURE);
731 }
732 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
733
734
735
736
737 dev = qdev_new(TYPE_PNV_PNOR);
738 if (pnor) {
739 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor));
740 }
741 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
742 pnv->pnor = PNV_PNOR(dev);
743
744
745 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
746 if (!fw_filename) {
747 error_report("Could not find OPAL firmware '%s'", bios_name);
748 exit(1);
749 }
750
751 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
752 if (fw_size < 0) {
753 error_report("Could not load OPAL firmware '%s'", fw_filename);
754 exit(1);
755 }
756 g_free(fw_filename);
757
758
759 if (machine->kernel_filename) {
760 long kernel_size;
761
762 kernel_size = load_image_targphys(machine->kernel_filename,
763 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
764 if (kernel_size < 0) {
765 error_report("Could not load kernel '%s'",
766 machine->kernel_filename);
767 exit(1);
768 }
769 }
770
771
772 if (machine->initrd_filename) {
773 pnv->initrd_base = INITRD_LOAD_ADDR;
774 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
775 pnv->initrd_base, INITRD_MAX_SIZE);
776 if (pnv->initrd_size < 0) {
777 error_report("Could not load initial ram disk '%s'",
778 machine->initrd_filename);
779 exit(1);
780 }
781 }
782
783
784 msi_nonbroken = true;
785
786
787
788
789
790 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
791 error_report("invalid CPU model '%s' for %s machine",
792 machine->cpu_type, mc->name);
793 exit(1);
794 }
795
796
797 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
798 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
799 i, machine->cpu_type);
800 if (!object_class_by_name(chip_typename)) {
801 error_report("invalid chip model '%.*s' for %s machine",
802 i, machine->cpu_type, mc->name);
803 exit(1);
804 }
805
806 pnv->num_chips =
807 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
808
809
810
811
812 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) {
813 error_report("invalid number of chips: '%d'", pnv->num_chips);
814 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n");
815 exit(1);
816 }
817
818 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
819 for (i = 0; i < pnv->num_chips; i++) {
820 char chip_name[32];
821 Object *chip = OBJECT(qdev_new(chip_typename));
822
823 pnv->chips[i] = PNV_CHIP(chip);
824
825
826
827
828
829 if (i == 0) {
830 object_property_set_int(chip, "ram-size", machine->ram_size,
831 &error_fatal);
832 }
833
834 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
835 object_property_add_child(OBJECT(pnv), chip_name, chip);
836 object_property_set_int(chip, "chip-id", PNV_CHIP_HWID(i),
837 &error_fatal);
838 object_property_set_int(chip, "nr-cores", machine->smp.cores,
839 &error_fatal);
840 object_property_set_int(chip, "nr-threads", machine->smp.threads,
841 &error_fatal);
842
843
844
845
846 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
847 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort);
848 }
849 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
850 object_property_set_link(chip, "xive-fabric", OBJECT(pnv),
851 &error_abort);
852 }
853 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
854 }
855 g_free(chip_typename);
856
857
858 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
859
860
861 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
862
863
864 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
865
866
867
868
869
870 if (defaults_enabled()) {
871 pnv->bmc = pnv_bmc_create(pnv->pnor);
872 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
873 }
874
875
876
877
878
879
880 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET,
881 &pnv->pnor->mmio);
882
883
884
885
886
887 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
888 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
889}
890
891
892
893
894
895
896
897static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
898{
899 return (chip->chip_id << 7) | (core_id << 3);
900}
901
902static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
903 Error **errp)
904{
905 Pnv8Chip *chip8 = PNV8_CHIP(chip);
906 Error *local_err = NULL;
907 Object *obj;
908 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
909
910 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
911 if (local_err) {
912 error_propagate(errp, local_err);
913 return;
914 }
915
916 pnv_cpu->intc = obj;
917}
918
919
920static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
921{
922 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
923
924 icp_reset(ICP(pnv_cpu->intc));
925}
926
927static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
928{
929 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
930
931 icp_destroy(ICP(pnv_cpu->intc));
932 pnv_cpu->intc = NULL;
933}
934
935static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
936 Monitor *mon)
937{
938 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
939}
940
941
942
943
944
945
946
947
948
949
950
951static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
952{
953 return (chip->chip_id << 8) | (core_id << 2);
954}
955
956static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
957{
958 return (chip->chip_id << 8) | (core_id << 2);
959}
960
961static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
962 Error **errp)
963{
964 Pnv9Chip *chip9 = PNV9_CHIP(chip);
965 Error *local_err = NULL;
966 Object *obj;
967 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
968
969
970
971
972
973
974 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
975 &local_err);
976 if (local_err) {
977 error_propagate(errp, local_err);
978 return;
979 }
980
981 pnv_cpu->intc = obj;
982}
983
984static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
985{
986 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
987
988 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
989}
990
991static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
992{
993 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
994
995 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
996 pnv_cpu->intc = NULL;
997}
998
999static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1000 Monitor *mon)
1001{
1002 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1003}
1004
1005static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1006 Error **errp)
1007{
1008 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1009
1010
1011 pnv_cpu->intc = NULL;
1012}
1013
1014static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1015{
1016 ;
1017}
1018
1019static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1020{
1021 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1022
1023 pnv_cpu->intc = NULL;
1024}
1025
1026static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1027 Monitor *mon)
1028{
1029}
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050#define POWER8E_CORE_MASK (0x7070ull)
1051#define POWER8_CORE_MASK (0x7e7eull)
1052
1053
1054
1055
1056#define POWER9_CORE_MASK (0xffffffffffffffull)
1057
1058
1059#define POWER10_CORE_MASK (0xffffffffffffffull)
1060
1061static void pnv_chip_power8_instance_init(Object *obj)
1062{
1063 PnvChip *chip = PNV_CHIP(obj);
1064 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1065 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1066 int i;
1067
1068 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1069 (Object **)&chip8->xics,
1070 object_property_allow_set_link,
1071 OBJ_PROP_LINK_STRONG);
1072
1073 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
1074
1075 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
1076
1077 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
1078
1079 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
1080
1081 for (i = 0; i < pcc->num_phbs; i++) {
1082 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3);
1083 }
1084
1085
1086
1087
1088 chip->num_phbs = pcc->num_phbs;
1089}
1090
1091static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1092 {
1093 PnvChip *chip = PNV_CHIP(chip8);
1094 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1095 int i, j;
1096 char *name;
1097
1098 name = g_strdup_printf("icp-%x", chip->chip_id);
1099 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1100 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1101 g_free(name);
1102
1103 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1104
1105
1106 for (i = 0; i < chip->nr_cores; i++) {
1107 PnvCore *pnv_core = chip->cores[i];
1108 int core_hwid = CPU_CORE(pnv_core)->core_id;
1109
1110 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1111 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1112 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1113
1114 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1115 &icp->mmio);
1116 }
1117 }
1118}
1119
1120static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1121{
1122 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1123 PnvChip *chip = PNV_CHIP(dev);
1124 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1125 Pnv8Psi *psi8 = &chip8->psi;
1126 Error *local_err = NULL;
1127 int i;
1128
1129 assert(chip8->xics);
1130
1131
1132 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1133 if (local_err) {
1134 error_propagate(errp, local_err);
1135 return;
1136 }
1137 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1138
1139 pcc->parent_realize(dev, &local_err);
1140 if (local_err) {
1141 error_propagate(errp, local_err);
1142 return;
1143 }
1144
1145
1146 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip),
1147 &error_fatal);
1148 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS,
1149 OBJECT(chip8->xics), &error_abort);
1150 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) {
1151 return;
1152 }
1153 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1154 &PNV_PSI(psi8)->xscom_regs);
1155
1156
1157 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi),
1158 &error_abort);
1159 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
1160 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1161
1162 chip->fw_mr = &chip8->lpc.isa_fw;
1163 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1164 (uint64_t) PNV_XSCOM_BASE(chip),
1165 PNV_XSCOM_LPC_BASE);
1166
1167
1168
1169
1170
1171 pnv_chip_icp_realize(chip8, &local_err);
1172 if (local_err) {
1173 error_propagate(errp, local_err);
1174 return;
1175 }
1176
1177
1178 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi),
1179 &error_abort);
1180 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
1181 return;
1182 }
1183 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1184
1185
1186 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1187 &chip8->occ.sram_regs);
1188
1189
1190 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip),
1191 &error_abort);
1192 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) {
1193 return;
1194 }
1195
1196 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1197
1198
1199 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1200 &chip8->homer.regs);
1201
1202
1203 for (i = 0; i < chip->num_phbs; i++) {
1204 PnvPHB3 *phb = &chip8->phbs[i];
1205 PnvPBCQState *pbcq = &phb->pbcq;
1206
1207 object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
1208 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
1209 &error_fatal);
1210 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
1211 return;
1212 }
1213
1214
1215 pnv_xscom_add_subregion(chip,
1216 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id,
1217 &pbcq->xscom_nest_regs);
1218 pnv_xscom_add_subregion(chip,
1219 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id,
1220 &pbcq->xscom_pci_regs);
1221 pnv_xscom_add_subregion(chip,
1222 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id,
1223 &pbcq->xscom_spci_regs);
1224 }
1225}
1226
1227static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1228{
1229 addr &= (PNV_XSCOM_SIZE - 1);
1230 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1231}
1232
1233static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1234{
1235 DeviceClass *dc = DEVICE_CLASS(klass);
1236 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1237
1238 k->chip_cfam_id = 0x221ef04980000000ull;
1239 k->cores_mask = POWER8E_CORE_MASK;
1240 k->num_phbs = 3;
1241 k->core_pir = pnv_chip_core_pir_p8;
1242 k->intc_create = pnv_chip_power8_intc_create;
1243 k->intc_reset = pnv_chip_power8_intc_reset;
1244 k->intc_destroy = pnv_chip_power8_intc_destroy;
1245 k->intc_print_info = pnv_chip_power8_intc_print_info;
1246 k->isa_create = pnv_chip_power8_isa_create;
1247 k->dt_populate = pnv_chip_power8_dt_populate;
1248 k->pic_print_info = pnv_chip_power8_pic_print_info;
1249 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1250 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1251 dc->desc = "PowerNV Chip POWER8E";
1252
1253 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1254 &k->parent_realize);
1255}
1256
1257static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1258{
1259 DeviceClass *dc = DEVICE_CLASS(klass);
1260 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1261
1262 k->chip_cfam_id = 0x220ea04980000000ull;
1263 k->cores_mask = POWER8_CORE_MASK;
1264 k->num_phbs = 3;
1265 k->core_pir = pnv_chip_core_pir_p8;
1266 k->intc_create = pnv_chip_power8_intc_create;
1267 k->intc_reset = pnv_chip_power8_intc_reset;
1268 k->intc_destroy = pnv_chip_power8_intc_destroy;
1269 k->intc_print_info = pnv_chip_power8_intc_print_info;
1270 k->isa_create = pnv_chip_power8_isa_create;
1271 k->dt_populate = pnv_chip_power8_dt_populate;
1272 k->pic_print_info = pnv_chip_power8_pic_print_info;
1273 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1274 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1275 dc->desc = "PowerNV Chip POWER8";
1276
1277 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1278 &k->parent_realize);
1279}
1280
1281static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1282{
1283 DeviceClass *dc = DEVICE_CLASS(klass);
1284 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1285
1286 k->chip_cfam_id = 0x120d304980000000ull;
1287 k->cores_mask = POWER8_CORE_MASK;
1288 k->num_phbs = 3;
1289 k->core_pir = pnv_chip_core_pir_p8;
1290 k->intc_create = pnv_chip_power8_intc_create;
1291 k->intc_reset = pnv_chip_power8_intc_reset;
1292 k->intc_destroy = pnv_chip_power8_intc_destroy;
1293 k->intc_print_info = pnv_chip_power8_intc_print_info;
1294 k->isa_create = pnv_chip_power8nvl_isa_create;
1295 k->dt_populate = pnv_chip_power8_dt_populate;
1296 k->pic_print_info = pnv_chip_power8_pic_print_info;
1297 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1298 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1299 dc->desc = "PowerNV Chip POWER8NVL";
1300
1301 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1302 &k->parent_realize);
1303}
1304
1305static void pnv_chip_power9_instance_init(Object *obj)
1306{
1307 PnvChip *chip = PNV_CHIP(obj);
1308 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1309 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1310 int i;
1311
1312 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
1313 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1314 "xive-fabric");
1315
1316 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
1317
1318 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
1319
1320 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
1321
1322 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
1323
1324 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
1325 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1326 TYPE_PNV_PHB4_PEC);
1327 }
1328
1329
1330
1331
1332 chip->num_phbs = pcc->num_phbs;
1333}
1334
1335static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1336{
1337 PnvChip *chip = PNV_CHIP(chip9);
1338 int i;
1339
1340 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1341 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1342
1343 for (i = 0; i < chip9->nr_quads; i++) {
1344 char eq_name[32];
1345 PnvQuad *eq = &chip9->quads[i];
1346 PnvCore *pnv_core = chip->cores[i * 4];
1347 int core_id = CPU_CORE(pnv_core)->core_id;
1348
1349 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1350 object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1351 sizeof(*eq), TYPE_PNV_QUAD,
1352 &error_fatal, NULL);
1353
1354 object_property_set_int(OBJECT(eq), "id", core_id, &error_fatal);
1355 qdev_realize(DEVICE(eq), NULL, &error_fatal);
1356
1357 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id),
1358 &eq->xscom_regs);
1359 }
1360}
1361
1362static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp)
1363{
1364 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1365 int i, j;
1366 int phb_id = 0;
1367
1368 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
1369 PnvPhb4PecState *pec = &chip9->pecs[i];
1370 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1371 uint32_t pec_nest_base;
1372 uint32_t pec_pci_base;
1373
1374 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1375
1376
1377
1378
1379
1380 object_property_set_int(OBJECT(pec), "num-stacks", i + 1,
1381 &error_fatal);
1382 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1383 &error_fatal);
1384 object_property_set_link(OBJECT(pec), "system-memory",
1385 OBJECT(get_system_memory()), &error_abort);
1386 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1387 return;
1388 }
1389
1390 pec_nest_base = pecc->xscom_nest_base(pec);
1391 pec_pci_base = pecc->xscom_pci_base(pec);
1392
1393 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1394 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1395
1396 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs;
1397 j++, phb_id++) {
1398 PnvPhb4PecStack *stack = &pec->stacks[j];
1399 Object *obj = OBJECT(&stack->phb);
1400
1401 object_property_set_int(obj, "index", phb_id, &error_fatal);
1402 object_property_set_int(obj, "chip-id", chip->chip_id,
1403 &error_fatal);
1404 object_property_set_int(obj, "version", PNV_PHB4_VERSION,
1405 &error_fatal);
1406 object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID,
1407 &error_fatal);
1408 object_property_set_link(obj, "stack", OBJECT(stack),
1409 &error_abort);
1410 if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) {
1411 return;
1412 }
1413
1414
1415 pnv_xscom_add_subregion(chip,
1416 pec_nest_base + 0x40 * (stack->stack_no + 1),
1417 &stack->nest_regs_mr);
1418 pnv_xscom_add_subregion(chip,
1419 pec_pci_base + 0x40 * (stack->stack_no + 1),
1420 &stack->pci_regs_mr);
1421 pnv_xscom_add_subregion(chip,
1422 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 +
1423 0x40 * stack->stack_no,
1424 &stack->phb_regs_mr);
1425 }
1426 }
1427}
1428
1429static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1430{
1431 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1432 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1433 PnvChip *chip = PNV_CHIP(dev);
1434 Pnv9Psi *psi9 = &chip9->psi;
1435 Error *local_err = NULL;
1436
1437
1438 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1439 if (local_err) {
1440 error_propagate(errp, local_err);
1441 return;
1442 }
1443 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1444
1445 pcc->parent_realize(dev, &local_err);
1446 if (local_err) {
1447 error_propagate(errp, local_err);
1448 return;
1449 }
1450
1451 pnv_chip_quad_realize(chip9, &local_err);
1452 if (local_err) {
1453 error_propagate(errp, local_err);
1454 return;
1455 }
1456
1457
1458 object_property_set_int(OBJECT(&chip9->xive), "ic-bar",
1459 PNV9_XIVE_IC_BASE(chip), &error_fatal);
1460 object_property_set_int(OBJECT(&chip9->xive), "vc-bar",
1461 PNV9_XIVE_VC_BASE(chip), &error_fatal);
1462 object_property_set_int(OBJECT(&chip9->xive), "pc-bar",
1463 PNV9_XIVE_PC_BASE(chip), &error_fatal);
1464 object_property_set_int(OBJECT(&chip9->xive), "tm-bar",
1465 PNV9_XIVE_TM_BASE(chip), &error_fatal);
1466 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip),
1467 &error_abort);
1468 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) {
1469 return;
1470 }
1471 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1472 &chip9->xive.xscom_regs);
1473
1474
1475 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip),
1476 &error_fatal);
1477 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {
1478 return;
1479 }
1480 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1481 &PNV_PSI(psi9)->xscom_regs);
1482
1483
1484 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi),
1485 &error_abort);
1486 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
1487 return;
1488 }
1489 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1490 &chip9->lpc.xscom_regs);
1491
1492 chip->fw_mr = &chip9->lpc.isa_fw;
1493 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1494 (uint64_t) PNV9_LPCM_BASE(chip));
1495
1496
1497 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi),
1498 &error_abort);
1499 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
1500 return;
1501 }
1502 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1503
1504
1505 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1506 &chip9->occ.sram_regs);
1507
1508
1509 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
1510 &error_abort);
1511 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) {
1512 return;
1513 }
1514
1515 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1516
1517
1518 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1519 &chip9->homer.regs);
1520
1521
1522 pnv_chip_power9_phb_realize(chip, &local_err);
1523 if (local_err) {
1524 error_propagate(errp, local_err);
1525 return;
1526 }
1527}
1528
1529static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1530{
1531 addr &= (PNV9_XSCOM_SIZE - 1);
1532 return addr >> 3;
1533}
1534
1535static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1536{
1537 DeviceClass *dc = DEVICE_CLASS(klass);
1538 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1539
1540 k->chip_cfam_id = 0x220d104900008000ull;
1541 k->cores_mask = POWER9_CORE_MASK;
1542 k->core_pir = pnv_chip_core_pir_p9;
1543 k->intc_create = pnv_chip_power9_intc_create;
1544 k->intc_reset = pnv_chip_power9_intc_reset;
1545 k->intc_destroy = pnv_chip_power9_intc_destroy;
1546 k->intc_print_info = pnv_chip_power9_intc_print_info;
1547 k->isa_create = pnv_chip_power9_isa_create;
1548 k->dt_populate = pnv_chip_power9_dt_populate;
1549 k->pic_print_info = pnv_chip_power9_pic_print_info;
1550 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1551 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1552 dc->desc = "PowerNV Chip POWER9";
1553 k->num_phbs = 6;
1554
1555 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1556 &k->parent_realize);
1557}
1558
1559static void pnv_chip_power10_instance_init(Object *obj)
1560{
1561 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1562
1563 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
1564 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
1565}
1566
1567static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1568{
1569 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1570 PnvChip *chip = PNV_CHIP(dev);
1571 Pnv10Chip *chip10 = PNV10_CHIP(dev);
1572 Error *local_err = NULL;
1573
1574
1575 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1576 if (local_err) {
1577 error_propagate(errp, local_err);
1578 return;
1579 }
1580 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1581
1582 pcc->parent_realize(dev, &local_err);
1583 if (local_err) {
1584 error_propagate(errp, local_err);
1585 return;
1586 }
1587
1588
1589 object_property_set_int(OBJECT(&chip10->psi), "bar",
1590 PNV10_PSIHB_BASE(chip), &error_fatal);
1591 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
1592 return;
1593 }
1594 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1595 &PNV_PSI(&chip10->psi)->xscom_regs);
1596
1597
1598 object_property_set_link(OBJECT(&chip10->lpc), "psi",
1599 OBJECT(&chip10->psi), &error_abort);
1600 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
1601 return;
1602 }
1603 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1604 &chip10->lpc.xscom_regs);
1605
1606 chip->fw_mr = &chip10->lpc.isa_fw;
1607 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1608 (uint64_t) PNV10_LPCM_BASE(chip));
1609}
1610
1611static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1612{
1613 addr &= (PNV10_XSCOM_SIZE - 1);
1614 return addr >> 3;
1615}
1616
1617static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1618{
1619 DeviceClass *dc = DEVICE_CLASS(klass);
1620 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1621
1622 k->chip_cfam_id = 0x120da04900008000ull;
1623 k->cores_mask = POWER10_CORE_MASK;
1624 k->core_pir = pnv_chip_core_pir_p10;
1625 k->intc_create = pnv_chip_power10_intc_create;
1626 k->intc_reset = pnv_chip_power10_intc_reset;
1627 k->intc_destroy = pnv_chip_power10_intc_destroy;
1628 k->intc_print_info = pnv_chip_power10_intc_print_info;
1629 k->isa_create = pnv_chip_power10_isa_create;
1630 k->dt_populate = pnv_chip_power10_dt_populate;
1631 k->pic_print_info = pnv_chip_power10_pic_print_info;
1632 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
1633 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
1634 dc->desc = "PowerNV Chip POWER10";
1635
1636 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1637 &k->parent_realize);
1638}
1639
1640static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1641{
1642 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1643 int cores_max;
1644
1645
1646
1647
1648
1649 if (!chip->cores_mask) {
1650 chip->cores_mask = pcc->cores_mask;
1651 }
1652
1653
1654 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1655 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1656 chip->cores_mask);
1657 return;
1658 }
1659 chip->cores_mask &= pcc->cores_mask;
1660
1661
1662 cores_max = ctpop64(chip->cores_mask);
1663 if (chip->nr_cores > cores_max) {
1664 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1665 cores_max);
1666 return;
1667 }
1668}
1669
1670static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1671{
1672 Error *error = NULL;
1673 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1674 const char *typename = pnv_chip_core_typename(chip);
1675 int i, core_hwid;
1676 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1677
1678 if (!object_class_by_name(typename)) {
1679 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1680 return;
1681 }
1682
1683
1684 pnv_chip_core_sanitize(chip, &error);
1685 if (error) {
1686 error_propagate(errp, error);
1687 return;
1688 }
1689
1690 chip->cores = g_new0(PnvCore *, chip->nr_cores);
1691
1692 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1693 && (i < chip->nr_cores); core_hwid++) {
1694 char core_name[32];
1695 PnvCore *pnv_core;
1696 uint64_t xscom_core_base;
1697
1698 if (!(chip->cores_mask & (1ull << core_hwid))) {
1699 continue;
1700 }
1701
1702 pnv_core = PNV_CORE(object_new(typename));
1703
1704 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1705 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
1706 chip->cores[i] = pnv_core;
1707 object_property_set_int(OBJECT(pnv_core), "nr-threads",
1708 chip->nr_threads, &error_fatal);
1709 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
1710 core_hwid, &error_fatal);
1711 object_property_set_int(OBJECT(pnv_core), "pir",
1712 pcc->core_pir(chip, core_hwid), &error_fatal);
1713 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
1714 &error_fatal);
1715 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
1716 &error_abort);
1717 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
1718
1719
1720 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
1721
1722 pnv_xscom_add_subregion(chip, xscom_core_base,
1723 &pnv_core->xscom_regs);
1724 i++;
1725 }
1726}
1727
1728static void pnv_chip_realize(DeviceState *dev, Error **errp)
1729{
1730 PnvChip *chip = PNV_CHIP(dev);
1731 Error *error = NULL;
1732
1733
1734 pnv_chip_core_realize(chip, &error);
1735 if (error) {
1736 error_propagate(errp, error);
1737 return;
1738 }
1739}
1740
1741static Property pnv_chip_properties[] = {
1742 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1743 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1744 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1745 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1746 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1747 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
1748 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0),
1749 DEFINE_PROP_END_OF_LIST(),
1750};
1751
1752static void pnv_chip_class_init(ObjectClass *klass, void *data)
1753{
1754 DeviceClass *dc = DEVICE_CLASS(klass);
1755
1756 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1757 dc->realize = pnv_chip_realize;
1758 device_class_set_props(dc, pnv_chip_properties);
1759 dc->desc = "PowerNV Chip";
1760}
1761
1762PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
1763{
1764 int i, j;
1765
1766 for (i = 0; i < chip->nr_cores; i++) {
1767 PnvCore *pc = chip->cores[i];
1768 CPUCore *cc = CPU_CORE(pc);
1769
1770 for (j = 0; j < cc->nr_threads; j++) {
1771 if (ppc_cpu_pir(pc->threads[j]) == pir) {
1772 return pc->threads[j];
1773 }
1774 }
1775 }
1776 return NULL;
1777}
1778
1779static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1780{
1781 PnvMachineState *pnv = PNV_MACHINE(xi);
1782 int i, j;
1783
1784 for (i = 0; i < pnv->num_chips; i++) {
1785 PnvChip *chip = pnv->chips[i];
1786 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1787
1788 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1789 return &chip8->psi.ics;
1790 }
1791 for (j = 0; j < chip->num_phbs; j++) {
1792 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) {
1793 return &chip8->phbs[j].lsis;
1794 }
1795 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) {
1796 return ICS(&chip8->phbs[j].msis);
1797 }
1798 }
1799 }
1800 return NULL;
1801}
1802
1803static void pnv_ics_resend(XICSFabric *xi)
1804{
1805 PnvMachineState *pnv = PNV_MACHINE(xi);
1806 int i, j;
1807
1808 for (i = 0; i < pnv->num_chips; i++) {
1809 PnvChip *chip = pnv->chips[i];
1810 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1811
1812 ics_resend(&chip8->psi.ics);
1813 for (j = 0; j < chip->num_phbs; j++) {
1814 ics_resend(&chip8->phbs[j].lsis);
1815 ics_resend(ICS(&chip8->phbs[j].msis));
1816 }
1817 }
1818}
1819
1820static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1821{
1822 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1823
1824 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
1825}
1826
1827static void pnv_pic_print_info(InterruptStatsProvider *obj,
1828 Monitor *mon)
1829{
1830 PnvMachineState *pnv = PNV_MACHINE(obj);
1831 int i;
1832 CPUState *cs;
1833
1834 CPU_FOREACH(cs) {
1835 PowerPCCPU *cpu = POWERPC_CPU(cs);
1836
1837
1838 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
1839 mon);
1840 }
1841
1842 for (i = 0; i < pnv->num_chips; i++) {
1843 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
1844 }
1845}
1846
1847static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
1848 uint8_t nvt_blk, uint32_t nvt_idx,
1849 bool cam_ignore, uint8_t priority,
1850 uint32_t logic_serv,
1851 XiveTCTXMatch *match)
1852{
1853 PnvMachineState *pnv = PNV_MACHINE(xfb);
1854 int total_count = 0;
1855 int i;
1856
1857 for (i = 0; i < pnv->num_chips; i++) {
1858 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
1859 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
1860 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
1861 int count;
1862
1863 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
1864 priority, logic_serv, match);
1865
1866 if (count < 0) {
1867 return count;
1868 }
1869
1870 total_count += count;
1871 }
1872
1873 return total_count;
1874}
1875
1876static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
1877{
1878 MachineClass *mc = MACHINE_CLASS(oc);
1879 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1880 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1881 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
1882
1883 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
1884 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1885
1886 xic->icp_get = pnv_icp_get;
1887 xic->ics_get = pnv_ics_get;
1888 xic->ics_resend = pnv_ics_resend;
1889
1890 pmc->compat = compat;
1891 pmc->compat_size = sizeof(compat);
1892}
1893
1894static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
1895{
1896 MachineClass *mc = MACHINE_CLASS(oc);
1897 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
1898 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1899 static const char compat[] = "qemu,powernv9\0ibm,powernv";
1900
1901 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
1902 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
1903 xfc->match_nvt = pnv_match_nvt;
1904
1905 mc->alias = "powernv";
1906
1907 pmc->compat = compat;
1908 pmc->compat_size = sizeof(compat);
1909 pmc->dt_power_mgt = pnv_dt_power_mgt;
1910}
1911
1912static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
1913{
1914 MachineClass *mc = MACHINE_CLASS(oc);
1915 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1916 static const char compat[] = "qemu,powernv10\0ibm,powernv";
1917
1918 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
1919 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0");
1920
1921 pmc->compat = compat;
1922 pmc->compat_size = sizeof(compat);
1923 pmc->dt_power_mgt = pnv_dt_power_mgt;
1924}
1925
1926static bool pnv_machine_get_hb(Object *obj, Error **errp)
1927{
1928 PnvMachineState *pnv = PNV_MACHINE(obj);
1929
1930 return !!pnv->fw_load_addr;
1931}
1932
1933static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
1934{
1935 PnvMachineState *pnv = PNV_MACHINE(obj);
1936
1937 if (value) {
1938 pnv->fw_load_addr = 0x8000000;
1939 }
1940}
1941
1942static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
1943{
1944 PowerPCCPU *cpu = POWERPC_CPU(cs);
1945 CPUPPCState *env = &cpu->env;
1946
1947 cpu_synchronize_state(cs);
1948 ppc_cpu_do_system_reset(cs);
1949 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
1950
1951
1952
1953
1954
1955 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
1956 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
1957 env->spr[SPR_SRR1] |= SRR1_WAKERESET;
1958 }
1959 } else {
1960
1961
1962
1963
1964
1965
1966
1967 env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
1968 }
1969}
1970
1971static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
1972{
1973 CPUState *cs;
1974
1975 CPU_FOREACH(cs) {
1976 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
1977 }
1978}
1979
1980static void pnv_machine_class_init(ObjectClass *oc, void *data)
1981{
1982 MachineClass *mc = MACHINE_CLASS(oc);
1983 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
1984 NMIClass *nc = NMI_CLASS(oc);
1985
1986 mc->desc = "IBM PowerNV (Non-Virtualized)";
1987 mc->init = pnv_init;
1988 mc->reset = pnv_reset;
1989 mc->max_cpus = MAX_CPUS;
1990
1991 mc->block_default_type = IF_IDE;
1992 mc->no_parallel = 1;
1993 mc->default_boot_order = NULL;
1994
1995
1996
1997
1998 mc->default_ram_size = 1 * GiB;
1999 mc->default_ram_id = "pnv.ram";
2000 ispc->print_info = pnv_pic_print_info;
2001 nc->nmi_monitor_handler = pnv_nmi;
2002
2003 object_class_property_add_bool(oc, "hb-mode",
2004 pnv_machine_get_hb, pnv_machine_set_hb);
2005 object_class_property_set_description(oc, "hb-mode",
2006 "Use a hostboot like boot loader");
2007}
2008
2009#define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2010 { \
2011 .name = type, \
2012 .class_init = class_initfn, \
2013 .parent = TYPE_PNV8_CHIP, \
2014 }
2015
2016#define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2017 { \
2018 .name = type, \
2019 .class_init = class_initfn, \
2020 .parent = TYPE_PNV9_CHIP, \
2021 }
2022
2023#define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2024 { \
2025 .name = type, \
2026 .class_init = class_initfn, \
2027 .parent = TYPE_PNV10_CHIP, \
2028 }
2029
2030static const TypeInfo types[] = {
2031 {
2032 .name = MACHINE_TYPE_NAME("powernv10"),
2033 .parent = TYPE_PNV_MACHINE,
2034 .class_init = pnv_machine_power10_class_init,
2035 },
2036 {
2037 .name = MACHINE_TYPE_NAME("powernv9"),
2038 .parent = TYPE_PNV_MACHINE,
2039 .class_init = pnv_machine_power9_class_init,
2040 .interfaces = (InterfaceInfo[]) {
2041 { TYPE_XIVE_FABRIC },
2042 { },
2043 },
2044 },
2045 {
2046 .name = MACHINE_TYPE_NAME("powernv8"),
2047 .parent = TYPE_PNV_MACHINE,
2048 .class_init = pnv_machine_power8_class_init,
2049 .interfaces = (InterfaceInfo[]) {
2050 { TYPE_XICS_FABRIC },
2051 { },
2052 },
2053 },
2054 {
2055 .name = TYPE_PNV_MACHINE,
2056 .parent = TYPE_MACHINE,
2057 .abstract = true,
2058 .instance_size = sizeof(PnvMachineState),
2059 .class_init = pnv_machine_class_init,
2060 .class_size = sizeof(PnvMachineClass),
2061 .interfaces = (InterfaceInfo[]) {
2062 { TYPE_INTERRUPT_STATS_PROVIDER },
2063 { TYPE_NMI },
2064 { },
2065 },
2066 },
2067 {
2068 .name = TYPE_PNV_CHIP,
2069 .parent = TYPE_SYS_BUS_DEVICE,
2070 .class_init = pnv_chip_class_init,
2071 .instance_size = sizeof(PnvChip),
2072 .class_size = sizeof(PnvChipClass),
2073 .abstract = true,
2074 },
2075
2076
2077
2078
2079 {
2080 .name = TYPE_PNV10_CHIP,
2081 .parent = TYPE_PNV_CHIP,
2082 .instance_init = pnv_chip_power10_instance_init,
2083 .instance_size = sizeof(Pnv10Chip),
2084 },
2085 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2086
2087
2088
2089
2090 {
2091 .name = TYPE_PNV9_CHIP,
2092 .parent = TYPE_PNV_CHIP,
2093 .instance_init = pnv_chip_power9_instance_init,
2094 .instance_size = sizeof(Pnv9Chip),
2095 },
2096 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2097
2098
2099
2100
2101 {
2102 .name = TYPE_PNV8_CHIP,
2103 .parent = TYPE_PNV_CHIP,
2104 .instance_init = pnv_chip_power8_instance_init,
2105 .instance_size = sizeof(Pnv8Chip),
2106 },
2107 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2108 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2109 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2110 pnv_chip_power8nvl_class_init),
2111};
2112
2113DEFINE_TYPES(types)
2114
