LXR qemu/include/hw/misc/xlnx-aes.h

   1/*
   2 * QEMU model of the Xilinx AES
   3 *
   4 * Copyright (c) 2018 Xilinx Inc.
   5 *
   6 * Written by Edgar E. Iglesias <edgari@xilinx.com>
   7 *            Sai Pavan Boddu <saipava@xilinx.com>
   8 *
   9 * Permission is hereby granted, free of charge, to any person obtaining a copy
  10 * of this software and associated documentation files (the "Software"), to deal
  11 * in the Software without restriction, including without limitation the rights
  12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13 * copies of the Software, and to permit persons to whom the Software is
  14 * furnished to do so, subject to the following conditions:
  15 *
  16 * The above copyright notice and this permission notice shall be included in
  17 * all copies or substantial portions of the Software.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25 * THE SOFTWARE.
  26 */
  27#ifndef XLNX_AES_H
  28#define XLNX_AES_H
  29
  30#include "qemu/gcm.h"
  31#include "hw/qdev-core.h"
  32
  33#define TYPE_XLNX_AES "xlnx-aes"
  34
  35enum XlnxAESState {
  36    IDLE,
  37    IV,
  38    AAD,
  39    PAYLOAD,
  40    TAG0,
  41    TAG1,
  42    TAG2,
  43    TAG3
  44};
  45
  46typedef struct XlnxAES {
  47    DeviceState parent_obj;
  48    gcm_context gcm_ctx;
  49    const char *prefix;
  50    qemu_irq s_done;
  51    qemu_irq s_busy;
  52
  53    /* Fields from here to the end will be autoreset to zero at reset. */
  54    enum XlnxAESState state;
  55    bool encrypt;
  56    bool tag_ok;
  57    bool key_zeroed;
  58
  59    /* inp ready not directly derived from state because
  60       we will add delayed inp_ready handling at some point.  */
  61    bool inp_ready;
  62
  63    /* Once ended, aad-feed must end until next start of message */
  64    bool aad_ready;
  65
  66    /* 16-byte packing is needed for stream-push of IV and AAD. */
  67    unsigned pack_next;
  68    union {
  69        uint8_t u8[16];
  70        uint32_t u32[4];
  71    } pack_buf;
  72    uint32_t iv[4];
  73    uint32_t tag[4];
  74    uint32_t key[8];
  75    uint16_t keylen;
  76} XlnxAES;
  77
  78void xlnx_aes_write_key(XlnxAES *s, unsigned int pos, uint32_t val);
  79void xlnx_aes_load_key(XlnxAES *s, int len);
  80void xlnx_aes_key_zero(XlnxAES *s);
  81void xlnx_aes_start_message(XlnxAES *s, bool encrypt);
  82int xlnx_aes_push_data(XlnxAES *s,
  83                       const uint8_t *data8, unsigned len,
  84                       bool is_aad, bool last_word, int lw_len,
  85                       uint8_t *outbuf, int *outlen);
  86uint32_t xlnx_aes_k256_crc(const uint32_t *k256, unsigned zpad_cnt);
  87
  88/*
  89 * Wrap calls with statement expression macros to do build-time
  90 * type-checking 'key' as a 32-byte fixed-length array.
  91 */
  92#define XLNX_AES_K256_TYPE_CHECK(x) \
  93    QEMU_BUILD_BUG_MSG((sizeof(x) != 32 || ARRAY_SIZE(x) != 32), \
  94                       #x " is not a 32-byte array")
  95
  96#define xlnx_aes_k256_get_provided(_O, _ID, _D, _K, _E) ({              \
  97            XLNX_AES_K256_TYPE_CHECK(_K);                               \
  98            xlnx_aes_k256_get_provided_i((_O), (_ID), (_D), (_K), (_E)); \
  99        })
 100
 101int xlnx_aes_k256_get_provided_i(Object *obj, const char *id_prop,
 102                                 const char *default_xd,
 103                                 uint8_t key[32], Error **errp);
 104
 105#define xlnx_aes_k256_swap32(_DK, _SK) ({           \
 106            XLNX_AES_K256_TYPE_CHECK(_DK);          \
 107            XLNX_AES_K256_TYPE_CHECK(_SK);          \
 108            xlnx_aes_k256_swap32_i((_DK), (_SK));   \
 109        })
 110
 111void xlnx_aes_k256_swap32_i(uint8_t dst[32], const uint8_t src[32]);
 112
 113#define xlnx_aes_k256_is_zero(_K) ({                \
 114            XLNX_AES_K256_TYPE_CHECK(_K);           \
 115            xlnx_aes_k256_is_zero_i((_K));          \
 116        })
 117
 118bool xlnx_aes_k256_is_zero_i(const uint8_t key[32]);
 119
 120uint32_t xlnx_calc_crc(const uint32_t *data, unsigned data_length);
 121
 122#endif
 123