qemu/include/hw/misc/xlnx-xppu.h
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   1/*
   2 * QEMU model of the XPPU xppu
   3 *
   4 * Copyright (c) 2020 Xilinx Inc.
   5 *
   6 * Autogenerated by xregqemu.py 2020-01-13.
   7 * Written by Joe Komlodi <komlodi@xilinx.com>
   8 *
   9 * Permission is hereby granted, free of charge, to any person obtaining a copy
  10 * of this software and associated documentation files (the "Software"), to deal
  11 * in the Software without restriction, including without limitation the rights
  12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13 * copies of the Software, and to permit persons to whom the Software is
  14 * furnished to do so, subject to the following conditions:
  15 *
  16 * The above copyright notice and this permission notice shall be included in
  17 * all copies or substantial portions of the Software.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25 * THE SOFTWARE.
  26 */
  27#ifndef XLNX_XPPU_H
  28#define XLNX_XPPU_H
  29
  30#include "hw/register.h"
  31
  32#ifndef XILINX_XPPU_ERR_DEBUG
  33#define XILINX_XPPU_ERR_DEBUG 0
  34#endif
  35
  36/* Registers shared between all XPPUs */
  37REG32(CTRL, 0x0)
  38    FIELD(CTRL, APER_PARITY_EN, 2, 1)
  39    FIELD(CTRL, MID_PARITY_EN, 1, 1)
  40    FIELD(CTRL, ENABLE, 0, 1)
  41REG32(ERR_STATUS1, 0x4)
  42REG32(ERR_STATUS2, 0x8)
  43    FIELD(ERR_STATUS2, AXI_ID, 0, 10)
  44REG32(ISR, 0x10)
  45    FIELD(ISR, APER_PARITY, 7, 1)
  46    FIELD(ISR, APER_TZ, 6, 1)
  47    FIELD(ISR, APER_PERM, 5, 1)
  48    FIELD(ISR, MID_PARITY, 3, 1)
  49    FIELD(ISR, MID_RO, 2, 1)
  50    FIELD(ISR, MID_MISS, 1, 1)
  51    FIELD(ISR, INV_APB, 0, 1)
  52REG32(IMR, 0x14)
  53    FIELD(IMR, APER_PARITY, 7, 1)
  54    FIELD(IMR, APER_TZ, 6, 1)
  55    FIELD(IMR, APER_PERM, 5, 1)
  56    FIELD(IMR, MID_PARITY, 3, 1)
  57    FIELD(IMR, MID_RO, 2, 1)
  58    FIELD(IMR, MID_MISS, 1, 1)
  59    FIELD(IMR, INV_APB, 0, 1)
  60REG32(IEN, 0x18)
  61    FIELD(IEN, APER_PARITY, 7, 1)
  62    FIELD(IEN, APER_TZ, 6, 1)
  63    FIELD(IEN, APER_PERM, 5, 1)
  64    FIELD(IEN, MID_PARITY, 3, 1)
  65    FIELD(IEN, MID_RO, 2, 1)
  66    FIELD(IEN, MID_MISS, 1, 1)
  67    FIELD(IEN, INV_APB, 0, 1)
  68REG32(IDS, 0x1c)
  69    FIELD(IDS, APER_PARITY, 7, 1)
  70    FIELD(IDS, APER_TZ, 6, 1)
  71    FIELD(IDS, APER_PERM, 5, 1)
  72    FIELD(IDS, MID_PARITY, 3, 1)
  73    FIELD(IDS, MID_RO, 2, 1)
  74    FIELD(IDS, MID_MISS, 1, 1)
  75    FIELD(IDS, INV_APB, 0, 1)
  76REG32(M_MASTER_IDS, 0x3c)
  77REG32(M_APERTURE_64KB, 0x44)
  78REG32(M_APERTURE_1MB, 0x48)
  79REG32(M_APERTURE_512MB, 0x4c)
  80REG32(BASE_64KB, 0x54)
  81REG32(BASE_1MB, 0x58)
  82REG32(BASE_512MB, 0x5c)
  83REG32(MASTER_ID00, 0x100)
  84    FIELD(MASTER_ID00, MIDP, 31, 1)
  85    FIELD(MASTER_ID00, MIDR, 30, 1)
  86    FIELD(MASTER_ID00, MIDM, 16, 10)
  87    FIELD(MASTER_ID00, MID, 0, 10)
  88REG32(MASTER_ID01, 0x104)
  89    FIELD(MASTER_ID01, MIDP, 31, 1)
  90    FIELD(MASTER_ID01, MIDR, 30, 1)
  91    FIELD(MASTER_ID01, MIDM, 16, 10)
  92    FIELD(MASTER_ID01, MID, 0, 10)
  93REG32(MASTER_ID02, 0x108)
  94    FIELD(MASTER_ID02, MIDP, 31, 1)
  95    FIELD(MASTER_ID02, MIDR, 30, 1)
  96    FIELD(MASTER_ID02, MIDM, 16, 10)
  97    FIELD(MASTER_ID02, MID, 0, 10)
  98REG32(MASTER_ID03, 0x10c)
  99    FIELD(MASTER_ID03, MIDP, 31, 1)
 100    FIELD(MASTER_ID03, MIDR, 30, 1)
 101    FIELD(MASTER_ID03, MIDM, 16, 10)
 102    FIELD(MASTER_ID03, MID, 0, 10)
 103REG32(MASTER_ID04, 0x110)
 104    FIELD(MASTER_ID04, MIDP, 31, 1)
 105    FIELD(MASTER_ID04, MIDR, 30, 1)
 106    FIELD(MASTER_ID04, MIDM, 16, 10)
 107    FIELD(MASTER_ID04, MID, 0, 10)
 108REG32(MASTER_ID05, 0x114)
 109    FIELD(MASTER_ID05, MIDP, 31, 1)
 110    FIELD(MASTER_ID05, MIDR, 30, 1)
 111    FIELD(MASTER_ID05, MIDM, 16, 10)
 112    FIELD(MASTER_ID05, MID, 0, 10)
 113REG32(MASTER_ID06, 0x118)
 114    FIELD(MASTER_ID06, MIDP, 31, 1)
 115    FIELD(MASTER_ID06, MIDR, 30, 1)
 116    FIELD(MASTER_ID06, MIDM, 16, 10)
 117    FIELD(MASTER_ID06, MID, 0, 10)
 118REG32(MASTER_ID07, 0x11c)
 119    FIELD(MASTER_ID07, MIDP, 31, 1)
 120    FIELD(MASTER_ID07, MIDR, 30, 1)
 121    FIELD(MASTER_ID07, MIDM, 16, 10)
 122    FIELD(MASTER_ID07, MID, 0, 10)
 123REG32(MASTER_ID08, 0x120)
 124    FIELD(MASTER_ID08, MIDP, 31, 1)
 125    FIELD(MASTER_ID08, MIDR, 30, 1)
 126    FIELD(MASTER_ID08, MIDM, 16, 10)
 127    FIELD(MASTER_ID08, MID, 0, 10)
 128REG32(MASTER_ID09, 0x124)
 129    FIELD(MASTER_ID09, MIDP, 31, 1)
 130    FIELD(MASTER_ID09, MIDR, 30, 1)
 131    FIELD(MASTER_ID09, MIDM, 16, 10)
 132    FIELD(MASTER_ID09, MID, 0, 10)
 133REG32(MASTER_ID10, 0x128)
 134    FIELD(MASTER_ID10, MIDP, 31, 1)
 135    FIELD(MASTER_ID10, MIDR, 30, 1)
 136    FIELD(MASTER_ID10, MIDM, 16, 10)
 137    FIELD(MASTER_ID10, MID, 0, 10)
 138REG32(MASTER_ID11, 0x12c)
 139    FIELD(MASTER_ID11, MIDP, 31, 1)
 140    FIELD(MASTER_ID11, MIDR, 30, 1)
 141    FIELD(MASTER_ID11, MIDM, 16, 10)
 142    FIELD(MASTER_ID11, MID, 0, 10)
 143REG32(MASTER_ID12, 0x130)
 144    FIELD(MASTER_ID12, MIDP, 31, 1)
 145    FIELD(MASTER_ID12, MIDR, 30, 1)
 146    FIELD(MASTER_ID12, MIDM, 16, 10)
 147    FIELD(MASTER_ID12, MID, 0, 10)
 148REG32(MASTER_ID13, 0x134)
 149    FIELD(MASTER_ID13, MIDP, 31, 1)
 150    FIELD(MASTER_ID13, MIDR, 30, 1)
 151    FIELD(MASTER_ID13, MIDM, 16, 10)
 152    FIELD(MASTER_ID13, MID, 0, 10)
 153REG32(MASTER_ID14, 0x138)
 154    FIELD(MASTER_ID14, MIDP, 31, 1)
 155    FIELD(MASTER_ID14, MIDR, 30, 1)
 156    FIELD(MASTER_ID14, MIDM, 16, 10)
 157    FIELD(MASTER_ID14, MID, 0, 10)
 158REG32(MASTER_ID15, 0x13c)
 159    FIELD(MASTER_ID15, MIDP, 31, 1)
 160    FIELD(MASTER_ID15, MIDR, 30, 1)
 161    FIELD(MASTER_ID15, MIDM, 16, 10)
 162    FIELD(MASTER_ID15, MID, 0, 10)
 163REG32(MASTER_ID16, 0x140)
 164    FIELD(MASTER_ID16, MIDP, 31, 1)
 165    FIELD(MASTER_ID16, MIDR, 30, 1)
 166    FIELD(MASTER_ID16, MIDM, 16, 10)
 167    FIELD(MASTER_ID16, MID, 0, 10)
 168REG32(MASTER_ID17, 0x144)
 169    FIELD(MASTER_ID17, MIDP, 31, 1)
 170    FIELD(MASTER_ID17, MIDR, 30, 1)
 171    FIELD(MASTER_ID17, MIDM, 16, 10)
 172    FIELD(MASTER_ID17, MID, 0, 10)
 173REG32(MASTER_ID18, 0x148)
 174    FIELD(MASTER_ID18, MIDP, 31, 1)
 175    FIELD(MASTER_ID18, MIDR, 30, 1)
 176    FIELD(MASTER_ID18, MIDM, 16, 10)
 177    FIELD(MASTER_ID18, MID, 0, 10)
 178REG32(MASTER_ID19, 0x14c)
 179    FIELD(MASTER_ID19, MIDP, 31, 1)
 180    FIELD(MASTER_ID19, MIDR, 30, 1)
 181    FIELD(MASTER_ID19, MIDM, 16, 10)
 182    FIELD(MASTER_ID19, MID, 0, 10)
 183
 184#if XILINX_XPPU_ERR_DEBUG
 185#define DPRINTF(fmt, ...) \
 186do { printf(fmt, ## __VA_ARGS__); } while (0)
 187#else
 188#define DPRINTF(fmt, ...) {} while (0)
 189#endif
 190
 191#define XPPU_R_MAX 0x200
 192
 193#define NR_MID_ENTRIES 20
 194
 195#define NR_32B_APL_ENTRIES 128
 196#define NR_64K_APL_ENTRIES 256
 197#define NR_1M_APL_ENTRIES 16
 198#define NR_512M_APL_ENTRIES 1
 199
 200/*
 201 * Even though Versal does not have a 32B aperture, it allocates space for
 202 * it as if it was there.
 203 */
 204#define NR_APL_ENTRIES (NR_32B_APL_ENTRIES + NR_64K_APL_ENTRIES + \
 205                        NR_1M_APL_ENTRIES + NR_512M_APL_ENTRIES)
 206
 207#define PERM_RAM_BASE 0x1000
 208#define PERM_RAM_MAX (PERM_RAM_BASE + ((NR_APL_ENTRIES + 1) * 4))
 209
 210typedef enum {
 211    XPPU_REGION_LPD = 0,
 212    XPPU_REGION_PMC = 1,
 213    XPPU_REGION_PMC_NPI = 2
 214} XPPURegion;
 215
 216typedef enum {
 217    GRANULE_32B,
 218    GRANULE_64K,
 219    GRANULE_1M,
 220    GRANULE_512M,
 221} XPPUGranule;
 222
 223typedef struct {
 224    const XPPUGranule *granules;
 225    const uint64_t *bases;
 226    const uint64_t *masks;
 227    const unsigned int *shifts;
 228    const uint32_t *ram_bases;
 229} XPPUApertureInfo;
 230
 231typedef struct XPPU XPPU;
 232
 233typedef struct XPPUAperture {
 234    XPPU *parent;
 235    MemoryRegion iomem;
 236
 237    XPPUGranule granule;
 238    /* MR base so we can offset the forwarded access.  */
 239    uint64_t base;
 240    /* Mask used to extract parts of the incoming address.  */
 241    uint64_t extract_mask;
 242    uint64_t extract_shift;
 243    /* RAM base. Start of APL tables for this particular Aperture.  */
 244    uint32_t ram_base;
 245} XPPUAperture;
 246
 247struct XPPU {
 248    SysBusDevice parent_obj;
 249    MemoryRegion iomem;
 250    MemoryRegion perm_ram_iomem;
 251    qemu_irq irq_isr;
 252
 253    MemoryRegion *mr;
 254    AddressSpace as;
 255
 256    XPPUAperture *ap;
 257    uint8_t num_ap;
 258
 259    uint32_t perm_ram[NR_APL_ENTRIES];
 260
 261    uint32_t regs[XPPU_R_MAX];
 262    RegisterInfo regs_info[XPPU_R_MAX];
 263    uint8_t region;
 264};
 265
 266bool parity32(uint32_t v);
 267bool check_mid_parity(XPPU *s, uint32_t val32);
 268void check_mid_parities(XPPU *s);
 269bool check_apl_parity(XPPU *s, uint32_t val32);
 270void update_mrs(XPPU *s);
 271bool xppu_ap_check(XPPU *s, MemTxAttrs attr, bool rw, uint32_t apl);
 272void isr_update_irq(XPPU *s);
 273MemTxResult xppu_read_common(void *opaque, XPPU *s, hwaddr addr,
 274                             uint64_t *value, unsigned size, MemTxAttrs attr);
 275MemTxResult xppu_write_common(void *opaque, XPPU *s, hwaddr addr,
 276                              uint64_t value, unsigned size, MemTxAttrs attr);
 277MemTxResult xppu_perm_ram_write_common(XPPU *s, hwaddr addr, uint64_t val,
 278                                       unsigned size, MemTxAttrs attr);
 279MemTxResult xppu_perm_ram_read_common(XPPU *s, hwaddr addr, uint64_t *val,
 280                                      unsigned size, MemTxAttrs attr);
 281bool xppu_parse_reg_common(XPPU *s, const char *tn, FDTGenericRegPropInfo reg,
 282                           FDTGenericMMap *obj, const XPPUApertureInfo *ap_info,
 283                           const MemoryRegionOps *ap_ops, Error **errp);
 284void xppu_init_common(XPPU *s, Object *obj, const char *tn,
 285                      const MemoryRegionOps *ops,
 286                      const MemoryRegionOps *pr_ops,
 287                      const RegisterAccessInfo *regs_info, size_t regs_info_sz);
 288
 289#endif
 290
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.