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29#include "qemu/osdep.h"
30#include "hw/sysbus.h"
31#include "hw/register.h"
32#include "hw/hw.h"
33#include "qemu/bitops.h"
34#include "qemu/log.h"
35#include "qapi/error.h"
36#include "qapi/qmp/qerror.h"
37#include "qemu/error-report.h"
38#include "migration/vmstate.h"
39#include "hw/qdev-properties.h"
40
41#include "hw/stream.h"
42#include "sysemu/dma.h"
43#include "hw/zynqmp_aes_key.h"
44#include "hw/fdt_generic_util.h"
45#include "hw/misc/xlnx-aes.h"
46
47#ifndef XILINX_AES_ERR_DEBUG
48#define XILINX_AES_ERR_DEBUG 0
49#endif
50
51#define TYPE_XILINX_AES "xlnx,versal-aes"
52#define TYPE_XILINX_PMC_KEY_SINK "xlnx.pmc-key-sink"
53
54#define XILINX_AES(obj) \
55 OBJECT_CHECK(Zynq3AES, (obj), TYPE_XILINX_AES)
56
57#define XILINX_PMC_KEY_SINK(obj) \
58 OBJECT_CHECK(PMCKeySink, (obj), TYPE_XILINX_PMC_KEY_SINK)
59
60#define DPRINT(fmt, args...) do { \
61 if (XILINX_AES_ERR_DEBUG) { \
62 qemu_log("%s: " fmt, __func__, ## args);\
63 } \
64 } while (0)
65
66
67enum key_sel {
68 KEY_SEL_BBRAM_KEY = 0xBBDE6600,
69 KEY_SEL_BBRAM_RD_KEY = 0xBBDE8200,
70 KEY_SEL_BH_KEY = 0xBDB06600,
71 KEY_SEL_BH_RD_KEY = 0xBDB08200,
72 KEY_SEL_EFUSE_KEY = 0xEFDE6600,
73 KEY_SEL_EFUSE_RED_KEY = 0xEFDE8200,
74 KEY_SEL_EFUSE_USR_KEY0 = 0xEF856601,
75 KEY_SEL_EFUSE_USR_KEY1 = 0xEF856602,
76 KEY_SEL_EFUSE_USR_RD_KEY0 = 0xEF858201,
77 KEY_SEL_EFUSE_USR_RD_KEY1 = 0xEF858202,
78 KEY_SEL_KUP_KEY = 0xBDC98200,
79 KEY_SEL_FAMILY_KEY = 0xFEDE8200,
80 KEY_SEL_PUF_KEY = 0xDBDE8200,
81 KEY_SEL_USR_KEY_0 = 0xBD858201,
82 KEY_SEL_USR_KEY_1 = 0xBD858202,
83 KEY_SEL_USR_KEY_2 = 0xBD858204,
84 KEY_SEL_USR_KEY_3 = 0xBD858208,
85 KEY_SEL_USR_KEY_4 = 0xBD858210,
86 KEY_SEL_USR_KEY_5 = 0xBD858220,
87 KEY_SEL_USR_KEY_6 = 0xBD858240,
88 KEY_SEL_USR_KEY_7 = 0xBD858280,
89};
90
91REG32(AES_STATUS, 0x0)
92 FIELD(AES_STATUS, CM_ENABLED, 12, 1)
93 FIELD(AES_STATUS, BLACK_KEY_DEC_DONE, 5, 1)
94 FIELD(AES_STATUS, KEY_INIT_DONE, 4, 1)
95 FIELD(AES_STATUS, GCM_TAG_PASS, 3, 1)
96 FIELD(AES_STATUS, DONE, 2, 1)
97 FIELD(AES_STATUS, READY, 1, 1)
98 FIELD(AES_STATUS, BUSY, 0, 1)
99REG32(AES_KEY_SEL, 0x4)
100REG32(AES_KEY_LOAD, 0x8)
101 FIELD(AES_KEY_LOAD, VAL, 0, 1)
102REG32(AES_START_MSG, 0xc)
103 FIELD(AES_START_MSG, VAL, 0, 1)
104REG32(AES_SOFT_RST, 0x10)
105 FIELD(AES_SOFT_RST, VAL, 0, 1)
106REG32(AES_KEY_CLEAR, 0x14)
107 FIELD(AES_KEY_CLEAR, RESERVED_2, 22, 10)
108 FIELD(AES_KEY_CLEAR, PUF_KEY, 21, 1)
109 FIELD(AES_KEY_CLEAR, BBRAM_RED_KEY, 20, 1)
110 FIELD(AES_KEY_CLEAR, BH_RED_KEY, 19, 1)
111 FIELD(AES_KEY_CLEAR, BH_KEY, 18, 1)
112 FIELD(AES_KEY_CLEAR, EFUSE_USER_RED_KEY_1, 17, 1)
113 FIELD(AES_KEY_CLEAR, EFUSE_USER_RED_KEY_0, 16, 1)
114 FIELD(AES_KEY_CLEAR, EFUSE_RED_KEY, 15, 1)
115 FIELD(AES_KEY_CLEAR, EFUSE_USER_KEY_1, 14, 1)
116 FIELD(AES_KEY_CLEAR, EFUSE_USER_KEY_0, 13, 1)
117 FIELD(AES_KEY_CLEAR, EFUSE_KEY, 12, 1)
118 FIELD(AES_KEY_CLEAR, USER_KEY_7, 11, 1)
119 FIELD(AES_KEY_CLEAR, USER_KEY_6, 10, 1)
120 FIELD(AES_KEY_CLEAR, USER_KEY_5, 9, 1)
121 FIELD(AES_KEY_CLEAR, USER_KEY_4, 8, 1)
122 FIELD(AES_KEY_CLEAR, USER_KEY_3, 7, 1)
123 FIELD(AES_KEY_CLEAR, USER_KEY_2, 6, 1)
124 FIELD(AES_KEY_CLEAR, USER_KEY_1, 5, 1)
125 FIELD(AES_KEY_CLEAR, USER_KEY_0, 4, 1)
126 FIELD(AES_KEY_CLEAR, RESERVED_1, 2, 2)
127 FIELD(AES_KEY_CLEAR, KUP_KEY, 1, 1)
128 FIELD(AES_KEY_CLEAR, AES_KEY_ZEROIZE, 0, 1)
129REG32(AES_MODE, 0x18)
130 FIELD(AES_MODE, ENC_DEC_N, 0, 1)
131REG32(AES_KUP_WR, 0x1c)
132 FIELD(AES_KUP_WR, IV_SAVE, 1, 1)
133 FIELD(AES_KUP_WR, KEY_SAVE, 0, 1)
134REG32(AES_IV_0, 0x40)
135REG32(AES_IV_1, 0x44)
136REG32(AES_IV_2, 0x48)
137REG32(AES_IV_3, 0x4c)
138REG32(AES_KEY_SIZE, 0x50)
139 FIELD(AES_KEY_SIZE, VAL, 0, 2)
140REG32(AES_KEY_DEC, 0x58)
141REG32(KEY_DEC_TRIG, 0x5c)
142 FIELD(KEY_DEC_TRIG, VAL, 0, 1)
143REG32(KEY_DEC_SEL, 0x60)
144 FIELD(KEY_DEC_SEL, VAL, 0, 3)
145REG32(KEY_ZEROED_STATUS, 0x64)
146 FIELD(KEY_ZEROED_STATUS, RESERVED_2, 22, 10)
147 FIELD(KEY_ZEROED_STATUS, PUF_KEY, 21, 1)
148 FIELD(KEY_ZEROED_STATUS, BBRAM_RED_KEY, 20, 1)
149 FIELD(KEY_ZEROED_STATUS, BH_RED_KEY, 19, 1)
150 FIELD(KEY_ZEROED_STATUS, BH_KEY, 18, 1)
151 FIELD(KEY_ZEROED_STATUS, EFUSE_USER_RED_KEY_1, 17, 1)
152 FIELD(KEY_ZEROED_STATUS, EFUSE_USER_RED_KEY_0, 16, 1)
153 FIELD(KEY_ZEROED_STATUS, EFUSE_RED_KEY, 15, 1)
154 FIELD(KEY_ZEROED_STATUS, EFUSE_USER_KEY_1, 14, 1)
155 FIELD(KEY_ZEROED_STATUS, EFUSE_USER_KEY_0, 13, 1)
156 FIELD(KEY_ZEROED_STATUS, EFUSE_KEY, 12, 1)
157 FIELD(KEY_ZEROED_STATUS, USER_KEY_7, 11, 1)
158 FIELD(KEY_ZEROED_STATUS, USER_KEY_6, 10, 1)
159 FIELD(KEY_ZEROED_STATUS, USER_KEY_5, 9, 1)
160 FIELD(KEY_ZEROED_STATUS, USER_KEY_4, 8, 1)
161 FIELD(KEY_ZEROED_STATUS, USER_KEY_3, 7, 1)
162 FIELD(KEY_ZEROED_STATUS, USER_KEY_2, 6, 1)
163 FIELD(KEY_ZEROED_STATUS, USER_KEY_1, 5, 1)
164 FIELD(KEY_ZEROED_STATUS, USER_KEY_0, 4, 1)
165 FIELD(KEY_ZEROED_STATUS, RESERVED_1, 2, 2)
166 FIELD(KEY_ZEROED_STATUS, KUP_KEY, 1, 1)
167 FIELD(KEY_ZEROED_STATUS, AES_KEY_ZEROED, 0, 1)
168REG32(AES_KEY_LOCK_STATUS, 0x68)
169 FIELD(AES_KEY_LOCK_STATUS, BBRAM, 1, 1)
170 FIELD(AES_KEY_LOCK_STATUS, EFUSE, 0, 1)
171REG32(AES_AAD, 0x6c)
172 FIELD(AES_AAD, HDR_PAYLOAD_N, 0, 1)
173REG32(AES_USER_SEL, 0x70)
174 FIELD(AES_USER_SEL, VAL, 0, 3)
175REG32(AES_USER_KEY_CRC, 0x74)
176REG32(AES_USER_KEY_CRC_STATUS, 0x78)
177 FIELD(AES_USER_KEY_CRC_STATUS, DONE, 1, 1)
178 FIELD(AES_USER_KEY_CRC_STATUS, PASS, 0, 1)
179REG32(AES_CM_EN, 0x7c)
180 FIELD(AES_CM_EN, VAL, 0, 1)
181REG32(AES_SPLIT_CFG, 0x80)
182 FIELD(AES_SPLIT_CFG, KEY_SPLIT, 1, 1)
183 FIELD(AES_SPLIT_CFG, DATA_SPLIT, 0, 1)
184REG32(AES_DATA_ENDIANNESS_SWAP, 0x84)
185 FIELD(AES_DATA_ENDIANNESS_SWAP, VAL, 0, 1)
186REG32(BH_KEY_0, 0xf0)
187REG32(BH_KEY_1, 0xf4)
188REG32(BH_KEY_2, 0xf8)
189REG32(BH_KEY_3, 0xfc)
190REG32(BH_KEY_4, 0x100)
191REG32(BH_KEY_5, 0x104)
192REG32(BH_KEY_6, 0x108)
193REG32(BH_KEY_7, 0x10c)
194REG32(USER_KEY_0_0, 0x110)
195REG32(USER_KEY_0_1, 0x114)
196REG32(USER_KEY_0_2, 0x118)
197REG32(USER_KEY_0_3, 0x11c)
198REG32(USER_KEY_0_4, 0x120)
199REG32(USER_KEY_0_5, 0x124)
200REG32(USER_KEY_0_6, 0x128)
201REG32(USER_KEY_0_7, 0x12c)
202REG32(USER_KEY_1_0, 0x130)
203REG32(USER_KEY_1_1, 0x134)
204REG32(USER_KEY_1_2, 0x138)
205REG32(USER_KEY_1_3, 0x13c)
206REG32(USER_KEY_1_4, 0x140)
207REG32(USER_KEY_1_5, 0x144)
208REG32(USER_KEY_1_6, 0x148)
209REG32(USER_KEY_1_7, 0x14c)
210REG32(USER_KEY_2_0, 0x150)
211REG32(USER_KEY_2_1, 0x154)
212REG32(USER_KEY_2_2, 0x158)
213REG32(USER_KEY_2_3, 0x15c)
214REG32(USER_KEY_2_4, 0x160)
215REG32(USER_KEY_2_5, 0x164)
216REG32(USER_KEY_2_6, 0x168)
217REG32(USER_KEY_2_7, 0x16c)
218REG32(USER_KEY_3_0, 0x170)
219REG32(USER_KEY_3_1, 0x174)
220REG32(USER_KEY_3_2, 0x178)
221REG32(USER_KEY_3_3, 0x17c)
222REG32(USER_KEY_3_4, 0x180)
223REG32(USER_KEY_3_5, 0x184)
224REG32(USER_KEY_3_6, 0x188)
225REG32(USER_KEY_3_7, 0x18c)
226REG32(USER_KEY_4_0, 0x190)
227REG32(USER_KEY_4_1, 0x194)
228REG32(USER_KEY_4_2, 0x198)
229REG32(USER_KEY_4_3, 0x19c)
230REG32(USER_KEY_4_4, 0x1a0)
231REG32(USER_KEY_4_5, 0x1a4)
232REG32(USER_KEY_4_6, 0x1a8)
233REG32(USER_KEY_4_7, 0x1ac)
234REG32(USER_KEY_5_0, 0x1b0)
235REG32(USER_KEY_5_1, 0x1b4)
236REG32(USER_KEY_5_2, 0x1b8)
237REG32(USER_KEY_5_3, 0x1bc)
238REG32(USER_KEY_5_4, 0x1c0)
239REG32(USER_KEY_5_5, 0x1c4)
240REG32(USER_KEY_5_6, 0x1c8)
241REG32(USER_KEY_5_7, 0x1cc)
242REG32(USER_KEY_6_0, 0x1d0)
243REG32(USER_KEY_6_1, 0x1d4)
244REG32(USER_KEY_6_2, 0x1d8)
245REG32(USER_KEY_6_3, 0x1dc)
246REG32(USER_KEY_6_4, 0x1e0)
247REG32(USER_KEY_6_5, 0x1e4)
248REG32(USER_KEY_6_6, 0x1e8)
249REG32(USER_KEY_6_7, 0x1ec)
250REG32(USER_KEY_7_0, 0x1f0)
251REG32(USER_KEY_7_1, 0x1f4)
252REG32(USER_KEY_7_2, 0x1f8)
253REG32(USER_KEY_7_3, 0x1fc)
254REG32(USER_KEY_7_4, 0x200)
255REG32(USER_KEY_7_5, 0x204)
256REG32(USER_KEY_7_6, 0x208)
257REG32(USER_KEY_7_7, 0x20c)
258REG32(AES_ISR, 0x214)
259 FIELD(AES_ISR, SLVERR, 2, 1)
260 FIELD(AES_ISR, ENCDEC_ERR, 1, 1)
261 FIELD(AES_ISR, DONE, 0, 1)
262REG32(AES_IMR, 0x218)
263 FIELD(AES_IMR, SLVERR, 2, 1)
264 FIELD(AES_IMR, ENCDEC_ERR, 1, 1)
265 FIELD(AES_IMR, DONE, 0, 1)
266REG32(AES_IER, 0x21c)
267 FIELD(AES_IER, SLVERR, 2, 1)
268 FIELD(AES_IER, ENCDEC_ERR, 1, 1)
269 FIELD(AES_IER, DONE, 0, 1)
270REG32(AES_IDR, 0x220)
271 FIELD(AES_IDR, SLVERR, 2, 1)
272 FIELD(AES_IDR, ENCDEC_ERR, 1, 1)
273 FIELD(AES_IDR, DONE, 0, 1)
274
275#define R_MAX (R_AES_IDR + 1)
276
277typedef struct Zynq3AES Zynq3AES;
278
279typedef struct PMCKeySink {
280 Object parent;
281 Zynq3AES *tmr;
282
283 uint8_t key[256 / 8];
284} PMCKeySink;
285
286struct Zynq3AES {
287 SysBusDevice parent_obj;
288 MemoryRegion iomem;
289 qemu_irq irq_aes_imr;
290 bool aes_busy;
291 bool aes_done;
292 bool key_dec_done;
293 bool inSoftRst;
294
295 StreamSink *tx_dev;
296 char *family_key_id;
297 char *puf_key_id;
298
299 uint32_t regs[R_MAX];
300 RegisterInfo regs_info[R_MAX];
301
302 qemu_irq aes_rst;
303 XlnxAES *aes;
304 uint32_t device_key[8];
305 bool key_loaded;
306
307 PMCKeySink bbram_key;
308 PMCKeySink bbram_key_red;
309
310 PMCKeySink bh_key_red;
311
312 PMCKeySink efuse_key;
313 PMCKeySink efuse_key_red;
314
315 PMCKeySink efuse_user_key[2];
316 PMCKeySink efuse_user_key_red[2];
317
318 PMCKeySink puf_key;
319 PMCKeySink family_key;
320
321 PMCKeySink kup_key;
322
323 uint8_t *bh_key;
324 uint8_t *user_key[8];
325 bool user_key_lock_status[8];
326
327 ZynqMPAESKeySink *key_sync;
328 struct {
329 uint32_t key[256 / 32];
330 uint32_t iv[128 / 32];
331 } feedback;
332
333
334 const char *prefix;
335
336
337 uint8_t gcm_tag[16];
338 uint8_t gcm_pos;
339 uint8_t gcm_len;
340 bool gcm_push_eop;
341};
342
343static void bswap32_buf8(uint8_t *buf, int len)
344{
345 int i;
346
347 assert((len & 3) == 0);
348 for (i = 0; i < len; i += 4) {
349 uint8_t v[4];
350
351 v[0] = buf[i];
352 v[1] = buf[i + 1];
353 v[2] = buf[i + 2];
354 v[3] = buf[i + 3];
355 buf[i] = v[3];
356 buf[i + 1] = v[2];
357 buf[i + 2] = v[1];
358 buf[i + 3] = v[0];
359 }
360}
361
362static void wswap128_buf8(uint8_t *buf, int len)
363{
364 int i, j, copyl;
365 int wlen = len / 4;
366 uint32_t *buf32 = (uint32_t *) buf;
367 for (i = 0; i < wlen; i += 4) {
368 uint32_t v[4] = {0};
369
370 copyl = (i + 4 <= wlen) ? 4 : wlen - i;
371
372 memcpy(v, &buf32[i], copyl * 4);
373 for (j = 0; j < copyl; j++) {
374 buf32[i + j] = v[copyl - 1 - j];
375 }
376 }
377}
378
379static int aes_key_size(Zynq3AES *s)
380{
381 return s->regs[R_AES_KEY_SIZE] == 0 ? 128 : 256;
382}
383
384static void pmc_key_sink_update(ZynqMPAESKeySink *obj, uint8_t *key,
385 size_t len)
386{
387 PMCKeySink *ks = XILINX_PMC_KEY_SINK(obj);
388
389 assert(len == 256 / 8);
390
391 memcpy(ks->key, key, len);
392}
393
394static void aes_imr_update_irq(Zynq3AES *s)
395{
396 bool pending = s->regs[R_AES_ISR] & ~s->regs[R_AES_IMR];
397 qemu_set_irq(s->irq_aes_imr, pending);
398}
399
400static void aes_isr_postw(RegisterInfo *reg, uint64_t val64)
401{
402 Zynq3AES *s = XILINX_AES(reg->opaque);
403 aes_imr_update_irq(s);
404}
405
406static uint64_t aes_ier_prew(RegisterInfo *reg, uint64_t val64)
407{
408 Zynq3AES *s = XILINX_AES(reg->opaque);
409 uint32_t val = val64;
410
411 s->regs[R_AES_IMR] &= ~val;
412 aes_imr_update_irq(s);
413 return 0;
414}
415
416static uint64_t aes_idr_prew(RegisterInfo *reg, uint64_t val64)
417{
418 Zynq3AES *s = XILINX_AES(reg->opaque);
419 uint32_t val = val64;
420
421 s->regs[R_AES_IMR] |= val;
422 aes_imr_update_irq(s);
423 return 0;
424}
425
426static int xlx_aes_push_data(Zynq3AES *s,
427 uint8_t *data8x, int len,
428 bool last_word , int lw_len,
429 uint8_t *outbuf, int *outlen);
430static void xlx_aes_load_key(Zynq3AES *s, int len)
431{
432 unsigned int src, i;
433 bool efuse_locked = ARRAY_FIELD_EX32(s->regs, AES_KEY_LOCK_STATUS, EFUSE);
434 bool bbram_locked = ARRAY_FIELD_EX32(s->regs, AES_KEY_LOCK_STATUS, BBRAM);
435 typedef union AESKey {
436 uint8_t *u8;
437 uint32_t *u32;
438 } AESKey;
439
440 AESKey key = { .u8 = 0 };
441 uint8_t zerokey[32] = { 0 };
442 int be_adj = 7;
443
444 src = s->regs[R_AES_KEY_SEL];
445
446 switch (src) {
447 case KEY_SEL_EFUSE_KEY:
448 key.u8 = efuse_locked ? zerokey : s->efuse_key.key;
449 be_adj = 0;
450 break;
451 case KEY_SEL_EFUSE_RED_KEY:
452 key.u8 = s->efuse_key_red.key;
453 break;
454 case KEY_SEL_EFUSE_USR_KEY0:
455 key.u8 = efuse_locked ? zerokey : s->efuse_user_key[0].key;
456 break;
457 case KEY_SEL_EFUSE_USR_KEY1:
458 key.u8 = efuse_locked ? zerokey : s->efuse_user_key[1].key;
459 break;
460 case KEY_SEL_EFUSE_USR_RD_KEY0:
461 key.u8 = s->efuse_user_key_red[0].key;
462 break;
463 case KEY_SEL_EFUSE_USR_RD_KEY1:
464 key.u8 = s->efuse_user_key_red[1].key;
465 break;
466 case KEY_SEL_BBRAM_KEY:
467 key.u8 = bbram_locked ? zerokey : s->bbram_key.key;
468 be_adj = 0;
469 break;
470 case KEY_SEL_BBRAM_RD_KEY:
471 key.u8 = s->bbram_key_red.key;
472 break;
473 case KEY_SEL_PUF_KEY:
474 key.u8 = s->puf_key.key;
475 be_adj = 0;
476 break;
477 case KEY_SEL_KUP_KEY:
478 key.u8 = s->kup_key.key;
479 break;
480 case KEY_SEL_USR_KEY_0:
481 key.u8 = s->user_key[0];
482 break;
483 case KEY_SEL_USR_KEY_1:
484 key.u8 = s->user_key[1];
485 break;
486 case KEY_SEL_USR_KEY_2:
487 key.u8 = s->user_key[2];
488 break;
489 case KEY_SEL_USR_KEY_3:
490 key.u8 = s->user_key[3];
491 break;
492 case KEY_SEL_USR_KEY_4:
493 key.u8 = s->user_key[4];
494 break;
495 case KEY_SEL_USR_KEY_5:
496 key.u8 = s->user_key[5];
497 break;
498 case KEY_SEL_USR_KEY_6:
499 key.u8 = s->user_key[6];
500 break;
501 case KEY_SEL_USR_KEY_7:
502 key.u8 = s->user_key[7];
503 break;
504 case KEY_SEL_BH_KEY:
505 key.u8 = s->bh_key;
506 break;
507 case KEY_SEL_BH_RD_KEY:
508 key.u8 = s->bh_key_red.key;
509 break;
510 case KEY_SEL_FAMILY_KEY:
511 if (xlnx_aes_k256_is_zero(s->family_key.key)) {
512 hw_error("%s: AES Key source FAMILY_KEY: key value missing.\n",
513 s->prefix);
514 }
515 key.u8 = s->family_key.key;
516 be_adj = 0;
517 break;
518 default:
519 hw_error("%s: Unsupported AES Key source %d\n", s->prefix, src);
520 break;
521 }
522
523 if (s->regs[R_AES_KEY_DEC] != 0xFFFFFFFF) {
524
525
526
527
528
529 for (i = 0; i < 8; i++) {
530 xlnx_aes_write_key(s->aes, i , key.u32[i ^ be_adj]);
531 }
532 xlnx_aes_load_key(s->aes, len);
533 } else {
534 AESKey dec_key;
535 uint32_t *enc_key = g_new0(uint32_t, 8);
536 uint8_t *outbuf = g_new0(uint8_t, 32 + 16);
537 uint32_t *outbuf32 = (uint32_t *) outbuf;
538 int outlen = 0;
539
540 switch (s->regs[R_KEY_DEC_SEL]) {
541 case 0:
542 dec_key.u8 = s->bbram_key_red.key;
543 break;
544 case 1:
545 dec_key.u8 = s->bh_key_red.key;
546 break;
547 case 2:
548 dec_key.u8 = s->efuse_key_red.key;
549 break;
550 case 3:
551 dec_key.u8 = s->efuse_user_key_red[0].key;
552 break;
553 case 4:
554 dec_key.u8 = s->efuse_user_key_red[1].key;
555 break;
556 default:
557 DPRINT("Invalid KEY_DEC_SEL\n");
558 dec_key.u8 = zerokey;
559 };
560 memcpy(enc_key, key.u8, len / 8);
561
562
563
564 bswap32_buf8((uint8_t *)enc_key, len / 8);
565 wswap128_buf8((uint8_t *)enc_key, len / 8);
566 xlx_aes_push_data(s, (uint8_t *)enc_key, len / 8, true, 4, outbuf,
567 &outlen);
568
569 bswap32_buf8(outbuf, len / 8);
570 for (i = 0; i < len / 32; i++) {
571 dec_key.u32[i] = outbuf32[len / 32 - i - 1];
572 }
573 DPRINT("Key Decrypt Done!\n");
574 s->key_dec_done = true;
575 qemu_irq_pulse(s->aes_rst);
576 g_free(outbuf);
577 g_free(enc_key);
578 }
579 s->key_loaded = true;
580}
581
582
583static void aes_key_load_postw(RegisterInfo *reg, uint64_t val)
584{
585 Zynq3AES *s = XILINX_AES(reg->opaque);
586 if (val) {
587 xlx_aes_load_key(s, aes_key_size(s));
588 }
589}
590
591static void aes_start_msg_postw(RegisterInfo *reg, uint64_t val)
592{
593 Zynq3AES *s = XILINX_AES(reg->opaque);
594 if (val) {
595 s->gcm_len = 0;
596 xlnx_aes_start_message(s->aes,
597 s->regs[R_AES_MODE] & R_AES_MODE_ENC_DEC_N_MASK);
598 }
599}
600
601static void aes_reset(DeviceState *dev);
602static void aes_soft_rst_postw(RegisterInfo *reg, uint64_t val)
603{
604 Zynq3AES *s = XILINX_AES(reg->opaque);
605 if (val && !s->inSoftRst) {
606 qemu_irq_pulse(s->aes_rst);
607 s->inSoftRst = true;
608 aes_reset(DEVICE(s));
609 }
610}
611
612static void aes_key_clear_postw(RegisterInfo *reg, uint64_t val)
613{
614 Zynq3AES *s = XILINX_AES(reg->opaque);
615 unsigned int i;
616 uint8_t *key = 0;
617
618 for (i = 0; val && (i < R_AES_KEY_CLEAR_RESERVED_2_SHIFT); i++) {
619 if (!(val & (1 << i))) {
620 continue;
621 }
622
623 switch (1 << i) {
624 case R_AES_KEY_CLEAR_AES_KEY_ZEROIZE_MASK:
625 xlnx_aes_key_zero(s->aes);
626 break;
627 case R_AES_KEY_CLEAR_KUP_KEY_MASK:
628 key = &s->kup_key.key[0];
629 break;
630 case R_AES_KEY_CLEAR_USER_KEY_0_MASK ...
631 R_AES_KEY_CLEAR_USER_KEY_1_MASK:
632 key = s->user_key[i - R_AES_KEY_CLEAR_USER_KEY_0_SHIFT];
633 break;
634 case R_AES_KEY_CLEAR_EFUSE_KEY_MASK:
635 key = &s->efuse_key.key[0];
636 break;
637 case R_AES_KEY_CLEAR_EFUSE_USER_KEY_0_MASK:
638 case R_AES_KEY_CLEAR_EFUSE_USER_KEY_1_MASK:
639 key = &s->efuse_user_key[i -
640 R_AES_KEY_CLEAR_EFUSE_USER_KEY_0_SHIFT].key[0];
641 break;
642 case R_AES_KEY_CLEAR_EFUSE_RED_KEY_MASK:
643 key = &s->efuse_key_red.key[0];
644 break;
645 case R_AES_KEY_CLEAR_EFUSE_USER_RED_KEY_0_MASK:
646 case R_AES_KEY_CLEAR_EFUSE_USER_RED_KEY_1_MASK:
647 key = &s->efuse_user_key[i -
648 R_AES_KEY_CLEAR_EFUSE_USER_KEY_0_SHIFT].key[0];
649 break;
650 case R_AES_KEY_CLEAR_BH_KEY_MASK:
651 key = s->bh_key;
652 break;
653 case R_AES_KEY_CLEAR_BH_RED_KEY_MASK:
654 key = &s->bh_key_red.key[0];
655 break;
656 case R_AES_KEY_CLEAR_PUF_KEY_MASK:
657 key = &s->puf_key.key[0];
658 break;
659 case R_AES_KEY_CLEAR_BBRAM_RED_KEY_MASK:
660 key = &s->bbram_key_red.key[0];
661 break;
662 default:
663 continue;
664 };
665
666 if (key) {
667 memset(key, 0, 8 * 4);
668 }
669
670 val &= ~(1 << i);
671 s->regs[R_KEY_ZEROED_STATUS] |= 1 << i;
672 }
673}
674
675static uint64_t aes_status_postr(RegisterInfo *reg, uint64_t val)
676{
677 Zynq3AES *s = XILINX_AES(reg->opaque);
678 uint32_t v = 0;
679 v |= s->regs[R_AES_CM_EN] ? R_AES_STATUS_CM_ENABLED_MASK : 0;
680 v |= s->key_dec_done ? R_AES_STATUS_BLACK_KEY_DEC_DONE_MASK : 0 ;
681 v |= s->key_loaded ? R_AES_STATUS_KEY_INIT_DONE_MASK : 0;
682 v |= s->aes->tag_ok ? R_AES_STATUS_GCM_TAG_PASS_MASK : 0;
683 v |= s->aes_done ? R_AES_STATUS_DONE_MASK : 0;
684 v |= s->aes->inp_ready ? R_AES_STATUS_READY_MASK : 0;
685 v |= s->aes_busy ? R_AES_STATUS_BUSY_MASK : 0;
686 return v;
687}
688
689static void key_dec_trig_postw(RegisterInfo *reg, uint64_t val)
690{
691 Zynq3AES *s = XILINX_AES(reg->opaque);
692
693 if (val & R_KEY_DEC_TRIG_VAL_MASK) {
694 if (s->regs[R_AES_KEY_DEC] == 0xFFFFFFFF) {
695 DPRINT("Start Key Decrypt..\n");
696 xlx_aes_load_key(s, aes_key_size(s));
697 } else {
698 qemu_log_mask(LOG_GUEST_ERROR, "Key Decrypt triggred before "
699 "AES_KEY_DEC is programmed\n");
700 }
701 }
702}
703
704static RegisterAccessInfo aes_regs_info[] = {
705 { .name = "AES_STATUS", .addr = A_AES_STATUS,
706 .post_read = aes_status_postr,
707 .rsvd = 0xfc0,
708 .ro = 0x1fff,
709 },{ .name = "AES_KEY_SEL", .addr = A_AES_KEY_SEL,
710 },{ .name = "AES_KEY_LOAD", .addr = A_AES_KEY_LOAD,
711 .post_write = aes_key_load_postw,
712 },{ .name = "AES_START_MSG", .addr = A_AES_START_MSG,
713 .post_write = aes_start_msg_postw,
714 },{ .name = "AES_SOFT_RST", .addr = A_AES_SOFT_RST,
715 .post_write = aes_soft_rst_postw,
716 .reset = 0x1,
717 },{ .name = "AES_KEY_CLEAR", .addr = A_AES_KEY_CLEAR,
718 .post_write = aes_key_clear_postw,
719 },{ .name = "AES_MODE", .addr = A_AES_MODE,
720 },{ .name = "AES_KUP_WR", .addr = A_AES_KUP_WR,
721 },{ .name = "AES_IV_0", .addr = A_AES_IV_0,
722 .ro = 0xffffffff,
723 },{ .name = "AES_IV_1", .addr = A_AES_IV_1,
724 .ro = 0xffffffff,
725 },{ .name = "AES_IV_2", .addr = A_AES_IV_2,
726 .ro = 0xffffffff,
727 },{ .name = "AES_IV_3", .addr = A_AES_IV_3,
728 .ro = 0xffffffff,
729 },{ .name = "AES_KEY_SIZE", .addr = A_AES_KEY_SIZE,
730 .reset = 0x2,
731 },{ .name = "AES_KEY_DEC", .addr = A_AES_KEY_DEC,
732 },{ .name = "KEY_DEC_TRIG", .addr = A_KEY_DEC_TRIG,
733 .post_write = key_dec_trig_postw,
734 },{ .name = "KEY_DEC_SEL", .addr = A_KEY_DEC_SEL,
735 },{ .name = "KEY_ZEROED_STATUS", .addr = A_KEY_ZEROED_STATUS,
736 .ro = 0xffffffff,
737 },{ .name = "AES_KEY_LOCK_STATUS", .addr = A_AES_KEY_LOCK_STATUS,
738 .ro = 0x3,
739
740 },{ .name = "AES_AAD", .addr = A_AES_AAD,
741 },{ .name = "AES_USER_SEL", .addr = A_AES_USER_SEL,
742 },{ .name = "AES_USER_KEY_CRC", .addr = A_AES_USER_KEY_CRC,
743 },{ .name = "AES_USER_KEY_CRC_STATUS", .addr = A_AES_USER_KEY_CRC_STATUS,
744 .ro = 0x3,
745 },{ .name = "AES_CM_EN", .addr = A_AES_CM_EN,
746 .reset = 0x1,
747 },{ .name = "AES_SPLIT_CFG", .addr = A_AES_SPLIT_CFG,
748 },{ .name = "AES_DATA_ENDIANNESS_SWAP", .addr = A_AES_DATA_ENDIANNESS_SWAP,
749 },{ .name = "BH_KEY_0", .addr = A_BH_KEY_0,
750 },{ .name = "BH_KEY_1", .addr = A_BH_KEY_1,
751 },{ .name = "BH_KEY_2", .addr = A_BH_KEY_2,
752 },{ .name = "BH_KEY_3", .addr = A_BH_KEY_3,
753 },{ .name = "BH_KEY_4", .addr = A_BH_KEY_4,
754 },{ .name = "BH_KEY_5", .addr = A_BH_KEY_5,
755 },{ .name = "BH_KEY_6", .addr = A_BH_KEY_6,
756 },{ .name = "BH_KEY_7", .addr = A_BH_KEY_7,
757 },{ .name = "USER_KEY_0_0", .addr = A_USER_KEY_0_0,
758 },{ .name = "USER_KEY_0_1", .addr = A_USER_KEY_0_1,
759 },{ .name = "USER_KEY_0_2", .addr = A_USER_KEY_0_2,
760 },{ .name = "USER_KEY_0_3", .addr = A_USER_KEY_0_3,
761 },{ .name = "USER_KEY_0_4", .addr = A_USER_KEY_0_4,
762 },{ .name = "USER_KEY_0_5", .addr = A_USER_KEY_0_5,
763 },{ .name = "USER_KEY_0_6", .addr = A_USER_KEY_0_6,
764 },{ .name = "USER_KEY_0_7", .addr = A_USER_KEY_0_7,
765 },{ .name = "USER_KEY_1_0", .addr = A_USER_KEY_1_0,
766 },{ .name = "USER_KEY_1_1", .addr = A_USER_KEY_1_1,
767 },{ .name = "USER_KEY_1_2", .addr = A_USER_KEY_1_2,
768 },{ .name = "USER_KEY_1_3", .addr = A_USER_KEY_1_3,
769 },{ .name = "USER_KEY_1_4", .addr = A_USER_KEY_1_4,
770 },{ .name = "USER_KEY_1_5", .addr = A_USER_KEY_1_5,
771 },{ .name = "USER_KEY_1_6", .addr = A_USER_KEY_1_6,
772 },{ .name = "USER_KEY_1_7", .addr = A_USER_KEY_1_7,
773 },{ .name = "USER_KEY_2_0", .addr = A_USER_KEY_2_0,
774 },{ .name = "USER_KEY_2_1", .addr = A_USER_KEY_2_1,
775 },{ .name = "USER_KEY_2_2", .addr = A_USER_KEY_2_2,
776 },{ .name = "USER_KEY_2_3", .addr = A_USER_KEY_2_3,
777 },{ .name = "USER_KEY_2_4", .addr = A_USER_KEY_2_4,
778 },{ .name = "USER_KEY_2_5", .addr = A_USER_KEY_2_5,
779 },{ .name = "USER_KEY_2_6", .addr = A_USER_KEY_2_6,
780 },{ .name = "USER_KEY_2_7", .addr = A_USER_KEY_2_7,
781 },{ .name = "USER_KEY_3_0", .addr = A_USER_KEY_3_0,
782 },{ .name = "USER_KEY_3_1", .addr = A_USER_KEY_3_1,
783 },{ .name = "USER_KEY_3_2", .addr = A_USER_KEY_3_2,
784 },{ .name = "USER_KEY_3_3", .addr = A_USER_KEY_3_3,
785 },{ .name = "USER_KEY_3_4", .addr = A_USER_KEY_3_4,
786 },{ .name = "USER_KEY_3_5", .addr = A_USER_KEY_3_5,
787 },{ .name = "USER_KEY_3_6", .addr = A_USER_KEY_3_6,
788 },{ .name = "USER_KEY_3_7", .addr = A_USER_KEY_3_7,
789 },{ .name = "USER_KEY_4_0", .addr = A_USER_KEY_4_0,
790 },{ .name = "USER_KEY_4_1", .addr = A_USER_KEY_4_1,
791 },{ .name = "USER_KEY_4_2", .addr = A_USER_KEY_4_2,
792 },{ .name = "USER_KEY_4_3", .addr = A_USER_KEY_4_3,
793 },{ .name = "USER_KEY_4_4", .addr = A_USER_KEY_4_4,
794 },{ .name = "USER_KEY_4_5", .addr = A_USER_KEY_4_5,
795 },{ .name = "USER_KEY_4_6", .addr = A_USER_KEY_4_6,
796 },{ .name = "USER_KEY_4_7", .addr = A_USER_KEY_4_7,
797 },{ .name = "USER_KEY_5_0", .addr = A_USER_KEY_5_0,
798 },{ .name = "USER_KEY_5_1", .addr = A_USER_KEY_5_1,
799 },{ .name = "USER_KEY_5_2", .addr = A_USER_KEY_5_2,
800 },{ .name = "USER_KEY_5_3", .addr = A_USER_KEY_5_3,
801 },{ .name = "USER_KEY_5_4", .addr = A_USER_KEY_5_4,
802 },{ .name = "USER_KEY_5_5", .addr = A_USER_KEY_5_5,
803 },{ .name = "USER_KEY_5_6", .addr = A_USER_KEY_5_6,
804 },{ .name = "USER_KEY_5_7", .addr = A_USER_KEY_5_7,
805 },{ .name = "USER_KEY_6_0", .addr = A_USER_KEY_6_0,
806 },{ .name = "USER_KEY_6_1", .addr = A_USER_KEY_6_1,
807 },{ .name = "USER_KEY_6_2", .addr = A_USER_KEY_6_2,
808 },{ .name = "USER_KEY_6_3", .addr = A_USER_KEY_6_3,
809 },{ .name = "USER_KEY_6_4", .addr = A_USER_KEY_6_4,
810 },{ .name = "USER_KEY_6_5", .addr = A_USER_KEY_6_5,
811 },{ .name = "USER_KEY_6_6", .addr = A_USER_KEY_6_6,
812 },{ .name = "USER_KEY_6_7", .addr = A_USER_KEY_6_7,
813 },{ .name = "USER_KEY_7_0", .addr = A_USER_KEY_7_0,
814 },{ .name = "USER_KEY_7_1", .addr = A_USER_KEY_7_1,
815 },{ .name = "USER_KEY_7_2", .addr = A_USER_KEY_7_2,
816 },{ .name = "USER_KEY_7_3", .addr = A_USER_KEY_7_3,
817 },{ .name = "USER_KEY_7_4", .addr = A_USER_KEY_7_4,
818 },{ .name = "USER_KEY_7_5", .addr = A_USER_KEY_7_5,
819 },{ .name = "USER_KEY_7_6", .addr = A_USER_KEY_7_6,
820 },{ .name = "USER_KEY_7_7", .addr = A_USER_KEY_7_7,
821 },{ .name = "AES_ISR", .addr = A_AES_ISR,
822 .w1c = 0x7,
823 .post_write = aes_isr_postw,
824 },{ .name = "AES_IMR", .addr = A_AES_IMR,
825 .reset = 0x7,
826 .ro = 0x7,
827 },{ .name = "AES_IER", .addr = A_AES_IER,
828 .pre_write = aes_ier_prew,
829 },{ .name = "AES_IDR", .addr = A_AES_IDR,
830 .pre_write = aes_idr_prew,
831 }
832};
833
834static uint64_t aes_reg_read(void *opaque, hwaddr addr, unsigned size)
835{
836 uint64_t ret;
837
838 ret = register_read_memory(opaque, addr, size);
839 switch (addr) {
840
841 case A_AES_KEY_CLEAR:
842 case A_AES_KEY_DEC:
843 case A_KEY_DEC_TRIG:
844 case A_KEY_DEC_SEL:
845 case A_AES_USER_KEY_CRC:
846 case A_BH_KEY_0 ... A_USER_KEY_7_7:
847 case A_AES_IER:
848 case A_AES_IDR:
849 ret = 0;
850 break;
851 default:
852 break;
853 };
854
855 return ret;
856}
857
858static void aes_reg_write(void *opaque, hwaddr addr, uint64_t data,
859 unsigned size)
860{
861 RegisterInfoArray *reg_array = opaque;
862 Zynq3AES *s;
863 bool no_reg_update = false;
864
865 if (R_MAX < (addr / 4)) {
866 DPRINT("Reg 0x%x not implemented\n", (unsigned int)addr);
867 return;
868 }
869
870
871
872 s = XILINX_AES(reg_array->r[0]->opaque);
873
874 switch (addr) {
875 case A_USER_KEY_0_0 ... A_USER_KEY_0_7:
876 no_reg_update = s->user_key_lock_status[0];
877 break;
878 case A_USER_KEY_1_0 ... A_USER_KEY_1_7:
879 no_reg_update = s->user_key_lock_status[1];
880 break;
881 case A_USER_KEY_2_0 ... A_USER_KEY_2_7:
882 no_reg_update = s->user_key_lock_status[2];
883 break;
884 case A_USER_KEY_3_0 ... A_USER_KEY_3_7:
885 no_reg_update = s->user_key_lock_status[3];
886 break;
887 case A_USER_KEY_4_0 ... A_USER_KEY_4_7:
888 no_reg_update = s->user_key_lock_status[4];
889 break;
890 case A_USER_KEY_5_0 ... A_USER_KEY_5_7:
891 no_reg_update = s->user_key_lock_status[5];
892 break;
893 case A_USER_KEY_6_0 ... A_USER_KEY_6_7:
894 no_reg_update = s->user_key_lock_status[6];
895 break;
896 case A_USER_KEY_7_0 ... A_USER_KEY_7_7:
897 no_reg_update = s->user_key_lock_status[7];
898 break;
899 default:
900 break;
901 };
902
903 if (no_reg_update) {
904 DPRINT("addr:0x%x: Write reg locked!\n", (uint32_t)addr);
905 } else {
906 register_write_memory(opaque, addr, data, size);
907 }
908}
909
910static void aes_reset(DeviceState *dev)
911{
912 Zynq3AES *s = XILINX_AES(dev);
913 unsigned int i;
914
915 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
916 if (s->inSoftRst) {
917 switch (i) {
918 case R_AES_KEY_LOCK_STATUS:
919 case R_KEY_ZEROED_STATUS:
920 case R_BH_KEY_0 ... R_BH_KEY_7:
921 case R_USER_KEY_0_0 ... R_USER_KEY_7_7:
922 continue;
923 default:
924 break;
925 };
926 }
927 register_reset(&s->regs_info[i]);
928 }
929 aes_imr_update_irq(s);
930 s->key_loaded = false;
931 s->gcm_len = 0;
932 s->key_dec_done = false;
933 s->inSoftRst = false;
934}
935
936static const MemoryRegionOps aes_ops = {
937 .read = aes_reg_read,
938 .write = aes_reg_write,
939 .endianness = DEVICE_LITTLE_ENDIAN,
940 .valid = {
941 .min_access_size = 4,
942 .max_access_size = 4,
943 },
944};
945
946static void aes_busy_update(void *opaque, int n, int level)
947{
948 Zynq3AES *s = XILINX_AES(opaque);
949
950 s->aes_busy = level;
951}
952
953static void aes_done_update(void *opaque, int n, int level)
954{
955 Zynq3AES *s = XILINX_AES(opaque);
956
957 s->aes_done = level;
958}
959
960static void device_key_update(ZynqMPAESKeySink *obj, uint8_t *key, size_t len)
961{
962 Zynq3AES *s = XILINX_AES(obj);
963
964 assert(len == 256 / 8);
965
966 memcpy(s->device_key, key, len);
967}
968
969static int xlx_aes_push_data(Zynq3AES *s,
970 uint8_t *data8x, int len,
971 bool last_word , int lw_len,
972 uint8_t *outbuf, int *outlen)
973{
974 return xlnx_aes_push_data(s->aes, data8x, len, !!s->regs[R_AES_AAD],
975 last_word, lw_len, outbuf, outlen);
976}
977
978static uint32_t shift_in_u32(uint32_t *a, unsigned int size, uint32_t data)
979{
980 unsigned int i;
981 uint32_t r = a[0];
982
983 for (i = 1; i < size; i++) {
984 a[i - 1] = a[i];
985 }
986 a[i - 1] = data;
987
988 return r;
989}
990
991static void xlx_aes_feedback(Zynq3AES *s, unsigned char *buf, int len)
992{
993 bool kup_key_feedback;
994 bool iv_feedback;
995 int i;
996 uint8_t *key8;
997
998 iv_feedback = !!(s->regs[R_AES_KUP_WR] & R_AES_KUP_WR_IV_SAVE_MASK);
999
1000 kup_key_feedback = !!(s->regs[R_AES_KUP_WR] & R_AES_KUP_WR_KEY_SAVE_MASK);
1001
1002 assert((len & 3) == 0);
1003
1004 for (i = 0; i < len; i += 4) {
1005 uint32_t data;
1006 memcpy(&data, buf + i, 4);
1007
1008 if (iv_feedback) {
1009 data = shift_in_u32(s->feedback.iv, ARRAY_SIZE(s->feedback.iv),
1010 data);
1011 }
1012 if (kup_key_feedback) {
1013 shift_in_u32(s->feedback.key, ARRAY_SIZE(s->feedback.key), data);
1014 }
1015 }
1016
1017
1018 if (iv_feedback) {
1019 memcpy(&s->regs[R_AES_IV_0], s->feedback.iv, 16);
1020 s->regs[R_AES_KUP_WR] &= ~(R_AES_KUP_WR_IV_SAVE_MASK);
1021 }
1022 if (kup_key_feedback) {
1023 key8 = (uint8_t *) s->feedback.key;
1024 bswap32_buf8(key8, aes_key_size(s) / 8);
1025 for (i = 0; i < ARRAY_SIZE(s->feedback.key) * 4; i++) {
1026 s->kup_key.key[(aes_key_size(s) / 8) - i - 1] = key8[i];
1027 }
1028 s->regs[R_AES_KUP_WR] &= ~(R_AES_KUP_WR_KEY_SAVE_MASK);
1029 }
1030}
1031
1032static void aes_stream_gcm_push(void *opaque)
1033{
1034 Zynq3AES *s = XILINX_AES(opaque);
1035
1036 while (s->gcm_len && stream_can_push(s->tx_dev, aes_stream_gcm_push, s)) {
1037 size_t ret;
1038
1039 ret = stream_push(s->tx_dev, (s->gcm_tag + s->gcm_pos),
1040 s->gcm_len, s->gcm_push_eop);
1041 s->gcm_pos += ret;
1042 s->gcm_len -= ret;
1043 }
1044}
1045
1046static void aes_stream_dst_push(Zynq3AES *s, uint8_t *outbuf, int outlen,
1047 size_t len, bool eop, bool encrypt)
1048{
1049 int limit = sizeof(s->gcm_tag);
1050 size_t pushed;
1051
1052 pushed = stream_push(s->tx_dev, outbuf, outlen, eop);
1053
1054
1055 if (!encrypt || !eop) {
1056 return;
1057 }
1058
1059
1060 if (pushed >= outlen) {
1061 return;
1062 }
1063
1064
1065 if (pushed < len) {
1066 qemu_log_mask(LOG_GUEST_ERROR,
1067 "%s: DST channel dropping %zd b of data.\n",
1068 s->prefix, (len - pushed));
1069 return;
1070 }
1071
1072 outlen -= pushed;
1073 if (outlen > limit) {
1074 qemu_log_mask(LOG_GUEST_ERROR,
1075 "%s: Excessive GCM-tag data dropped: %d - %d\n",
1076 s->prefix, outlen, limit);
1077 outlen = limit;
1078 }
1079
1080
1081
1082
1083
1084
1085
1086 memcpy(s->gcm_tag, (outbuf + pushed), outlen);
1087 s->gcm_len = outlen;
1088 s->gcm_pos = 0;
1089 s->gcm_push_eop = eop;
1090
1091 aes_stream_gcm_push(s);
1092}
1093
1094static size_t aes_stream_push(StreamSink *obj, uint8_t *buf, size_t len,
1095 bool eop)
1096{
1097 Zynq3AES *s = XILINX_AES(obj);
1098 unsigned char outbuf[8 * 1024 + 16];
1099 int outlen = 0;
1100 bool feedback;
1101 bool encrypt;
1102 size_t ret;
1103
1104
1105 encrypt = s->aes->encrypt;
1106 if (encrypt && len > (sizeof(outbuf) - 16)) {
1107 len = sizeof(outbuf) - 16;
1108 eop = false;
1109 }
1110
1111
1112
1113
1114
1115 if (!s->regs[R_AES_DATA_ENDIANNESS_SWAP]) {
1116 wswap128_buf8(buf, len);
1117 }
1118 bswap32_buf8(buf, len);
1119 ret = xlx_aes_push_data(s, buf, len, eop, 4, outbuf, &outlen);
1120 if (!s->regs[R_AES_DATA_ENDIANNESS_SWAP]) {
1121 wswap128_buf8(outbuf, outlen);
1122 }
1123 bswap32_buf8(outbuf, outlen);
1124
1125 feedback = !!(s->regs[R_AES_KUP_WR]
1126 & (R_AES_KUP_WR_IV_SAVE_MASK | R_AES_KUP_WR_KEY_SAVE_MASK));
1127 if (feedback) {
1128 xlx_aes_feedback(s, outbuf, outlen);
1129 } else {
1130 aes_stream_dst_push(s, outbuf, outlen, ret, eop, encrypt);
1131 }
1132
1133
1134
1135 return ret;
1136}
1137
1138static bool aes_stream_can_push(StreamSink *obj,
1139 StreamCanPushNotifyFn notify,
1140 void *notify_opaque)
1141{
1142 Zynq3AES *s = XILINX_AES(obj);
1143
1144 return s->aes->inp_ready;
1145}
1146
1147static void efuse_key_lock_update(void *opaque, int n, int level)
1148{
1149 Zynq3AES *s = XILINX_AES(opaque);
1150
1151 ARRAY_FIELD_DP32(s->regs, AES_KEY_LOCK_STATUS, EFUSE, level);
1152}
1153
1154static void bbram_key_lock_update(void *opaque, int n, int level)
1155{
1156 Zynq3AES *s = XILINX_AES(opaque);
1157
1158 ARRAY_FIELD_DP32(s->regs, AES_KEY_LOCK_STATUS, BBRAM, level);
1159}
1160
1161static void user_key_lock_update(void *opaque, int n, int level)
1162{
1163 Zynq3AES *s = XILINX_AES(opaque);
1164
1165 if (0 <= n && n < ARRAY_SIZE(s->user_key_lock_status))
1166 s->user_key_lock_status[n] = (bool)level;
1167}
1168
1169static void aes_realize(DeviceState *dev, Error **errp)
1170{
1171 Zynq3AES *s = XILINX_AES(dev);
1172
1173 s->prefix = object_get_canonical_path(OBJECT(s));
1174 s->aes->prefix = g_strdup(s->prefix);
1175
1176 s->bh_key = (uint8_t *) &s->regs[R_BH_KEY_0];
1177#define USER_KEY(x) { \
1178 s->user_key[x] = (uint8_t *) &s->regs[R_USER_KEY_ ## x ## _0]; \
1179 }
1180 USER_KEY(0)
1181 USER_KEY(1)
1182 USER_KEY(2)
1183 USER_KEY(3)
1184 USER_KEY(4)
1185 USER_KEY(5)
1186 USER_KEY(6)
1187 USER_KEY(7)
1188#undef USER_KEY
1189 qdev_init_gpio_in_named(dev, aes_busy_update, "busy", 1);
1190 qdev_init_gpio_in_named(dev, aes_done_update, "done", 1);
1191 qdev_init_gpio_out(dev, &s->aes_rst, 1);
1192 qdev_init_gpio_in_named(dev, bbram_key_lock_update, "bbram-key-lock", 1);
1193 qdev_init_gpio_in_named(dev, efuse_key_lock_update, "efuse-key-lock", 1);
1194 qdev_init_gpio_in_named(dev, user_key_lock_update, "user-key-lock", 8);
1195
1196
1197
1198
1199
1200
1201 xlnx_aes_k256_get_provided(OBJECT(s), "family-key-id",
1202 "00000000" "00000000" "00000000" "00000000"
1203 "00000000" "00000000" "00000000" "00000000",
1204 s->family_key.key, NULL);
1205 xlnx_aes_k256_swap32(s->family_key.key, s->family_key.key);
1206}
1207
1208static void pmc_init_key_sink(Zynq3AES *s,
1209 const char *name, PMCKeySink *ks)
1210{
1211 char *ch_name;
1212
1213 ch_name = g_strdup_printf("zynqmp-aes-key-sink-%s-target", name);
1214 object_initialize(ks, sizeof(*ks), TYPE_XILINX_PMC_KEY_SINK);
1215 object_property_add_child(OBJECT(s), ch_name, (Object *)ks);
1216 free(ch_name);
1217
1218
1219 ks->tmr = s;
1220}
1221
1222static void aes_init(Object *obj)
1223{
1224 Zynq3AES *s = XILINX_AES(obj);
1225 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1226 RegisterInfoArray *reg_array;
1227
1228 pmc_init_key_sink(s, "bbram", &s->bbram_key);
1229 pmc_init_key_sink(s, "efuses", &s->efuse_key);
1230 pmc_init_key_sink(s, "efuses-user0", &s->efuse_user_key[0]);
1231 pmc_init_key_sink(s, "efuses-user1", &s->efuse_user_key[1]);
1232 pmc_init_key_sink(s, "family", &s->family_key);
1233 pmc_init_key_sink(s, "puf", &s->puf_key);
1234
1235 if (s->family_key_id == NULL) {
1236 s->family_key_id = g_strdup("xlnx-aes-family-key");
1237 }
1238 if (s->puf_key_id == NULL) {
1239 s->puf_key_id = g_strdup("xlnx-aes-puf-key");
1240 }
1241
1242 memory_region_init(&s->iomem, obj, TYPE_XILINX_AES, R_MAX * 4);
1243 reg_array =
1244 register_init_block32(DEVICE(obj), aes_regs_info,
1245 ARRAY_SIZE(aes_regs_info),
1246 s->regs_info, s->regs,
1247 &aes_ops,
1248 XILINX_AES_ERR_DEBUG,
1249 R_MAX * 4);
1250 memory_region_add_subregion(&s->iomem,
1251 0x0,
1252 ®_array->mem);
1253 object_property_add_link(obj, "aes-core", TYPE_XLNX_AES,
1254 (Object **)&s->aes,
1255 qdev_prop_allow_set_link_before_realize,
1256 OBJ_PROP_LINK_STRONG);
1257 object_property_add_link(obj, "stream-connected-aes", TYPE_STREAM_SINK,
1258 (Object **)&s->tx_dev,
1259 qdev_prop_allow_set_link_before_realize,
1260 OBJ_PROP_LINK_STRONG);
1261 sysbus_init_mmio(sbd, &s->iomem);
1262 sysbus_init_irq(sbd, &s->irq_aes_imr);
1263}
1264
1265static const VMStateDescription vmstate_aes = {
1266 .name = TYPE_XILINX_AES,
1267 .version_id = 1,
1268 .minimum_version_id = 1,
1269 .fields = (VMStateField[]) {
1270 VMSTATE_UINT32_ARRAY(regs, Zynq3AES, R_MAX),
1271 VMSTATE_END_OF_LIST(),
1272 }
1273};
1274
1275static Property aes_properties[] = {
1276 DEFINE_PROP_STRING("family-key-id", Zynq3AES, family_key_id),
1277 DEFINE_PROP_STRING("puf-key-id", Zynq3AES, puf_key_id),
1278
1279 DEFINE_PROP_END_OF_LIST(),
1280};
1281
1282static void aes_class_init(ObjectClass *klass, void *data)
1283{
1284 DeviceClass *dc = DEVICE_CLASS(klass);
1285 ZynqMPAESKeySinkClass *ksc = ZYNQMP_AES_KEY_SINK_CLASS(klass);
1286 StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
1287
1288 dc->reset = aes_reset;
1289 dc->realize = aes_realize;
1290 dc->vmsd = &vmstate_aes;
1291 device_class_set_props(dc, aes_properties);
1292 ksc->update = device_key_update;
1293
1294 ssc->push = aes_stream_push;
1295 ssc->can_push = aes_stream_can_push;
1296}
1297
1298static void pmc_key_sink_class_init(ObjectClass *klass, void *data)
1299{
1300 ZynqMPAESKeySinkClass *c = ZYNQMP_AES_KEY_SINK_CLASS(klass);
1301 c->update = pmc_key_sink_update;
1302}
1303
1304static const TypeInfo aes_info = {
1305 .name = TYPE_XILINX_AES,
1306 .parent = TYPE_SYS_BUS_DEVICE,
1307 .instance_size = sizeof(Zynq3AES),
1308 .class_init = aes_class_init,
1309 .instance_init = aes_init,
1310 .interfaces = (InterfaceInfo[]) {
1311 { TYPE_ZYNQMP_AES_KEY_SINK },
1312 { TYPE_STREAM_SINK },
1313 { }
1314 }
1315};
1316
1317static const TypeInfo pmc_key_sink_info = {
1318 .name = TYPE_XILINX_PMC_KEY_SINK,
1319 .parent = TYPE_OBJECT,
1320 .instance_size = sizeof(PMCKeySink),
1321 .class_init = pmc_key_sink_class_init,
1322 .interfaces = (InterfaceInfo[]) {
1323 { TYPE_ZYNQMP_AES_KEY_SINK },
1324 { }
1325 }
1326};
1327
1328
1329static void aes_register_types(void)
1330{
1331 type_register_static(&aes_info);
1332 type_register_static(&pmc_key_sink_info);
1333}
1334
1335type_init(aes_register_types)
1336
