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28#include "qemu/osdep.h"
29#include "hw/sysbus.h"
30#include "hw/register.h"
31#include "qemu/bitops.h"
32#include "qemu/log.h"
33#include "qemu/config-file.h"
34#include "qemu/option.h"
35#include "sysemu/sysemu.h"
36#include "migration/vmstate.h"
37#include "hw/qdev-properties.h"
38
39#include "hw/fdt_generic_util.h"
40
41#ifndef XILINX_CRP_ERR_DEBUG
42#define XILINX_CRP_ERR_DEBUG 0
43#endif
44
45#define TYPE_XILINX_CRP "xlnx,pmc-clk-rst"
46
47#define XILINX_CRP(obj) \
48 OBJECT_CHECK(CRP, (obj), TYPE_XILINX_CRP)
49
50REG32(ERR_CTRL, 0x0)
51 FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
52REG32(IR_STATUS, 0x4)
53 FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
54REG32(IR_MASK, 0x8)
55 FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
56REG32(IR_ENABLE, 0xc)
57 FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
58REG32(IR_DISABLE, 0x10)
59 FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
60REG32(WPROT, 0x1c)
61 FIELD(WPROT, ACTIVE, 0, 1)
62REG32(PLL_CLK_OTHER_DMN, 0x20)
63 FIELD(PLL_CLK_OTHER_DMN, RPLL_BYPASS, 1, 1)
64 FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1)
65REG32(PMCPLL_CTRL, 0x40)
66 FIELD(PMCPLL_CTRL, POST_SRC, 24, 3)
67 FIELD(PMCPLL_CTRL, PRE_SRC, 20, 3)
68 FIELD(PMCPLL_CTRL, CLKOUTDIV, 16, 2)
69 FIELD(PMCPLL_CTRL, FBDIV, 8, 8)
70 FIELD(PMCPLL_CTRL, BYPASS, 3, 1)
71 FIELD(PMCPLL_CTRL, RESET, 0, 1)
72REG32(PMCPLL_CFG, 0x44)
73 FIELD(PMCPLL_CFG, LOCK_DLY, 25, 7)
74 FIELD(PMCPLL_CFG, LOCK_CNT, 13, 10)
75 FIELD(PMCPLL_CFG, LFHF, 10, 2)
76 FIELD(PMCPLL_CFG, CP, 5, 4)
77 FIELD(PMCPLL_CFG, RES, 0, 4)
78REG32(PMCPLL_FRAC_CFG, 0x48)
79 FIELD(PMCPLL_FRAC_CFG, ENABLED, 31, 1)
80 FIELD(PMCPLL_FRAC_CFG, SEED, 22, 3)
81 FIELD(PMCPLL_FRAC_CFG, ALGRTHM, 19, 1)
82 FIELD(PMCPLL_FRAC_CFG, ORDER, 18, 1)
83 FIELD(PMCPLL_FRAC_CFG, DATA, 0, 16)
84REG32(NOCPLL_CTRL, 0x50)
85 FIELD(NOCPLL_CTRL, POST_SRC, 24, 3)
86 FIELD(NOCPLL_CTRL, PRE_SRC, 20, 3)
87 FIELD(NOCPLL_CTRL, CLKOUTDIV, 16, 2)
88 FIELD(NOCPLL_CTRL, FBDIV, 8, 8)
89 FIELD(NOCPLL_CTRL, BYPASS, 3, 1)
90 FIELD(NOCPLL_CTRL, RESET, 0, 1)
91REG32(NOCPLL_CFG, 0x54)
92 FIELD(NOCPLL_CFG, LOCK_DLY, 25, 7)
93 FIELD(NOCPLL_CFG, LOCK_CNT, 13, 10)
94 FIELD(NOCPLL_CFG, LFHF, 10, 2)
95 FIELD(NOCPLL_CFG, CP, 5, 4)
96 FIELD(NOCPLL_CFG, RES, 0, 4)
97REG32(NOCPLL_FRAC_CFG, 0x58)
98 FIELD(NOCPLL_FRAC_CFG, ENABLED, 31, 1)
99 FIELD(NOCPLL_FRAC_CFG, SEED, 22, 3)
100 FIELD(NOCPLL_FRAC_CFG, ALGRTHM, 19, 1)
101 FIELD(NOCPLL_FRAC_CFG, ORDER, 18, 1)
102 FIELD(NOCPLL_FRAC_CFG, DATA, 0, 16)
103REG32(PLL_STATUS, 0x60)
104 FIELD(PLL_STATUS, NOCPLL_STABLE, 3, 1)
105 FIELD(PLL_STATUS, PMCPLL_STABLE, 2, 1)
106 FIELD(PLL_STATUS, NOCPLL_LOCK, 1, 1)
107 FIELD(PLL_STATUS, PMCPLL_LOCK, 0, 1)
108REG32(PPLL_TO_XPD_CTRL, 0x100)
109 FIELD(PPLL_TO_XPD_CTRL, CLKACT, 25, 1)
110 FIELD(PPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
111REG32(NPLL_TO_XPD_CTRL, 0x104)
112 FIELD(NPLL_TO_XPD_CTRL, CLKACT, 25, 1)
113 FIELD(NPLL_TO_XPD_CTRL, DIVISOR0, 8, 10)
114REG32(CFU_REF_CTRL, 0x108)
115 FIELD(CFU_REF_CTRL, CLKACT, 25, 1)
116 FIELD(CFU_REF_CTRL, DIVISOR0, 8, 10)
117 FIELD(CFU_REF_CTRL, SRCSEL, 0, 3)
118REG32(SPARE_REF_CTRL, 0x110)
119 FIELD(SPARE_REF_CTRL, CLKACT, 25, 1)
120 FIELD(SPARE_REF_CTRL, DIVISOR0, 8, 10)
121 FIELD(SPARE_REF_CTRL, SRCSEL, 0, 3)
122REG32(NPI_REF_CTRL, 0x114)
123 FIELD(NPI_REF_CTRL, CLKACT, 25, 1)
124 FIELD(NPI_REF_CTRL, DIVISOR0, 8, 10)
125 FIELD(NPI_REF_CTRL, SRCSEL, 0, 3)
126REG32(QSPI_REF_CTRL, 0x118)
127 FIELD(QSPI_REF_CTRL, CLKACT, 24, 1)
128 FIELD(QSPI_REF_CTRL, DIVISOR0, 8, 10)
129 FIELD(QSPI_REF_CTRL, SRCSEL, 0, 3)
130REG32(OSPI_REF_CTRL, 0x120)
131 FIELD(OSPI_REF_CTRL, CLKACT, 24, 1)
132 FIELD(OSPI_REF_CTRL, DIVISOR0, 8, 10)
133 FIELD(OSPI_REF_CTRL, SRCSEL, 0, 3)
134REG32(SDIO0_REF_CTRL, 0x124)
135 FIELD(SDIO0_REF_CTRL, CLKACT, 24, 1)
136 FIELD(SDIO0_REF_CTRL, DIVISOR0, 8, 10)
137 FIELD(SDIO0_REF_CTRL, SRCSEL, 0, 3)
138REG32(SDIO1_REF_CTRL, 0x128)
139 FIELD(SDIO1_REF_CTRL, CLKACT, 24, 1)
140 FIELD(SDIO1_REF_CTRL, DIVISOR0, 8, 10)
141 FIELD(SDIO1_REF_CTRL, SRCSEL, 0, 3)
142REG32(PMC_LSBUS_REF_CTRL, 0x12c)
143 FIELD(PMC_LSBUS_REF_CTRL, CLKACT, 24, 1)
144 FIELD(PMC_LSBUS_REF_CTRL, DIVISOR0, 8, 10)
145 FIELD(PMC_LSBUS_REF_CTRL, SRCSEL, 0, 3)
146REG32(I2C_REF_CTRL, 0x130)
147 FIELD(I2C_REF_CTRL, CLKACT, 24, 1)
148 FIELD(I2C_REF_CTRL, DIVISOR0, 8, 10)
149 FIELD(I2C_REF_CTRL, SRCSEL, 0, 3)
150REG32(EFUSE_REF_CTRL, 0x134)
151 FIELD(EFUSE_REF_CTRL, SRCSEL, 2, 1)
152REG32(SYSMON_REF_CTRL, 0x138)
153 FIELD(SYSMON_REF_CTRL, SRCSEL, 2, 1)
154REG32(USB_SUSPEND_CTRL, 0x140)
155 FIELD(USB_SUSPEND_CTRL, DIVISOR0, 8, 10)
156REG32(SWITCH_TIMEOUT_CTRL, 0x144)
157 FIELD(SWITCH_TIMEOUT_CTRL, DIVISOR0, 8, 10)
158REG32(HSM0_REF_CTRL, 0x148)
159 FIELD(HSM0_REF_CTRL, CLKACT, 25, 1)
160 FIELD(HSM0_REF_CTRL, DIVISOR0, 8, 10)
161 FIELD(HSM0_REF_CTRL, SRCSEL, 0, 3)
162REG32(HSM1_REF_CTRL, 0x14c)
163 FIELD(HSM1_REF_CTRL, CLKACT, 25, 1)
164 FIELD(HSM1_REF_CTRL, DIVISOR0, 8, 10)
165 FIELD(HSM1_REF_CTRL, SRCSEL, 0, 3)
166REG32(SAFETY_CHK, 0x150)
167REG32(SD_DLL_REF_CTRL, 0x160)
168 FIELD(SD_DLL_REF_CTRL, CLKACT, 25, 1)
169 FIELD(SD_DLL_REF_CTRL, DIVISOR0, 8, 10)
170 FIELD(SD_DLL_REF_CTRL, SRCSEL, 0, 3)
171REG32(BOOT_MODE_USER, 0x200)
172 FIELD(BOOT_MODE_USER, ALT_BOOT_MODE, 12, 4)
173 FIELD(BOOT_MODE_USER, USE_ALT, 8, 1)
174 FIELD(BOOT_MODE_USER, BOOT_MODE, 0, 4)
175REG32(BOOT_MODE_POR, 0x204)
176 FIELD(BOOT_MODE_POR, BOOT_MODE2, 8, 4)
177 FIELD(BOOT_MODE_POR, BOOT_MODE1, 4, 4)
178 FIELD(BOOT_MODE_POR, BOOT_MODE0, 0, 4)
179REG32(RESET_REASON, 0x220)
180 FIELD(RESET_REASON, SLR_SYS, 10, 1)
181 FIELD(RESET_REASON, SW_SYS, 9, 1)
182 FIELD(RESET_REASON, ERR_SYS, 8, 1)
183 FIELD(RESET_REASON, DAP_SYS, 7, 1)
184 FIELD(RESET_REASON, ERR_POR, 3, 1)
185 FIELD(RESET_REASON, SLR_POR, 2, 1)
186 FIELD(RESET_REASON, SW_POR, 1, 1)
187 FIELD(RESET_REASON, EXTERNAL_POR, 0, 1)
188REG32(CLKMON_STATUS, 0x240)
189 FIELD(CLKMON_STATUS, CNTA7_OVER_ERR, 15, 1)
190 FIELD(CLKMON_STATUS, MON7_ERR, 14, 1)
191 FIELD(CLKMON_STATUS, CNTA6_OVER_ERR, 13, 1)
192 FIELD(CLKMON_STATUS, MON6_ERR, 12, 1)
193 FIELD(CLKMON_STATUS, CNTA5_OVER_ERR, 11, 1)
194 FIELD(CLKMON_STATUS, MON5_ERR, 10, 1)
195 FIELD(CLKMON_STATUS, CNTA4_OVER_ERR, 9, 1)
196 FIELD(CLKMON_STATUS, MON4_ERR, 8, 1)
197 FIELD(CLKMON_STATUS, CNTA3_OVER_ERR, 7, 1)
198 FIELD(CLKMON_STATUS, MON3_ERR, 6, 1)
199 FIELD(CLKMON_STATUS, CNTA2_OVER_ERR, 5, 1)
200 FIELD(CLKMON_STATUS, MON2_ERR, 4, 1)
201 FIELD(CLKMON_STATUS, CNTA1_OVER_ERR, 3, 1)
202 FIELD(CLKMON_STATUS, MON1_ERR, 2, 1)
203 FIELD(CLKMON_STATUS, CNTA0_OVER_ERR, 1, 1)
204 FIELD(CLKMON_STATUS, MON0_ERR, 0, 1)
205REG32(CLKMON_MASK, 0x244)
206 FIELD(CLKMON_MASK, CNTA7_OVER_ERR, 15, 1)
207 FIELD(CLKMON_MASK, MON7_ERR, 14, 1)
208 FIELD(CLKMON_MASK, CNTA6_OVER_ERR, 13, 1)
209 FIELD(CLKMON_MASK, MON6_ERR, 12, 1)
210 FIELD(CLKMON_MASK, CNTA5_OVER_ERR, 11, 1)
211 FIELD(CLKMON_MASK, MON5_ERR, 10, 1)
212 FIELD(CLKMON_MASK, CNTA4_OVER_ERR, 9, 1)
213 FIELD(CLKMON_MASK, MON4_ERR, 8, 1)
214 FIELD(CLKMON_MASK, CNTA3_OVER_ERR, 7, 1)
215 FIELD(CLKMON_MASK, MON3_ERR, 6, 1)
216 FIELD(CLKMON_MASK, CNTA2_OVER_ERR, 5, 1)
217 FIELD(CLKMON_MASK, MON2_ERR, 4, 1)
218 FIELD(CLKMON_MASK, CNTA1_OVER_ERR, 3, 1)
219 FIELD(CLKMON_MASK, MON1_ERR, 2, 1)
220 FIELD(CLKMON_MASK, CNTA0_OVER_ERR, 1, 1)
221 FIELD(CLKMON_MASK, MON0_ERR, 0, 1)
222REG32(CLKMON_ENABLE, 0x248)
223 FIELD(CLKMON_ENABLE, CNTA7_OVER_ERR, 15, 1)
224 FIELD(CLKMON_ENABLE, MON7_ERR, 14, 1)
225 FIELD(CLKMON_ENABLE, CNTA6_OVER_ERR, 13, 1)
226 FIELD(CLKMON_ENABLE, MON6_ERR, 12, 1)
227 FIELD(CLKMON_ENABLE, CNTA5_OVER_ERR, 11, 1)
228 FIELD(CLKMON_ENABLE, MON5_ERR, 10, 1)
229 FIELD(CLKMON_ENABLE, CNTA4_OVER_ERR, 9, 1)
230 FIELD(CLKMON_ENABLE, MON4_ERR, 8, 1)
231 FIELD(CLKMON_ENABLE, CNTA3_OVER_ERR, 7, 1)
232 FIELD(CLKMON_ENABLE, MON3_ERR, 6, 1)
233 FIELD(CLKMON_ENABLE, CNTA2_OVER_ERR, 5, 1)
234 FIELD(CLKMON_ENABLE, MON2_ERR, 4, 1)
235 FIELD(CLKMON_ENABLE, CNTA1_OVER_ERR, 3, 1)
236 FIELD(CLKMON_ENABLE, MON1_ERR, 2, 1)
237 FIELD(CLKMON_ENABLE, CNTA0_OVER_ERR, 1, 1)
238 FIELD(CLKMON_ENABLE, MON0_ERR, 0, 1)
239REG32(CLKMON_DISABLE, 0x24c)
240 FIELD(CLKMON_DISABLE, CNTA7_OVER_ERR, 15, 1)
241 FIELD(CLKMON_DISABLE, MON7_ERR, 14, 1)
242 FIELD(CLKMON_DISABLE, CNTA6_OVER_ERR, 13, 1)
243 FIELD(CLKMON_DISABLE, MON6_ERR, 12, 1)
244 FIELD(CLKMON_DISABLE, CNTA5_OVER_ERR, 11, 1)
245 FIELD(CLKMON_DISABLE, MON5_ERR, 10, 1)
246 FIELD(CLKMON_DISABLE, CNTA4_OVER_ERR, 9, 1)
247 FIELD(CLKMON_DISABLE, MON4_ERR, 8, 1)
248 FIELD(CLKMON_DISABLE, CNTA3_OVER_ERR, 7, 1)
249 FIELD(CLKMON_DISABLE, MON3_ERR, 6, 1)
250 FIELD(CLKMON_DISABLE, CNTA2_OVER_ERR, 5, 1)
251 FIELD(CLKMON_DISABLE, MON2_ERR, 4, 1)
252 FIELD(CLKMON_DISABLE, CNTA1_OVER_ERR, 3, 1)
253 FIELD(CLKMON_DISABLE, MON1_ERR, 2, 1)
254 FIELD(CLKMON_DISABLE, CNTA0_OVER_ERR, 1, 1)
255 FIELD(CLKMON_DISABLE, MON0_ERR, 0, 1)
256REG32(CLKMON_TRIGGER, 0x250)
257 FIELD(CLKMON_TRIGGER, CNTA7_OVER_ERR, 15, 1)
258 FIELD(CLKMON_TRIGGER, MON7_ERR, 14, 1)
259 FIELD(CLKMON_TRIGGER, CNTA6_OVER_ERR, 13, 1)
260 FIELD(CLKMON_TRIGGER, MON6_ERR, 12, 1)
261 FIELD(CLKMON_TRIGGER, CNTA5_OVER_ERR, 11, 1)
262 FIELD(CLKMON_TRIGGER, MON5_ERR, 10, 1)
263 FIELD(CLKMON_TRIGGER, CNTA4_OVER_ERR, 9, 1)
264 FIELD(CLKMON_TRIGGER, MON4_ERR, 8, 1)
265 FIELD(CLKMON_TRIGGER, CNTA3_OVER_ERR, 7, 1)
266 FIELD(CLKMON_TRIGGER, MON3_ERR, 6, 1)
267 FIELD(CLKMON_TRIGGER, CNTA2_OVER_ERR, 5, 1)
268 FIELD(CLKMON_TRIGGER, MON2_ERR, 4, 1)
269 FIELD(CLKMON_TRIGGER, CNTA1_OVER_ERR, 3, 1)
270 FIELD(CLKMON_TRIGGER, MON1_ERR, 2, 1)
271 FIELD(CLKMON_TRIGGER, CNTA0_OVER_ERR, 1, 1)
272 FIELD(CLKMON_TRIGGER, MON0_ERR, 0, 1)
273REG32(CHKR0_CLKA_UPPER, 0x260)
274REG32(CHKR0_CLKA_LOWER, 0x264)
275REG32(CHKR0_CLKB_CNT, 0x268)
276REG32(CHKR0_CTRL, 0x26c)
277 FIELD(CHKR0_CTRL, IDLE_STATE, 10, 1)
278 FIELD(CHKR0_CTRL, START_SINGLE, 9, 1)
279 FIELD(CHKR0_CTRL, START_CONTINUOUS, 8, 1)
280 FIELD(CHKR0_CTRL, CLKB_MUX_CTRL, 6, 1)
281 FIELD(CHKR0_CTRL, CLKA_MUX_CTRL, 1, 4)
282 FIELD(CHKR0_CTRL, ENABLE, 0, 1)
283REG32(CHKR1_CLKA_UPPER, 0x270)
284REG32(CHKR1_CLKA_LOWER, 0x274)
285REG32(CHKR1_CLKB_CNT, 0x278)
286REG32(CHKR1_CTRL, 0x27c)
287 FIELD(CHKR1_CTRL, IDLE_STATE, 10, 1)
288 FIELD(CHKR1_CTRL, START_SINGLE, 9, 1)
289 FIELD(CHKR1_CTRL, START_CONTINUOUS, 8, 1)
290 FIELD(CHKR1_CTRL, CLKB_MUX_CTRL, 6, 1)
291 FIELD(CHKR1_CTRL, CLKA_MUX_CTRL, 1, 4)
292 FIELD(CHKR1_CTRL, ENABLE, 0, 1)
293REG32(CHKR2_CLKA_UPPER, 0x280)
294REG32(CHKR2_CLKA_LOWER, 0x284)
295REG32(CHKR2_CLKB_CNT, 0x288)
296REG32(CHKR2_CTRL, 0x28c)
297 FIELD(CHKR2_CTRL, IDLE_STATE, 10, 1)
298 FIELD(CHKR2_CTRL, START_SINGLE, 9, 1)
299 FIELD(CHKR2_CTRL, START_CONTINUOUS, 8, 1)
300 FIELD(CHKR2_CTRL, CLKB_MUX_CTRL, 6, 1)
301 FIELD(CHKR2_CTRL, CLKA_MUX_CTRL, 1, 4)
302 FIELD(CHKR2_CTRL, ENABLE, 0, 1)
303REG32(CHKR3_CLKA_UPPER, 0x290)
304REG32(CHKR3_CLKA_LOWER, 0x294)
305REG32(CHKR3_CLKB_CNT, 0x298)
306REG32(CHKR3_CTRL, 0x29c)
307 FIELD(CHKR3_CTRL, IDLE_STATE, 10, 1)
308 FIELD(CHKR3_CTRL, START_SINGLE, 9, 1)
309 FIELD(CHKR3_CTRL, START_CONTINUOUS, 8, 1)
310 FIELD(CHKR3_CTRL, CLKB_MUX_CTRL, 6, 1)
311 FIELD(CHKR3_CTRL, CLKA_MUX_CTRL, 1, 4)
312 FIELD(CHKR3_CTRL, ENABLE, 0, 1)
313REG32(CHKR4_CLKA_UPPER, 0x2a0)
314REG32(CHKR4_CLKA_LOWER, 0x2a4)
315REG32(CHKR4_CLKB_CNT, 0x2a8)
316REG32(CHKR4_CTRL, 0x2ac)
317 FIELD(CHKR4_CTRL, IDLE_STATE, 10, 1)
318 FIELD(CHKR4_CTRL, START_SINGLE, 9, 1)
319 FIELD(CHKR4_CTRL, START_CONTINUOUS, 8, 1)
320 FIELD(CHKR4_CTRL, CLKB_MUX_CTRL, 6, 1)
321 FIELD(CHKR4_CTRL, CLKA_MUX_CTRL, 1, 4)
322 FIELD(CHKR4_CTRL, ENABLE, 0, 1)
323REG32(CHKR5_CLKA_UPPER, 0x2b0)
324REG32(CHKR5_CLKA_LOWER, 0x2b4)
325REG32(CHKR5_CLKB_CNT, 0x2b8)
326REG32(CHKR5_CTRL, 0x2bc)
327 FIELD(CHKR5_CTRL, IDLE_STATE, 10, 1)
328 FIELD(CHKR5_CTRL, START_SINGLE, 9, 1)
329 FIELD(CHKR5_CTRL, START_CONTINUOUS, 8, 1)
330 FIELD(CHKR5_CTRL, CLKB_MUX_CTRL, 6, 1)
331 FIELD(CHKR5_CTRL, CLKA_MUX_CTRL, 1, 4)
332 FIELD(CHKR5_CTRL, ENABLE, 0, 1)
333REG32(CHKR6_CLKA_UPPER, 0x2c0)
334REG32(CHKR6_CLKA_LOWER, 0x2c4)
335REG32(CHKR6_CLKB_CNT, 0x2c8)
336REG32(CHKR6_CTRL, 0x2cc)
337 FIELD(CHKR6_CTRL, IDLE_STATE, 10, 1)
338 FIELD(CHKR6_CTRL, START_SINGLE, 9, 1)
339 FIELD(CHKR6_CTRL, START_CONTINUOUS, 8, 1)
340 FIELD(CHKR6_CTRL, CLKB_MUX_CTRL, 6, 1)
341 FIELD(CHKR6_CTRL, CLKA_MUX_CTRL, 1, 4)
342 FIELD(CHKR6_CTRL, ENABLE, 0, 1)
343REG32(CHKR7_CLKA_UPPER, 0x2d0)
344REG32(CHKR7_CLKA_LOWER, 0x2d4)
345REG32(CHKR7_CLKB_CNT, 0x2d8)
346REG32(CHKR7_CTRL, 0x2dc)
347 FIELD(CHKR7_CTRL, IDLE_STATE, 10, 1)
348 FIELD(CHKR7_CTRL, START_SINGLE, 9, 1)
349 FIELD(CHKR7_CTRL, START_CONTINUOUS, 8, 1)
350 FIELD(CHKR7_CTRL, CLKB_MUX_CTRL, 6, 1)
351 FIELD(CHKR7_CTRL, CLKA_MUX_CTRL, 1, 4)
352 FIELD(CHKR7_CTRL, ENABLE, 0, 1)
353REG32(RST_QSPI, 0x300)
354 FIELD(RST_QSPI, RESET, 0, 1)
355REG32(RST_OSPI, 0x304)
356 FIELD(RST_OSPI, RESET, 0, 1)
357REG32(RST_SDIO0, 0x308)
358 FIELD(RST_SDIO0, RESET, 0, 1)
359REG32(RST_SDIO1, 0x30c)
360 FIELD(RST_SDIO1, RESET, 0, 1)
361REG32(RST_I2C, 0x314)
362 FIELD(RST_I2C, RESET, 0, 1)
363REG32(RST_GPIO, 0x318)
364 FIELD(RST_GPIO, RESET, 0, 1)
365REG32(RST_PS, 0x31c)
366 FIELD(RST_PS, PMC_POR, 7, 1)
367 FIELD(RST_PS, PS_POR, 6, 1)
368 FIELD(RST_PS, PL_POR, 5, 1)
369 FIELD(RST_PS, PMC_SRST, 3, 1)
370 FIELD(RST_PS, PS_SRST, 2, 1)
371 FIELD(RST_PS, PL_SRST, 1, 1)
372REG32(RST_NONPS, 0x320)
373 FIELD(RST_NONPS, NOC_RESET, 6, 1)
374 FIELD(RST_NONPS, NOC_POR, 5, 1)
375 FIELD(RST_NONPS, NPI_RESET, 4, 1)
376 FIELD(RST_NONPS, SYS_RST_1, 2, 1)
377 FIELD(RST_NONPS, SYS_RST_2, 1, 1)
378 FIELD(RST_NONPS, SYS_RST_3, 0, 1)
379REG32(RST_SBI, 0x324)
380 FIELD(RST_SBI, RESET, 0, 1)
381REG32(RST_PDMA, 0x328)
382 FIELD(RST_PDMA, RESET1, 1, 1)
383 FIELD(RST_PDMA, RESET0, 0, 1)
384REG32(RST_SYSMON, 0x32c)
385 FIELD(RST_SYSMON, SEQ_RST, 1, 1)
386 FIELD(RST_SYSMON, CFG_RST, 0, 1)
387REG32(RST_PL, 0x330)
388 FIELD(RST_PL, RESET3, 3, 1)
389 FIELD(RST_PL, RESET2, 2, 1)
390 FIELD(RST_PL, RESET1, 1, 1)
391 FIELD(RST_PL, RESET0, 0, 1)
392REG32(RST_USB, 0x334)
393 FIELD(RST_USB, PHY_RST, 0, 1)
394REG32(RST_DBG, 0x400)
395 FIELD(RST_DBG, DPC, 1, 1)
396 FIELD(RST_DBG, RESET, 0, 1)
397REG32(PMC_PL0_REF_CTRL, 0x5c0)
398 FIELD(PMC_PL0_REF_CTRL, CLKACT, 24, 1)
399 FIELD(PMC_PL0_REF_CTRL, DIVISOR0, 8, 10)
400 FIELD(PMC_PL0_REF_CTRL, SRCSEL, 0, 3)
401REG32(PMC_PL1_REF_CTRL, 0x5c4)
402 FIELD(PMC_PL1_REF_CTRL, CLKACT, 24, 1)
403 FIELD(PMC_PL1_REF_CTRL, DIVISOR0, 8, 10)
404 FIELD(PMC_PL1_REF_CTRL, SRCSEL, 0, 3)
405REG32(PMC_PL2_REF_CTRL, 0x5c8)
406 FIELD(PMC_PL2_REF_CTRL, CLKACT, 24, 1)
407 FIELD(PMC_PL2_REF_CTRL, DIVISOR0, 8, 10)
408 FIELD(PMC_PL2_REF_CTRL, SRCSEL, 0, 3)
409REG32(PMC_PL3_REF_CTRL, 0x5cc)
410 FIELD(PMC_PL3_REF_CTRL, CLKACT, 24, 1)
411 FIELD(PMC_PL3_REF_CTRL, DIVISOR0, 8, 10)
412 FIELD(PMC_PL3_REF_CTRL, SRCSEL, 0, 3)
413
414#define R_MAX (R_PMC_PL3_REF_CTRL + 1)
415
416typedef struct CRP {
417 SysBusDevice parent_obj;
418 MemoryRegion iomem;
419 qemu_irq irq_ir;
420 qemu_irq irq_clkmon;
421
422 qemu_irq rst_qspi;
423 qemu_irq rst_ospi;
424 qemu_irq rst_sdio[2];
425 qemu_irq rst_i2c;
426 qemu_irq rst_gpio;
427
428 qemu_irq rst_ps_pl_srst;
429 qemu_irq rst_ps_ps_srst;
430 qemu_irq rst_ps_pmc_srst;
431 qemu_irq rst_ps_pl_por;
432 qemu_irq rst_ps_ps_por;
433 qemu_irq rst_ps_pmc_por;
434
435 qemu_irq rst_nonps_sys3;
436 qemu_irq rst_nonps_sys2;
437 qemu_irq rst_nonps_sys1;
438 qemu_irq rst_nonps_npi;
439 qemu_irq rst_nonps_noc_por;
440 qemu_irq rst_nonps_noc;
441
442 qemu_irq rst_sbi;
443 qemu_irq rst_pdma[2];
444 qemu_irq rst_sysmon_cfg;
445 qemu_irq rst_sysmon_seq;
446 qemu_irq rst_pl[4];
447 qemu_irq rst_usb;
448 qemu_irq rst_dbg;
449 qemu_irq rst_dbg_dpc;
450
451 uint32_t regs[R_MAX];
452 RegisterInfo regs_info[R_MAX];
453} CRP;
454
455static void ir_update_irq(CRP *s)
456{
457 bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
458 qemu_set_irq(s->irq_ir, pending);
459}
460
461static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
462{
463 CRP *s = XILINX_CRP(reg->opaque);
464 ir_update_irq(s);
465}
466
467static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
468{
469 CRP *s = XILINX_CRP(reg->opaque);
470 uint32_t val = val64;
471
472 s->regs[R_IR_MASK] &= ~val;
473 ir_update_irq(s);
474 return 0;
475}
476
477static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
478{
479 CRP *s = XILINX_CRP(reg->opaque);
480 uint32_t val = val64;
481
482 s->regs[R_IR_MASK] |= val;
483 ir_update_irq(s);
484 return 0;
485}
486
487static void clkmon_update_irq(CRP *s)
488{
489 bool pending = s->regs[R_CLKMON_STATUS] & ~s->regs[R_CLKMON_MASK];
490 qemu_set_irq(s->irq_clkmon, pending);
491}
492
493static void clkmon_status_postw(RegisterInfo *reg, uint64_t val64)
494{
495 CRP *s = XILINX_CRP(reg->opaque);
496 clkmon_update_irq(s);
497}
498
499static uint64_t clkmon_enable_prew(RegisterInfo *reg, uint64_t val64)
500{
501 CRP *s = XILINX_CRP(reg->opaque);
502 uint32_t val = val64;
503
504 s->regs[R_CLKMON_MASK] &= ~val;
505 clkmon_update_irq(s);
506 return 0;
507}
508
509static uint64_t clkmon_disable_prew(RegisterInfo *reg, uint64_t val64)
510{
511 CRP *s = XILINX_CRP(reg->opaque);
512 uint32_t val = val64;
513
514 s->regs[R_CLKMON_MASK] |= val;
515 clkmon_update_irq(s);
516 return 0;
517}
518
519static uint64_t clkmon_trigger_prew(RegisterInfo *reg, uint64_t val64)
520{
521 CRP *s = XILINX_CRP(reg->opaque);
522 uint32_t val = val64;
523
524 s->regs[R_CLKMON_STATUS] |= val;
525 clkmon_update_irq(s);
526 return 0;
527}
528
529static void update_boot_mode_user(CRP *s)
530{
531 unsigned int boot_mode;
532 bool use_alt;
533
534
535
536
537 use_alt = ARRAY_FIELD_EX32(s->regs, BOOT_MODE_USER, USE_ALT);
538 if (use_alt) {
539 boot_mode = ARRAY_FIELD_EX32(s->regs, BOOT_MODE_USER, ALT_BOOT_MODE);
540 } else {
541 boot_mode = ARRAY_FIELD_EX32(s->regs, BOOT_MODE_POR, BOOT_MODE0);
542 }
543 ARRAY_FIELD_DP32(s->regs, BOOT_MODE_USER, BOOT_MODE, boot_mode);
544}
545
546static void boot_mode_user_postw(RegisterInfo *reg, uint64_t val64)
547{
548 CRP *s = XILINX_CRP(reg->opaque);
549 update_boot_mode_user(s);
550}
551
552#define PROPAGATE_GPIO(reg, f, irq) { \
553 bool val = ARRAY_FIELD_EX32(s->regs, reg, f); \
554 qemu_set_irq(irq, val); \
555}
556
557static void crp_update_gpios(CRP *s)
558{
559 PROPAGATE_GPIO(RST_QSPI, RESET, s->rst_qspi);
560 PROPAGATE_GPIO(RST_OSPI, RESET, s->rst_ospi);
561 PROPAGATE_GPIO(RST_SDIO0, RESET, s->rst_sdio[0]);
562 PROPAGATE_GPIO(RST_SDIO1, RESET, s->rst_sdio[1]);
563 PROPAGATE_GPIO(RST_I2C, RESET, s->rst_i2c);
564 PROPAGATE_GPIO(RST_GPIO, RESET, s->rst_gpio);
565
566 PROPAGATE_GPIO(RST_PS, PL_SRST, s->rst_ps_pl_srst);
567 PROPAGATE_GPIO(RST_PS, PS_SRST, s->rst_ps_ps_srst);
568 PROPAGATE_GPIO(RST_PS, PMC_SRST, s->rst_ps_pmc_srst);
569 PROPAGATE_GPIO(RST_PS, PL_POR, s->rst_ps_pl_por);
570 PROPAGATE_GPIO(RST_PS, PS_POR, s->rst_ps_ps_por);
571 PROPAGATE_GPIO(RST_PS, PMC_POR, s->rst_ps_pmc_por);
572
573 PROPAGATE_GPIO(RST_NONPS, SYS_RST_3, s->rst_nonps_sys3);
574 PROPAGATE_GPIO(RST_NONPS, SYS_RST_2, s->rst_nonps_sys2);
575 PROPAGATE_GPIO(RST_NONPS, SYS_RST_1, s->rst_nonps_sys1);
576 PROPAGATE_GPIO(RST_NONPS, NPI_RESET, s->rst_nonps_npi);
577 PROPAGATE_GPIO(RST_NONPS, NOC_POR, s->rst_nonps_noc_por);
578 PROPAGATE_GPIO(RST_NONPS, NOC_RESET, s->rst_nonps_noc);
579
580 PROPAGATE_GPIO(RST_SBI, RESET, s->rst_sbi);
581 PROPAGATE_GPIO(RST_PDMA, RESET0, s->rst_pdma[0]);
582 PROPAGATE_GPIO(RST_PDMA, RESET1, s->rst_pdma[1]);
583 PROPAGATE_GPIO(RST_SYSMON, CFG_RST, s->rst_sysmon_cfg);
584 PROPAGATE_GPIO(RST_SYSMON, SEQ_RST, s->rst_sysmon_seq);
585 PROPAGATE_GPIO(RST_PL, RESET0, s->rst_pl[0]);
586 PROPAGATE_GPIO(RST_PL, RESET1, s->rst_pl[1]);
587 PROPAGATE_GPIO(RST_PL, RESET2, s->rst_pl[2]);
588 PROPAGATE_GPIO(RST_PL, RESET3, s->rst_pl[3]);
589 PROPAGATE_GPIO(RST_USB, PHY_RST, s->rst_usb);
590 PROPAGATE_GPIO(RST_DBG, RESET, s->rst_dbg);
591 PROPAGATE_GPIO(RST_DBG, DPC, s->rst_dbg_dpc);
592}
593
594static void crp_update_gpios_pw(RegisterInfo *reg, uint64_t val64)
595{
596 CRP *s = XILINX_CRP(reg->opaque);
597 crp_update_gpios(s);
598}
599
600static uint64_t rst_ps_prew(RegisterInfo *reg, uint64_t val64)
601{
602 CRP *s = XILINX_CRP(reg->opaque);
603 uint32_t val = val64;
604
605 ARRAY_FIELD_DP32(s->regs, RESET_REASON, SW_SYS,
606 ARRAY_FIELD_EX32(s->regs, RESET_REASON, SW_SYS) |
607 !!(val & (R_RST_PS_PMC_SRST_MASK |
608 R_RST_PS_PS_SRST_MASK |
609 R_RST_PS_PL_SRST_MASK)));
610 ARRAY_FIELD_DP32(s->regs, RESET_REASON, SW_POR,
611 ARRAY_FIELD_EX32(s->regs, RESET_REASON, SW_POR) |
612 !!(val & (R_RST_PS_PMC_POR_MASK |
613 R_RST_PS_PS_POR_MASK |
614 R_RST_PS_PL_POR_MASK)));
615 return val64;
616}
617
618static RegisterAccessInfo crp_regs_info[] = {
619 { .name = "ERR_CTRL", .addr = A_ERR_CTRL,
620 },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
621 .w1c = 0x1,
622 .post_write = ir_status_postw,
623 },{ .name = "IR_MASK", .addr = A_IR_MASK,
624 .reset = 0x1,
625 .ro = 0x1,
626 },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
627 .pre_write = ir_enable_prew,
628 },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
629 .pre_write = ir_disable_prew,
630 },{ .name = "WPROT", .addr = A_WPROT,
631 },{ .name = "PLL_CLK_OTHER_DMN", .addr = A_PLL_CLK_OTHER_DMN,
632 .reset = 0x3,
633 .rsvd = 0xc,
634 },{ .name = "PMCPLL_CTRL", .addr = A_PMCPLL_CTRL,
635 .reset = 0x24809,
636 .rsvd = 0xf88c00f6,
637 },{ .name = "PMCPLL_CFG", .addr = A_PMCPLL_CFG,
638 .reset = 0x2000000,
639 .rsvd = 0x1801210,
640 },{ .name = "PMCPLL_FRAC_CFG", .addr = A_PMCPLL_FRAC_CFG,
641 .rsvd = 0x7e330000,
642 },{ .name = "NOCPLL_CTRL", .addr = A_NOCPLL_CTRL,
643 .reset = 0x24809,
644 .rsvd = 0xf88c00f6,
645 },{ .name = "NOCPLL_CFG", .addr = A_NOCPLL_CFG,
646 .reset = 0x2000000,
647 .rsvd = 0x1801210,
648 },{ .name = "NOCPLL_FRAC_CFG", .addr = A_NOCPLL_FRAC_CFG,
649 .rsvd = 0x7e330000,
650 },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS,
651 .reset = R_PLL_STATUS_PMCPLL_LOCK_MASK |
652 R_PLL_STATUS_NOCPLL_LOCK_MASK |
653 R_PLL_STATUS_PMCPLL_STABLE_MASK |
654 R_PLL_STATUS_NOCPLL_STABLE_MASK,
655 .rsvd = 0xf0,
656 .ro = 0xf,
657 },{ .name = "PPLL_TO_XPD_CTRL", .addr = A_PPLL_TO_XPD_CTRL,
658 .reset = 0x2000100,
659 .rsvd = 0xfdfc00ff,
660 },{ .name = "NPLL_TO_XPD_CTRL", .addr = A_NPLL_TO_XPD_CTRL,
661 .reset = 0x2000100,
662 .rsvd = 0xfdfc00ff,
663 },{ .name = "CFU_REF_CTRL", .addr = A_CFU_REF_CTRL,
664 .reset = 0x2000300,
665 .rsvd = 0xfdfc00f8,
666 },{ .name = "SPARE_REF_CTRL", .addr = A_SPARE_REF_CTRL,
667 .reset = 0x200,
668 .rsvd = 0xfdfc00f8,
669 },{ .name = "NPI_REF_CTRL", .addr = A_NPI_REF_CTRL,
670 .reset = 0x400,
671 .rsvd = 0xfdfc00f8,
672 },{ .name = "QSPI_REF_CTRL", .addr = A_QSPI_REF_CTRL,
673 .reset = 0x1000400,
674 .rsvd = 0xfefc00f8,
675 },{ .name = "OSPI_REF_CTRL", .addr = A_OSPI_REF_CTRL,
676 .reset = 0x1000400,
677 .rsvd = 0xfefc00f8,
678 },{ .name = "SDIO0_REF_CTRL", .addr = A_SDIO0_REF_CTRL,
679 .reset = 0x1000600,
680 .rsvd = 0xfefc00f8,
681 },{ .name = "SDIO1_REF_CTRL", .addr = A_SDIO1_REF_CTRL,
682 .reset = 0x1000600,
683 .rsvd = 0xfefc00f8,
684 },{ .name = "PMC_LSBUS_REF_CTRL", .addr = A_PMC_LSBUS_REF_CTRL,
685 .reset = 0x1000800,
686 .rsvd = 0xfefc00f8,
687 },{ .name = "I2C_REF_CTRL", .addr = A_I2C_REF_CTRL,
688 .reset = 0xc00,
689 .rsvd = 0xfefc00f8,
690 },{ .name = "EFUSE_REF_CTRL", .addr = A_EFUSE_REF_CTRL,
691 .rsvd = 0xb,
692 },{ .name = "SYSMON_REF_CTRL", .addr = A_SYSMON_REF_CTRL,
693 .rsvd = 0xb,
694 },{ .name = "USB_SUSPEND_CTRL", .addr = A_USB_SUSPEND_CTRL,
695 .reset = 0x1f400,
696 .rsvd = 0xfffc00ff,
697 },{ .name = "SWITCH_TIMEOUT_CTRL", .addr = A_SWITCH_TIMEOUT_CTRL,
698 .reset = 0x6400,
699 .rsvd = 0xfffc00ff,
700 },{ .name = "HSM0_REF_CTRL", .addr = A_HSM0_REF_CTRL,
701 .reset = 0x2000,
702 .rsvd = 0xfdfc00f8,
703 },{ .name = "HSM1_REF_CTRL", .addr = A_HSM1_REF_CTRL,
704 .reset = 0x2000,
705 .rsvd = 0xfdfc00f8,
706 },{ .name = "SAFETY_CHK", .addr = A_SAFETY_CHK,
707 },{ .name = "SD_DLL_REF_CTRL", .addr = A_SD_DLL_REF_CTRL,
708 .reset = 0x100,
709 .rsvd = 0xfdfc00f8,
710 },{ .name = "BOOT_MODE_USER", .addr = A_BOOT_MODE_USER,
711 .rsvd = 0xf0ef0,
712 .ro = 0xf,
713 .post_write = boot_mode_user_postw,
714 },{ .name = "BOOT_MODE_POR", .addr = A_BOOT_MODE_POR,
715 .rsvd = 0xf000,
716 .ro = 0xfff,
717 },{ .name = "RESET_REASON", .addr = A_RESET_REASON,
718 .reset = 0x1,
719 .rsvd = 0xf870,
720 .ro = 0xf870,
721 .w1c = 0x78f,
722 },{ .name = "CLKMON_STATUS", .addr = A_CLKMON_STATUS,
723 .w1c = 0xffff,
724 .post_write = clkmon_status_postw,
725 },{ .name = "CLKMON_MASK", .addr = A_CLKMON_MASK,
726 .reset = 0xffff,
727 .ro = 0xffff,
728 },{ .name = "CLKMON_ENABLE", .addr = A_CLKMON_ENABLE,
729 .pre_write = clkmon_enable_prew,
730 },{ .name = "CLKMON_DISABLE", .addr = A_CLKMON_DISABLE,
731 .pre_write = clkmon_disable_prew,
732 },{ .name = "CLKMON_TRIGGER", .addr = A_CLKMON_TRIGGER,
733 .pre_write = clkmon_trigger_prew,
734 },{ .name = "CHKR0_CLKA_UPPER", .addr = A_CHKR0_CLKA_UPPER,
735 },{ .name = "CHKR0_CLKA_LOWER", .addr = A_CHKR0_CLKA_LOWER,
736 },{ .name = "CHKR0_CLKB_CNT", .addr = A_CHKR0_CLKB_CNT,
737 },{ .name = "CHKR0_CTRL", .addr = A_CHKR0_CTRL,
738 .reset = 0x400,
739 .rsvd = 0xa0,
740 .ro = 0x400,
741 },{ .name = "CHKR1_CLKA_UPPER", .addr = A_CHKR1_CLKA_UPPER,
742 },{ .name = "CHKR1_CLKA_LOWER", .addr = A_CHKR1_CLKA_LOWER,
743 },{ .name = "CHKR1_CLKB_CNT", .addr = A_CHKR1_CLKB_CNT,
744 },{ .name = "CHKR1_CTRL", .addr = A_CHKR1_CTRL,
745 .reset = 0x400,
746 .rsvd = 0xa0,
747 .ro = 0x400,
748 },{ .name = "CHKR2_CLKA_UPPER", .addr = A_CHKR2_CLKA_UPPER,
749 },{ .name = "CHKR2_CLKA_LOWER", .addr = A_CHKR2_CLKA_LOWER,
750 },{ .name = "CHKR2_CLKB_CNT", .addr = A_CHKR2_CLKB_CNT,
751 },{ .name = "CHKR2_CTRL", .addr = A_CHKR2_CTRL,
752 .reset = 0x400,
753 .rsvd = 0xa0,
754 .ro = 0x400,
755 },{ .name = "CHKR3_CLKA_UPPER", .addr = A_CHKR3_CLKA_UPPER,
756 },{ .name = "CHKR3_CLKA_LOWER", .addr = A_CHKR3_CLKA_LOWER,
757 },{ .name = "CHKR3_CLKB_CNT", .addr = A_CHKR3_CLKB_CNT,
758 },{ .name = "CHKR3_CTRL", .addr = A_CHKR3_CTRL,
759 .reset = 0x400,
760 .rsvd = 0xa0,
761 .ro = 0x400,
762 },{ .name = "CHKR4_CLKA_UPPER", .addr = A_CHKR4_CLKA_UPPER,
763 },{ .name = "CHKR4_CLKA_LOWER", .addr = A_CHKR4_CLKA_LOWER,
764 },{ .name = "CHKR4_CLKB_CNT", .addr = A_CHKR4_CLKB_CNT,
765 },{ .name = "CHKR4_CTRL", .addr = A_CHKR4_CTRL,
766 .reset = 0x400,
767 .rsvd = 0xa0,
768 .ro = 0x400,
769 },{ .name = "CHKR5_CLKA_UPPER", .addr = A_CHKR5_CLKA_UPPER,
770 },{ .name = "CHKR5_CLKA_LOWER", .addr = A_CHKR5_CLKA_LOWER,
771 },{ .name = "CHKR5_CLKB_CNT", .addr = A_CHKR5_CLKB_CNT,
772 },{ .name = "CHKR5_CTRL", .addr = A_CHKR5_CTRL,
773 .reset = 0x400,
774 .rsvd = 0xa0,
775 .ro = 0x400,
776 },{ .name = "CHKR6_CLKA_UPPER", .addr = A_CHKR6_CLKA_UPPER,
777 },{ .name = "CHKR6_CLKA_LOWER", .addr = A_CHKR6_CLKA_LOWER,
778 },{ .name = "CHKR6_CLKB_CNT", .addr = A_CHKR6_CLKB_CNT,
779 },{ .name = "CHKR6_CTRL", .addr = A_CHKR6_CTRL,
780 .reset = 0x400,
781 .rsvd = 0xa0,
782 .ro = 0x400,
783 },{ .name = "CHKR7_CLKA_UPPER", .addr = A_CHKR7_CLKA_UPPER,
784 },{ .name = "CHKR7_CLKA_LOWER", .addr = A_CHKR7_CLKA_LOWER,
785 },{ .name = "CHKR7_CLKB_CNT", .addr = A_CHKR7_CLKB_CNT,
786 },{ .name = "CHKR7_CTRL", .addr = A_CHKR7_CTRL,
787 .reset = 0x400,
788 .rsvd = 0xa0,
789 .ro = 0x400,
790 },{ .name = "RST_QSPI", .addr = A_RST_QSPI,
791 .reset = 0x1,
792 .post_write = crp_update_gpios_pw,
793 },{ .name = "RST_OSPI", .addr = A_RST_OSPI,
794 .reset = 0x1,
795 .post_write = crp_update_gpios_pw,
796 },{ .name = "RST_SDIO0", .addr = A_RST_SDIO0,
797 .reset = 0x1,
798 .post_write = crp_update_gpios_pw,
799 },{ .name = "RST_SDIO1", .addr = A_RST_SDIO1,
800 .reset = 0x1,
801 .post_write = crp_update_gpios_pw,
802 },{ .name = "RST_I2C", .addr = A_RST_I2C,
803 .reset = 0x1,
804 .post_write = crp_update_gpios_pw,
805 },{ .name = "RST_GPIO", .addr = A_RST_GPIO,
806 .reset = 0x1,
807 .post_write = crp_update_gpios_pw,
808 },{ .name = "RST_PS", .addr = A_RST_PS,
809 .reset = 0x66,
810 .rsvd = 0x11,
811 .pre_write = rst_ps_prew,
812 .post_write = crp_update_gpios_pw,
813 },{ .name = "RST_NONPS", .addr = A_RST_NONPS,
814 .reset = 0x77,
815 .rsvd = 0x88,
816 .post_write = crp_update_gpios_pw,
817 },{ .name = "RST_SBI", .addr = A_RST_SBI,
818 .reset = 0x1,
819 .post_write = crp_update_gpios_pw,
820 },{ .name = "RST_PDMA", .addr = A_RST_PDMA,
821 .reset = 0x3,
822 .post_write = crp_update_gpios_pw,
823 },{ .name = "RST_SYSMON", .addr = A_RST_SYSMON,
824 .post_write = crp_update_gpios_pw,
825 },{ .name = "RST_PL", .addr = A_RST_PL,
826 .reset = 0xf,
827 .post_write = crp_update_gpios_pw,
828 },{ .name = "RST_USB", .addr = A_RST_USB,
829 .reset = 0x1,
830 .post_write = crp_update_gpios_pw,
831 },{ .name = "RST_DBG", .addr = A_RST_DBG,
832 .reset = 0x3,
833 .post_write = crp_update_gpios_pw,
834 },{ .name = "PMC_PL0_REF_CTRL", .addr = A_PMC_PL0_REF_CTRL,
835 .reset = 0x500,
836 .rsvd = 0xfefc00f8,
837 },{ .name = "PMC_PL1_REF_CTRL", .addr = A_PMC_PL1_REF_CTRL,
838 .reset = 0x500,
839 .rsvd = 0xfefc00f8,
840 },{ .name = "PMC_PL2_REF_CTRL", .addr = A_PMC_PL2_REF_CTRL,
841 .reset = 0x500,
842 .rsvd = 0xfefc00f8,
843 },{ .name = "PMC_PL3_REF_CTRL", .addr = A_PMC_PL3_REF_CTRL,
844 .reset = 0x500,
845 .rsvd = 0xfefc00f8,
846 }
847};
848
849static void crp_reset(DeviceState *dev)
850{
851 CRP *s = XILINX_CRP(dev);
852 QemuOpts *opts = qemu_find_opts_singleton("boot-opts");
853 uint32_t boot_mode = qemu_opt_get_number(opts, "mode", 0);
854 unsigned int i;
855 hwaddr addr;
856
857 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
858 if (s->regs_info[i].access) {
859 addr = s->regs_info[i].access->addr;
860 } else {
861 continue;
862 }
863 switch (addr) {
864 case A_RESET_REASON:
865 continue;
866 default:
867 register_reset(&s->regs_info[i]);
868 }
869 }
870
871
872 if (ARRAY_FIELD_EX32(s->regs, RST_PS, PMC_SRST) ||
873 ARRAY_FIELD_EX32(s->regs, RST_PS, PMC_POR)) {
874 ARRAY_FIELD_DP32(s->regs, RST_PS, PMC_SRST, 0);
875 ARRAY_FIELD_DP32(s->regs, RST_PS, PMC_POR, 0);
876
877
878 }
879
880 s->regs[R_BOOT_MODE_POR] = boot_mode;
881 update_boot_mode_user(s);
882
883 ir_update_irq(s);
884 clkmon_update_irq(s);
885 crp_update_gpios(s);
886}
887
888static const MemoryRegionOps crp_ops = {
889 .read = register_read_memory,
890 .write = register_write_memory,
891 .endianness = DEVICE_LITTLE_ENDIAN,
892 .valid = {
893 .min_access_size = 4,
894 .max_access_size = 4,
895 },
896};
897
898static void crp_init(Object *obj)
899{
900 CRP *s = XILINX_CRP(obj);
901 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
902 RegisterInfoArray *reg_array;
903
904 memory_region_init(&s->iomem, obj, TYPE_XILINX_CRP, R_MAX * 4);
905 reg_array =
906 register_init_block32(DEVICE(obj), crp_regs_info,
907 ARRAY_SIZE(crp_regs_info),
908 s->regs_info, s->regs,
909 &crp_ops,
910 XILINX_CRP_ERR_DEBUG,
911 R_MAX * 4);
912 memory_region_add_subregion(&s->iomem,
913 0x0,
914 ®_array->mem);
915 sysbus_init_mmio(sbd, &s->iomem);
916 sysbus_init_irq(sbd, &s->irq_ir);
917 sysbus_init_irq(sbd, &s->irq_clkmon);
918
919 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_qspi, "rst-qspi", 1);
920 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_ospi, "rst-ospi", 1);
921 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_sdio[0], "rst-sdio0", 1);
922 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_sdio[1], "rst-sdio1", 1);
923 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_i2c, "rst-i2c", 1);
924 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_gpio, "rst-gpio", 1);
925
926 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_ps_pl_srst,
927 "rst-ps-pl-srst", 1);
928 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_ps_ps_srst,
929 "rst-ps-ps-srst", 1);
930 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_ps_pmc_srst,
931 "rst-ps-pmc-srst", 1);
932 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_ps_pl_por,
933 "rst-ps-pl-por", 1);
934 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_ps_ps_por,
935 "rst-ps-ps-por", 1);
936 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_ps_pmc_por,
937 "rst-ps-pmc-por", 1);
938
939 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_nonps_sys3,
940 "rst-nonps-sys3", 1);
941 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_nonps_sys2,
942 "rst-nonps-sys2", 1);
943 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_nonps_sys1,
944 "rst-nonps-sys1", 1);
945 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_nonps_npi,
946 "rst-nonps-npi", 1);
947 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_nonps_noc_por,
948 "rst-nonps-noc-por", 1);
949 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_nonps_noc,
950 "rst-nonps-noc", 1);
951
952 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_sbi, "rst-sbi", 1);
953 qdev_init_gpio_out_named(DEVICE(obj), s->rst_pdma, "rst-pdma", 2);
954 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_sysmon_cfg,
955 "rst-sysmon-cfg", 1);
956 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_sysmon_seq,
957 "rst-sysmon-seq", 1);
958 qdev_init_gpio_out_named(DEVICE(obj), s->rst_pl, "rst-pl", 4);
959 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_usb, "rst-usb", 1);
960 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_dbg, "rst-dbg-reset", 1);
961 qdev_init_gpio_out_named(DEVICE(obj), &s->rst_dbg_dpc, "rst-dbg-dpc", 1);
962
963}
964
965static const VMStateDescription vmstate_crp = {
966 .name = TYPE_XILINX_CRP,
967 .version_id = 1,
968 .minimum_version_id = 1,
969 .fields = (VMStateField[]) {
970 VMSTATE_UINT32_ARRAY(regs, CRP, R_MAX),
971 VMSTATE_END_OF_LIST(),
972 }
973};
974
975static const FDTGenericGPIOSet crp_gpios[] = {
976 {
977 .names = &fdt_generic_gpio_name_set_gpio,
978 .gpios = (FDTGenericGPIOConnection[]) {
979#include "xlnx-versal-pmc-clk-rst-gpio-map.h"
980 { },
981 },
982 },
983 { },
984};
985
986static void crp_class_init(ObjectClass *klass, void *data)
987{
988 DeviceClass *dc = DEVICE_CLASS(klass);
989 FDTGenericGPIOClass *fggc = FDT_GENERIC_GPIO_CLASS(klass);
990
991 dc->reset = crp_reset;
992 dc->vmsd = &vmstate_crp;
993 fggc->controller_gpios = crp_gpios;
994}
995
996static const TypeInfo crp_info = {
997 .name = TYPE_XILINX_CRP,
998 .parent = TYPE_SYS_BUS_DEVICE,
999 .instance_size = sizeof(CRP),
1000 .class_init = crp_class_init,
1001 .instance_init = crp_init,
1002 .interfaces = (InterfaceInfo[]) {
1003 { TYPE_FDT_GENERIC_GPIO },
1004 { }
1005 },
1006};
1007
1008static void crp_register_types(void)
1009{
1010 type_register_static(&crp_info);
1011}
1012
1013type_init(crp_register_types)
1014
